FC8J33040L FC8J33040L Dual N-channel MOSFET Unit: mm For switching Features y Low drain-source ON resistance:Rss(on)typ. = 48 mΩ (VGS = 4.5V) y High-speed switching :Qg = 2.8 nC y Halogen-free / RoHS compliant (EU RoHS / UL-94 V-0 / MSL:Level 1 compliant) Marking Symbol: 7A 1. Source(FET1) 2. Gate(FET1) 3. Source(FET2) 4. Gate(FET2) Basic Part Number Dual Nch MOS 33V (Individual) 5. Drain(FET2) 6. Drain(FET2) 7. Drain(FET1) 8. Drain(FET1) Packaging FC8J33040L Embossed type (Thermo-compression sealing): 3 000 pcs / reel (standard) Absolute Maximum Ratings Panasonic JEITA Code WMini8-F1 SC-115 ― Ta = 25°C FET1 Parameter Drain-source Voltage Gate-source Voltage Drain Current (Steady State) *1 FET1 Drain Current (t=10s) *1 FET2 Drain Current (Pulsed) *1,2 Source Current (Pulsed) (Body Diode) *1,2 Power Dissipation (Steady State) Power Dissipation (t=10s) *1 Overall Channel Temperature Storage Temperature Range Note Symbol Rating Unit VDS VGS 33 ±20 5 5.5 20 V V ID IDp ISp (BD) *1 PD Tch Tstg A 5 1 1.3 150 -55 to +150 1 8 2 7 3 6 4 FET2 5 Pin name W °C °C 1. Source(FET1) 2. Gate(FET1) 3. Source(FET2) 4. Gate(FET2) 5. Drain(FET2) 6. Drain(FET2) 7. Drain(FET1) 8. Drain(FET1) *1 Device mounted on a glass-epoxy board (See Figure 1) *2 Pulse test: Ensure that the channel temperature does not exceed 150 °C FR-4 (Unit:mm) 25.4 x 25.4 x 0.8 (Figure 1) Glass-Epoxy Board Publication date: September 2012 Ver. CED 1 FC8J33040L Electrical Characteristics Ta = 25°C±3°C FET1, FET2 Static Characteristics Parameter Symbol Drain-source Breakdown Voltage Zero Gate Voltage Drain Current Gate-source Leakage Current Gate-source Threshold Voltage Drain-source On-state Resistance VDSS IDSS IGSS Vth *1 RDS(on) Conditions ID = 1 mA, VGS = 0 V VDS = 33 V, VGS = 0 V VGS = ±16 V, VDS = 0 V ID = 0.26 mA, VDS = 10 V ID = 2.5 A, VGS = 10 V ID = 2.5 A, VGS = 4.5 V Min. Typ. Max. 33 1 32 48 1 ±10 2.5 38 68 Unit V μA μA V mΩ Note *1 Pulse test: Ensure that the channel temperature does not exceed 150 °C Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd VDS = 10 V, VGS = 0 V, f = 1 MHz VDD = 15 V, VGS = 0 to 10 V ID = 2.5 A (See Figure 2) VDD = 15 V, VGS = 10 to 0 V ID = 2.5 A (See Figure 2) VDD = 15 V, VGS = 0 to 4.5 V, ID = 5 A 220 40 35 7 3 15 9 2.8 1.1 1.2 pF ns nC Body Diode Characteristic Diode Forward Voltage *1 VSD IS = 2.5 A, VGS = 0 V 0.8 1.2 V Note *1 Pulse test: Ensure that the channel temperature does not exceed 150 °C Ver. CED 2 FC8J33040L VDD = 15 V ID=2.5A Vin Vout 10V PW = 10μs D.C. ≦ 1 % 0V D Vin G 50 Ω S 90% Vin 10% 90% 90% Vout 10% td(on) tr 10% td(off) tf (Figure 2) Measuremet circuit for Turn-On Delay Time/Rise Time/Turn-Off Delay Time/Fall Time Ver. CED 3 FC8J33040L 4 2.5 3 4.5V 2 Drain Current ID (A) Drain Current ID (A) 10.0V 4.0V 2 3.5V 1 Ta=85°C 1.5 25°C 1 -30°C 0.5 VGS=3.0V 0 0 0 0.1 0.2 0 0.3 1 Drain-source Voltage VDS (V) ID - VDS 4 5 1000 Drain-source On-state Resistance RDS(on) (mΩ) Drain-source Voltage VDS (V) 3 ID - VGS 1 0.8 ID=5.0A 0.6 2.5A 0.4 0.2 1.25A 100 4.5V VGS=10.0V 10 0 1 0 2 4 6 8 10 0.1 1 Gate-source Voltage VGS (V) Drain Current ID (A) VDS - VGS RDS(on) - ID 15 Gate-source Voltage VGS (V) 1000 Capacitance C (pF) 2 Gate-source Voltage VGS (V) Ciss 100 Coss Crss 10 VDD=15V 10 5 0 1 0.1 1 10 0 100 2 4 6 8 10 Total Gate Charge Qg (nC) Drain-source Voltage VDS (V) Capacitance - VDS Dynamic Input/Output Characteristics Ver. CED 4 3 80 Drain-source On-state Resistance RDS(on) (mΩ) Gate- source Threshold Voltage Vth (V) FC8J33040L 2 1 0 -50 0 50 100 4.5V 60 40 VGS=10.0V 20 0 150 -50 0 Temperature Ta (°C) 50 100 150 200 Temperature Ta (°C) Vth - Ta RDS(on) - Ta Total Power Dissipation PD (W) 2 1.5 Mounted on a glass-epoxy board (25.4 x 25.4 x 0.8 mm) 1 0.5 0 0 50 100 150 Temperature Ta (°C) PD - Ta 1000 Drain Current ID (A) Thermal Resistance Rth (°C/W) 1000 100 10 100 IDp=20A 0.1 1 10 100 1000 2 which has more than 300mm . 10 1 0.1 0.01 0.01 1 Ta=25°C, Glass epoxy board (25.4×25.4×t0.8mm) coated with copper foil, 1ms 10ms Operation in this area is limited by RDS(on) 100ms 1s DC 0.1 1 10 100 Drain-source Voltage VDS (V) Pulse Width tsw (s) Rth - tsw Safe Operating Area Ver. CED 5 FC8J33040L WMini8-F1 Unit: mm Land Pattern (Reference) (Unit: mm) Ver. CED 6 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. 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(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202