TI1 MSP430I2021TPW Mixed-signal microcontroller Datasheet

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MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
SLAS887 – AUGUST 2014
MSP430i204x, MSP430i203x, MSP430i202x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Supply Voltage Range 2.2 V to 3.6 V
• 16-Bit RISC Architecture, up to 16.384-MHz
System Clock
• Power Consumption
– Active Mode (AM):
All System Clocks Active
275 µA/MHz at 16.384-MHz, 3.0 V, Flash
Program Execution (Typical)
– Standby Mode (LPM3):
Watchdog Timer Active, Full RAM Retention
210 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention
70 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
75 nA at 3.0 V (Typical)
• Wake Up From Standby Mode in 1 µs
• Memories
– Up to 32KB of Flash Main Memory
– 1KB of Flash Information Memory
– Up to of 2KB of RAM
• Power Management System
– Integrated LDO With 1.8-V Regulated Core
Supply Voltage
– Supply Voltage Monitor With Programmable
Level Detection
– Brownout Detector
– Built-in Voltage Reference
– Temperature Sensor
1.2
•
•
• Clock System
– 16.384-MHz Internal DCO
– DCO Operation With Internal or External
Resistor
– External Digital Clock Source
• Up to Four 24-Bit Sigma-Delta Analog-to-Digital
Converters (ADCs) With Differential PGA Inputs
• Two 16-Bit Timers With Three Capture/Compare
Registers Each
• Enhanced Universal Serial Communication
Interfaces (eUSCIs)
– eUSCI_A0
• Enhanced UART With Automatic Baud-Rate
Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– eUSCI_B0
• Synchronous SPI
• I2C
• 16-Bit Hardware Multiplier
• Serial Onboard Programming, No External
Programming Voltage Needed
• Programmable Code Protection
• On-Chip Emulation Module
• Family Members are Summarized in Section 3
• Available in 28-Pin TSSOP (PW) and 32-Pin
VQFN (RHB) Packages
• For Complete Module Descriptions, See the
MSP430i2xx Family User's Guide (SLAU335)
Applications
Metering
Submetering
•
•
Power Monitoring and Control
Industrial Sensors
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
SLAS887 – AUGUST 2014
1.3
www.ti.com
Description
The MSP430i204x, MSP430i203x, MSP430i202x devices consist of a powerful 16-bit RISC CPU, a DCObased clock system that generates system clocks, a power management module (PMM) with built-in
voltage reference and voltage monitor, two to four 24-bit sigma-delta analog-to-digital converters (ADCs),
a temperature sensor, a 16-bit hardware multiplier, two 16-bit timers, one eUSCI-A module and one
eUSCI-B module, a watchdog timer (WDT), and up to 16 I/O pins.
Device Information (1)
PACKAGE
BODY SIZE (NOM) (2)
MSP430i2041PW
TSSOP (28)
9.7 mm x 4.4 mm
MSP430i2041RHB
VQFN (32)
5 mm x 5 mm
PART NUMBER
(1)
(2)
1.4
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI web site at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Functional Block Diagram
Figure 1-1 shows the functional block diagram for the MSP430i204x devices in the RHB package. For the
functional block diagrams of all device variants and packages, see Section 6.2.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
8
ACLK
Clock
System
Flash
32KB
16KB
SMCLK
RAM
TA0
TA1
Port P1
Port P2
2KB
1KB
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
8 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
JTAG
Interface
Spy-Bi
Wire
Power
Management
LDO
REF
VMON
Brownout
SD24
4 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 1-1. Functional Block Diagram - RHB Package - MSP430i204x
2
Device Overview
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MSP430i2021, MSP430i2020
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SLAS887 – AUGUST 2014
Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
6.2
Functional Block Diagrams.......................... 33
1.1
Features .............................................. 1
6.3
CPU
1.2
Applications ........................................... 1
6.4
Instruction Set ....................................... 37
1.3
Description ............................................ 2
6.5
Operating Modes .................................... 38
1.4
Functional Block Diagram ............................ 2
6.6
Interrupt Vector Addresses.......................... 39
Revision History ......................................... 3
Device Comparison ..................................... 4
Terminal Configuration and Functions .............. 5
6.7
Special Function Registers.......................... 40
6.8
Flash Memory ....................................... 40
36
6.9
JTAG Operation ..................................... 41
4.1
Pin Diagrams ......................................... 5
6.10
Peripherals
4.2
Signal Descriptions .................................. 11
6.11
Memory .............................................. 55
4.3
Pin Multiplexing
6.12
Identification ......................................... 59
4.4
Connection of Unused Pins ......................... 13
.....................................
13
Specifications ........................................... 14
7
8
..........................................
43
Applications, Implementation, and Layout ....... 60
Device and Documentation Support ............... 62
5.1
Absolute Maximum Ratings ......................... 14
8.1
Device Support ...................................... 62
5.2
Handling Ratings .................................... 14
8.2
Documentation Support ............................. 65
5.3
5.4
Recommended Operating Conditions ............... 14
Active Mode Supply Current (Into VCC) Excluding
External Current .................................... 15
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current ......................... 15
8.3
Related Links ........................................ 65
8.4
Community Resources .............................. 65
8.5
Trademarks.......................................... 66
8.6
Electrostatic Discharge Caution ..................... 66
8.7
Glossary ............................................. 66
5.5
5.6
6
.................................................
Timing and Switching Characteristics ............... 16
Detailed Description ................................... 32
6.1
Overview
............................................
32
9
Mechanical Packaging and Orderable
Information .............................................. 66
9.1
Packaging Information
..............................
66
2 Revision History
DATE
REVISION
NOTES
August 2014
*
Initial Release
Revision History
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MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
SLAS887 – AUGUST 2014
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3 Device Comparison
Family members available are summarized in Table 3-1.
Table 3-1. Device Comparison (1)
eUSCI
Device
MSP430i2041
MSP430i2040
MSP430i2031
MSP430i2030
MSP430i2021
MSP430i2020
(1)
(2)
4
Flash
(KB)
SRAM
(KB)
SD24
Converters
Multiplier
Timer_A (2)
Channel A:
UART, IrDA,
SPI
Channel B:
SPI, I2C
32
2
4
1
3, 3
1
1
16
32
16
32
16
1
2
1
2
1
4
3
3
2
2
1
1
1
1
1
3, 3
3, 3
3, 3
3, 3
3, 3
1
1
1
1
1
1
1
1
1
1
I/O
Package
Type
16
32 RHB
12
28 PW
16
32 RHB
12
28 PW
16
32 RHB
12
28 PW
16
32 RHB
12
28 PW
16
32 RHB
12
28 PW
16
32 RHB
12
28 PW
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9,
or see the TI web site at www.ti.com.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Device Comparison
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MSP430i2021, MSP430i2020
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SLAS887 – AUGUST 2014
4 Terminal Configuration and Functions
4.1
Pin Diagrams
P2.0/TA1.0/CLKIN
P2.1/TA1.1
P2.2/TA1.2
P2.3/VMONIN
P2.4/TA1.0
P2.5/TA0.0
P2.6/TA0.1
P2.7/TA0.2
Figure 4-1 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the RHB
package.
32 31 30 29 28 27 26 25
A0.0+
1
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0-
2
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+
3
22
P1.5/UCB0CLK/TA0.1
MSP430i2041TRHB
MSP430i2040TRHB
A1.0-
4
21
P1.4/UCB0STE/TA0.0
A2.0+
5
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
A2.0-
6
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
A3.0+
7
18
P1.1/UCA0CLK/SMCLK/TMS
A3.0-
8
17
P1.0/UCA0STE/MCLK/TCK
TEST/SBWTCK
RST/NMI/SBWTDIO
VCORE
VCC
DVSS
AVSS
ROSC
VREF
9 10 11 12 13 14 15 16
NOTE: It is recommended to connect the thermal pad on the RHB package to DVSS.
Figure 4-1. 32-Pin RHB Package (Top View) - MSP430i2041, MSP430i2040
Terminal Configuration and Functions
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MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
SLAS887 – AUGUST 2014
www.ti.com
Figure 4-2 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the PW
package.
A0.0+
1
28
P2.3/VMONIN
A0.0-
2
27
P2.2/TA1.2
A1.0+
3
26
P2.1/TA1.1
A1.0-
4
25
P2.0/TA1.0/CLKIN
A2.0+
5
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A2.0-
6
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
MSP430i2041TPW
MSP430i2040TPW
A3.0+
7
22
P1.5/UCB0CLK/TA0.1
A3.0-
8
21
P1.4/UCB0STE/TA0.0
VREF
9
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS
10
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC
11
18
P1.1/UCA0CLK/SMCLK/TMS
DVSS
12
17
P1.0/UCA0STE/MCLK/TCK
VCC
13
16
TEST/SBWTCK
VCORE
14
15
RST/NMI/SBWTDIO
Figure 4-2. 28-Pin PW Package (Top View) - MSP430i2041, MSP430i2040
6
Terminal Configuration and Functions
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SLAS887 – AUGUST 2014
P2.0/TA1.0/CLKIN
P2.1/TA1.1
P2.2/TA1.2
P2.3/VMONIN
P2.4/TA1.0
P2.5/TA0.0
P2.6/TA0.1
P2.7/TA0.2
Figure 4-3 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the RHB
package.
32 31 30 29 28 27 26 25
A0.0+
1
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0-
2
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+
3
22
P1.5/UCB0CLK/TA0.1
A1.0-
4
21
P1.4/UCB0STE/TA0.0
A2.0+
5
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
A2.0-
6
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
NC
7
18
P1.1/UCA0CLK/SMCLK/TMS
NC
8
17
P1.0/UCA0STE/MCLK/TCK
MSP430i2031TRHB
MSP430i2030TRHB
TEST/SBWTCK
RST/NMI/SBWTDIO
VCORE
VCC
DVSS
AVSS
ROSC
VREF
9 10 11 12 13 14 15 16
NOTE: It is recommended to connect the thermal pad on the RHB package to DVSS.
NOTE: It is recommended to connect NC pins to AVSS.
Figure 4-3. 32-Pin RHB Package (Top View) - MSP430i2031, MSP430i2030
Terminal Configuration and Functions
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MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
SLAS887 – AUGUST 2014
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Figure 4-4 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the PW
package.
A0.0+
1
28
P2.3/VMONIN
A0.0-
2
27
P2.2/TA1.2
A1.0+
3
26
P2.1/TA1.1
A1.0-
4
25
P2.0/TA1.0/CLKIN
A2.0+
5
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A2.0-
6
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
MSP430i2031TPW
MSP430i2030TPW
NC
7
22
P1.5/UCB0CLK/TA0.1
NC
8
21
P1.4/UCB0STE/TA0.0
VREF
9
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS
10
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC
11
18
P1.1/UCA0CLK/SMCLK/TMS
DVSS
12
17
P1.0/UCA0STE/MCLK/TCK
VCC
13
16
TEST/SBWTCK
VCORE
14
15
RST/NMI/SBWTDIO
NOTE: It is recommended to connect NC pins to AVSS.
Figure 4-4. 28-Pin PW Package (Top View) - MSP430i2031, MSP430i2030
8
Terminal Configuration and Functions
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P2.0/TA1.0/CLKIN
P2.1/TA1.1
P2.2/TA1.2
P2.3/VMONIN
P2.4/TA1.0
P2.5/TA0.0
P2.6/TA0.1
P2.7/TA0.2
Figure 4-5 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the RHB
package.
32 31 30 29 28 27 26 25
A0.0+
1
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0-
2
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+
3
22
P1.5/UCB0CLK/TA0.1
A1.0-
4
21
P1.4/UCB0STE/TA0.0
NC
5
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
NC
6
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
NC
7
18
P1.1/UCA0CLK/SMCLK/TMS
NC
8
17
P1.0/UCA0STE/MCLK/TCK
MSP430i2021TRHB
MSP430i2020TRHB
TEST/SBWTCK
RST/NMI/SBWTDIO
VCORE
VCC
DVSS
AVSS
ROSC
VREF
9 10 11 12 13 14 15 16
NOTE: It is recommended to connect the thermal pad on the RHB package to DVSS.
NOTE: It is recommended to connect NC pins to AVSS.
Figure 4-5. 32-Pin RHB Package (Top View) - MSP430i2021, MSP430i2020
Terminal Configuration and Functions
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MSP430i2041, MSP430i2040
MSP430i2031, MSP430i2030
MSP430i2021, MSP430i2020
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Figure 4-5 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the PW
package.
A0.0+
1
28
P2.3/VMONIN
A0.0-
2
27
P2.2/TA1.2
A1.0+
3
26
P2.1/TA1.1
A1.0-
4
25
P2.0/TA1.0/CLKIN
NC
5
24
P1.7/UCB0SDA/UCB0SIMO/TA1CLK
NC
6
23
P1.6/UCB0SCL/UCB0SOMI/TA0.2
MSP430i2021TPW
MSP430i2020TPW
NC
7
22
P1.5/UCB0CLK/TA0.1
NC
8
21
P1.4/UCB0STE/TA0.0
VREF
9
20
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS
10
19
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC
11
18
P1.1/UCA0CLK/SMCLK/TMS
DVSS
12
17
P1.0/UCA0STE/MCLK/TCK
VCC
13
16
TEST/SBWTCK
VCORE
14
15
RST/NMI/SBWTDIO
NOTE: It is recommended to connect NC pins to AVSS.
Figure 4-6. 28-Pin PW Package (Top View) - MSP430i2021, MSP430i2020
10
Terminal Configuration and Functions
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4.2
SLAS887 – AUGUST 2014
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO. (2)
I/O (1)
DESCRIPTION
PW
RHB
A0.0+
1
1
I
SD24 positive analog input A0.0.
A0.0-
2
2
I
SD24 negative analog input A0.0.
(3)
(3)
(3)
A1.0+
3
3
I
SD24 positive analog input A1.0.
A1.0-
4
4
I
SD24 negative analog input A1.0.
(3)
(3) (4)
A2.0+
5
5
I
SD24 positive analog input A2.0.
A2.0-
6
6
I
SD24 negative analog input A2.0.
(3) (4)
(3) (4) (5)
A3.0+
7
7
I
SD24 positive analog input A3.0.
A3.0-
8
8
I
SD24 negative analog input A3.0.
VREF (6)
9
9
I
SD24 external reference voltage input.
AVSS
10
10
(3) (4) (5)
Analog supply voltage, negative terminal.
External resistor pin for DCO.
ROSC
11
Recommended resistor must be connected between ROSC and AVSS for
DCO operation in external resistor mode.
11
Recommended to connect ROSC to AVSS while operating DCO in internal
resistor mode.
DVSS
12
12
Digital supply voltage, negative terminal.
VCC
13
13
Analog and digital supply voltage, positive terminal.
(7)
14
14
Regulated core power supply (internal use only, no external current loading).
RST/NMI/SBWTDIO
15
15
VCORE
I/O
Reset or non-maskable interrupt input.
Spy-Bi-Wire test data input/output for device programming and test.
TEST/SBWTCK
16
16
I
Selects test mode for JTAG pins on P1.0 to P1.3.
Spy-Bi-Wire test clock input for device programming and test.
General-purpose digital I/O pin.
P1.0/UCA0STE/MCLK/TCK
17
17
I/O
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI).
MCLK output.
JTAG test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 clock input/output (direction controlled by eUSCI).
P1.1/UCA0CLK/SMCLK/TMS
18
18
I/O
SMCLK output.
JTAG test mode select. TMS is used as an input port for device programming
and test.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
I = input, O = output
N/A = not available
It is recommended to short unused analog input pairs and connect them to analog ground (see Section 4.4 for recommendations on all
unused pins).
Not available on MSP430i2021 and MSP430i2020 devices.
Not available on MSP430i2031 and MSP430i2030 devices.
When SD24 operates with internal reference (SD24REFS = 1) the VREF pin must not be loaded externally. Only the recommended
capacitor value, CVREF must be connected at VREF pin to AVSS (see Table 5-19).
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE (see Section 5.3).
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
PW
I/O (1)
DESCRIPTION
RHB
General-purpose digital I/O pin.
P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK
19
19
I/O
eUSCI_A0 UART receive data or eUSCI_A0 SPI slave out/master in (direction
controlled by eUSCI).
ACLK output.
JTAG test data input or test clock input for device programming and test.
General-purpose digital I/O pin.
P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI
20
20
I/O
eUSCI_A0 UART transmit data or eUSCI_A0 SPI slave in/master out (direction
controlled by eUSCI).
Timer external clock input TACLK for TA0.
JTAG test data output port. TDO/TDI data output or programming data input
terminal.
General-purpose digital I/O pin.
P1.4/UCB0STE/TA0.0
21
21
I/O
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI).
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output.
General-purpose digital I/O pin.
P1.5/UCB0CLK/TA0.1
22
22
I/O
eUSCI_B0 clock input/output (direction controlled by eUSCI).
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output.
General-purpose digital I/O pin.
P1.6/UCB0SCL/UCB0SOMI/
TA0.2
23
23
I/O
eUSCI_B0 I2C clock or eUSCI_B0 SPI slave out/master in (direction controlled
by eUSCI).
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output.
General-purpose digital I/O pin.
P1.7/UCB0SDA/UCB0SIMO/
TA1CLK
24
24
I/O
eUSCI_B0 I2C data or eUSCI_B0 slave input/master output (direction
controlled by eUSCI).
Timer external clock input TACLK for TA1.
General-purpose digital I/O pin.
P2.0/TA1.0/CLKIN
25
25
I/O
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output.
DCO bypass clock input.
P2.1/TA1.1
26
26
I/O
General-purpose digital I/O pin.
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output.
P2.2/TA1.2
27
27
I/O
General-purpose digital I/O pin.
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 output.
P2.3/VMONIN
28
28
I/O
General-purpose digital I/O pin.
Voltage monitor input.
P2.4/TA1.0 (8)
N/A
29
I/O
General-purpose digital I/O pin.
Timer TA1 CCR0 capture: CCI0B input, compare: Out0 output.
(8)
12
These pins are not available on the 28-pin PW package. It is necessary to program these four pins to output direction and drive value 0
in software.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. (2)
NAME
P2.5/TA0.0 (8)
PW
RHB
N/A
30
I/O (1)
I/O
DESCRIPTION
General-purpose digital I/O pin.
Timer TA0 CCR0 capture: CCI0B input, compare: Out0 output.
P2.6/TA0.1 (8)
N/A
31
I/O
General-purpose digital I/O pin.
Timer TA0 CCR1 compare: Out1 output.
P2.7/TA0.2 (8)
N/A
32
I/O
General-purpose digital I/O pin.
Timer TA0 CCR2 compare: Out2 output.
4.3
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.10.10.
4.4
Connection of Unused Pins
The correct termination of all unused pins is listed in Table 4-2.
Table 4-2. Connection of Unused Pins (1)
PIN
POTENTIAL
AVCC
DVCC
AVSS
DVSS
COMMENT
VREF
Open
ROSC
AVSS
Connect ROSC pin to AVSS when DCO is used in internal resistor mode
Px.0 to Px.7
Open
Switched to port function, output direction
Ax.0+ and Ax.0-
AVSS
Short unused analog input pairs and connect them to analog ground
RST/NMI
DVCC or VCC
TEST
Open
This pin always has an internal pulldown enabled
Open
The JTAG pins are shared with general-purpose I/O function (P1.x). If not being used, these
should be switched to port function, output direction. When used as JTAG pins, these pins
should remain open.
47-kΩ pullup with 10 nF (or 2.2 nF (2)) pulldown
P1.3/TDO
P1.2/TDI
P1.1/TMS
P1.0/TCK
(1)
(2)
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
Voltage applied at VCC to DVSS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, ROSC) (2) (3)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
±2 mA
Maximum junction temperature, TJ,MAX
115°C
(1)
(2)
(3)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
No external DC loading or voltage should be applied at ROSC. Recommended resistor should be connected at ROSC for use of DCO in
external resistor mode. Recommended to connect ROSC to AVSS while operating DCO in internal resistor mode.
5.2
Handling Ratings
Tstg
(1)
Storage temperature range
(1)
MIN
MAX
UNIT
-55
150
°C
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.3
Recommended Operating Conditions
MIN
VCC
Supply voltage during program execution and flash programming or erase (VCC = VCC)
VSS
Supply voltage (AVSS = DVSS = VSS)
TA
Operating free-air temperature
T version
TJ
Operating junction temperature
T version
CVCORE
Recommended capacitor at VCORE
CVCC/
CVCORE
Capacitor ratio of VCC to VCORE
fSYSTEM
Processor frequency (maximum MCLK frequency)
(1)
(2)
NOM
MAX
2.2
UNIT
3.6
V
–40
105
°C
–40
105
°C
0
V
470
nF
10
(1) (2)
0
16.384
MHz
The MSP430i CPU is clocked directly with MCLK.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
System Frequency - MHz
3
2, 3
16.384
0
2.2
3.6
Supply Voltage - V
Figure 5-1. Maximum System Frequency
14
Specifications
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Active Mode Supply Current (Into VCC) Excluding External Current (1)
5.4
(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IAM,
1.024MHz
Active mode
current at
1.024 MHz
fDCO = 16.384 MHz, fMCLK = fSMCLK = 1.024 MHz,
fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
3V
1.6
mA
IAM,
8.192MHz
Active mode
current at
8.192 MHz
fDCO = 16.384 MHz, fMCLK = fSMCLK = 8.192 MHz,
fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
3V
3.0
mA
IAM,
16.384MHz
Active mode
current at
16.384 MHz
fDCO = fMCLK = fSMCLK = 16.384 MHz,
fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
3V
4.5
mA
(1)
(2)
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
All peripherals are inactive.
4.5
4.5
3.5
3
2.5
2
1.5
1
0.5
fMCLK = 1.024 MHz
fMCLK = 2.048 MHz
fMCLK = 4.096 MHz
fMCLK = 8.192 MHz
fMCLK = 16.348 MHz
IAM - Active Mode Current (mA)
IAM - Active Mode Current (mA)
4
0
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC - Supply Voltage (V)
D007
Figure 5-2. Active Mode Current vs Supply Voltage
5.5
4
3.5
3
2.5
2
TA = 25°C, V CC = 2.2 V
TA = 25°C, V CC = 3 V
TA = 105°C, V CC = 2.2 V
TA = 105°C, V CC = 3 V
1.5
1
0
2
4
6
8
10
12
fMCLK - Frequency (MHz)
14
16
18
D008
Figure 5-3. Active Mode Current vs MCLK Frequency
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ILPM3
Low-power mode 3
(LPM3) current (2)
fDCO = 16.384 MHz, fMCLK = fSMCLK = 0 MHz,
fACLK = 32 kHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0
ILPM4
Low-power mode 4
(LPM4) current (3)
fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1
ILPM4.5
Low-power mode 4.5
(LPM4.5) current (3)
fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,
REGOFF = 1, CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
(1)
(2)
(3)
TA
VCC
25°C
3V
210
µA
25°C
3V
70
µA
75
nA
325
nA
25°C
105°C
3V
MIN
TYP MAX UNIT
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Current for Watchdog Timer clocked by ACLK included. All other peripherals are inactive.
All peripherals are inactive.
Specifications
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Timing and Switching Characteristics
5.6.1
Reset Timing
Table 5-1. Reset Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tRESET
MIN
Pulse duration required at RST/NMI pin to accept a reset
5.6.2
MAX
UNIT
4
µs
Clock Specifications
Table 5-2. DCO in External Resistor Mode
recommended resistor at ROSC Pin: 20 kΩ, 0.1%, ±50ppm/°C) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
IDCO
DCO current consumption
85
fDCO
DCO frequency calibrated
16.384
DCO absolute tolerance calibrated
dfDCO/dT
DCO frequency temperature drift
dfDCO/dVC
C
DCO frequency supply voltage drift
DCDCO
Duty cycle
Tdcoon
DCO startup time
(1)
VCC = 3 V, TA = 25ºC
MAX
UNIT
µA
MHz
± 0.25%
200
± 20
ppm/°C
600
ppm/V
50%
40
µs
The maximum parasitic capacitance at ROSC pin should not exceed 5 pF to ensure the specified DCO startup time.
Table 5-3. DCO in Internal Resistor Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
IDCO
DCO current consumption
85
fDCO
DCO frequency calibrated
16.384
DCO absolute tolerance calibrated
dfDCO/dT
DCO frequency temperature drift
dfDCO/dVC
C
DCO frequency supply voltage drift
DCDCO
Duty cycle
Tdcoon
DCO startup time
VCC = 3 V, TA = 25ºC
MAX
UNIT
µA
MHz
± 0.9%
200
± 200
ppm/°C
600
ppm/V
50%
40
µs
Table 5-4. DCO Overall Tolerance Table
over operating free-air temperature range (unless otherwise noted)
Resistor Option
Internal resistor
External resistor with
50-ppm TCR
16
Specifications
Temperature
Change
Temperature
Drift (%)
Voltage change
Voltage Drift (%)
Overall Drift (%)
Overall
Accuracy (%)
-40°C to 105 °C
±2.9
2.2 V to 3.6 V
±0.084
±2.984
±3.884
0°C
0
2.2 V to 3.6 V
±0.084
±0.084
±0.984
-40°C to 105 °C
±2.9
0V
0
±2.9
±3.8
-40°C to 105 °C
±0.29
2.2 V to 3.6 V
±0.084
±0.374
±0.624
0°C
0
2.2 V to 3.6 V
±0.084
±0.084
±0.334
-40°C to 105 °C
±0.29
0V
0
±0.29
±0.54
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Table 5-5. DCO in Bypass Mode Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fDCOBYP
(1)
Frequency in DCO bypass mode (1)
MIN
MAX
UNIT
0
16.384
MHz
External digital clock frequency in DCO bypass mode must be 16.384 MHz for the SD24 module to meet the specified performance.
5.6.3
Wake-Up Characteristics
Table 5-6. Wake-Up From Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tWAKE-UP-LPM3
Wake-up time from LPM3 to active mode
MCLK = SMCLK = 1.024 MHz
1
µs
tWAKE-UP-LPM4
Wake-up time from LPM4 to active mode
MCLK = SMCLK = 1.024 MHz
35
µs
tWAKE-UP-LPM4.5-IO
Wake-up time from LPM4.5 to active
mode upon I/O event (1)
CVCORE = 470 nF
0.45
ms
tWAKE-UP-LPM4.5-
Wake-up time from LPM4.5 to active
mode upon external reset (RST) (1)
CVCORE = 470 nF
0.45
ms
RESET
(1)
This value represents the time from the wake up event to the reset vector execution by CPU.
Specifications
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I/O Ports
Table 5-7. Schmitt-Trigger Inputs - General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT-)
CI
Input capacitance
VCC
MIN
TYP
MAX
0.5 VCC
0.7 VCC
1.50
2.10
3V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.4
UNIT
V
V
1.1
VIN = VSS or VCC
5
V
pF
Table 5-8. Inputs – Ports P1 and P2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger pulse
duration to set interrupt flag
(1)
VCC
MIN
3V
20
MAX
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Table 5-9. Leakage Current - General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Py.x)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
See
VCC
(1) (2)
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input.
Table 5-10. Outputs – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VOH
High-level output voltage
I(OHmax) = –6 mA
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
(1)
VCC
MIN
MAX
UNIT
3.0 V
VCC – 0.60
VCC
V
3.0 V
VSS
VSS + 0.60
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Table 5-11. Output Frequency - General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPy.x
Port output frequency (with load)
fPort_CLK Clock output frequency
(1)
(2)
18
TEST CONDITIONS
Py.x, CL = 20 pF, RL = 3.2 kΩ
Py.x, CL = 20 pF (2)
(1) (2)
VCC
TYP
UNIT
3V
16.384
MHz
3V
16.384
MHz
A resistive divider with two times 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% of VCC at the specified toggle frequency.
Specifications
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5.6.4.1
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Typical Characteristics - Outputs
One output loaded at a time.
22
20
12
IOL - Low Output Current (mA)
IOL - Low-Level Output Current (mA)
14
10
8
6
4
2
0
TA = 25°C
TA = 105°C
16
14
12
10
8
6
4
2
TA = 25°C
TA = 105°C
0
-2
-2
0
0.25
0.5 0.75
1
1.25 1.5 1.75
VOL - Low-Level Output Voltage (V)
VCC = 2.2 V
2
2.25
0
0.3
0.6
D004
Measured at P1.3
0.9 1.2 1.5 1.8 2.1 2.4
VOL - Low Output Voltage (V)
VCC = 3 V
Figure 5-4. Typical Low-Level Output Current vs Low-Level
Output Voltage
2.7
3
D003
Measured at P1.3
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
TA = 25°C
TA = 105°C
-2
IOH - High-Level Output Current (mA)
IOH - High-Level Output Current (mA)
18
-4
-6
-8
-10
-12
TA = 25°C
TA = 105°C
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
0
0.2
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOH - High-Level Output Voltage (V)
VCC = 2.2 V
2
2.2
D006
Measured at P1.3
Figure 5-6. Typical High-Level Output Current vs High-Level
Output Voltage
0
0.3
0.6 0.9 1.2 1.5 1.8 2.1 2.4
VOH - High-Level Output Voltage (V)
VCC = 3 V
2.7
D005
Measured at P1.3
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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Power Management Module
Table 5-12. PMM, High-Side Brown-Out Reset (BORH)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(VCC_BOR_IT–)
BORH on voltage, VCC falling level
| dVCC/dt | < 3 V/s
1.08
V
V(VCC_BOR_IT+)
BORH off voltage, VCC rising level
| dVCC/dt | < 3 V/s
1.18
V
V(VCC_BOR_hys)
BORH hysteresis
tPOWERUP
(1)
(1)
100
Cold power-up time
mV
0.75
ms
MAX
UNIT
This is the time duration between application of VCC and execution of reset vector by CPU.
Table 5-13. PMM, Low-Side SVS (SVSL)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(SVSL)
MIN
SVSL trip voltage on VCORE
1.70
V(SVSL_hys) SVSL hysteresis
I(SVSL)
TYP
SVSL current consumption
V
14
mV
3
µA
Table 5-14. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCORE
MIN
Core voltage
TYP
MAX
1.83
UNIT
V
Table 5-15. PMM, Voltage Monitor (VMON)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VMONtrip_level
MIN
TYP
VMONLVLx = 111b
1.17
VCC trip level - 1
VMONLVLx = 001b
2.32
VCC trip level - 2
VMONLVLx = 010b
2.62
VCC trip level - 3
VMONLVLx = 011b
2.82
IVMON
VMON current consumption
tVMON
VMON settling time
20
TEST CONDITIONS
VMONIN trip level
Specifications
MAX
UNIT
V
6
µA
0.5
µs
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Reference Module
Table 5-16. Voltage Reference (REF)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
Supply voltage range
VBG
Bandgap output voltage calibrated
VCC = 3 V
PSRR_DC
Power supply rejection ratio (dc)
VCC = 2.2 V to 3.6 V
PSRR_AC
Power supply rejection ratio (ac)
VCC = 2.2 V to 3.6 V, f = 1 kHz,
ΔVpp = 100 mV
dVBG/dT
Bandgap reference temperature coefficient
VCC = 3 V
MIN
TYP
2.2
1.146
1.158
MAX
UNIT
3.6
V
1.17
V
50
µV/V
0.35
mV/V
10
50 ppm/°C
Table 5-17. Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Vsensor
Temperature sensor output voltage
Isensor
Temperature sensor quiescent current consumption
TCsensor
Temperature coefficient of sensor
MIN
TYP
MAX
VCC = 3 V, TA = 30ºC
TEST CONDITIONS
610
650
690
VCC = 3 V, TA = 105ºC
765
805
845
1.96
2.07
3
mV
uA
2.17
Specifications
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UNIT
mV/°C
21
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SD24
Table 5-18. SD24, Power Supply and Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage range
ISD24
VCC
MIN
AVSS = DVSS = 0 V
Analog plus digital supply current per
converter (reference current not included)
SD24OSRx = 256
TYP
MAX
2.2
GAIN: 1, 2, 4, 8, 16
3V
GAIN: 1, 16
3V
3.6
190
250
UNIT
V
µA
Table 5-19. SD24, Internal Voltage Reference (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSD24REF
SD24 internal reference voltage
CVREF
Recommended capacitor at VREF
tSD24REF_settle
SD24 reference buffer settling time
(1)
SD24REFS = 1
VCC
MIN
TYP
MAX
3V
1.146
1.158
1.17
SD24REFS = 0 → 1, CVREF = 100 nF
UNIT
V
100
nF
200
µs
When SD24 operates with internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Only the recommended
capacitor value, CVREF must be connected at the VREF pin to AVSS.
Table 5-20. SD24, External Voltage Reference
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
TYP
MAX
VREF(I)
Input voltage range
PARAMETER
SD24REFS = 0
TEST CONDITIONS
3V
1.0
1.2
1.5
UNIT
V
IREF(I)
Input current
SD24REFS = 0
3V
50
nA
Table 5-21. SD24, Input Range (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VID,FSR
VID
Differential full-scale input voltage
range
Differential input voltage range for
specified performance (2)
TEST CONDITIONS
VCC
VID = VI,A+ - VI,A-
SD24REFS = 1
MIN
TYP
-VREF/
GAIN
MAX
+VREF/
GAIN
SD24GAINx = 1
±928
SD24GAINx = 2
±464
SD24GAINx = 4
±232
SD24GAINx = 8
±116
SD24GAINx = 16
±58
UNIT
V
mV
ZI
Input impedance
(pin A+ or A- to AVSS) (3)
SD24GAINx = 1, 16
3V
ZID
Differential input impedance (pin A+
to pin A-) (3)
SD24GAINx = 1, 16
3V
VI
Absolute input voltage range
AVSS - 1
VCC
V
VIC
Common-mode input voltage range
AVSS - 1
VCC
V
(1)
(2)
(3)
22
300
200
kΩ
400
kΩ
All parameters pertain to each SD24 channel.
The full-scale range is defined by VFSR+ = +VREF/GAIN and VFSR- = -VREF/GAIN; FSR = VFSR+ - VFSR- = 2xVREF/GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VREF is
sourced internally, the given VID ranges apply.
Applicable for SD24 modulator OFF as well as ON conditions.
Specifications
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Table 5-22. SD24, Performance - Internal Reference (SD24REFS = 1, SD24OSRx = 256)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SD24GAINx = 1
MIN
TYP
84
89
SD24GAINx = 2
SINAD
Signal-to-noise +
distortion ratio
SD24GAINx = 4
Total harmonic
distortion
3V
87
SD24GAINx = 8
83
SD24GAINx = 16
77
SD24GAINx = 8
3V
95
SD24GAINx = 8
100
fIN = 50 Hz (1)
3V
95
SD24GAINx = 16
Integral non-linearity,
SD24GAINx: 1, 8, 16
end-point fit
INL
G
Nominal gain
3V
1
2
3V
8
SD24GAINx = 16
16
SD24GAINx: 1, 8, 16
3V
ΔEG/ ΔT
SD24GAINx: 1, 8, 16
3V
EOS
Offset error
ΔEOS/ΔT
Offset error
temperature
coefficient
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz
Crosstalk between
converters
2%
50 ppm/°C
4
2
±5
3V
±3
ppm
±10 FSR/°C
-55
dB
-60
3V
-90
SD24GAINx: 8, VCC = 3 V ± 50 mV × sin(2π × fVCC × t),
fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
3V
-95
SD24GAINx: 16, VCC = 3 V ± 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
3V
-95
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter
under test: SD24GAINx = 8
mV
±25
3V
SD24GAINx: 1, VCC = 3 V ± 50 mV × sin(2π × fVCC × t),
fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter
under test: SD24GAINx = 16
(1)
-2%
3V
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter
under test: SD24GAINx = 1
XT
4
SD24GAINx = 8
Gain error
temperature
coefficient
AC power supply
rejection ratio
0.003 % FSR
SD24GAINx = 2
Gain error
AC PSRR
-0.003
SD24GAINx = 1
SD24GAINx = 4
dB
90
EG
Common-mode
CMRR,50Hz rejection ratio at
50 Hz
dB
90
SD24GAINx = 1
Spurious-free
dynamic range
dB
100
fIN = 50 Hz (1)
SD24GAINx = 16
SFDR
UNIT
89
fIN = 50 Hz (1)
SD24GAINx = 1
THD
MAX
dB
-120
3V
-110
dB
-110
The following voltages were applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) - VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).
Specifications
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Table 5-23. SD24, Performance - External Reference (SD24REFS = 0, SD24OSRx = 256)
external reference voltage is 1.2 V., over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
SD24GAINx = 1
SD24GAINx = 4
3V
88
SD24GAINx = 8
83
SD24GAINx = 16
77
SD24GAINx = 8
3V
95
SD24GAINx = 8
100
fIN = 50 Hz (2)
3V
95
SD24GAINx = 16
Integral non-linearity,
end-point fit
INL
G
Nominal gain
SD24GAINx: 1, 8, 16
3V
1
2
3V
8
SD24GAINx = 16
16
SD24GAINx: 1, 8, 16
3V
ΔEG/ ΔT
SD24GAINx: 1, 8, 16
3V
EOS
Offset error
ΔEOS/ΔT
Offset error
temperature coefficient
(1)
(2)
24
4
SD24GAINx = 8
Gain error temperature
coefficient
AC power supply
rejection ratio
0.003 % FSR
SD24GAINx = 2
Gain error
AC PSRR
-0.003
SD24GAINx = 1
SD24GAINx = 4
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz
dB
90
EG
Common-mode
CMRR,50Hz
rejection ratio at 50 Hz
dB
90
SD24GAINx = 1
Spurious-free dynamic
range
dB
100
fIN = 50 Hz (2)
SD24GAINx = 16
SFDR
UNIT
90
fIN = 50 Hz (1)
SD24GAINx = 1
Total harmonic
distortion
THD
MAX
91
SD24GAINx = 2
Signal-to-noise +
distortion ratio
SINAD
TYP
-1%
+1%
10 ppm/°C
4
3V
3V
2
±5
±3
mV
±25
ppm
±10 FSR/°C
-55
3V
dB
-60
SD24GAINx: 1, VCC = 3V ± 50mV × sin(2π × fVCC × t),
fVCC = 50 Hz, Inputs grounded (no analog signal
applied)
3V
-90
SD24GAINx: 8, VCC = 3V ± 50mV × sin(2π × fVCC × t),
fVCC = 50 Hz, Inputs grounded (no analog signal
applied)
3V
-95
SD24GAINx: 16, VCC = 3 V ± 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz, Inputs grounded (no analog signal
applied)
3V
-95
dB
The following voltages were applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) - VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).
The following voltages were applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) - VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).
Specifications
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SD24, Performance - External Reference (SD24REFS = 0, SD24OSRx = 256) (continued)
external reference voltage is 1.2 V., over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAINx = 1
Crosstalk between
converters
XT
UNIT
-120
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAINx = 8
3V
-110
Crosstalk source: SD24GAINx = 1, Sine-wave with
maximum possible VPP, fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAINx = 16
90
MAX
dB
-110
90
87
85
84
80
78
SINAD (dB)
SINAD (dB)
81
75
72
69
75
70
65
66
63
60
60
57
25
55
50
75
fSD24 = 1.024 MHz
100
125
150 175
OSR
200
SD24REFS = 1
Figure 5-8. SINAD vs OSR
225
250
275
0
0.2
0.4
D001
SD24GAINx = 1
fSD24 = 1.024 MHz
OSR = 256
0.6
VPP (V)
0.8
1
1.2
D002
SD24REFS = 1
SD24GAINx = 1
Figure 5-9. SINAD vs VPP
Specifications
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eUSCI
Table 5-24. eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
4
MHz
UNIT
Table 5-25. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UART receive deglitch time (1)
tt
VCC
MIN
TYP
MAX
UCGLITx = 0
8
15
20
UCGLITx = 1
30
50
60
50
70
100
70
100
150
2.2 V, 3 V
UCGLITx = 2
UCGLITx = 3
(1)
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
Table 5-26. eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
feUSCI
CONDITIONS
MIN
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
eUSCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
Table 5-27. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
VCC
MIN
tSTE,LEAD
STE lead time, STE active to clock
PARAMETER
UCSTEM = 1, UCMODEx = 01 or 10
TEST CONDITIONS
2.2 V, 3 V
150
ns
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
2.2 V, 3 V
200
ns
tSTE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,DIS
STE disable time, STE inactive to SIMO
high impedance
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid, CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
26
UCSTEM = 0, UCMODEx = 01 or 10
MAX
UNIT
2.2 V
40
ns
3V
30
ns
2.2 V
40
ns
3V
30
ns
2.2 V
50
ns
3V
30
ns
2.2 V, 3 V
0
ns
2.2 V
7
ns
3V
5
ns
2.2 V, 3 V
0
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-10 and Figure 5-11.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-10 and Figure 5-11.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-11. SPI Master Mode, CKPH = 1
Specifications
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Table 5-28. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
tSTE,LEAD
STE lead time, STE active to clock
2.2 V, 3 V
3
tSTE,LAG
STE lag time, Last clock to STE inactive
2.2 V, 3 V
0
MAX
UNIT
ns
ns
2.2 V
35
ns
3V
25
ns
35
ns
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
2.2 V, 3 V
tSU,SI
SIMO input data setup time
2.2 V, 3 V
1
ns
tHD,SI
SIMO input data hold time
2.2 V, 3 V
5
ns
tVALID,SO
SOMI output data valid time (2)
tHD,SO
(1)
(2)
(3)
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data hold time (3)
CL = 20 pF
2.2 V
35
ns
3V
25
ns
2.2 V
35
ns
3V
25
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-12 and Figure 5-13.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-12 and Figure 5-13.
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 0
28
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-29. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-14)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
MIN
2.2 V, 3 V
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
fSCL = 100 kHz
tSU,DAT
Data setup time
tSU,STO
Setup time for STOP
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
VCC
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V, 3 V
2.2 V, 3 V
fSYSTEM
MHz
400
kHz
0
5.5
µs
1.5
5.5
µs
1.5
0.4
µs
5.5
µs
1.5
5.5
µs
1.5
75
110
160
ns
UCGLITx = 1
35
50
80
ns
15
25
40
ns
10
15
20
UCGLITx = 2
2.2 V, 3 V
UCCLTOx = 1
Clock low timeout
UNIT
UCGLITx = 0
UCGLITx = 3
tTIMEOUT
MAX
UCCLTOx = 2
2.2 V, 3 V
UCCLTOx = 3
tSU,STA
tHD,STA
tHD,STA
ns
33
ms
37
ms
41
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-14. I2C Mode Timing
30
Specifications
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5.6.9
SLAS887 – AUGUST 2014
Timer_A
Table 5-30. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK
External: TACLK
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
VCC
3.0 V
3.0 V
MIN
TYP
MAX
UNIT
16.384
MHz
20
ns
5.6.10 Flash
Table 5-31. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE) Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
8
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
13
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
8
Program and erase endurance
20000
tRetention
Data retention duration
tWord
Word or byte program time
(2)
25
Block program time for first byte or word
(2)
20
Block program time for each additional
byte or word
(2)
11
Block program end-sequence wait time
(2)
6
tMass Erase
Mass erase time
(2)
10593
tSeg
Segment erase time
(2)
9628
tBlock,
0
tBlock, 1-63
tBlock,
(1)
(2)
End
Erase
TJ = 25°C
ms
cycles
100
years
tFTG
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word-write mode, individual byte-write mode, and block-write mode.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
5.6.11 Emulation and Debug
Table 5-32. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
3.0 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
3.0 V
0.025
15
μs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
3.0 V
1
μs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
3.0 V
100
μs
10
MHz
80
kΩ
(2)
fTCK
TCK input frequency, 4-wire JTAG
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
MIN
TYP
15
3.0 V
0
3.0 V
45
60
Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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6 Detailed Description
6.1
Overview
The MSP430i204x, MSP430i203x, MSP430i202x devices consist of a powerful 16-bit RISC CPU, a DCObased clock system that generates system clocks, a power management module (PMM) with built-in
voltage reference and voltage monitor, two to four 24-bit sigma-delta analog-to-digital converters (ADCs),
a temperature sensor, a 16-bit hardware multiplier, two 16-bit timers, one eUSCI-A module and one
eUSCI-B module, a watchdog timer (WDT), and up to 16 I/O pins.
32
Detailed Description
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6.2
SLAS887 – AUGUST 2014
Functional Block Diagrams
Figure 6-1 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the RHB
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
8
ACLK
Clock
System
SMCLK
Flash
RAM
TA0
TA1
Port P1
Port P2
32KB
16KB
2KB
1KB
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
8 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
Power
Management
JTAG
Interface
LDO
REF
VMON
Brownout
Spy-Bi
Wire
SD24
4 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-1. Functional Block Diagram - RHB Package - MSP430i2041, MSP430i2040
Figure 6-2 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the PW
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
4
ACLK
Clock
System
SMCLK
Flash
RAM
TA0
TA1
Port P1
Port P2
32KB
16KB
2KB
1KB
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
4 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
JTAG
Interface
Power
Management
Spy-Bi
Wire
LDO
REF
VMON
Brownout
SD24
4 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-2. Functional Block Diagram - PW Package - MSP430i2041, MSP430i2040
Detailed Description
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Figure 6-3 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the RHB
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
8
TA1
Port P1
Port P2
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
8 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
ACLK
Clock
System
Flash
32KB
16KB
SMCLK
RAM
2KB
1KB
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
TA0
Timer_A
3 CC
Registers
Emulation
2BP
Power
Management
JTAG
Interface
LDO
REF
VMON
Brownout
Spy-Bi
Wire
SD24
3 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-3. Functional Block Diagram - RHB Package - MSP430i2031, MSP430i2030
Figure 6-4 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the PW
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
4
TA1
Port P1
Port P2
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
4 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
ACLK
Clock
System
Flash
32KB
16KB
SMCLK
RAM
2KB
1KB
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
TA0
Timer_A
3 CC
Registers
Emulation
2BP
JTAG
Interface
Spy-Bi
Wire
Power
Management
LDO
REF
VMON
Brownout
SD24
3 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-4. Functional Block Diagram - PW Package - MSP430i2031, MSP430i2030
34
Detailed Description
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Figure 6-5 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the RHB
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
8
TA1
Port P1
Port P2
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
8 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
ACLK
Clock
System
Flash
32KB
16KB
SMCLK
RAM
2KB
1KB
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
TA0
Timer_A
3 CC
Registers
Emulation
2BP
Power
Management
JTAG
Interface
LDO
REF
VMON
Brownout
Spy-Bi
Wire
SD24
2 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-5. Functional Block Diagram - RHB Package - MSP430i2021, MSP430i2020
Figure 6-6 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the PW
package.
VCC
ROSC
DVSS
AVSS VCORE RST/NMI
P1.x
8
P2.x
4
TA1
Port P1
Port P2
Timer_A
3 CC
Registers
8 I/O
Interrupt
capability
4 I/O
Interrupt
capability
eUSCI_A0
eUSCI_B0
UART,
IrDA, SPI
SPI, I C
ACLK
Clock
System
Flash
32KB
16KB
SMCLK
RAM
2KB
1KB
MCLK
16.384MHz
CPU
MAB
incl. 16
Registers
MDB
TA0
Timer_A
3 CC
Registers
Emulation
2BP
JTAG
Interface
Power
Management
Spy-Bi
Wire
LDO
REF
VMON
Brownout
SD24
2 SigmaDelta A/D
Converter
Watchdog
WDT
15/16-bit
Hardware
Multiplier
(16x16)
MPY,
MPYS,
MAC,
MACS
2
Figure 6-6. Functional Block Diagram - PW Package - MSP430i2021, MSP430i2020
Detailed Description
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6.3
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CPU
The MSP430i CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
36
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.4
SLAS887 – AUGUST 2014
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each
instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction
formats; Table 6-2 shows the address modes.
Table 6-1. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
Relative jump, unconditional/conditional
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
ADDRESS MODE
(1)
(2)
S
(1)
D
(2)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
OPERATION
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV &MEM,&TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source
D = destination
Detailed Description
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6.5
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Operating Modes
MSP430i204x, MSP430i203x, MSP430i202x devices have one active mode and four software-selectable
low-power modes. An interrupt event can wake up the device from the low-power modes LPM0 to LPM4,
service the request, and restore back to the low-power mode on return from the interrupt program.
The following five operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0/1 (LPM0 = LPM1)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK is disabled
– ACLK and SMCLK remain active
• Low-power mode 2/3 (LPM2 = LPM3)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK and SMCLK are disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– Internal regulator remains enabled
– DCO is disabled
– MCLK, SMCLK, and ACLK are disabled
• Low-power mode 4.5 (LPM4.5)
– Internal regulator is disabled
– No RAM retention
– I/O pad state retention
– Wakeup from RST/NMI, Ports Pins P2.1, P2.2
38
Detailed Description
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6.6
SLAS887 – AUGUST 2014
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range
0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed),
the CPU goes into LPM4 immediately after power up.
Table 6-3. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
Power up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
BORIFG
RSTIFG
WDTIFG
KEYV
PRIORITY
Reset
0FFFEh
15, highest
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
14
(2)
NMIIFG
OFIFG
ACCVIFG (2)
Timer TA1
TA1CCR0 CCIFG
(4)
Maskable
0FFFAh
13
Timer TA1
TA1CCR1 CCIFG,
TA1CCR2 CCIFG,
TA1CTL TAIFG (2) (4)
Maskable
0FFF8h
12
(3)
Voltage Monitor
VMONIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
eUSCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG
Maskable
0FFF2h
9
eUSCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG
Maskable
0FFF0h
8
SD24
SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG (2) (4)
Maskable
0FFEEh
7
Timer TA0
TA0CCR0 CCIFG
(4)
Maskable
0FFECh
6
Timer TA0
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG (2) (4)
Maskable
0FFEAh
5
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O Port P2
(2)
(3)
(4)
WORD ADDRESS
NMI
Oscillator fault
Flash memory access violation
I/O Port P1
(1)
SYSTEM
INTERRUPT
P1IFG.0 to P1IFG.7
P2IFG.0 to P2IFG.7
(2) (4)
(2) (4)
Maskable
0FFE2h
1
0FFE0h
0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
Detailed Description
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Special Function Registers
Some interrupt enable and interrupt flag bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
rw-[0], [1]
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
Bit can be read and written. It is Reset or Set by BOR.
SFR bit is not present in device.
Table 6-4. Interrupt Enable 1 (Address = 00h)
7
WDTIE
OFIE
NMIIE
ACCVIE
6
5
ACCVIE
rw-0
4
NMIIE
rw-0
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer
mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Table 6-5. Interrupt Flag Register 1 (Address = 02h)
7
WDTIFG
OFIFG
BORIFG
RSTIFG
NMIIFG
6.8
6
5
4
NMIIFG
rw-0
3
RSTIFG
rw-[0]
2
BORIFG
rw-[1]
1
OFIFG
rw-0
0
WDTIFG
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault. This flag can be cleared by software when the oscillator runs free of fault.
Brown out reset flag. This bit is set after VCC power up and can be cleared by software.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Set by the RST/NMI pin in NMI configuration.
Flash Memory
The flash memory can be programmed through the Spy-Bi-Wire or JTAG port, or in-system by the CPU.
The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash
memory:
• Flash memory has n segments of main memory and one segment of information memory.
• Segment size is 1KB for both main memory and information memory.
• Segments 0 to n in main memory can be erased in one step, or each segment may be individually
erased.
• Information memory segment can be erased separately or as a group with main memory segments 0
to n.
• Information memory segment contains calibration data. After reset, information memory segment is
protected against programming and erasing. It can be unlocked but care should be taken not to erase
this segment if the device-specific calibration data is required.
40
Detailed Description
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6.9
6.9.1
SLAS887 – AUGUST 2014
JTAG Operation
JTAG Standard Interface
The MSP430i family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430i development tools and device programmers. The JTAG pin requirements are shown in Table 66. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide (SLAU278).
Table 6-6. JTAG Pin Requirements and Functions
6.9.2
DEVICE SIGNAL
Direction
FUNCTION
P1.0/UCA0STE/MCLK/TCK
IN
JTAG clock input
P1.1/UCA0CLK/SMCLK/TMS
IN
JTAG state control
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
IN
JTAG data input/TCLK input
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
DVSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430i family supports the two wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430i development tools and device programmers.
The Spy-Bi-Wire interface pin requirements are shown in Table 6-7. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
Direction
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
DVSS
Ground supply
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JTAG Disable Register
The SYSJTAGDIS register can disable the JTAG port to provide code protection and device security.
JTAG is disabled when software writes the value 0xA5A5 to this register within 64 MCLK clock cycles after
a BOR or POR reset; otherwise, the JTAG port is enabled. Any writes to this register after the first 64
MCLK clock cycles are ignored. Reads from this register at any time return the JTAG enable or disable
status. The value 0xA5A5 indicates that JTAG is disabled, and 0x9696 indicates that JTAG is enabled.
The SYSJTAGDIS register is mapped to address 01FEh.
NOTE
Application programming the device to any of the low power modes within first 64 MCLK
clock cycles after a BOR or POR reset will lock the device for any JTAG/SBW access.
Table 6-8. SYSJTAGDIS Register
15
14
13
12
11
10
9
8
rw-[0]
rw-[1]
rw-[0]
rw-[1]
3
2
1
0
rw-[0]
rw-[1]
rw-[0]
rw-[1]
JTAGKEY
rw-[1]
rw-[0]
rw-[1]
rw-[0]
7
6
5
4
JTAGKEY
rw-[1]
JTAGKEY
42
rw-[0]
rw-[1]
rw-[0]
0xA5A5 indicates JTAG is disabled and 0x9696 indicates JTAG is enabled.
Detailed Description
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6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430i Family User's Guide
(SLAU335).
6.10.1 Clock System
The clock system consists of a fixed 16.384-MHz frequency internal DCO. The DCO can operate in
internal resistor mode or external resistor mode. The DCO clock accuracy is higher when operating in
external resistor mode especially upon variation in operating temperature. This feature can be useful in
applications like utility metering in which accurate clock is necessary under varying operating temperature.
When external resistor mode is selected by application, the resistor of recommended value must be
connected to ROSC pin of the device. Refer to Table 5-2 for the recommended value of resistor at ROSC
pin. It is recommended to connect the ROSC pin to AVSS while operating DCO in internal resistor mode.
When a resistor fault is detected in the external resistor mode, the DCO automatically switches to the
internal resistor mode as a fail-safe mechanism to keep the system clocks active.
The DCO can be completely bypassed and the system clocks can be sourced by external digital clock.
The clock system generates MCLK, SMCLK, and ACLK. MCLK is used by the CPU, while SMCLK and
ACLK are used by the peripheral modules. There are programmable clock dividers for MCLK and SMCLK.
ACLK runs at a fixed 32-kHz frequency. The clock system supports active mode and four low-power
modes.
6.10.2 Power Management Module (PMM)
The power management module consists of voltage regulator that generates 1.8-V regulated core voltage.
There is a brownout reset (BOR) circuit on the high-voltage domain, and a supply voltage supervisor
(SVS) module on the low-voltage domain. The BOR and SVS provide the proper internal reset signal to
the device during power-on and power-off.
A built-in voltage reference is used by sub-modules of the PMM and by the analog modules on the device.
A temperature sensor is also available within the built-in voltage reference.
The voltage monitor (VMON) on the high-voltage domain can monitor external voltage on the VMONIN pin
against the internal reference voltage or by comparing the on-chip VCC to one of three programmable
threshold voltages. During the LPM4.5 mode, the reference, voltage regulator, temperature sensor, and
voltage monitor are shut off, and only the high side brown-out circuit is active.
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6.10.3 Digital I/O
There are two 8-bit I/O ports (P1 and P2) implemented on the MSP430i204x, MSP430i203x,
MSP430i202x devices. On 32-pin RHB devices, ports P1 and P2 are complete, and 16 I/Os are available.
On 28-pin PW devices, port P2 is reduced to 4 bits, and 12 I/Os are available. On 28-pin PW devices, the
unavailable pins P2.4 to P2.7 must be programmed to port function, output direction and be driven with
value 0.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and P2
• LPM4.5 wake-up capability for Port pins P2.1 and P2.2
• Read and write access to port-control registers is supported by all instructions.
6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be disabled or configured as an interval timer and can generate
interrupts at selected time intervals.
6.10.5 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-9. TA0 Signal Connections
INPUT PORT PIN
P1.3
MODULE INPUT
SIGNAL
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.3
TA0CLK
INCLK
P1.4
TA0.0
CCI0A
P2.5
TA0.0
CCI0B
DVSS
GND
P1.5
P1.6
44
DEVICE INPUT
SIGNAL
VCC
VCC
TA0.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
VCC
VCC
TA0.2
CCI2A
TA1 CCR2 output
(internal)
CCI2B
DVSS
GND
VCC
VCC
Detailed Description
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PORT
PIN
NA
P1.4
CCR0
TA0
TA0.0
P2.5
P1.5
CCR1
TA1
TA0.1
P2.6
P1.6
TA0.2
CCR2
TA2
P2.7
TA1 CCI2B input
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6.10.6 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. TA1 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P1.7
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P1.7
TA1CLK
INCLK
P2.0
TA1.0
CCI0A
P2.4
TA1.0
CCI0B
DVSS
GND
VCC
VCC
P2.1
P2.2
TA1.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
VCC
VCC
TA1.2
CCI2A
TA0 CCR2 output
(internal)
CCI2B
DVSS
GND
VCC
VCC
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PORT
PIN
NA
P2.0
CCR0
TA0
TA1.0
P2.4
P2.1
CCR1
TA1
TA1.1
P2.2
TA1.2
CCR2
TA2
TA0 CCI2B input
6.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
One eUSCI_A and one eUSCI_B module are implemented on MSP430i204x, MSP430i203x,
MSP430i202x devices.
6.10.8 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16bit, 16x8-bit, 8x16-bit, and 8x8-bit operations. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply and accumulate operations. The result of an
operation can be accessed immediately after the operands have been loaded into the peripheral registers.
No additional clock cycles are required.
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6.10.9 SD24
There are up to four independent 24-bit sigma-delta ADCs. Each converter is designed with a fully
differential analog input pair and programmable gain amplifier input stage. Also the converters are based
on second-order over-sampling sigma-delta modulators and digital decimation filters. The decimation
filters are comb-type filters with selectable oversampling ratios of up to 256.
The SD24 converters can operate with internal reference (SD24REFS = 1) or with external reference
(SD24REFS = 0). When SD24 operates with internal reference the VREF pin must not be loaded
externally. Only the recommended capacitor value, CVREF must be connected at VREF pin to AVSS (see
Table 5-19).
46
Detailed Description
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6.10.10 Input/Output Schematics
6.10.10.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
JTAG enable
From JTAG
From JTAG
PyDIR.x
00
From module 1
01
10
1
Direction
0: Input
1: Output
Pad Logic
0
11
PyOUT.x
00
From module 1
01
1
From module 2
10
0
DVSS
11
Py.x/Mod1/Mod2/JTAG
PySEL1.x
PySEL0.x
PyIN.x
EN
To modules
and JTAG
D
NOTE: Functional representation only.
Figure 6-7. Py.x/Mod1/Mod2/JTAG Pin Schematic
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Table 6-11. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
P1.0/UCA0STE/MCLK/TCK
x
0
FUNCTION
P1.0 (I/O) (2)
UCA0STE
1
P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI
(1)
(2)
(3)
(4)
48
JTAG Enable
0
0
X (3)
0
1
0
1
0
0
1
1
0
X
X
X
1
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
X
1
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
1
N/A
0
DVSS
1
P1.1 (I/O) (2)
X
(3)
N/A
0
SMCLK
1
N/A
0
DVSS
1
P1.2 (I/O) (2)
UCA0RXD/UCA0SOMI
3
P1SEL0.x
0
0
TMS (4)
2
P1SEL1.x
MCLK
UCA0CLK
P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK
P1DIR.x
I: 0; O: 1
N/A
TCK (4)
P1.1/UCA0CLK/SMCLK/TMS
CONTROL BITS OR SIGNALS (1)
X
(3)
N/A
0
ACLK
1
N/A
0
DVSS
1
TDI/TCLK (4)
X
X
X
1
P1.3 (I/O) (2)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
UCA0TXD/UCA0SIMO
X
(3)
TA0CLK
0
DVSS
1
N/A
0
DVSS
1
TDO/TDI (4)
X
X = Don't care
Default condition.
Direction controlled by eUSCI_A0 module.
The pin direction is controlled by the JTAG module. The JTAG mode selection is made via the Spy-Bi-Wire four wire entry sequence.
Neither P1SEL0.x and P1SEL1.x nor P1DIR.x have an effect in these cases.
Detailed Description
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6.10.10.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
PyDIR.x
00
From module 1
01
Direction
0: Input
1: Output
10
11
PyOUT.x
00
From module 1
01
From module 2
10
DVSS
11
Py.x/Mod1/Mod2
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To module
NOTE: Functional representation only.
Figure 6-8. Py.x/Mod1/Mod2 Pin Schematic
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Table 6-12. Port P1 (P1.4 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.4/UCB0STE/TA0.0
P1.5/UCB0CLK/TA0.1
P1.6/UCB0SCL/UCB0SOMI/
TA0.2
P1.7/UCB0SDA/UCB0SIMO/
TA1CLK
(1)
(2)
50
x
4
5
6
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.4 (I/O)
I: 0; O: 1
0
0
UCB0STE
X (2)
0
1
TA0.CCI0A
0
TA0.0
1
1
0
N/A
0
DVSS
1
1
1
P1.5 (I/O)
I: 0; O: 1
0
0
UCB0CLK
X (2)
0
1
TA0.CCI1A
0
TA0.1
1
1
0
N/A
0
DVSS
1
1
1
I: 0; O: 1
0
0
X (2)
0
1
1
0
1
1
I: 0; O: 1
0
0
X (2)
0
1
1
0
1
1
P1.6 (I/O)
UCB0SCL/UCB0SOMI
7
CONTROL BITS OR SIGNALS (1)
TA0.CCI2A
0
TA0.2
1
N/A
0
DVSS
1
P1.7 (I/O)
UCB0SDA/UCB0SIMO
TA1CLK
0
DVSS
1
N/A
0
DVSS
1
X = Don't care
Direction controlled by eUSCI_B0 module.
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6.10.10.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
PyDIR.x
Direction
0: Input
1: Output
00
01
10
11
PyOUT.x
00
From module
01
DVSS
10
DVSS
11
Py.x/Mod1/Mod2
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To module
NOTE: Functional representation only.
Figure 6-9. Py.x/Mod1/Mod2 Pin Schematic
Table 6-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1.0/CLKIN
P2.1/TA1.1
P2.2/TA1.2
x
0
1
2
FUNCTION
P2.0 (I/O)
CONTROL BITS OR SIGNALS
P2DIR.x
P2SEL1.x
P2SEL0.x
I: 0; O: 1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TA1.CCI0A
0
TA1.0
1
CLKIN (DCO bypass clock)
0
DVSS
1
N/A
0
DVSS
1
P2.1 (I/O)
I: 0; O: 1
TA1.CCI1A
0
TA1.1
1
N/A
0
DVSS
1
N/A
0
DVSS
1
P2.2 (I/O)
I: 0; O: 1
TA1.CCI2A
0
TA1.2
1
N/A
0
DVSS
1
N/A
0
DVSS
1
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Table 6-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions (continued)
PIN NAME (P2.x)
P2.4/TA1.0
(1)
4
P2.5/TA0.0 (1)
5
P2.6/TA0.1 (2)
6
P2.7/TA0.2 (2)
(1)
(2)
52
x
7
FUNCTION
P2.4 (I/O)
CONTROL BITS OR SIGNALS
P2DIR.x
P2SEL1.x
P2SEL0.x
I: 0; O: 1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TA1.CCI0B
0
TA1.0
1
N/A
0
DVSS
1
N/A
0
DVSS
1
P2.5 (I/O)
I: 0; O: 1
TA0.CCI0B
0
TA0.0
1
N/A
0
DVSS
1
N/A
0
DVSS
1
P2.6 (I/O)
I: 0; O: 1
N/A
0
TA0.1
1
N/A
0
DVSS
1
N/A
0
DVSS
1
P2.7 (I/O)
I: 0; O: 1
N/A
0
TA0.2
1
N/A
0
DVSS
1
N/A
0
DVSS
1
Available only on 32-Pin RHB devices.
Available only on 32-Pin RHB devices.
Detailed Description
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6.10.10.4 Port P2, P2.3, Input/Output With Schmitt Trigger
Pad Logic
To VMON
From VMON
PyDIR.x
00
01
Direction
0: Input
1: Output
10
11
PyOUT.x
00
DVSS
01
DVSS
10
DVSS
11
Py.x/VMONIN
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
D
No connect
NOTE: Functional representation only.
Figure 6-10. Py.x/VMONIN Pin Schematic
Table 6-14. Port P2 (P2.3) Pin Functions
PIN NAME (P2.x)
P2.3/VMONIN
(1)
(2)
x
3
FUNCTION
P2.3 (I/O)
CONTROL BITS OR SIGNALS (1)
P2DIR.x
P2SEL1.x
P2SEL0.x
I: 0; O: 1
0
0
0
1
1
0
1
1
N/A
0
DVSS
1
N/A
0
DVSS
1
VMONIN (2)
X
X = Don't care
Setting P2SEL1.3 and P2SEL0.3 disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying voltage at VMONIN pin. To enable the VMONIN function, VMONLVLx bits must be set to 3'b111 in the VMONCTL register.
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6.10.11 Device Descriptor
Table 6-15 lists the contents of the tag-length-value (TLV) device descriptor structure for the
MSP430i204x, MSP430i203x, MSP430i202x devices.
Table 6-15. MSP430i204x, MSP430i203x, MSP430i202x TLV
Checksum
Die Record
REF Calibration
DCO Calibration
SD24 Calibration
Empty
54
Detailed Description
Description
Address
Size
(Bytes)
Value
TLV checksum
013C0h
2
per unit
Die Record Tag
013C2h
1
01h
Die Record Length
013C3h
1
0Ah
Lot/Wafer ID
013C4h
4
per unit
Die X position
013C8h
2
per unit
Die Y position
013CAh
2
per unit
Test results
013CCh
2
per unit
REF Calibration Tag
013CEh
1
02h
REF Calibration Length
013CFh
1
02h
Calibrate REF – for REFCAL1 register
013D0h
1
per unit
Calibrate REF – for REFCAL0 register
013D1h
1
per unit
DCO Calibration Tag
013D2h
1
03h
DCO Calibration Length
013D3h
1
04h
Calibrate DCO – for CSIRFCAL register
013D4h
1
per unit
Calibrate DCO – for CSIRTCAL register
013D5h
1
per unit
Calibrate DCO – for CSERFCAL register
013D6h
1
per unit
Calibrate DCO – for CSERTCAL register
013D7h
1
per unit
SD24 Calibration Tag
013D8h
1
04h
SD24 Calibration Length
013D9h
1
02h
Calibrate SD24 – for SD24TRIM register
013DAh
1
per unit
Empty
013DBh
1
FFh
Tag Empty
013DCh
1
FEh
Empty Length
013DDh
1
22h
Empty
013DEh
34
FFh
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6.11 Memory
Table 6-16 shows the memory organization for the specified devices.
Table 6-16. Memory Organization
MSP430i2040
MSP430i2030
MSP430i2020
Memory
MSP430i2041
MSP430i2031
MSP430i2021
Size
16 KB
32 KB
Main: interrupt vector
Flash
0xFFFF to 0xFFE0
0xFFFF to 0xFFE0
Main: code memory
Flash
0xFFFF to 0xC000
0xFFFF to 0x8000
Information memory
Size
Flash
1 KB
0x13FFh to 0x1000
1 KB
0x13FFh to 0x1000
Size
1 KB
0x05FF to 0x0200
2 KB
0x09FF to 0x0200
16-bit
0x01FF to 0x0100
0x01FF to 0x0100
8-bit
0x00FF to 0x0010
0x00FF to 0x0010
8-bit SFR
0x000F to 0x0000
0x000F to 0x0000
RAM
Peripherals
Detailed Description
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6.11.1 Peripheral File Map
Table 6-17 lists the peripherals that support word access, and Table 6-18 lists the peripherals that support
byte access. Peripherals that support both access types are listed in both tables.
Table 6-17. Peripherals With Word Access
MODULE
REGISTER DESCRIPTION
REGISTER NAME
ADDRESS
SYS
JTAG disable register
SYSJTAGDIS
0x01FE
Timer TA1
Capture/compare register 2
TA1CCR2
0x0196
Capture/compare register 1
TA1CCR1
0x0194
Capture/compare register 0
TA1CCR0
0x0192
Timer_A register
TA1R
0x0190
Capture/compare control 2
TA1CCTL2
0x0186
Capture/compare control 1
TA1CCTL1
0x0184
Capture/compare control 0
TA1CCTL0
0x0182
Timer_A control
TA1CTL
0x0180
Timer_A interrupt vector
TA1IV
0x011E
Capture/compare register 2
TA0CCR2
0x0176
Capture/compare register 1
TA0CCR1
0x0174
Capture/compare register 0
TA0CCR0
0x0172
Timer_A register
TA0R
0x0170
Capture/compare control 2
TA0CCTL2
0x0166
Capture/compare control 1
TA0CCTL1
0x0164
Capture/compare control 0
TA0CCTL0
0x0162
Timer_A control
TA0CTL
0x0160
Timer_A interrupt vector
TA0IV
0x012E
USCI_A control word 0
UCA0CTLW0
0x0140
USCI _A control word 1
UCA0CTLW1
0x0142
USCI_A baud rate 0
UCA0BR0
0x0146
USCI_A baud rate 1
UCA0BR1
0x0147
USCI_A modulation control
UCA0MCTLW
0x0148
USCI_A status
UCA0STAT
0x014A
USCI_A receive buffer
UCA0RXBUF
0x014C
USCI_A transmit buffer
UCA0TXBUF
0x014E
USCI_A LIN control
UCA0ABCTL
0x0150
USCI_A IrDA transmit control
UCA0IRTCTL
0x0152
USCI_A IrDA receive control
UCA0IRRCTL
0x0153
USCI_A interrupt enable
UCA0IE
0x015A
USCI_A interrupt flags
UCA0IFG
0x015C
USCI_A interrupt vector word
UCA0IV
0x015E
Timer TA0
eUSCI_A0
56
Detailed Description
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Table 6-17. Peripherals With Word Access (continued)
MODULE
REGISTER DESCRIPTION
REGISTER NAME
ADDRESS
eUSCI_B0
USCI_B control word 0
UCB0CTLW0
0x01C0
USCI_B control word 1
UCB0CTLW1
0x01C2
USCI_B bit rate 0
UCB0BR0
0x01C6
USCI_B bit rate 1
UCB0BR1
0x01C7
USCI_B status word
UCB0STATW
0x01C8
USCI_B byte counter threshold
UCB0TBCNT
0x01CA
USCI_B receive buffer
UCB0RXBUF
0x01CC
USCI_B transmit buffer
UCB0TXBUF
0x01CE
USCI_B I2C own address 0
UCB0I2COA0
0x01D4
USCI_B I2C own address 1
UCB0I2COA1
0x01D6
USCI_B I2C own address 2
UCB0I2COA2
0x01D8
USCI_B I2C own address 3
UCB0I2COA3
0x01DA
USCI_B received address
UCB0ADDRX
0x01DC
USCI_B address mask
UCB0ADDMASK
0x01DE
USCI I2C slave address
UCB0I2CSA
0x01E0
USCI interrupt enable
UCB0IE
0x01EA
USCI interrupt flags
UCB0IFG
0x01EC
USCI interrupt vector word
UCB0IV
0x01EE
Sum extend
SUMEXT
0x013E
Result high word
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
OP2
0x0138
Multiply signed + accumulate/operand 1
MACS
0x0136
Multiply + accumulate/operand 1
MAC
0x0134
Multiply signed/operand 1
MPYS
0x0132
Multiply unsigned/operand 1
MPY
0x0130
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
Watchdog Timer
Watchdog/timer control
WDTCTL
0x0120
SD24
(See also: Table 6-18)
SD24 interrupt vector word register
SD24IV
0x01F0
Hardware Multiplier
Flash Memory
(1)
(2)
Channel 3 conversion memory
(1) (2)
SD24MEM3
0x0116
Channel 2 conversion memory (2)
SD24MEM2
0x0114
Channel 1 conversion memory
SD24MEM1
0x0112
Channel 0 conversion memory
SD24MEM0
0x0110
Channel 3 control (1) (2)
SD24CCTL3
0x0108
Channel 2 control (2)
SD24CCTL2
0x0106
Channel 1 control
SD24CCTL1
0x0104
Channel 0 control
SD24CCTL0
0x0102
General Control
SD24CTL
0x0100
Not available on MSP430i2031, MSP430i2030 devices.
Not available on MSP430i2021, MSP430i2020 devices.
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Table 6-18. Peripherals With Byte Access
MODULE
REGISTER DESCRIPTION
REGISTER NAME
ADDRESS
SD24
(See also: Table 6-17)
SD24 trim
SD24TRIM
0x00BF
Channel 3 preload (1) (2)
SD24PRE3
0x00BB
Channel 2 preload (2)
SD24PRE2
0x00BA
Channel 1 preload
SD24PRE1
0x00B9
Channel 0 preload
SD24PRE0
0x00B8
Channel 3 input control (1) (2)
SD24INCTL3
0x00B3
Channel 2 input control
PMM
Clock System
Port P2
Port P1
Special Function
(1)
(2)
58
(2)
SD24INCTL2
0x00B2
Channel 1 input control
SD24INCTL1
0x00B1
Channel 0 input control
SD24INCTL0
0x00B0
Reference calibration 1
REFCAL1
0x0063
Reference calibration 0
REFCAL0
0x0062
Voltage monitor control
VMONCTL
0x0061
LPM4.5 control
LPM45CTL
0x0060
Clock system external resistor temperature calibration
CSERTCAL
0x0055
Clock system external resistor frequency calibration
CSERFCAL
0x0054
Clock system internal resistor temperature calibration
CSIRTCAL
0x0053
Clock system internal resistor frequency calibration
CSIRFCAL
0x0052
Clock system control 1
CSCTL1
0x0051
Clock system control 0
CSCTL0
0x0050
Port P2 interrupt flag
P2IFG
0x002D
Port P2 interrupt enable
P2IE
0x002B
Port P2 interrupt edge select
P2IES
0x0029
Port P2 interrupt vector word
P2IV
0x002E
Port P2 selection 1
P2SEL1
0x001D
Port P2 selection 0
P2SEL0
0x001B
Port P2 direction
P2DIR
0x0015
Port P2 output
P2OUT
0x0013
Port P2 input
P2IN
0x0011
Port P1 interrupt flag
P1IFG
0x002C
Port P1 interrupt enable
P1IE
0x002A
Port P1 interrupt edge select
P1IES
0x0028
Port P1 interrupt vector word
P1IV
0x001E
Port P1 selection 1
P1SEL1
0x001C
Port P1 selection 0
P1SEL0
0x001A
Port P1 direction
P1DIR
0x0014
Port P1 output
P1OUT
0x0012
Port P1 input
P1IN
0x0010
SFR interrupt flag 1
IFG1
0x0002
SFR interrupt enable 1
IE1
0x0000
Not available on MSP430i2031, MSP430i2030 devices.
Not available on MSP430i2021, MSP430i2020 devices.
Detailed Description
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6.12 Identification
6.12.1 Device Identification
The device type can be identified from the top-side marking on the device package. Refer to the TI web
site
at
the
following
address
for
help
with
Part
Mark
Look
Up:
http://focus.ti.com/quality/docs/gencontent.tsp?templateId=5909&navigationId=12626&contentId=5071
6.12.2 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
Detailed Description
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7 Applications, Implementation, and Layout
The following resources provide application guidelines and best practices when designing with the
MSP430i20xx devices.
Implementation of a One- or Two-Phase Electronic Watt-Hour Meter Using MSP430i20xx (SLAA637)
This application report describes the implementation of a low-cost one- or two-phase electronic electricity
meter that uses the Texas Instruments MSP430i20xx metering processor. This application report includes
the necessary information with regard to metrology software and hardware procedures for this single-chip
implementation.
Single-Phase and DC Embedded Metering Power Using MSP430i2040 (SLAA638)
This report describes an EVM design that uses the MSP430i2040 microcontroller in the application of
embedded metering (sub-metering). In this application space, the electricity measuring device is
embedded in the end application and provides the user with information about the voltage, current, and
power consumption of the device. In addition, the EVM can compensate for the line resistance and EMI
filter capacitance.
Single-Phase AC and DC Power Monitor With Wire Resistance and EMI Capacitor Compensation
(TIDM-SERVER_PWR_MON)
This reference design shows the application of a single-phase ac and dc power monitor (server power
monitor) using the MSP430i2040 microcontroller.
Hardware Features
• Spy-Bi-Wire debugging interface
• 14-pin debugger connector allows direct interface to MSP-FET430UIF without the need for an adaptor
• Built-in switching mode power supply that can be supplied by 85 to 265 VAC (47 Hz to 63 Hz) or 120
to 380 VDC simplifies evaluation setup
• Built-in RS232 external communication interface for reading measurements and performing calibration
• Seven built-in LEDs for customer debugging and visual monitoring
Software Features
• Measurement of root mean square voltage, root mean square current, active power, reactive power,
apparent power, power factor, ac frequency, voltage THD, current THD, fundamental voltage,
fundamental current, and fundamental active power
• Readings update every four ac cycles or every 80 ms in case of dc input
• Capable of ac and dc measurement
• Capable of switching between ac and dc measurement mode automatically
• Capable of doing EMI filter capacitor and wire resistance compensation
• No separate dc calibration required
Three-Outlet Smart Power Strip (TIDM-3OUTSMTSTRP)
This reference design shows the application of a 3-socket power strip with power consumption measuring
capability using the MSP430i2040 microcontroller.
Features
• Measures individual power and current of 3 socket outlets
• Built-in relay for further functionality expansion:
– Switch off an output based on user current limit setting
– Switch on or off an output based on user set master current trigger level
• Supports latched and nonlatched relay
• Built-in power supply and debugging interface
60
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•
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On-board connector to external communication modules:
– Isolated serial (on first version)
– Wi-Fi® (to be added in later version)
– Bluetooth® (to be added in later version)
Applications, Implementation, and Layout
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8 Device and Documentation Support
8.1
Device Support
8.1.1
Getting Started
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.1.2
Development Tools Support
All MSP430 microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.1.2.1
Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430
Yes
Yes
2
No
Yes
(General clock
control)
No
No
No
(Must reconnect
after LPMx.5)
8.1.2.2
Recommended Hardware Options
8.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
32-pin VQFN (RHB)
MSP-FET430U32A
MSP-TS430RHB32A
8.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
8.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
8.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
62
Part Number
PC Port
MSP-GANG
Serial and USB
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Device and Documentation Support
Texas Instruments
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8.1.2.3
SLAS887 – AUGUST 2014
Recommended Software Options
8.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
8.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
8.1.2.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for
an IDE.
8.1.3
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430i2041). Texas Instruments recommends two of
three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent
evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX
for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
Device and Documentation Support
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PW) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
MSP 430 i 2 041
T PW
T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Optional: Temperature Range
Feature Set
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
430 MCU Platform
TI’s Microcontroller Platform
Device Type
Specialized Application
i = Flash Industrial
Series
2 Series = Up to 16.384 MHz
Feature Set
Various Levels of Integration Within a Series
Optional: Temperature Range
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features
-EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
64
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8.2
SLAS887 – AUGUST 2014
Documentation Support
The following documents describe the MSP430i20xx MCUs. Copies of these documents are available on
the Internet at www.ti.com.
SLAU335
8.3
MSP430i2xx Family User's Guide. Detailed description of all modules and peripherals
available in this device family.
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
8.4
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430i2041
Click here
Click here
Click here
Click here
Click here
MSP430i2040
Click here
Click here
Click here
Click here
Click here
MSP430i2031
Click here
Click here
Click here
Click here
Click here
MSP430i2030
Click here
Click here
Click here
Click here
Click here
MSP430i2021
Click here
Click here
Click here
Click here
Click here
MSP430i2020
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
Device and Documentation Support
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8.5
www.ti.com
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical Packaging and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
66
Mechanical Packaging and Orderable Information
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: MSP430i2041 MSP430i2040 MSP430i2031 MSP430i2030 MSP430i2021 MSP430i2020
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430I2020TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2020T
MSP430I2020TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2020T
MSP430I2020TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2020T
MSP430I2020TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2020T
MSP430I2021TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2021T
MSP430I2021TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2021T
MSP430I2021TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2021T
MSP430I2021TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2021T
MSP430I2030TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2030T
MSP430I2030TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2030T
MSP430I2030TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2030T
MSP430I2030TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2030T
MSP430I2031TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2031T
MSP430I2031TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2031T
MSP430I2031TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2031T
MSP430I2031TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2031T
MSP430I2040TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2040T
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Nov-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430I2040TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2040T
MSP430I2040TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2040T
MSP430I2040TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2040T
MSP430I2041TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2041T
MSP430I2041TPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2041T
MSP430I2041TRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2041T
MSP430I2041TRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
I2041T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430I2020TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2020TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2020TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2021TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2021TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2021TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2030TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2030TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2030TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2031TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2031TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2031TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2040TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2040TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2040TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2041TPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430I2041TRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430I2041TRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430I2020TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2020TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2020TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430I2021TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2021TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2021TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430I2030TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2030TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2030TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430I2031TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2031TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2031TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430I2040TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2040TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2040TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
MSP430I2041TPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MSP430I2041TRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430I2041TRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
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