Renesas ISL68124IRAZ Digital dual output, 4-phase configurable, pwm controller with pmbus Datasheet

DATASHEET
ISL68124
Digital Dual Output, 4-Phase Configurable, PWM Controller with PMBus
The ISL68124 is a digital dual output, flexible multiphase
(X+Y ≤ 4) PWM controller supporting the latest PMBus 1.3
specifications. Either output can be configured to support any
desired phase assignments up to a maximum of four phases
across the two outputs (X+Y). For example, 3+1, 2+2, 2+1, or
even a single output operation as a 4+0 configuration are
supported. The ISL68124 uses Intersil’s proprietary linear
synthetic digital current modulation scheme to achieve the
industry’s best combination of transient response and ease
of tuning while addressing the challenges of modern
multiphase designs.
Device configuration and telemetry monitoring is
accomplished using Intersil's intuitive PowerNavigator™ GUI.
The ISL68124 device supports on-chip nonvolatile memory to
store various configuration settings that are user selectable
through pin-strap, giving system designers increased power
density to configure and deploy multiple configurations. The
device supports an automatic phase add/drop feature to allow
maximum efficiency across all load ranges. Thresholds for
automatic phase add/drop are user programmable using the
powerful PowerNavigator GUI.
The ISL68124 supports a comprehensive fault management
system to enable the design of highly reliable systems. From a
multitiered overcurrent protection scheme, to the configurable
power-good and output overvoltage/undervoltage fault
thresholds and temperature monitoring, almost any need is
accommodated.
With minimal external components, easy configuration, robust
fault management, and highly accurate regulation capability,
implementing a high-performance, multiphase regulator has
never been easier.
Applications
• Networking equipment
• Telecom/datacom equipment
• Server/storage equipment
• Point-of-load power supply (Memory, DSP, ASIC, FPGA)
FN8796
Rev.2.00
June 16, 2017
Features
• Advanced linear digital modulation scheme
- Zero latency synthetic current control for excellent HF
current balance
- Dual edge modulation for fastest transient response
• Auto phase add/drop for excellent load vs efficiency profile
• PMBus 1.3 support
- Telemetry - VIN, VOUT, IOUT, power IN/OUT, temperature,
and various fault status registers
- Up to 2MHz bus interface
• Flexible phase configuration
- 4+0, 3+1, 2+2 phase operation
- Operation using less than four phases between two
outputs is also supported
• Diode braking for overshoot reduction
• Differential remote voltage sensing supports ±0.5% closed
loop system accuracy over load, line, and temperature
• Highly accurate current sensing for excellent load line
regulation and accurate OCP
- Supports ISL99227 60A smart power stage
- Supports DCR sense with integrated temperature
compensation
• Comprehensive fault management enables high reliability
systems
- Pulse-by-pulse phase current limiting
- Total output current protection
- Output and input OV/UV
- Open voltage sense detect
- Black box recording capability for faults
• Intuitive configuration using PowerNavigator GUI
- NVM to store up to 8 configurations
• Pb-free (RoHS compliant)
Related Literature
• For a full list of related documents, visit our website
- ISL68124 product page
FN8796 Rev.2.00
June 16, 2017
Page 1 of 46
ISL68124
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Driver, DrMOS and Smart Power Stage Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application: 3+1 Configuration with ISL99227 SPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application: 2+2 Configuration with ISL99227 SPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application: 2+2 Configuration with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMBus Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Phase Add and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lossless Input Current and Power Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stored Configuration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
11
12
12
12
12
13
14
14
15
15
15
15
15
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Smart Power Stage OC Fault Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitoring (TWARN) and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
17
17
Layout and Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PMBus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMBus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMBus Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FN8796 Rev.2.00
June 16, 2017
Page 2 of 46
ISL68124
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL68124IRAZ
PART
MARKING
TEMP. RANGE
(°C)
ISL68124 IRZ
PACKAGE
(RoHS COMPLIANT)
-40 to +85
PKG.
DWG. #
40 Ld 5x5 TQFN
L40.5x5D
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page for ISL68124. For more information on MSL, see TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
PHASE CONFIGURATION
OUTPUT X/OUTPUT Y
SPECIFICATION SUPPORTED
PACKAGE
ISL68137
X+Y ≤ 7
PMBus/AVSBus
QFN 48 Ld, 6x6mm
ISL68134
X+Y ≤ 4
PMBus/AVSBus
TQFN 40 Ld, 5x5mm
ISL68127
X+Y ≤ 7
PMBus
QFN 48 Ld, 6x6mm
ISL68124
X+Y ≤ 4
PMBus
TQFN 40 Ld, 5x5mm
Pin Configuration
FN8796 Rev.2.00
June 16, 2017
DNC
DNC
DNC
SA
VCCS
VCC
TMON1
TMON0
VSEN0
RGND0
ISL68124
(40 LD TQFN)
TOP VIEW
40
39
38
37
36
35
34
33
32
31
PWM0
1
30 CS0
PWM1
2
29 CSRTN0
PWM2
3
28 CS1
PWM3
4
27 CSRTN1
GND
5
26 CS2
EPAD
(GND)
25 CSRTN2
22 RGND1
DNC
10
21 VSEN1
11
12
13
14
15
16
17
18
19
20
VINSEN
9
CONFIG
DNC
SALRT
23 CSRTN3
SDA
8
SCL
DNC
PG1
24 CS3
PG0
7
TWARN
GND
EN1
6
EN0
DNC
Page 3 of 46
ISL68124
Functional Pin Descriptions
Refer to Table 4 on page 18 for design layout considerations.
PIN NUMBER
4, 3, 2, 1
PIN NAME
DESCRIPTION
PWM[3:0] Pulse width modulation outputs. Connect these pins to the PWM input pins of 3.3V logic-compatible, Intersil smart power
stages, driver IC(s), or power stages.
5, 7
GND
Ground pins. Connect directly to system GND plane.
6, 8, 9, 10,
38, 39, 40
DNC
Do not connect any signals to these pins.
11
EN0
Input pin used for enable control of Output 0. Active high. Connect to ground if not used.
12
EN1
Input pin used for enable control of Output 1. Active high. Connect to ground if not used.
13
TWARN
14
PG0
Open-drain, power-good indicator for Output 0. Maximum pull-up voltage is VCC.
15
PG1
Open-drain, power-good indicator for Output 1. Maximum pull-up voltage is VCC.
16
SCL
Serial clock signal pin for SMBus interface. Maximum pull-up voltage is VCC.
17
SDA
Serial data signal pin for SMBus interface. Maximum pull-up voltage is VCC.
18
SALRT
Serial alert signal pin for SMBus interface. Maximum pull-up voltage is VCC.
19
CONFIG
Configuration ID selection pin. See Table 3 on page 15 for more details.
20
VINSEN
Input voltage sense pin. Connect to VIN through a resistor divider (typically 40.2k/10k) with a 10nF decoupling capacitor.
21
VSEN1
Positive differential voltage sense input for Output 1. Connect to positive remote sensing point. Connect to ground if not
used.
22
RGND1
Negative differential voltage sense input for Output 1. Connect to negative remote sensing point. Connect to ground if not
used.
Thermal warning flag. This open-drain output will be pulled low in the event of a sensed over-temperature at TMON pins
without disabling the outputs. Maximum pull-up voltage is VCC.
23, 25, 27, 29 CSRTN[3:0] The CS and CSRTN pins are current sense inputs to individual phase differential amplifiers. Unused phases should have their
respective current sense inputs grounded. The ISL68124 supports smart power stage, DCR, and resistor sensing.
24, 26, 28, 30 CS[3:0]
Connection details depend on the current sense method chosen.
31
RGND0
Negative differential voltage sense input for Output 0. Connect to negative remote sensing point. Connect to ground if not
used.
32
VSEN0
Positive differential voltage sense input for Output 0. Connect to positive remote sensing point. Connect to ground if not
used.
33
TMON0
Input pin for external temperature measurement at Output 0. Supports diode based temperature sensing as well as smart
power stage sensing. Refer to “Temperature Compensation” on page 14 for more information.
34
TMON1
Input pin for external temperature measurement at Output 1. Supports diode based temperature sensing as well as smart
power stage sensing. Refer to “Temperature Compensation” on page 14 for more information.
35
VCC
Chip primary bias input. Connect this pin directly to a +3.3V supply with a high quality MLCC bypass capacitor.
36
VCCS
Internally generated 1.2V LDO logic supply from VCC. Decouple with 4.7µF or greater MLCC (X5R or better).
37
SA
EPAD
GND
PMBus addresses selection pin. See Table 2 for more details.
Package pad serves as GND return for all chip functions. Connect directly to system GND plane with multiple thermal vias.
Driver, DrMOS, and Smart Power Stage Recommendation
QUIESCENT CURRENT
(mA)
GATE
DRIVE VOLTAGE
(V)
NUMBER OF
DRIVERS
ISL99227
4.85
5
Single
60A, 5x5 smart power stage
ISL99140
0.19
5
Single
40A, 6x6 DrMOS
ISL6596
0.19
5
Single
Connect ISL6596 VCTRL to 3.3V
INTERSIL PART
NUMBER
FN8796 Rev.2.00
June 16, 2017
COMMENTS
Page 4 of 46
ISL68124
Internal Block Diagram
PG0
CS0
CSRTN0
ADC
CYCLECYCLE OCP
ADC
CYCLECYCLE OCP
ADC
CYCLECYCLE OCP
ADC
CYCLECYCLE OCP
STATUS
MANAGER
PG1
TWARN
CS1
CSRTN1
CS2
CSRTN2
CS3
CSRTN3
EN0
LOOP
MANAGER
EN1
CONFIG
CPU
ISUM-0
SUMMED
OCP
VSA
ADC
NVM
SUMMED
OCP
DIGITAL
DUAL EDGE
MODULATOR
PID
OV
CURREN
T AC FB
VDROOP
VSE N1
RGND1
VSA
ADC
UV
+
+
PID
OV
VINSEN
UV
+
ADC
VCC
LDO
DIGITAL
DUAL EDGE
MODULATOR
+
TMO N0
TMO N1
BLACKBOX
FAULT AND
TELEMETRY
MANAGER
PHASE MANAGER
VSE N0
ISUM-1
CURREN
T AC FB
VDROOP
RGND0
SA
PWM0
PWM1
PWM2
PWM3
SCL
PMBus
INTERFACE
SDA
SALRT
VCCS
FIGURE 1. INTERNAL BLOCK DIAGRAM
FN8796 Rev.2.00
June 16, 2017
Page 5 of 46
ISL68124
Typical Application: 3+1 Configuration with ISL99227 SPS
RGND0
VSEN0
1k
EN0
VCCS
PG0
4.7µF
100
TMON0
ISL99227
VCC
3.3V
PWM0
PWM
100
CS0
CSRTN0
PVCC
VCC
TMON
470pF
4.7µF
0.1µF
470pF
IMON
REFIN
5V
VIN
BOOT
12V
0.1µF
2x22µF
PHASE
FAULT#
12V
GND
SW
ISL99227
40.2k
PVCC
VCC
TMON
VINSEN
PWM1
10k
10nF
100
CS1
CSRTN1
PWM
0.1µF
IMON
REFIN
470pF
5V
VIN
BOOT
COUT
VOUT0
COUT
VOUT1
12V
0.1µF
2x22µF
PHASE
ISL68124
FAULT#
GND
SW
ISL99227
PVCC
VCC
TMON
PWM2
100
CS2
CSRTN2
PWM
0.1µF
470pF
IMON
REFIN
5V
VIN
BOOT
12V
0.1µF
2x22µF
PHASE
FAULT#
TWARN
GND
SW
ISL99227
SCL
CS3
SDA
CSRTN3
PWM
100
0.1µF
470pF
IMON
REFIN
5V
PVCC
VCC
TMON
PWM3
12V
VIN
BOOT
0.1µF
2x22µF
PHASE
SALRT
FAULT#
GND
SW
SA
TMON1
470pF
CONFIG
PG1
1k
EN1
RGND1
VSEN1
FIGURE 2. TYPICAL APPLICATION: 3+1 CONFIGURATION WITH ISL99227 SPS
FN8796 Rev.2.00
June 16, 2017
Page 6 of 46
ISL68124
Typical Application: 2+2 Configuration with ISL99227 SPS
RGND0
VSEN 0
1k
EN0
VCCS
PG0
4.7µF
100
TMON0
ISL99227
VCC
3.3V
4.7µF
PWM0
PWM
100
CS0
CSRTN0
PVCC
VCC
TMON
470pF
0.1µF
470pF
IMON
REFIN
5V
VIN
BOOT
12V
0.1µF
2x22µF
PHASE
FAULT#
12V
SW
ISL99227
40.2k
PVCC
VCC
TMON
VINSEN
PWM1
10k
GND
10nF
100
CS1
CSRTN1
PWM
0.1µF
IMON
REFIN
470pF
C OUT
VIN
BOOT
VOUT0
5V
12V
0.1µF
2x22µF
PHASE
ISL68124
FAULT#
GND
SW
ISL99227
PVCC
VCC
TMON
PWM2
PWM
100
CS2
0.1µF
CSRTN2
IMON
REFIN
470pF
5V
VIN
BOOT
12V
0.1µF
2x22µF
PHASE
FAULT#
TWARN
GND
SW
ISL99227
PVCC
VCC
TMON
PWM3
SCL
CS3
SDA
CSRTN3
PWM
100
0.1µF
470pF
IMON
REFIN
5V
VIN
BOOT
12V
0.1µF
2x22µF
PHASE
SALRT
FAULT#
GND
SW
SA
TMON1
VOUT1
C OUT
470pF
CONFIG
PG1
1k
EN1
RGND1
VSEN 1
FIGURE 3. TYPICAL APPLICATION: 2+2 CONFIGURATION WITH ISL99227 SPS
FN8796 Rev.2.00
June 16, 2017
Page 7 of 46
ISL68124
Typical Application: 2+2 Configuration with DCR Sensing
RGND0
VSEN0
1k
EN0
VCCS
PG0
THDN
0.1µF
PWM0
3.3V
BOOT
PHASE
PWM
5V
PVCC
VCC
EN
ISL99140
VIN
12V
2x22µF
SW
GND
VCC
CS0
4.7uF
CSRTN0
12V
TMON0
40.1k
VINSEN
PVCC
VCC
EN
THDN
10k
10nF
0.1µF
BOOT
PHASE
PWM
PWM1
ISL99140
5V
COUT
VIN
VOUT0
12V
2x22µF
SW
GND
TWARN
CS1
CSRTN1
SCL
SDA
PVCC
VCC
EN
ISL68124
THDN
SALRT
0.1µF
BOOT
PHASE
PWM
PWM2
ISL99140
5V
VIN
12V
2x22µF
SW
GND
CS2
COUT
VOUT1
CSRTN2
PVCC
VCC
EN
THDN
SA
0.1µF
PWM3
CONFIG
BOOT
ISL99140
PHASE
PWM
5V
VIN
12V
2x22µF
SW
GND
CS3
CSRTN3
TMON1
PG1
1k
EN1
RGND1
VSEN1
FIGURE 4. TYPICAL APPLICATION: 2+2 CONFIGURATION WITH DCR SENSING
FN8796 Rev.2.00
June 16, 2017
Page 8 of 46
ISL68124
Absolute Maximum Ratings
Thermal Information
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.3V
VCCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to VCC + 0.3V
ESD Rating:
Human Body Model (Tested per JS-001-2014) . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JS-001-2014) . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Notes 4, 5)
JA (°C/W) JC (°C/W)
40 Ld 5x5 QFN Package . . . . . . . . . . . . . . .
30
1.2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.05V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended operating conditions, VCC = 3.3V, unless otherwise specified. Boldface limits apply across the
operating temperature range -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
VCC SUPPLY CURRENT
Nominal Supply Current
VCC = 3.3VDC; EN1/2 = VIH, fSW = 400kHz
Shutdown Supply Current
VCC = 3.3VDC; EN1/2 = 0V, no switching
63
mA
11.5
mA
VCCS LDO SUPPLY
Output Voltage
Maximum Current Capability
1.20
Excluding internal load
1.25
1.30
50
V
mA
POWER-ON RESET AND INPUT VOLTAGE LOCKOUT
VCC Rising POR Threshold
2.7
VCC Falling POR Threshold
1.0
Enable (EN0 and EN1) Input High Level
2.55
2.9
V
V
V
Enable (EN0 and EN1) Input Low Level
0.8
Enable (EN0 and EN1) Input LOW to HIGH Ramp Delay
(TON_DELAY)
200
POR to Initialization Complete Time
V
µs
30
40
ms
OUTPUT VOLTAGE CHARACTERISTICS (Note 6)
Output Voltage Adjustment Range
Output Voltage Set-Point Accuracy
Set-point 0.8V to 3.05V
Set-point 0.25V to <0.8V
0.25
3.05
V
-0.5
0.5
%
-5
5
mV
VOLTAGE SENSE AMPLIFIER
Open Sense Current
22
µA
Input Impedance (VSEN - RGND)
Only during open pin check of initialization
200
kΩ
Maximum Common-Mode Input
VCC - 0.2
Maximum Differential Input (VSEN - RGND)
V
3.05
V
CURRENT SENSE AND OVERCURRENT PROTECTION
Maximum Common-Mode Input (SPS mode)
CSRTNx - GND
Maximum Common-Mode Input (DCR mode)
CSRTNx - GND
Current Sense Accuracy
ISEN to ADC accuracy
Average Overcurrent Threshold Resolution
FN8796 Rev.2.00
June 16, 2017
1.6
V
3.3
-2
V
2
%
0.1
A
Page 9 of 46
ISL68124
Electrical Specifications Recommended operating conditions, VCC = 3.3V, unless otherwise specified. Boldface limits apply across the
operating temperature range -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
MAX
(Note 7)
TYP
UNIT
DIGITAL DROOP
Droop Resolution
0.01
mV/A
OSCILLATORS
Accuracy of Switching Frequency Setting
When set to 500kHz
Accuracy of Switching Frequency Setting
Switching Frequency Range
480
520
kHz
-4
500
+4
%
200
1000
kHz
SOFT-START RATE AND VOLTAGE TRANSITION RATE
Minimum Soft-Start Ramp Rate
Programmable minimum rate
20
µs
Maximum Soft-Start Ramp Rate
Programmable maximum rate
10
ms
Soft-Start Ramp Rate Accuracy
-4
Minimum Transition Rate
Programmable minimum rate
Maximum Transition Rate
Programmable maximum rate
Transition Rate Accuracy
4
0.1
%
mV/µs
100
mV/µs
-4
4
%
PWM OUTPUT
PWMx Output High Level
IOUT = 4mA
PWMx Output Low Level
IOUT = 4mA
PWMx Output Tri-State IOL
VOH = VCC
PWMx Output Tri-State IOH
VOL = 0V
VCC - 0.4
V
0.4
V
1
µA
-1
µA
THERMAL MONITORING AND PROTECTION
Temperature Sensor Range
Temperature Sensor Accuracy
TMON to ADC accuracy
TWARN Output Low Impedance
-50
150
°C
-4.5
4.5
%
4
TWARN Hysteresis
9
13
3
Ω
°C
POWER-GOOD AND PROTECTION MONITORS
PG Output Low Voltage
IOUT = 8mA load
PG Leakage Current
With pull-up resistor externally connected to VCC
0.4
0.5
Overvoltage Protection Threshold Resolution
Undervoltage Protection Threshold Resolution
Overvoltage Protection Threshold When Disabled
1
V
µA
1
mV
1
mV
VCC - 0.2
V
INPUT VOLTAGE SENSE
Input Voltage Accuracy
VINSEN to ADC accuracy
-2.5
Input Voltage Protection Threshold Resolution
2.5
1
%
mV
SMBus/PMBus
SALERT, SDA Output Low Level
IOUT = 4mA
SCL, SDA Input High Level
0.4
V
SCL, SDA Input Low Level
0.8
SCL, SDA Input Hysteresis
SCL Frequency Range
V
1.55
2
0.05
V
mV
2
MHz
NOTES:
6. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN8796 Rev.2.00
June 16, 2017
Page 10 of 46
ISL68124
0.08
0.05
0.07
0.04
0.06
0.03
ICC (A)
ICC (A)
Typical Performance Curves
0.05
0.04
0.02
0.01
0.03
-40
-20
0
20
40
60
80
0
100
-40
AMBIENT TEMPERATURE (oC)
FIGURE 5. NOMINAL SUPPLY CURRENT vs TEMPERATURE
Functional Description
Overview
The ISL68124 is a digital dual output, 4-phase PWM controller that
can be programmed for single output 4+0, dual output 3+1, or
2+2 phase operation. Operation using less than four phases
between two outputs is also supported. Existing digital
multiphase solutions use analog comparator based schemes
(nonlinear) to bolster the inadequate transient response common
to many digital multiphase solutions. The ISL68124 uses a linear
voltage regulation scheme to address transient loads. As a result,
it is much easier for users to configure and validate their designs
when compared with nonlinear schemes. By combining a
proprietary low noise and zero latency digital current sense
scheme with cutting edge digital design techniques, Intersil is able
to meet transient demands without resorting to nonlinear
schemes. In addition, the ISL68124 can store up to eight user
configurations in NVM and allows the user to select the desired
configuration through pin-strap (CONFIG). The result is a system
that is easy to configure and deploy.
A number of performance enhancing features are supported in
the ISL68124. These include diode braking, automatic phase
dropping, DCR/resistor/smart power stage current sense
support, load-line regulation, and multiple temperature sensing
options.
To facilitate configuration development, the PowerNavigator GUI
provides a step-by-step arrangement for setup and parametric
adjustment. After a configuration has been set, the user can
employ PowerNavigator to monitor telemetry or use direct
PMBus interface based on the supported command set.
PWM Modulation Scheme
The ISL68124 uses Intersil's proprietary linear synthetic current
modulation scheme to improve transient performance. This is a
unique, constant frequency, dual-edge PWM modulation scheme
with both PWM leading and trailing edges being independently
moved to give the best response to transient loads. Current
balance is an inherent part of the regulation scheme. The
modulation scheme is capable of overlapping pulses if the load
FN8796 Rev.2.00
June 16, 2017
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
FIGURE 6. SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
profile demands such operation. In addition, the modulator is
capable of adding or removing pulses from a given cycle in
response to regulation demands while still managing maximum
average frequency to safe levels. For DC load conditions, the
operating frequency is constant.
PMBus Address Selection
When communicating with multiple PMBus devices on a single
bus, each device must have its own unique address so the host
can distinguish between the devices. The device address can be
set using a 1% resistor on the SA pin according to the pin-strap
options listed in Table 2.
TABLE 2. RESISTOR VALUES TO ADDRESS MAPPING
R SA
(Ω)
PMBus
ADDRESS
R SA
(Ω)
PMBus
ADDRESS
0
60h
1500
52h
180
63h
1800
53h
330
66h
2200
56h
470
67h
2700
57h
680
42h
3300
5Ah
820
43h
3900
5Bh
1000
46h
4700
5Eh
1200
47h
5600
5Fh
Phase Configuration
The ISL68124 supports up to two regulated outputs through four
configurable phases. Either output is capable of controlling up to
four phases in any arbitrary mix. Phase assignments are
accomplished through the PowerNavigator GUI.
While the device supports arbitrary phase assignment, it is good
practice to assign phases to Output 1 in descending sequential
numerical order starting from Phase 3. For example, a 3-phase
rail could consist of Phases 3, 2, and 1. For Output 0, phases
should be assigned starting from Phase 0 in ascending
sequential numerical order.
Page 11 of 46
ISL68124
Automatic Phase Add and Drop
To produce the most optimal efficiency across a wide range of
output loading, the modulator supports automatic dropping or
adding of phases. Use of automatic phase dropping is optional. If
automatic phase dropping is enabled, the number of active
phases at any time is determined solely by load current. During
operation, phases of Output 1 will drop beginning with the lowest
phase number assigned. Phase dropping begins with the highest
assigned phase number. Figure 7 illustrates the typical
characteristic of efficiency vs load current vs phase count.
VOUT_OV_FAULT_LIMIT > VOUT_COMMAND
(VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW, if used) >
VOUT_UV_FAULT_LIMIT. Additionally, the VOUT commands are
bounded by VOUT_MAX and VOUT_MIN to provide protection
against incorrect set points being sent to the device.
Switching Frequency
The switching frequency is user-configurable over a range of
200kHz to 1MHz.
Current Sensing
The ISL68124 supports DCR, resistor, and smart power stage
current sensing. Connection to the various sense elements is
accomplished using the CS and CSRTN pins. Current-sensing
inputs are high impedance differential inputs to reject noise and
ground related inaccuracies.
I3
I2
EFFICIENCY (%)
I1
To accommodate a wide range of effective sense resistance,
information about the effective sense resistance and required
per phase current capability is used by the GUI to properly
configure the current sense circuitry.
3-PHASE
2-PHASE
1-PHASE
0
10
20
30
40
50
60
70
80
90
LOAD (A)
FIGURE 7. EFFICIENCY vs PHASE NUMBER
Phases are dropped one at a time with a user-programmed drop
delay between drop events. As an example, suppose the delay is
set to 1ms and three phases are active. If the load suddenly
drops to a level needing only one phase, the ISL68124 will begin
by dropping a phase after 1ms. An additional phase will be
dropped each 1ms thereafter until only one phase remains.
In addition to the described load current add/drop thresholds,
the fast phase add function provides a very rapid response to
transient load conditions. This feature continuously monitors the
system regulation error and, if it exceeds the user set threshold,
all dropped phases will be readied for use. In this way, there is no
delay if all phases are needed to support a load transient. The
fast phase add threshold is set in the PowerNavigator GUI. Output
current threshold for adding and dropping phases can also be
configured.
To ensure dropped phases have sufficient boot capacitor charge
to turn on the high-side MOSFET after a long period of disable, a
boot refresh circuit turns on the low-side MOSFET of each
dropped phase to refresh the boot capacitor. The frequency of
the boot refresh is programmable through PowerNavigator.
Output Voltage Configuration
Output voltage set points and thresholds for each output can be
configured with PowerNavigator GUI. Parameters such as output
voltage, VOUT margin high/low, and VOUT OV/UV faults thresholds
can be configured with the GUI. Additionally, output voltage and
margin high/low can be adjusted during regulation using the
PMBus commands VOUT_COMMAND, VOUT_MARGIN_HIGH, and
VOUT_MARGIN_LOW for further tuning. The following VOUT
relationships must be maintained for correct operation:
FN8796 Rev.2.00
June 16, 2017
INDUCTOR DCR SENSING
DCR sensing takes advantage of the fact that an inductor
winding has a resistive component (DCR) that will drop a voltage
proportional to the inductor current. Figure 8 shows that the DCR
is treated as a lumped element with one terminal inaccessible
for measurement. Fortunately, a simple R-C network as shown in
Figure 9 is capable of reproducing the hidden DCR voltage. By
simply matching the R-C time constant to the L/DCR time
constant, it is possible to precisely recreate the DCR voltage
across the capacitor. This means that VDCR(t) = VC(t), thus
preserving even the high frequency characteristic of the DCR
voltage.
L
DCR
VOUT
VPHASE
R
L
 R C
DCR
IC
CSRTNn
CURRENT
SENSE
C
CSn
FIGURE 8. DCR SENSING CONFIGURATION
Modern inductors often have such low DCR values that the
resulting signal is <10mV. To avoid noise problems, care must be
taken in the PCB layout to properly place the R-C components and
route the differential lines between controller and inductor.
Figure 8 shows one PCB design method that places the R
component near the inductor VPHASE and the C component very
close to the IC pins. This minimizes routing of the noisy VPHASE
and maximizes filtering near the IC. The lines between the inductor
and IC should be routed as a pair on a single layer directly to the
controller. Care must be taken to avoid routing the pair near any
switching signals including Phase, PWM etc. This is the method
used by Intersil on evaluation board designs.
Page 12 of 46
ISL68124
This method senses the resistance of a metal winding where the
DCR value will increase with temperature. This must be
compensated or the sensed (and reported) current will increase
with temperature. To compensate the temperature effect, the
ISL68124 provides temperature sensing options and an internal
methodology to apply the correction.
RESISTIVE SENSING
For more accurate current sensing, a dedicated current sense
resistor, RSENSE, in series with each output inductor can serve as the
current sense element. However, this technique reduces the overall
converter efficiency due to the additional power loss on the current
sense element, RSENSE.
when the R-C timing constant is too small. In this condition, VOUT
will sag excessively upon load insertion and may create a system
failure or early overcurrent trip. Figure 13 shows the transient
response when the R-C time constant is too large. VOUT is
sluggish in drooping to its final value. Use these general guides if
fine-tuning is needed.
IOUT
VOUT
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
RSENSE ESL
VOUT
VPHASE
ESL
 RC
RSENSE
IO U T
R
VOUT
IC
CSRTNn
C
CSn
CURRENT
SENSE
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO SMALL
IOUT
FIGURE 9. SENSE RESISTOR IN SERIES WITH INDUCTOR
A current-sensing resistor has a distributed parasitic inductance
known as Equivalent Series Inductance (ESL), which is typically
less than 4nH. Consider the ESL as a separate lumped quantity,
as shown in Figure 9. The phase current IL, flowing through the
inductor, will also pass through the ESL. Similar to DCR sensing
described previously, a simple R-C network across the current
sense resistor extracts the RSENSE voltage. Simply match the
ESL/RSENSE time constant to the R-C time constant.
Figure 10 shows the sensed waveforms with and without
matching RC when using resistive sense. PCB layout should be
treated similar to that described for DCR sense.
MATCHED RC
MISMATCHED RC
FIGURE 10. VOLTAGE ACROSS R WITH AND WITHOUT RC
L/DCR OR ESL/RSEN MATCHING
Assuming the compensator design is correct, Figure 11 shows the
expected load transient response waveforms if L/DCR or
ESL/RSEN is matching the R-C time constant. When the load
current IOUT has a square change, the output voltage VOUT also
has a square response, except for the potential overshoot at load
release. However, there is always some uncertainty in the true
parameter values involved in the time constant matching and
therefore, fine-tuning is generally required.
If the R-C time constant is too large or too small, VC(t) will not
accurately represent real-time IOUT(t) and will worsen the
transient response. Figure 12 shows the load transient response
FN8796 Rev.2.00
June 16, 2017
VOUT
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO LARGE
SPS CURRENT SENSING
SPS current sense is accomplished by sensing each SPS IMON
output individually using VCCS as a common reference. Connect
all SPS IREF input pins and all ISL68124 CSRTNx input pins
together and tie them to VCCS, then connect the SPS IMONx
output pins to the corresponding ISL68124 CSx input pins. The
signals should be run as differential pairs from the SPS back to
the ISL68124.
Temperature Sensing
The ISL68124 supports temperature sensing through BJT or
smart power stage sense elements. Support for BJT sense
elements uses the well known delta Vbe method and allows up
to two sensors (MMBT3906 or similar) on each temperature
sense input, TMON0 and TMON1. Support for smart power stage
uses a linear conversion algorithm and allows one sensor reading
per pin. The conversion from voltage to temperature for smart
power stage sensing is user-programmable through the
PowerNavigator GUI.
The SPS temperature sensing measures the
temperature-dependent voltage output on the SPS TMON pin. All
of the SPS devices attached to the Output 0 rail have their TMON
pins connected to the ISL68124 TMON0 pin. All of the SPS
devices attached to the Output 1 rail have their TMON pins
Page 13 of 46
ISL68124
connected to the ISL68124 TMON1 pin. The reported
temperature is that of the highest temperature SPS of the group.
IPHASE#
DCR
VOUT
In addition to the external temperature sense, the IC senses its
own die temperature, which can be monitored through
PowerNavigator.
CSRTNx
CURRENT
SENSE
CSx
Sensed temperature is used in the system for faults, telemetry,
and temperature compensation of sensed current.
TEMPERATURE
COMPENSATION
DCRCORR
Temperature Compensation
Compensating current sense for temperature variation generally
requires that the current sensing element temperature and its
temperature coefficient is known. Although temperature
coefficient is generally obtained easily, actual current sense
element temperature is essentially impossible to measure
directly. Instead, a temperature sensor (a BJT for the ISL68124)
placed near the inductors is measured and the current sense
element (DCR) temperature is calculated from that
measurement. Calculating current sense element temperature is
equivalent to applying gain and offset corrections to the
temperature sensor measurement. The ISL68124 supports both
corrections.
Figure 14 depicts the block diagram of temperature
compensation. A BJT placed near the inductors used for DCR
sensing is monitored by the IC using the well known delta Vbe
method of temperature sensing. TSENSE is the direct measured
temperature of the BJT. Because the BJT is not directly sensing
DCR, corrections must be made so that TDCR reflects the true
DCR temperature. Corrections are applied according to the
relationship shown in Equation 1, where kSLOPE represents a
gain scaling and TOFFSET represents an offset correction. These
parameters are provided by the designer using the
PowerNavigator GUI:
(EQ. 1)
After TDCR has been determined, the compensated DCR value
can be determined according to Equation 2, where DCR25 is the
DCR at +25°C and TC is the temperature coefficient of copper
(3900 ppm/°C). TDCR = TACTUAL here:
DCR CORR = DCR 25   1 + T C   T ACTUAL – 25  
(EQ. 2)
Thus, the temperature compensated DCR is now used to
determine the actual value of current in the DCR sense element.
FN8796 Rev.2.00
June 16, 2017
kSLOPE
TOFFSET
TO TELEMETRY
TC
The ISL68124 supports inductor DCR sensing, which generally
requires temperature compensation due to the copper wire used
to form inductors. Copper has a positive temperature coefficient
of approximately 0.39%/°C. Because the voltage across the
inductor is sensed for the output current information, the sensed
current has the same positive temperature coefficient as the
inductor DCR.
T DCR = k SLOPE  T SENSE + T OFFSET
IPHASE#
TMONx
Vbe
VCCS
IC
TSENSE
FIGURE 14. BLOCK DIAGRAM OF TEMPERATURE COMPENSATION
In the physical PCB design, the temperature sense diode (BJT) is
placed close to the inductor of the phase that is never dropped
during automatic phase drop operation. Additionally, a filter
capacitor no larger than 500pF should be added near the IC
between each TEMPx pin and VCCS. This is shown in Figure 15.
IC
TMON1
OPTIONAL AUXILIARY
TEMPERATURE SENSE
VCCS
TMON0
OPTIONAL AUXILIARY
TEMPERATURE SENSE
SW1
SW2
SW3
SW0
L1
L2
L3
L0
Output 1
Output 0
FIGURE 15. RECOMMENDED PLACEMENT OF TEMPERATURE
SENSORS
Lossless Input Current and Power Sensing
Input current telemetry is provided using an input current
synthesizer. By using the IC’s ability to precisely determine its
operational conditions, input current can be synthesized to a high
degree of accuracy without the need for a lossy sense resistor.
Fine-tuning of offset and gain are provided for in the GUI. Note
that input current sense fine-tuning must be done after output
current sense setup is finalized. With a precise knowledge of
input current and voltage, input power can be computed.
Input current and power telemetry is accessed using PMBus and
easily monitored in the PowerNavigator GUI.
Page 14 of 46
ISL68124
Soft-Start Delay and Ramp Times
VIN
IC
40.2k
VINSEN
ADC
10nF
10k
FIGURE 16. INPUT VOLTAGE SENSE CONFIGURATION
Voltage Regulation
Output voltage is sensed through the remote sense differential
amplifier and digitized. From this point, the regulation loop is
entirely digital. Traditional PID controls are used in conjunction
with several enhanced methods to compensate the voltage
regulation loop and tune the transient response.
Current Feedback
Current feedback in a voltage regulator is often used to ease the
stability design of the voltage feedback path. Additionally, many
microprocessors require the voltage regulator to have a
controlled output resistance (known as load line or droop
regulation) and this is accomplished using current feedback.
For applications requiring droop regulation, the designer simply
specifies the output resistance desired using the PowerNavigator
GUI.
Current feedback stability benefits are available for rails that do
not specify droop regulation such as system agent. For these
applications, the designer can enable the AC current feedback in
the GUI. With this configuration, the DC output voltage will be
steady regardless of load current.
Power-On Reset (POR)
Initialization of the ISL68124 begins after VCC crosses its rising
POR threshold. When POR conditions are met, the internal 1.2V
LDO is enabled and basic digital subsystem integrity checks
begin. During this process, the controller will load the selected
user configuration from NVM as indicated by the CONFIG pin
resistor value, read VIN UVLO thresholds from memory, and start
the telemetry subsystem. With telemetry enabled, VIN can be
monitored to determine when it exceeds its user-programmable
rising UVLO threshold. When VCC and VIN satisfy their respective
voltage conditions, the controller is in its shutdown state. It will
transition to its active state and begin soft-start when the state of
EN0/EN1 command is at start-up. While in shutdown mode, the
PWM outputs are held in a high-impedance state to ensure the
drivers remain off.
FN8796 Rev.2.00
June 16, 2017
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for an output to ramp to its target value after the delay
period has expired. These features can be used as part of an
overall inrush current management strategy or to precisely
control how fast a load IC is turned on. The ISL68124 gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods. The soft-start
delay period begins when the EN pin is asserted and ends when
the delay time expires.
The soft-start delay and ramp-up/down times can be configured
using the PowerNavigator GUI. The device needs approximately
200µs after enable to initialize before starting to ramp up. When
the soft-start ramp period is set to 0ms, the output ramps up as
quickly as the output load capacitance and loop settings allow. It is
recommended to set the ramps to a non-zero value to prevent
inadvertent fault conditions due to excessive inrush current.
Stored Configuration Selection
As many as eight configurations can be stored and used at any
time using the on-board nonvolatile memory. Configurations are
assigned an identifier number between 0 and 7 at power-up. The
device will load the configuration indicated by the 1% resistor
value detected on the CONFIG pin. Resistor values are used to
indicate use of one of the eight possible configurations. Table 3
provides the resistor value corresponding to each configuration
identifier.
TABLE 3. RESISTOR VALUES TO CONFIGURATION MAPPING
R CONFIG
(Ω)
CONFIG
ID
6800
0
1800
1
2200
2
2700
3
3300
4
3900
5
4700
6
5600
7
Only the most recent configuration with a given number can be
loaded. The device supports a total of eight stored operations. As
an example, a configuration with the identifier 0 could be saved
eight times or configurations with all eight identifiers could be
stored one time each for a total of eight save operations.
PowerNavigator provides a simple interface to save and load
configurations.
Page 15 of 46
ISL68124
Fault Monitoring and Protection
The ISL68124 actively monitors temperature, input voltage, output
voltage, and output current to detect and report fault conditions.
Fault monitors trigger configurable protective measures to prevent
damage to a load. The power-good indicators, PG0/PG1, are
provided for linking to external system monitors.
A high level of flexibility is provided in the ISL68124 fault logic.
Faults can be enabled or disabled individually. Each fault type can
also be configured to either latch off or retry indefinitely.
Power-Good Signals
The PG0/PG1 pins are open-drain, power-good outputs that
indicate completion of the soft-start sequence and output
voltage of the associated rail within the expected regulation
range.
The PG pins can be associated or disassociated with a number of
the available fault types. This allows a system design to be tailored
for virtually any condition. In addition, these power-good
indicators will be pulled low when a fault (OCP or OVP) condition
or UV condition is detected on the associated rail.
Output Voltage Protection
Output voltage is measured at the load sensing points
differentially for regulation and the same measurement is used
for OVP and UVP. The fault thresholds are set using PMBus
commands. Figure 17 shows a simplified OVP/UVP block
diagram. The output voltage comparisons are done in the digital
domain.
The device responds to an output overvoltage condition by
disabling the output, declaring a fault, setting the SALRT pin,
setting the PG pin, and then pulsing the LFET until the output
voltage has dropped below the threshold. Similarly, the device
responds to an output undervoltage condition by disabling the
output, declaring a fault, setting the SALRT pin, and setting the
PG pin. The output will not restart until the EN pin is cycled
(unless the device is configured to retry).
In addition, the ISL68124 features open pin sensing protection to
detect an open of the output voltage sensing circuit. This open
pin is detected as an OVP condition, which suspends the
controller operation.
Output Current Protection
The ISL68124 offers a comprehensive overcurrent protection
scheme. Each phase is protected from both excessive peak
current and sustained current. In addition, the system is
protected from sustained total output overcurrent.
Figure 18 depicts a block diagram of the system total output
current protection scheme. In this scheme, the phase currents
are summed to form ISUM. ISUM is then fed to dual response
paths allowing the user to program separate LPF, threshold, and
response time. One path is intended to allow response more
quickly than the other path. With this system, the user can allow
high peak total current for a short time and a lower level of
current for a sustained time. Note that neither of these paths
affect PWM activity on a cycle-by-cycle basis. The characteristics
of each path are easily set in PowerNavigator.
In addition to total output current, the ISL68124 provides an
individual phase peak current limit that will act on PWM in a
cycle-by-cycle manner. This means that if a phase current is
detected to exceed the OC threshold, the phase PWM signal will
be inverted to move current away from the threshold. In addition
to limiting positive or negative peak current on a cycle-by-cycle
basis, individual phase OC can be configured to limit current
indefinitely or to declare a fault after a programmable number of
consecutive OC cycles. This feature is useful for applications
where a fault shutdown of the system would not be acceptable,
but, some ability to limit phase currents is desired. Figures 21
and 22 depict this operation. If configured for indefinite current
limit, the converter will act as a current source and VOUT will not
remain at its regulation point. It should be noted that in this case,
VOUT OV or UV protection action may occur, which could shut the
regulator down.
TOTAL OUTPUT CURRENT FAULT
FILTER
FAST SUM OC
COMPARE
TIMER
PH1 Current
Synthesizer
TIMER

ISUM
FILTER
FILTER
PHn Current
Synthesizer
LIMIT
TO
FAULT
BLOCK
DELAY
SLOW SUM OC
COMPARE
TIMER
TIMER
FILTER
ACT
LIMIT
ACT
TO
FAULT
BLOCK
DELAY
PHASE PEAK CURRENT LIMITING AND FAULT
COMPARE
VSENx
DIGITAL OV
COMPARATOR
IC
ADC
RGNDx
+
-
IPHASEn
+PEAK
LIMIT
OCCOUNT
COMPARE
COUNT
fsw clk
+
THRESHOLD
REGISTER
Switching
Period
Count
POSITIVE PEAK LIMITING
THRESHOLD
REGISTER
SoC
May be set
for indefinite
limiting but
no fault
assertion
COUNT
fsw clk
DIGITAL UV
COMPARATOR
-PEAK
LIMIT
Switching
Period
Count
May be set
for indefinite
limiting but
no fault
assertion
UCCOUNT
NEGATIVE PEAK LIMITING
ACT
TO
FAULT
BLOCK
Pulse by
pulse
limit
ACT
TO
FAULT
BLOCK
Pulse by
pulse
limit
FIGURE 18. OCP FUNCTIONAL DIAGRAM
FIGURE 17. OVP, UVP COMPARATORS
FN8796 Rev.2.00
June 16, 2017
Page 16 of 46
ISL68124
Examples of OCP_Fast and OCP_Slow waveforms are shown in
Figures 19 and 20.
NEGATIVE_CURRENT_LIMITING_PER_PHASE
OCP_FAST_THRESHOLD
PWM
OCP_SLOW_THRESHOLD
PGOOD
OCP_FAST COUNTER
FILTER TIME CONSTANT
TWARN
PWM
FIGURE 22. NEGATIVE PEAK PHASE CURRENT LIMITING
PGOOD
FIGURE 19. OCP_FAST
OCP_FAST_THRESHOLD
OCP_SLOW_THRESHOLD
FILTER TIME CONSTANT
OCP_SLOW COUNTER
PWM
Smart Power Stage OC Fault Detect
Intersil Smart Power Stage (SPS) devices will output a large
signal on their IMON lines if peak current exceeds their
preprogrammed threshold. (For more detail about this
functionality, refer to the relevant SPS datasheet.) The ISL68124
is equipped to detect this fault flag and immediately shut down.
This detector is enabled on the GUI Overcurrent Fault setup
screen.
This feature functions by detecting signals that exceed the
current sense ADC full scale range. If this detector is disabled
while using an Intersil SPS, the SPS Fault# signal must be
connected to the controller Enable pin of the associated rail. This
will ensure that an SPS OC event will be detected and the
converter will shut down.
Thermal Monitoring (TWARN) and Protection
PGOOD
FIGURE 20. OCP_SLOW
The TWARN pin indicates the temperature status of the voltage
regulator. The TWARN pin is an open-drain output and an
external pull-up resistor is required. This signal is valid only after
the controller is enabled.
The TWARN signal can be used to inform the system that the
temperature of the voltage regulator is too high and the load
should reduce its power consumption. TWARN only indicates a
thermal warning, not a fault.
POSITIVE_CURRENT_LIMITING_PER_PHASE
PWM
PGOOD
The thermal monitoring function block diagram is shown in
Figure 23 on page 18. The ISL68124 has two over-temperature
thresholds, which allow both warning and fault indications. Each
temperature sensor threshold can be independently
programmed in the PowerNavigator GUI. Figure 24 on page 18
shows the thermal warning to TWARN and Figure 25 on page 18
shows the over-temperature fault to shutdown. PGOOD and
TWARN can be configured to indicate these warning and fault
thresholds through the PowerNavigator GUI.
TWARN
FIGURE 21. POSITIVE PEAK PHASE CURRENT LIMITING
FN8796 Rev.2.00
June 16, 2017
Page 17 of 46
ISL68124
TELEMETRY
CONTROL
TEMP
SENSORS
TMONx
DELTA
VBE
Layout and Design Considerations
IC
TMAX
ADC
TWARN
VCCS
TEMP
MONITOR
FIGURE 23. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION
In addition to TB379, the following PCB layout and design
strategies are intended to minimize noise coupling and the
impact of board parasitic impedances on converter performance.
In addition, these strategies will optimize the heat dissipating
capabilities of the printed circuit board. This section highlights
some important practices, which should be followed during the
layout process.
Table 4 provides general guidance on best practices related to
pin noise sensitivity. Good engineering judgment is required to
implement designs based on criteria specific to the situation.
TABLE 4. PIN DESIGN AND/OR LAYOUT CONSIDERATIONS
PIN NAME
NOISE
SENSITIVE
VINSEN
Yes
Connects to the resistor divider between
VIN and GND (see Figure 16 on page 15).
Filter VINSEN with 10nF to GND
RGNDx
VSENx
Yes
Treat each of the remote voltage sense
pairs as differential signals in the PCB
layout. They should be routed side by side
on the same layer. They should not be
routed in proximity to noisy signals like
PWM or Phase. Tie to ground when not
used.
PGx
No
Open-drain. 3.3V maximum pull-up
voltage. Tie to ground when not used.
SCL, SDA,
SALRT
Yes
50kHz to 2MHz signal during
communication, pair up with SALRT and
route carefully. 20 mils spacing within
SDA, SALRT, and SCL; and more than
30 mils to all other signals. Refer to the
SMBus design guidelines and place
proper termination resistance for
impedance matching. Tie to ground when
not used.
TMONx
Yes
When diode sensing is used, VCCS is the
return path for the delta Vbe currents. Use
a separate VCCS route specifically for
diode temp sense. A filter capacitor no
greater than 500pF should be placed
between each TEMP pin and the VCCS pin
near the IC. Tie to ground when not used.
TWARN
No
Open-drain. 3.3V maximum pull-up
voltage.
VCC
Yes
Place at least 2.2µF MLCC decoupling
capacitor directly at the pin.
VCCS
Yes
Place 4.7µF MLCC decoupling capacitor
directly at the pin.
PWMx
NO
Avoid routing near noise sensitive analog
lines such as current sense or voltage
sense.
HIGH OT THRESHOLD
LOW OT THRESHOLD
PWM
PGOOD
TWARN
FIGURE 24. THERMAL WARNING TO TWARN
HIGH OT THRESHOLD
LOW OT THRESHOLD
PWM
PGOOD
TWARN
FIGURE 25. OVER-TEMPERATURE FAULT
FN8796 Rev.2.00
June 16, 2017
DESCRIPTION
Page 18 of 46
ISL68124
TABLE 4. PIN DESIGN AND/OR LAYOUT CONSIDERATIONS (Continued)
PIN NAME
NOISE
SENSITIVE
DESCRIPTION
CSx
CSRTNx
Yes
Treat each of the current sense pairs as
differential signals in the PCB layout. They
should be routed side by side on the same
layer. They should not be routed in
proximity to noisy signals like PWM or
Phase. Proper routing of current sense is
perhaps the most critical of all the layout
tasks. Tie to ground when not used.
GND
Yes
This EPAD is the return of PWM output
drivers. Use four or more vias to directly
connect the EPAD to the power ground
plane.
General
Comments
PMBus Operation
The ISL68124 PMBus slave address is pin selectable using the
ADDRESS pin and resistor value described in Table 2 on page 11.
For proper operation, users should follow the PMBus protocol, as
shown in “PMBus Protocol” on page 20. The supported PMBus
addresses are in 8-bit format (including write and read bit),
shown in Table 5. The least significant bit of the 8-bit address is
for write (0h) and read (1h). PMBus commands are in the range
from 0x00h to 0xFFh. For the ISL68124, Page 0 corresponds to
Output 0 and Page 1 to Output 1. For reference purposes, the
7-bit format addresses are also summarized in Table 5.
TABLE 5. PMBus 8-BIT AND 7-BIT FORMAT ADDRESS (HEX)
The layer next to the top or bottom layer is
preferred to be ground layers, while the
signal layers can be sandwiched in the
ground layers if possible.
8-BIT
7-BIT
8-BIT
7-BIT
8-BIT
7-BIT
8-BIT
7-BIT
80/81
40
A0/A1
50
B0/B1
58
C0/C1
60
82/83
41
A2/A3
51
B2/B3
59
C2/C3
61
84/85
42
A4/A5
52
B4/B5
5A
C4/C5
62
86/87
43
A6/A7
53
B6/B7
5B
C6/C7
63
88/89
44
A8/A9
54
B8/B9
5C
C8/C9
64
8A/8B
45
AA/AB
55
BA/BB
5D
CA/CB
65
8C/8D
46
AC/AD
56
BC/BD
5E
CC/CD
66
8E/8F
47
AE/AF
57
BE/BF
5F
CE/CF
67
The PMBus data formats follow PMBus specification version 1.3
and SMBus version 2.0.
Basic PMBus telemetry commands are summarized in “PMBus
Command Summary” on page 21.
3.3V
VCC
1.2V
Tel ADC Customer Start-up
Fac
PLL
PROGRAM CONFIGURATION
USE PREVIOUS PROGRAMMED
VCCS
Config LOCKED Initialized Config Diagnostics (BT, TMAX, PS, DE, etc.)
CONFIGURATION FOR STAR-UP AND OPERATION
LOAD
DONE
LOAD
DONE
PROGRAM CONFIGURATION
PROGRAM CONFIGURATION
VCCS
(BT, TMAX, PS, DE, etc.)
(BT, TMAX, PS, DE, etc.)
POR
~30ms
ENABLE
INDEFINITELY
PMBus
COMMAND
PMBus
COMMAND
PMBus
COMMAND
PMBus
COMMAND
VOUT
FIGURE 26. SIMPLIFIED PMBus INITIALIZATION TIMING DIAGRAM
FN8796 Rev.2.00
June 16, 2017
Page 19 of 46
ISL68124
PMBus Protocol
1. Send Byte Protocol
S: Start Condition
A: Acknowledge (“0”)
S
7+1
1
Slave Address_0
A
1
8
1
A
PEC
A P
8
Command Code
1
N: Not Acknowledge (“1”)
W: Write (“0”)
RS: Repeated Start Condition
R: Read (“1”)
Optional 9 bits for SMBus/PMBus
NOT used in I2C
PEC: Packet Error Checking
P: Stop Condition
Example command: 03h Clear Faults
(This will clear all of the bits in Status Byte for the selected rail)
Acknowledge or DATA from Slave,
ISL68124 Controller
Not used for 1-byte word
2. Write Byte/Word Protocol
1
7+1
S
Slave Address_0
1
8
A
Command Code
1
8
1
8
1
8
1
1
A
Low Data Byte
A
High Data Byte
A
PEC
A
P
Optional 9 bits for SMBus/PMBus
NOT used in I2C
Example command: 21h VOUT_COMMAND
3. Read Byte/Word Protocol
1
7+1
1
8
1
S
Slave Address_0
A
Command Code
A
1
7+1
RS
Slave Address_1
Not used for 1-byte word read
1
8
1
8
1
8
1
1
A
Low Data Byte
A
High Data Byte
A
PEC
N
P
Optional 9 bits for SMBus/PMBus
NOT used in I2C
Example command: 8B READ_VOUT (Two words, read voltage of the selected rail).
STOP (P) bit is NOT allowed before the repeated START condition when “reading” contents of a register.
4. Group Command Protocol - No more than one command can be sent to the same Address
1
7+1
S
Slave ADDR1_0
1
7+1
Slave ADDR2_0
S
1
RS
1
8
A
Command Code
A
Low Data Byte
1
8
1
8
1
8
1
Data Byte
A
PEC
A
Command Code
A
7+1
1
Slave ADDR3_0
A
1
8
A
8
8
Command Code
Low Data Byte
A
1
8
1
8
1
A
High Data Byte
A
PEC
A
1
8
1
8
1
1
A
High Data Byte
A
PEC
A
P
Optional 9 bits for SMBus/PMBus
NOT used in I2C
5. Alert Response Address (ARA, 0001_1001, 25h) for SMBus and PMBus, not used for I2C
1
S
7+1
ALERT Addr_1
1
A
7+1
Slave_Address_1
1
8
1
1
A
PEC
A
P
Optional 9 bits for SMBus/PMBus
NOT used in I2C
FN8796 Rev.2.00
June 16, 2017
Page 20 of 46
ISL68124
PMBus Command Summary
CODE
COMMAND NAME
DESCRIPTION
DATA
TYPE FORMAT
DEFAULT
VALUE
DEFAULT SETTING
00h PAGE
Selects Output 0, 1, or both
R/W
Bit
00h
Page 0
01h OPERATION
Enable/disable, margin settings
R/W
Bit
08h
Off
02h ON_OFF_CONFIG
On/off configuration settings
R/W
Bit
16h
ENABLE pin control
03h CLEAR_FAULTS
Clears all fault bits in all registers and releases the Write N/A
SALRT pin
N/A
10h WRITE_PROTECT
Write protection to sets of commands
R/W
Bit
00h
No write protection
20h VOUT_MODE
Defines format for output voltage related
commands
Read Bit
40h
Direct format
21h VOUT_COMMAND
Sets the nominal VOUT target
R/W
Direct
0384h
900mV
22h VOUT_TRIM
Applies trim voltage to VOUT set-point
R/W
Direct
0000h
0mV
24h VOUT_MAX
Absolute maximum voltage setting
R/W
Direct
08FCh
2300mV
25h VOUT_MARGIN_HIGH
Sets VOUT target during margin high
R/W
Direct
0640h
1600mV
26h VOUT_MARGIN_LOW
Sets VOUT target during margin low
R/W
Direct
00FAh
250mV
27h VOUT_TRANSITION_RATE Slew rate setting for VOUT changes
R/W
Direct
0064h
10mV/µs
28h VOUT_DROOP
Sets the load line (V/I slope) resistance for the
output
R/W
Direct
0000h
0µV/A
2Bh VOUT_MIN
Absolute minimum target voltage setting
R/W
Direct
0000h
0V
40h VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault threshold
R/W
Direct
076Ch
1900mV
44h VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault threshold
R/W
Direct
0000h
0mV
4Fh OT_FAULT_LIMIT
Sets the over-temperature fault threshold
R/W
Direct
007Dh
+125°C
51h OT_WARN_LIMIT
Sets the over-temperature warn threshold
R/W
Direct
07D0h
+2000°C
55h VIN_OV_FAULT_LIMIT
Sets the VIN overvoltage fault threshold
R/W
Direct
36B0h
14,000mV
59h VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault threshold
R/W
Direct
1F40h
8,000mV
5Bh IIN_OC_FAULT_LIMIT
Sets the IIN overcurrent fault threshold
R/W
Direct
0032h
50A
60h TON_DELAY
Sets the delay time from enable to VOUT rise
R/W
Direct
0014h
200µs
61h TON_RISE
Turn-on rise time
R/W
Direct
01F4h
500µs
64h TOFF_DELAY
Turn-off delay time
R/W
Direct
0000h
0µs
65h TOFF_FALL
Turn-off fall time
R/W
Direct
01F4h
500µs
78h STATUS_BYTE
First byte of STATUS_WORD
Read Bit
N/A
N/A
79h STATUS_WORD
Summary of critical faults
Read Bit
N/A
N/A
7Ah STATUS_VOUT
Reports VOUT faults
Read Bit
N/A
N/A
7Bh STATUS_IOUT
Reports IOUT faults
Read Bit
N/A
N/A
7Ch STATUS_INPUT
Reports input faults
Read Bit
N/A
N/A
7Dh STATUS_TEMPERATURE
Reports temperature warnings/faults
Read Bit
N/A
N/A
7Eh STATUS_CML
Reports communication, memory, logic errors
Read Bit
N/A
N/A
80h STATUS_MFR_SPECIFIC
Reports specific events
Read Bit
N/A
N/A
88h READ_VIN
Reports input voltage measurement
Read Direct
N/A
N/A
89h READ_IIN
Reports input current measurement
Read Direct
N/A
N/A
8Bh READ_VOUT
Reports output voltage measurement
Read Direct
N/A
N/A
8Ch READ_IOUT
Reports output current measurement
Read Direct
N/A
N/A
FN8796 Rev.2.00
June 16, 2017
Page 21 of 46
ISL68124
PMBus Command Summary (Continued)
CODE
COMMAND NAME
DATA
TYPE FORMAT
DESCRIPTION
DEFAULT
VALUE
DEFAULT SETTING
8Dh READ_TEMPERATURE_1
Reports power stage temperature measurement
Read Direct
N/A
N/A
8Eh READ_TEMPERATURE_2
Reports TMON0 temperature measurement
Read Direct
N/A
N/A
8Fh READ_TEMPERATURE_3
Reports TMON1 temperature measurement
Read Direct
N/A
N/A
96h READ_POUT
Reports output power
Read Direct
N/A
N/A
97h READ_PIN
Reports input power
Read Direct
N/A
N/A
98h PMBUS_REVISION
Reports specific events
Read Bit
33h
Revision 1.3
ADh IC_DEVICE_ID
Reports device identification information
Block Bit
Read
49D21E00h
ISL68124
AEh IC_DEVICE_REV
Reports device revision information
Block Bit
Read
N/A
N/A
E7h APPLY_SETTINGS
Instructs device to apply PMBus setting changes
Write Bit
01h
N/A
F2h RESTORE_CONFIG
Allows selection of configurations from NVM
Write Bit
N/A
N/A
PMBus Use Guidelines
All commands can be read at any time.
Always disable the outputs when writing commands that change device settings. Exceptions to this rule are commands intended to be
written while the device is enabled, for example, OPERATION.
PMBus Data Formats
Direct (D)
The Direct data format is a 2-byte two’s complement binary integer.
Bit Field (BIT)
Break down of Bit Field is provided in “PMBus Command Detail” on page 23.
FN8796 Rev.2.00
June 16, 2017
Page 22 of 46
ISL68124
PMBus Command Detail
PAGE (00h)
Definition: Selects Controller 0, Controller 1, or both Controllers 0 and 1 to receive commands. All commands following this command
will be received and acted on by the selected controller or controllers.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Default Value: 00h
Units: N/A
COMMAND
PAGE (00h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
BITS 7:4
BITS 3:0
PAGE
0000
0000
0
0000
0001
1
1111
1111
Both
OPERATION (01h)
Definition: Sets enable state when configured for PMBus enable. Sets output voltage margin settings. The device always acts on faults
during margin. The following table reflects the valid settings for the device.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Default Value: 08h
COMMAND
OPERATION (01h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
See Following Table
Default Value
BIT NUMBER
Bits 7:6
Bits 5:4
PURPOSE
Enable/Disable
VOUT Source
0
1
BIT VALUE
00
MEANING
Immediate off (decay)
01
Soft-off (Use TOFF_DELAY and TOFF_FALL)
10
On
00
VOUT_COMMAND
01
VOUT_MARGIN_LOW
10
VOUT_MARGIN_HIGH
11
Not used
Bits 3:2
Margin Response
10
Act on faults
Bit 1:0
Not Used
0
Not used
FN8796 Rev.2.00
June 16, 2017
Page 23 of 46
ISL68124
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation of the OPERATION command and the ENABLE pin (EN).
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Default Value: 16h (ENABLE pin control)
COMMAND
ON_OFF_CONFIG (02h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
0
BIT NUMBER
PURPOSE
0
0
0
0
BIT VALUE
MEANING
7:5
Not Used
000
Not used
4:2
Sets the Source of Enable
000
Device always enabled regardless of pin or OPERATION
command state
1
Enable Pin Polarity
0
Enable Pin Turn Off Action
101
Device starts from Enable pin only
110
Device starts from OPERATION command only
111
Device starts from OPERATION command AND Enable pin
1
Active high only
1
Turn off immediately with decay
0
Use programmed TOFF_DELAY and TOFF_FALL settings
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exits, the
bit will reassert immediately. This command will not restart a device if it is shut down, it will only clear the faults.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Default Value: N/A
Units: N/A
FN8796 Rev.2.00
June 16, 2017
Page 24 of 46
ISL68124
WRITE_PROTECT (10h)
Definition: Sets the write protection of certain configuration commands.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Default Value: 00h (Enable all writes)
Units: N/A
COMMAND
WRITE_PROTECT (10h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
4
3:0
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
See Following Table
Default Value
0
0
0
0
SETTINGS
0
PROTECTION
40h
Disables all writes except to WRITE_PROTECT, OPERATION, CLEAR_FAULTS, PAGE
20h
Disables all writes except all above plus ON_OFF_CONFIG and VOUT_COMMAND, VOUT_TRIM
00h
Enables all writes
NOTE: Any settings other than the three shown above will result in an invalid data fault.
VOUT_MODE (20h)
Definition: Returns the supported VOUT mode. This device only supports absolute direct mode.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: 40h
Units: N/A
Equation: N/A
Range: N/A
VOUT_COMMAND (21h)
Definition: Sets the value of VOUT when the OPERATION command is configured for nominal operation.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0384h (900mV)
Units: mV
Equation: VOUT_COMMAND = (Direct value)
Range: VOUT_MIN to VOUT_MAX
COMMAND
VOUT_COMMAND (21h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
Unsigned Integer
0
0
0
0
0
0
1
1
1
Page 25 of 46
ISL68124
VOUT_TRIM (22h)
Definition: Sets a fixed trim voltage to the output voltage command value. This command is typically used to calibrate a device in the
application circuit.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0000h (0mV)
Units: mV
Equation: VOUT_TRIM = (Direct value)
Range: ±250mV
COMMAND
VOUT_TRIM (22h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
Default Value
Two’s Complement Integer
0
0
0
0
0
0
0
0
0
0
VOUT_MAX (24h)
Definition: Sets the maximum allowed VOUT target regardless of any other commands or combinations.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 08FCh (2300mV)
Units: mV
Equation: VOUT_MAX = (Direct value)
Range: 0 to 3300mV
COMMAND
VOUT_MAX (24h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
1
1
1
1
1
0
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
0
1
Page 26 of 46
ISL68124
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of VOUT when the OPERATION command is configured for margin high.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0640h (1600mV)
Units: mV
Equation: VOUT_MARGIN_HIGH = (Direct value)
Range: VOUT_MIN to VOUT_MAX
COMMAND
VOUT_MARGIN_HIGH (25h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
1
0
0
0
0
0
0
Function
Default Value
Unsigned Integer
0
0
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of VOUT when the OPERATION command is configured for margin low.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 00FAh (250mV)
Units: mV
Equation: VOUT_MARGIN_LOW = (Direct value)
Range: VOUT_MIN to VOUT_MAX
COMMAND
VOUT_MARGIN_LOW (26h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
1
1
1
0
1
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
0
1
Page 27 of 46
ISL68124
VOUT_TRANSITION_RATE (27h)
Definition: Sets the output voltage rate of change during regulation. Changes to this setting require a write to the APPLY_SETTINGS
command before the change will take effect.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0064h (10mV/µs)
Units: µV/µs
Equation: VOUT_TRANSITION_RATE = (Direct value)*100
Range: 100µV/µs to 100mV/µs
COMMAND
VOUT_TRANSITION_RATE (27h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
1
0
0
1
0
0
Function
Default Value
Unsigned Integer
0
0
VOUT_DROOP (28h)
Definition: Sets the output voltage rate of change during regulation. Changes to this setting require a write to the APPLY_SETTINGS
command before the change will take effect.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0000h (0µV/A)
Units: µV/A
Equation: VOUT_DROOP = (Direct value)*10
Range: 0 to 16mV/A
COMMAND
VOUT_DROOP (28h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
0
0
Page 28 of 46
ISL68124
VOUT_MIN (2Bh)
Definition: Sets the minimum allowed VOUT target regardless of any other commands or combinations.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0000h (0mV)
Units: mV
Equation: VOUT_MIN = (Direct value)
Range: 0V to VOUT_MAX
COMMAND
VOUT_MIN (2Bh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Default Value
Unsigned Integer
0
0
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the output overvoltage fault threshold. Changes to this setting require a write to the APPLY_SETTINGS command before
the change will take effect.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 076Ch (1900mV)
Units: mV
Equation: VOUT_OV_FAULT_LIMIT = (Direct value)
Range: 0V to VOUT_MAX
COMMAND
VOUT_OV_FAULT_LIMIT (40h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
1
1
0
1
1
0
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
1
0
Page 29 of 46
ISL68124
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0000h (0mV)
Units: mV
Equation: VOUT_UV_FAULT_LIMIT = (Direct value)
Range: 0V to VOUT_MAX
COMMAND
VOUT_UV_FAULT_LIMIT (44h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Default Value
Unsigned Integer
0
0
OT_FAULT_LIMIT (4Fh)
Definition: Sets the power stage over-temperature fault limit.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 007Dh (+125°C)
Units: °C
Equation: OT_FAULT_LIMIT = (Direct value)
Range: 0°C to +2000°C
COMMAND
OT_FAULT_LIMIT (4Fh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
1
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Two’s Complement Integer
0
0
0
0
0
0
0
0
0
1
Page 30 of 46
ISL68124
OT_WARN_LIMIT (51h)
Definition: Sets the system over-temperature warn limit. If any measured temperature exceeds this value, the device will:
• Set the TEMPERATURE bit in STATUS_BYTE and STATUS_WORD
• Set the OT_WARNING bit in STATUS_TEMPERATURE
• Set the SALRT pin
• Set the TWARN pin
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 07D0h (+2000°C)
Units: °C
Equation: OT_WARN_LIMIT = (Direct value)
Range: 0°C to +2000°C
COMMAND
OT_WARN_LIMIT (51h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
0
1
0
0
0
0
Function
Default Value
Two’s Complement Integer
1
1
1
1
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold. Changes to this setting requires a write to the APPLY_SETTINGS command before
the change will take effect.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 36B0h (14,000mV)
Units: mV
Equation: VIN_OV_FAULT_LIMIT = (Direct value)
Range: 0mV to 16,000mV
COMMAND
VIN_OV_FAULT_LIMIT (55h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
0
0
0
Unsigned Integer
0
0
1
1
0
1
1
0
1
Page 31 of 46
ISL68124
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold. Also referred to as Undervoltage Lockout (UVLO). Changes to this setting require a
write to the APPLY_SETTINGS command before the change will take effect.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 1F40h (8,000mV)
Units: mV
Equation: VIN_UV_FAULT_LIMIT = (Direct value)
Range: 0mV to 16,000mV
COMMAND
VIN_UV_FAULT_LIMIT (59h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
0
Unsigned Integer
0
0
0
1
1
1
1
1
0
IIN_OC_FAULT_LIMIT (5Bh)
Definition: Sets the IIN overcurrent fault threshold. Changes to this setting require a write to the APPLY_SETTINGS command before the
change will take effect.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0032h (50A)
Units: A
Equation: IIN_OC_FAULT_LIMIT = (Direct value)
Range: 0A to 50A
COMMAND
IIN_OC_FAULT_LIMIT (5Bh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
1
1
0
0
1
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
0
0
Page 32 of 46
ISL68124
TON_DELAY (60h)
Definition: Sets the delay time of VOUT during enable.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0014h (200µs)
Units: µs
Equation: TON_DELAY = (Direct value)*10
Range: 200µs to 655,340µs
COMMAND
TON_DELAY (60h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
0
Unsigned Integer
Default Value
0
0
0
0
0
0
0
0
0
TON_RISE (61h)
Definition: Sets the rise time of VOUT during enable. Changes to this setting require a write to the APPLY_SETTINGS command before
the change will take effect. This function uses the value of VOUT to calculate rise time, so APPLY_SETTINGS must be sent after any
change to the VOUT target for accurate rise time.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 01F4h (500µs)
Units: µs
Equation: TON_RISE = (Direct value)
Range: 0µs to 10,000µs
COMMAND
TON_RISE (61h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
1
1
0
1
0
0
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
Unsigned Integer
1
1
Page 33 of 46
ISL68124
TOFF_DELAY (64h)
Definition: Sets the delay time of VOUT during disable.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 0000h (0µs)
Units: µs
Equation: TOFF_DELAY = (Direct value)*10
Range: 0µs to 100,000µs
COMMAND
TOFF_DELAY (64h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Unsigned Integer
Default Value
0
0
TOFF_FALL (65h)
Definition: Sets the fall time of VOUT during disable. Changes to this setting require a write to the APPLY_SETTINGS command before
the change will take effect. This function uses the value of VOUT to calculate fall time, so APPLY_SETTINGS must be sent after any
change to the VOUT target for accurate fall time.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Default Value: 01F4h (500µs)
Units: µs
Equation: TOFF_FALL = (Direct value)
Range: 0µs to 10,000µs
COMMAND
TOFF_FALL (65h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
FN8796 Rev.2.00
June 16, 2017
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
1
0
0
Unsigned Integer
0
0
0
0
0
0
0
1
1
Page 34 of 46
ISL68124
STATUS_BYTE (78h)
Definition: Returns a summary of the unit’s fault status. Based on the information in this byte, the host can get more information by
reading the appropriate status registers. A fault in either output will be reported here.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_BYTE (78h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
7
Not Used
Not used
6
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory, or logic fault has occurred.
0
None of the Above
A status change other than those listed above has occurred.
FN8796 Rev.2.00
June 16, 2017
Page 35 of 46
ISL68124
STATUS_WORD (79h)
Definition: Returns a summary of the device’s fault status. Based on the information in these bytes, the host can get more information
by reading the appropriate status registers. A fault in either output will be reported here. The low byte of the STATUS_WORD contains
the same information as the STATUS_BYTE (78h) command.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_WORD (79h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
See Following Table
BIT NUMBER
STATUS BIT NAME
MEANING
15
VOUT
An output voltage fault has occurred.
14
IOUT
An output current fault has occurred.
13
INPUT
An input voltage fault has occurred.
12
MFR_SPECIFIC
A manufacturer specific event has occurred.
11
POWER_GOOD #
The POWER_GOOD signal, if present, is negated. (Note 8)
Not Used
Not used
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory, or logic fault has occurred.
0
None of the Above
A status change other than those listed above has occurred.
10:7
6
NOTE:
8. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.
FN8796 Rev.2.00
June 16, 2017
Page 36 of 46
ISL68124
STATUS_VOUT (7Ah)
Definition: Returns a summary of output voltage faults.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_VOUT (7Ah)
Format
Bit Field
Bit Position
7
6
5
Access
R
R
R
Function
4
3
2
1
0
R
R
R
R
R
See Following Table
BIT NUMBER
STATUS BIT NAME
7
6:5
MEANING
VOUT_OV_FAULT
Indicates an output overvoltage fault.
Not Used
Not used
4
VOUT_UV_FAULT
Indicates an output undervoltage fault.
3
VOUT_MAX Warning
Indicates an output voltage maximum warning.
Not Used
Not used
2:0
STATUS_IOUT (7Bh)
Definition: Returns a summary of output current faults.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_IOUT (7Bh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Function
See Following Table
BIT NUMBER
MEANING
7
An output overcurrent fault has occurred.
6
An output overcurrent and undervoltage fault has occurred.
5:4
3
2:0
FN8796 Rev.2.00
June 16, 2017
Not used
A current share fault has occurred.
Not used
Page 37 of 46
ISL68124
STATUS_INPUT (7Ch)
Definition: Returns a summary of input voltage faults.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_INPUT (7Ch)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Function
See Following Table
BIT NUMBER
MEANING
7
6:5
An input overvoltage fault has occurred.
Not used
4
An input undervoltage fault has occurred. This fault is initially masked until VIN exceeds the UV threshold.
3
Not used
2
An input overcurrent fault has occurred.
1:0
Not used
STATUS_TEMPERATURE (7Dh)
Definition: Returns a summary of temperature related faults.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_TEMPERATURE (7Dh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Function
See Following Table
BIT NUMBER
MEANING
7
An over-temperature fault has occurred.
6
An over-temperature warning has occurred.
5
Not used
4
An under-temperature fault has occurred.
3:0
FN8796 Rev.2.00
June 16, 2017
Not used
Page 38 of 46
ISL68124
STATUS_CML (7Eh)
Definition: Returns a summary of any communications, logic, and/or memory errors.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_CML (7Eh)
Format
Bit Field
Bit Position
7
6
5
Access
R
R
R
Function
4
3
2
1
0
R
R
R
R
R
See Following Table
BIT NUMBER
MEANING
7
Invalid or unsupported PMBus Command was received.
6
The PMBus command was sent with invalid or unsupported data.
5
A packet error was detected in the PMBus command.
4
Memory fault detected.
3
Processor fault detected.
2
Not used
1
A communication fault other than the ones listed in this table has occurred.
0
A memory or logic fault not listed above was detected.
STATUS_MFR_SPECIFIC (80h)
Definition: Returns the status of specific information detailed as follows:
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: N/A
Units: N/A
COMMAND
STATUS_MFR_SPECIFIC (80h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Function
See Following Table
BIT
MEANING
7:2
Not used
1
OTP NVM memory is full.
0
Not used
FN8796 Rev.2.00
June 16, 2017
Page 39 of 46
ISL68124
READ_VIN (88h)
Definition: Returns the input voltage reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: mV
Equation: READ_VIN = (Direct value)
COMMAND
READ_VIN (88h)
Format
Direct
Bit Position
15
14
13
12
11
10
Access
R
R
R
R
R
R
Function
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
Two’s Complement Integer
READ_IIN (89h)
Definition: Returns the input current reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: A
Equation: READ_IIN = (Direct value)/100
COMMAND
READ_IIN (89h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Two’s Complement Integer
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: V
Equation: READ_VOUT = (Direct value)
COMMAND
READ_VOUT (8Bh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
FN8796 Rev.2.00
June 16, 2017
Two’s Complement Integer
Page 40 of 46
ISL68124
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: A
Equation: READ_IOUT = (Direct value)/10
COMMAND
READ_IOUT (8Ch)
Format
Direct
Bit Position
15
14
13
12
11
10
Access
R
R
R
R
R
R
Function
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
Two’s Complement Integer
READ_TEMPERATURE_1 (8Dh)
Definition: Returns the temperature reading of the power stage.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_1 = (Direct value)
COMMAND
READ_TEMPERATURE_1 (8Dh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Two’s Complement Integer
READ_TEMPERATURE_2 (8Eh)
Definition: Returns the temperature reading from a remote diode connected to TMON0 when configured for diode sensing.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_2 = (Direct value)
COMMAND
READ_TEMPERATURE_2 (8Eh)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
FN8796 Rev.2.00
June 16, 2017
Two’s Complement Integer
Page 41 of 46
ISL68124
READ_TEMPERATURE_3 (8Fh)
Definition: Returns the temperature reading from a remote diode connected to TMON1 when configured for diode sensing.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_3 = (Direct value)
COMMAND
READ_TEMPERATURE_3 (8Fh)
Format
Direct
Bit Position
15
14
13
12
11
10
Access
R
R
R
R
R
R
Function
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
Two’s Complement Integer
READ_POUT (96h)
Definition: Returns the output power.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: W
Equation: READ_POUT = (Direct value)
COMMAND
READ_POUT (96h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Two’s Complement Integer
READ_PIN (97h)
Definition: Returns the input power.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Direct
Type: Read Only
Default Value: N/A
Units: W
Equation: READ_PIN = (Direct value)
COMMAND
READ_PIN (97h)
Format
Direct
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
FN8796 Rev.2.00
June 16, 2017
Two’s Complement Integer
Page 42 of 46
ISL68124
PMBUS_REVISION (98h)
Definition: Returns the revision of the PMBus Specification to which the device is compliant.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Default Value: 33h (Part 1 Revision 1.3, Part 2 Revision 1.3)
Units: N/A
COMMAND
PMBUS_REVISION (98h)
Format
Bit Field
Bit Position
7
6
5
Access
R
R
R
Function
Default Value
4
3
2
1
0
R
R
R
R
R
0
1
1
See Following Table
0
0
1
1
0
BITS 7:4
PART 1 REVISION
BITS 3:0
PART 2 REVISION
0000
1.0
0000
1.0
0001
1.1
0001
1.1
0010
1.2
0010
1.2
0011
1.3
0011
1.3
IC_DEVICE_ID (ADh)
Definition: Returns device identification information.
Paged or Global: Global
Data Length in Bytes: 4
Data Format: Bit Field
Type: Block Read
Default Value: 49D21E00h
Units: N/A
COMMAND
IC_DEVICE_ID (ADh)
Format
Block Read
Byte Position
3
2
1
0
Function
MFR Code
ID High Byte
ID Low Byte
Reserved
Default Value
49h
D2h
1Eh
00h
IC_DEVICE_REV (AEh)
Definition: Returns device revision information.
Paged or Global: Global
Data Length in Bytes: 4
Data Format: Bit Field
Type: Block Read
Default Value: N/A
Units: N/A
COMMAND
IC_DEVICE_REV (AEh)
Format
Block Read
Bit Position
23:16
15:8
7:4
3:0
Function
Firmware Revision
Factory Configuration
Chip Foundry Site
IC Revision
Default Value
N/A
N/A
N/A
N/A
FN8796 Rev.2.00
June 16, 2017
Page 43 of 46
ISL68124
APPLY_SETTINGS (E7h)
Definition: Instructs the controller to use new PMBus parameters. Send 01h to this command after making one or more changes to
certain PMBus threshold commands that require rescaling of operational values. The commands that require this are
VOUT_TRANSITION_RATE, VOUT_DROOP, VOUT_OV_FAULT_LIMIT, VIN_OV_FAULT_LIMIT, VIN_UV_FAULT_LIMIT, IIN_OC_FAULT_LIMIT,
TON_RISE, and TOFF_FALL.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: Write Only
Default Value: 01h
RESTORE_CONFIG (F2h)
Definition: Identifies the configuration to be restored from NVM and loads the store’s settings into the device’s active memory. This
command must only be sent while the outputs are disabled.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: BIT
Type: Write Only
Default Value: N/A
COMMAND
RESTORE_CONFIG (F2h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
Default Value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
N/A
N/A
N/A
See Following Table
N/A
BIT NUMBER
N/A
N/A
N/A
STATUS BIT NAME
N/A
MEANING
7:4
Reserved
Reserved
3:0
CONFIG
Selected configuration to restore
FN8796 Rev.2.00
June 16, 2017
Page 44 of 46
ISL68124
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
June 16, 2017
FN8796.2
Applied new header/footer.
Updated “Enable (EN0 and EN1) Input High Level” spec on page 9, removed typical and added a min spec of
2.55V.
Added “Enable (EN0 and EN1) Input Low Level” spec on page 9.
On page 10, changed from “SCL, SDA Input High/Low Threshold” to “SCL, SDA Input High Level” removed
typical and added Min spec of 1.55V.
Added “SCL, SDA Input Low Level” spec on page 10.
On pages 25 through 34, Updated the tables in the PMBus Command Detail section for the following
commands, changed from “Two’s Complement Integer” to “Unsigned Integer”.
-VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_TRANSITION_RATE,
VOUT_DROOP, VOUT_MIN, VOUT_OV_FAULT_LIMIT, VOUT_UV_FAULT_LIMIT, VIN_OV_FAULT_LIMIT,
VIN_UV_FAULT_LIMIT, IIN_OC_FAULT_LIMIT, TON_DELAY, TON_RISE, TOFF_DELAY, and TOFF_FALL
Updated default value for ADh Command from “49D21300h” to “49D21E00h” in both the PMBus Command
Summary and PMBus Command Detail sections.
Updated “STATUS_CML (7Eh)” on page 39, changed Bit 1 meaning to “A communication fault other than the
ones listed in this table has occurred.”
Updated “READ_PIN (97h)” on page 42, changed Paged to Global.
January 27, 2017
FN8796.1
Pin descriptions on page 4:
Pin 31, RGND0 description changed “Positive” to “Negative”.
Pin 32, VSEN0 description changed “Negative” to “Positive”.
September 28, 2016
FN8796.0
Initial release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, please see the respective product
information page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2016-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8796 Rev.2.00
June 16, 2017
Page 45 of 46
ISL68124
Package Outline Drawing
For the most recent package outline drawing, see L40.5x5D.
L40.5x5D
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/10
4X 3.60
5.00
36X 0.40
A B
6
PIN #1 INDEX AREA
5.00
3.65
6
PIN 1
INDEX AREA
(4X)
0.15
40X 0.4± 0.1
TOP VIEW
b
BOTTOM VIEW
0.20
0.10 M
C A B
4
PACKAGE OUTLINE
0.40
SEE DETAIL "X"
0.750
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
0.050
3.65
5.00
SIDE VIEW
(36X 0.40)
(40X 0.20)
5
C 0.2 REF
(40X 0.60)
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220WHHE-1
either a mold or mark feature.
FN8796 Rev.2.00
June 16, 2017
Page 46 of 46