LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 LMV951 1V, 2.7 MHz, Rail-to-Rail Input and Output Amplifier with Shutdown Option Check for Samples: LMV951 FEATURES DESCRIPTION • • • • • The LMV951 amplifier is capable of operating at supply voltages from 0.9V to 3V with specified specs at 1V and 1.8V single supply. 1 2 • • • • • (Typical 1.0V Supply, unless Otherwise Noted) Ensured 1V Single Supply Operation Wide Bandwidth No VOS Glitch over the Input CMVR No Input IBIAS Current Reversal over VCM Range Buffered Output Stage High Output Drive Capability Output Short Circuit – Sink Current 35 mA – Source Current 45 mA Rail-to-Rail Buffered Output – At 600Ω Load 32 mV from Either Rail – At 2 kΩ Load 12 mV from Either Rail Temperature Range −40°C to 125°C The input common mode range extends to both power supply rails without the offset glitch and input bias current phase reversal inherent to most rail to rail input amplifiers. Contrary to a conventional rail to rail output amplifier the LMV951 has a buffered output stage providing an open loop gain which is relatively unaffected by resistive output loading. At 1V supply voltage, the LMV951 is able to source and sink in excess of 35 mA and offers a gain bandwidth product of 2.7 MHz. In shutdown mode the LMV951 consumes less than 50 nA of supply current. APPLICATIONS • • • Battery Operated Systems Battery Monitoring Supply Current Monitoring VIRTUAL GROUND CIRCUIT Open Loop Gain and Phase 140 R1 120 VIRTUAL GROUND R2 SD V - C1 .01 PF C2 1 PF GAIN (dB) + 140 120 PHASE + V 160 + V = 1V 100 100 80 80 60 60 GAIN 40 40 20 20 0 0 -20 1 10 100 1k 10k 100k PHASE (°) 160 1V 1M -20 10M FREQUENCY (Hz) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS ESD Tolerance (3) (1) (2) Human Body Model Machine Model Supply Voltage (V+ – V−) ±0.3V V+ +0.3V, V− −0.3V Voltage at Input/Output Pin Current at Input Pin ±10 mA Junction Temperature (4) +150°C Mounting Temperature (2) (3) (4) Infrared or Convection (20 sec) Temperature Range (1) (2) −40°C to +125°C Supply Voltage Thermal Resistance (θJA) (2) 2 235°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board. OPERATING RATINGS (1) 200V 3.1V VIN Differential (1) 2000V 0.9V to 3V (2) 170°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 (1) 1V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1, V− = 0V, VCM = 0.5V, Shutdown = 0V, and RL = 1 MΩ.Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) VOS Input Offset Voltage 1.5 TC VOS Input Offset Average Drift 0.15 IB Input Bias Current IOS Input Offset Current CMRR Common Mode Rejection Ratio PSRR VCM 32 Power Supply Rejection Ratio Large Signal Voltage Gain VOUT Output Voltage Swing High Output Voltage Swing Low IOUT Output Short Circuit Current IS (4) Supply Current SR Slew Rate GBWP Gain Bandwidth Product en Input - Referred Voltage Noise in Input-Referred Current Noise THD ISD VSD (2) (3) (4) (5) Units 2.8 3.0 mV μV/°C 80 85 nA nA 0V ≤ VCM ≤ 1V 67 55 77 0.1V ≤ VCM ≤ 1V 76 73 85 1V ≤ V+ ≤ 1.8V, VCM = 0.5V 70 67 92 1V ≤ V+ ≤ 3V, VCM = 0.5V 68 65 85 CMRR ≥ 67 dB 0 1.2 CMRR ≥ 55 dB 0 1.2 VOUT = 0.1V to 0.9V RL = 600Ω to 0.5V 90 85 106 VOUT = 0.1V to 0.9V RL = 2 kΩ to 0.5V 90 86 112 RL = 600Ω to 0.5V 50 62 25 RL = 2 kΩ to 0.5V 25 36 12 RL = 600Ω to 0.5V 70 85 32 RL = 2 kΩ to 0.5V 35 40 10 Sourcing VO = 0V, VIN(DIFF) = ±0.2V 20 15 45 Sinking VO = 1V, VIN(DIFF) = ±0.2V 20 13 35 dB dB mV from rail mA 370 480 520 Shutdown Mode VSD >0.6V 0.01 1.0 3.0 (5) μA 1.4 V/μs 2.7 MHz f = 1 kHz 25 nV/√Hz f = 1 kHz 0.2 pA/√Hz Total Harmonic Distortion f = 1 kHz, AV = 1, RL = 1 kΩ 0.02 Shutdown Pin Current Active Mode, VSD = 0V .001 1 Shutdown Mode, VSD = 1V .001 1 Shutdown Pin Voltage Range See V dB Active Mode VSD <0.4V Active Mode Shutdown Mode (1) (2) 0.2 Input Common-Mode Voltage Range AV Max % 0 0.4 0.65 1 µA V Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions is very limited selfheating of the device. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The short circuit test is a momentary test, the short circuit duration is 1.5 ms Number specified is the average of the positive and negative slew rates. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 3 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com 1.8V ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1.8V, V− = 0V, VCM = 0.9V, Shutdown = 0V, and RL = 1 MΩ.Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ Max Units 2.8 3.0 mV (3) (2) VOS Input Offset Voltage 1.5 TC VOS Input Offset Average Drift 0.15 IB Input Bias Current IOS Input Offset Current 0.2 nA CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 1.8V 82 80 93 dB PSRR Power Supply Rejection Ratio 1V ≤ V+ ≤ 1.8V, VCM = 0.5V 70 67 92 1V ≤ V+ ≤ 3V, VCM = 0.5V 68 65 85 VCM AV VOUT 36 CMRR ≥ 82 dB −0.2 2 CMRR ≥ 80 dB −0.2 2 Large Signal Voltage Gain VOUT = 0.2 to 1.6V RL = 600Ω to 0.9V 86 83 110 VOUT = 0.2 to 1.6V RL = 2 kΩ to 0.9V 86 83 116 RL = 600Ω to 0.9V 50 60 33 RL = 2 kΩ to 0.9V 25 34 13 RL = 600Ω to 0.9V 80 105 54 RL = 2 kΩ to 0.9V 35 44 17 Sourcing VO = 0V, VIN(DIFF) = ±0.2V 50 35 85 Sinking VO = 1.8V, VIN(DIFF) = ±0.2V 45 25 80 Output Voltage Swing High Output Short Circuit Current IS (4) Supply Current SR Slew Rate GBWP Gain Bandwidth Product en Input - Referred Voltage Noise in Input-Referred Current Noise THD ISD VSD (2) (3) (4) (5) 4 mA 780 880 Shutdown Mode VSD >1.3V 0.3 2.2 10 μA 1.4 V/μs 2.8 MHz f = 1 kHz 25 nV/√Hz f = 1 kHz 0.2 pA/Hz Total Harmonic Distortion f = 1 kHz, AV = 1, RL = 1 kΩ 0.02 Shutdown Pin Current Active Mode, VSD = 0V .001 1 Shutdown Mode, VSD = 1.8V .001 1 Shutdown Pin Voltage Range Active Mode Shutdown Mode (1) mV from rail 570 (5) V dB Active Mode VSD <0.5V See nA dB Input Common-Mode Voltage Range Output Voltage Swing Low IOUT μV/°C 80 85 % 0 0.5 1.45 1.8 µA V Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions is very limited selfheating of the device. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The short circuit test is a momentary test, the short circuit duration is 1.5 ms Number specified is the average of the positive and negative slew rates. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 CONNECTION DIAGRAM 1 6 OUTPUT V - 5 2 + +IN 3 + V SHUTDOWN 4 -IN Figure 1. 6-Pin SOT23- Top View See Package Number DDC SIMPLIFIED SCHEMATIC + ABOVE V GENERATOR 5 SHUTDOWN V + 6 INTERNAL GAIN STAGE IN- IN+ 1 OUTPUT 4 3 2 V - - BELOW V GENERATOR Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 5 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Supply Current vs. Supply Voltage Supply Current vs. Supply Voltage in Shutdown Mode 1.6 120 100 SUPPLY CURRENT (nA) SUPPLY CURRENT (mA) 1.4 1.2 1 125°C 0.8 25°C 0.6 -40°C 0.4 1.2 1.6 2.4 2 60 125°C 40 25°C 2.8 0 0.8 3.2 1.2 1.6 2 2.4 2.8 3.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 2. Figure 3. Supply Current vs. Shutdown Voltage Supply Current vs. Shutdown Voltage 0.5 0.8 + 125°C V = 1V 25°C 25°C 125°C 0.4 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) -40°C 20 0.2 0.8 80 0.3 -40°C 0.2 0.1 + V = 1.8V 0.6 0.4 -40°C 0.2 0 0 0 0.2 0.4 0.6 0.8 0.3 0 1 0.6 0.9 1.2 1.5 SHUTDOWN VOLTAGE (V) SHUTDOWN VOLTAGE (V) Figure 4. Figure 5. Supply Current vs. Shutdown Voltage VOS vs. VCM 2 1.8 2 + V = 3V 25°C 1.8 125°C 25°C 1.2 VOS (mV) SUPPLY CURRENT (mA) 125°C 1.6 -40°C 0 1.6 1.4 -40°C 0.4 1.2 0 1 + V = 1V 0 6 0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 SHUTDOWN VOLTAGE (V) VCM (V) Figure 6. Figure 7. Submit Documentation Feedback 0.8 1 Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. VOS vs. VCM VOS vs. VCM 1.4 1.6 125°C 1.2 125°C VOS ( mV) VOS (mV) 1.5 25°C 1.4 1.3 1 25°C 0.8 -40°C 0.6 -40°C + + V = 3V V = 1.8V 0.4 1.2 0.3 0 0.6 0.9 1.2 1.5 1.8 0.5 0 1 VCM (V) 1.5 2 2.5 3 VCM (V) Figure 8. Figure 9. VOS vs. Supply Voltage IBIAS vs. VCM 1.9 40 + 125°C V = 1V 125°C 25°C 35 IBIAS (nA) VOS (mV) 1.5 1.1 25°C -40°C 30 25 0.7 -40°C 0.3 20 1.2 0.8 1.6 2 2.4 2.8 3.2 0 0.6 Figure 10. Figure 11. IBIAS vs. VCM IBIAS vs. VCM 0.8 1 + + V = 3V V = 1.8V 40 0.4 VCM (V) 46 41 0.2 SUPPLY VOLTAGE (V) 43 125°C 125°C IBIAS (nA) IBIAS (nA) 39 -40°C 38 40 25°C -40°C 37 37 25°C 34 36 31 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 VCM (V) VCM (V) Figure 12. Figure 13. 2 2.5 3 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 7 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Sourcing Current vs. Supply Voltage Sinking Current vs Supply Voltage 160 200 140 170 -40°C -40°C 140 25°C ISINK (mA) ISOURCE (mA) 120 100 80 125°C 25°C 110 80 60 125°C 50 40 20 0.8 1.2 1.6 2.4 2.8 2 SUPPLY VOLTAGE (V) 20 0.8 3.2 1.2 1.6 2 Figure 14. Figure 15. Sourcing Current vs. Output Voltage Sinking Current vs. Output Voltage 60 2.8 3.2 50 + + V = 1V V = 1V 50 40 -40°C -40°C 40 ISINK (mA) ISOURCE (mA) 2.4 SUPPLY VOLTAGE (V) 25°C 30 125°C 30 25°C 20 20 125°C 10 10 0 0 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 VOUT VOUT (V) Figure 16. Figure 17. Sourcing Current vs. Output Voltage Sinking Current vs. Output Voltage 120 100 1 + + V = 1.8V V = 1.8V -40°C 90 25°C ISINK (mA) ISOURCE (mA) 75 50 125°C -40°C 60 25°C 30 25 125°C 0 0 0 8 0.3 0.6 0.9 1.2 1.5 1.8 0 0.3 0.6 0.9 1.2 VOUT (V) VOUT (V) Figure 18. Figure 19. Submit Documentation Feedback 1.5 1.8 Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Sourcing Current vs. Output Voltage Sinking Current vs. Output Voltage 160 210 + + V = 3V V = 3V 140 180 -40°C 150 100 ISINK (mA) ISOURCE (mA) 120 25°C 80 125°C 60 25°C 90 60 40 125°C 30 20 0 -40°C 120 0.5 0 1 2 1.5 2.5 0 0 3 0.5 1 VOUT (V) Figure 21. Positive Output Swing vs. Supply Voltage Negative Output Swing vs. Supply Voltage RL = 2 k: 40 VOUT FROM RAIL (mV) 30 125°C 20 25°C 10 125°C 20 10 0 0.8 1.2 1.6 2 2.4 2.8 -40°C 0 0.8 3.2 25°C 30 -40°C 1.2 1.6 2 2.4 2.8 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 22. Figure 23. Positive Output Swing vs. Supply Voltage Negative Output Swing vs. Supply Voltage 3.2 140 70 RL = 600: RL = 600: 120 60 125°C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 3 50 RL = 2 k: 50 2.5 Figure 20. 40 VOUT FROM RAIL (mV) 2 1.5 VOUT (V) 25°C 40 -40°C 30 100 125°C 25°C 80 60 40 -40°C 20 0.8 1.2 1.6 2 2.4 2.8 3.2 20 0.8 1.2 1.6 2 2.4 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 24. Figure 25. 2.8 3.2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 9 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Open Loop Gain and Phase with Capacitive Load Open Loop Gain and Phase with Resistive Load 100 100 100 100 10 k: 20 pF 50 pF 60 80 60 60 40 40 80 PHASE 2 k: 20 20 20 pF 0 0 -20 -40 -20 50 pF + V = 1V 100 pF RL = 2 k: 200 pF -60 1k 100k 10k 1M GAIN (dB) 200 pF GAIN PHASE (°) GAIN (dB) 40 40 GAIN 10 k: 20 20 0 0 600: -20 V = 1V -40 -40 CL = 20 pF 10M -60 100M -60 1k 100k 10k 1M Figure 26. Open Loop Gain and Phase with Resistive Load 100 100 100 100 10 k: 20 pF PHASE 60 80 80 50 pF 60 60 40 40 80 PHASE 2 k: 20 pF 20 0 0 GAIN (dB) 20 PHASE (°) 200 pF GAIN 60 600: 100 pF 40 -60 100M Figure 27. Open Loop Gain and Phase with Capacitive Load GAIN (dB) 10M FREQUENCY (Hz) FREQUENCY (Hz) 80 -20 2 k: + -40 60 600: 100 pF PHASE (°) 80 PHASE 40 GAIN 10 k: 20 20 0 0 PHASE (°) 80 600: -20 -20 -20 50 pF + -40 -40 1M 10M -60 100M -60 1k -40 100k 10k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 28. Figure 29. Open Loop Gain and Phase with Capacitive Load 100 100 20 pF PHASE 10 k: 80 80 60 60 40 40 80 2 k: PHASE 50 pF 60 -60 100M Open Loop Gain and Phase with Resistive Load 100 100 80 V = 1.8V CL = 20 pF 200 pF 100k -20 2 k: + 100 pF -40 V = 1.8V RL = 2 k: -60 1k 10k 600: 60 20 20 pF 0 0 50 pF -20 -40 V = 3V RL = 2 k: -60 1k 10k -20 200 pF 100k 1M 10M 10 k: 20 20 0 0 600: -20 100 pF + 10 20 40 GAIN 2 k: + -40 -40 V = 3V PHASE (°) 200 pF GAIN GAIN (dB) 40 PHASE (°) GAIN (dB) 100 pF -20 -40 CL = 20 pF -60 100M -60 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Figure 31. Submit Documentation Feedback 10M -60 100M Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV Small Signal Transient Response, AV = +1 INPUT = 20 mVPP f = 500 kHz INPUT = 0.8 VPP f = 100 kHz + + V = 1V V = 1V 2 PV/DIV Figure 32. Figure 33. Small Signal Transient Response, AV = +1 Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV 500 ns/DIV INPUT = 20 mVPP f = 500 kHz INPUT = 0.8 VPP f = 100 kHz + + V = 1.8V V = 1.8V 500 ns/DIV 2 PV/DIV Figure 35. Small Signal Transient Response, AV = +1 Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV Figure 34. INPUT = 20 mVPP f = 500 kHz INPUT = 0.8 VPP f = 100 kHz + + V = 3V V = 3V 500 ns/DIV 2 PV/DIV Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 11 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. Phase Margin vs. Capacitive Load (stability) 100 Phase Margin vs. Capacitive Load (stability) 100 + + V = 1V V = 1.8V 75 PHASE MARGIN (°) PHASE MARGIN (°) 75 600: 50 2 k: 10 k: 25 0 10 100 1000 600: 50 2 k: 10 k: 25 0 10 10000 100 CAPACITIVE LOAD (pF) 1000 Figure 38. Figure 39. Phase Margin vs. Capacitive Load (stability) PSRR vs. Frequency 100 10000 CAPACITIVE LOAD (pF) 120 + V = 3V 1.8V 100 1V 600: +PSRR 80 PSRR (dB) PHASE MARGIN (°) 75 50 2 k: 3V 60 -PSRR 40 10 k: 1V, 1.8V, 3V 25 20 0 10 100 1000 0 100 10000 1k CAPACITIVE LOAD (pF) 110 10k 100k 1M FREQUENCY (Hz) Figure 40. Figure 41. CMRR vs. Frequency Input Referenced Voltage Noise vs. Frequency 140 + V = 1.8V CMRR (dB) 90 + V = 3V VOLTAGE NOISE (nV/ Hz) 100 + V = 1V 80 70 60 50 40 100 + V = 1V 100 V+ = 1.8V 80 + V = 3V 60 40 + V = 1V 20 1k 10k 100k 1M 0 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 42. 12 120 Figure 43. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at the temperature extremes. THD+N vs. Frequency THD+N vs. Frequency 0.16 0.18 + + V = 1.8V V = 1V 0.14 0.15 600: 0.12 600: 0.1 THD+N (%) THD+N (%) 0.12 0.09 0.08 0.06 0.06 100 k: 0.04 100 k: 0.03 0.02 0 0 10 100 1k 10k 100k 10 100 FREQUENCY (Hz) 0.14 1k 10k 100k FREQUENCY (Hz) Figure 44. Figure 45. THD+N vs. Frequency Closed Loop Output Impedance vs. Frequency 1000 + V = 3V + V = 1V OUTPUT IMPEDANCE (:) 0.12 THD+N (%) 0.1 600: 0.08 0.06 100 k: 0.04 100 10 1 0.1 0.02 0 10 100 1k 10k 100k 0.01 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 46. Figure 47. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 13 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION CIRCUIT DESCRIPTION AND ADVANTAGE OF THE LMV951 The LMV951 utilizes an internal voltage generator which allows for rail to rail input and output operation from 1 to 3V supplies. An internal switching frequency between 10 MHz and 15 MHz is used for generating the internal voltages. The bipolar input stage provides rail to rail input operation with no input bias current phase reversal and a constant input offset voltage over the entire input common mode range. The CMOS output stage provides a gain that is virtually independent of resistive loads and an output drive current in excess of 35 mA at 1V. A further benefit of the output stage is that the LMV951 is stable in positive unity gain at capacitive loads in excess of 1000 pF. BATTERY OPERATED SYSTEMS The maximum operating voltage is 3V and the operating characteristics are ensured down to 1V which makes the LMV951 an excellent choice for battery operated systems using one or two NiCd or NiMH cells. The LMV951 is also functional at 0.9V making it an appropriate choice for a single cell alkaline battery. SHUTDOWN CAPABILITY While in shutdown mode, the LMV951 typically consumes less than 50 nA of supply current making it ideal for power conscious applications. Full functionality is restored within 3 μs of enable. SMALL SIZE The small footprint of the LMV951 package is ideal for high density board systems. By using the small 6-Pin SOT23 package, the amplifier can be placed closer to the signal source, reducing noise pickup and increasing signal integrity. POWER SUPPLY BYPASSING As in any high performance IC, proper power supply bypassing is necessary for optimizing the performance of the LMV951. The internal voltage generator needs proper bypassing for optimum operation. A surface mount ceramic .01 µF capacitor must be located as close as possible to the V+ and V− pins (pins 2 and 6). This capacitor needs to have low ESR and a self resonant frequency above 15 MHz. A small tantalum or electrolytic capacitor with a value between 1 µF and 10 µF also needs to be located close to the LMV951. DRIVING CAPACITIVE LOAD The unity gain follower is the most sensitive op amp configuration to capacitive loading; the LMV951 can drive up to 10,000 pF in this configuration without oscillation. If the application requires a phase margin greater than those shown in the datasheet graphs, a snubber network is recommended. The snubber offers the advantage of reducing the output signal ringing while maintaining the output swing which ensures a wider dynamic range; this is especially important at lower supply voltages. VCC - V + VOUT + - V + VIN VEE RS RL CL CS - Figure 48. Snubber Network to Improve Phase Margin 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 The chart below gives recommended values for some common values of large capacitors. For these values RL = 2 kΩ; RS CS 500 pF 330Ω 6800 pF 680 pF 270Ω 8200 pF 1000 pF 220Ω .015 μF 25 mV/DIV 25 mV/DIV CL + + V = 1V V = 1V 1 Ps/DIV 1 Ps/DIV Figure 49. 1000 pF and no Snubber Figure 50. 1000 pF with Snubber BRIDGE CONFIGURATION AMPLIFIER Some applications may benefit from doubling the voltage across the load. With V+ = 1V a bridge configuration can provide a 2 VPP output to the load with a resistance as low as 300Ω. The output stage of the LMV951 enables it to drive a load of 120Ω and still swing at least 70% of the supply rails. The bridge configuration shown in Figure 51 enables the amplifier to maintain a low dropout voltage thus maximizing its dynamic range. It has been configured in a gain of 1 and uses the fewest number of parts. Resistor values have been selected to keep the current consumption to a minimum and voltage errors due to bias currents negligible. Using the selected resistor values makes this circuit quite practical in a battery operated design. R1, R2 and R5, R6 set up a virtual ground that is half of V+. Note that the accuracy of the resistor values will establish how well the two virtual grounds match. Any errors in the virtual grounds will show as current across RL when there is no input signal. AC coupling the input signal sets the DC bias point of this signal to the virtual ground of the circuit. Using the large resistor values with a 1 µF capacitor (C1) sets the frequency rolloff of this circuit below 10 Hz. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 15 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 + R7 10 k: + C1 1 PF 5V V A2 A1 R2 100 k: - RL - V VL R5 100 k: + V + VIN C4 .1 PF - - R1 100 k: C3 .01 PF C2 .01 PF + V www.ti.com V R6 100 k: SD SD R3 100 k: R4 100 k: Figure 51. Bridge Amplifier • • • C2 and C3 are .01 μF ceramic capacitors that must be located as close as possible to pin 6, the V+ pin. As covered in the power supply bypassing section these capacitors must have low ESR and a self resonant frequency above 15 MHz. C4 is a 1 μF tantalum or electrolytic capacitor that should also be located close to the supply pin. To use the shutdown feature tie pin 5 of the two parts together and connect through a 470 kΩ resistor to V+. Add a switch between pin 5 and ground. Closing the switch keeps the parts in the active mode, opening the switch sets the parts in the shutdown mode without adding any additional current to V+. VIRTUAL GROUND CIRCUIT The front page of this data sheet shows the LMV951 being used in a system establishing a virtual ground. Having a buffered output stage gives this part the ability to handle load currents higher than 35 mA at 1V. R3 and R4 are used to set the voltage of the virtual ground. To maintain low noise the values should be between 1 kΩ and 10 kΩ. C1 and C2 provide the recommended bypassing for the LMV951. These caps must be placed as close as possible to pins 2 and 6. TWO WIRE LINE TRANSMISSION The robust output stage of the LMV951 makes it an excellent choice for driving long cables. The circuit shown below in Figure 52 can drive a long cable using only two wires; power and ground. When many sensors are located remotely from the control area the wiring becomes a significant expense. Using only two wires helps minimize the wiring expense in a large project such as an industrial plant. Figure 53 shows a 25 kHz signal after passing though 1000 ft. of twisted pair cable. Figure 54 shows a 200 kHz signal after passing through 50 ft. of twisted pair cable. 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 R3 1 k: R1 10 k: C2 10 PF C6 .01 PF + V + C1 1 PF SENSOR C3 20 PF CABLE 3V 3V 3V R4 1 k: R5 10 k: R2 10 k: - V + A1 - V C4 1 PF R6 10 k: SD + A2 - C5 10 PF C6 .01 PF OUTPUT - V SD 200 mV/DIV 200 mV/DIV Figure 52. Two Wire Line Driver INPUT = 1 VPP INPUT = 1 VPP 5 Ps/DIV 1 Ps/DIV Figure 53. 25 kHz Through 1000 ft. Figure 54. 200 kHz Through 50 ft. The power supply of 3V is recommended to power this system. A1 and A2 are set up as unity gain buffers. It is easy to configure A1 with the required gain if a gain of greater than one is required. C1 along with R1 and R2 are used to ensure the correct DC operating point at the input of A1. C4 along with R5 and R6 are used to setup the correct DC operating point for A2. C1, C3, and C4 have been selected to give about a 20% droop with a 1 kHz square wave input. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 17 LMV951 SNOSAI3C – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMV951 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMV951MK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AS3A LMV951MKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AS3A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMV951MK/NOPB SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV951MKX/NOPB SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV951MK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 LMV951MKX/NOPB SOT DDC 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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