DV2003S1 Fast Charge Development System Control of On-Board P-FET Switch-Mode Regulator Features ➤ bq2003 fast-charge control evaluation and development ➤ Charge current sourced from an on-board switch-mode regulator (up to 3.0 A) ➤ Fast charge of 2 to 16 NiCd or NiMH cells ➤ Fast-charge termination by delta temperature/delta time (∆T/∆t), negative delta voltage (-∆V), maximum temperature, maximum time, and maximum voltage ➤ -∆V enable, hold-off, top-off, maximum time, and number of cells are jumper-configurable ➤ Charging status displayed on charge and temperature LEDs ➤ Discharge-before-charge control with push-button switch ➤ Inhibit fast charge by external logic-level input Connection Descriptions J6 General Description The DV2003S1 Development System provides a development environment for the bq2003 Fast-Charge IC. The DV2003S1 incorporates a bq2003 and a buck-type switch-mode regulator to provide fast charge control for 2 to 16 NiCd or NiMH cells. Review the bq2003 data sheet and the application note, “Using the bq2003 to Control Fast Charge,” before using the DV2003S1 board. The fast charge is terminated by any of the following: ∆T/∆t, -∆V, maximum temperature, maximum time, maximum voltage, or an external inhibit command. Jumper settings select the -∆V enabled state, and the hold-off, top-off, and maximum time limits. DC+ DC input from charger supply THERM Thermistor connection DSCHG Low side of discharge load BAT+ Positive battery terminal and high side of discharge load BAT– Negative battery terminal and thermistor connection GND Ground from charger supply +V Voltage source for inhibit input IN Inhibit input to prevent bq2003 activity J2 The user provides a power supply and batteries. The user configures the DV2003S1 for the number of cells, -∆V charge termination and maximum charge time (with or without top-off), and commands the discharge-beforecharge option with the push-button switch S1. 3/98 JP1 DVEN Negative voltage termination enable JP2 TM1 TM1 setting JP3 TM2 TM2 setting JP4 NOC Select number of cells Rev. A Board 1 DV2003S1 Fixed Configuration Table 1. Lookup Table for D9 Selection The DV2003S1 board has the following fixed characteristics : VCC (4.75–5.25V) is regulated on-board from the supply at connector JP6 DC+. LEDs indicate charge status and temperature fault status. Pin CCMD is grounded, providing charge initiation on the later application of the battery or DC+, which provides VCC to the bq2003. Pin DCMD is pulled to ground through R12. A toggle of switch S1 momentarily pulls DCMD high and initiates a discharge-before-charge. The bq2003 output activates FET Q4, allowing current to flow through an external current-limiting load between BAT+ and DSCHG on connector JP6. Motorola Part No. Nominal Zener Voltage Below 15 15–18 18–21 21–24 24–27 27–30 30–32 32–35 Shorted 1N749 1N755 1N758 1N964A 1N966A 1N967A 1N968A 0 4.3 7.5 10 13 16 18 20 With the provided NTC thermistor connected between THERM and BAT–, values are: LTF = 10°C, HTF = 45°C, and TCO = 50°C. The ∆T/∆t settings at 30°C (T∆T) are: minimum = 0.82°C/minute, typical = 1.10°C/minute. Trickle current is limited by a 150Ω/2W resistor R10 between DC+ and BAT+ (maximum potential across R10 = 17.3V). Note that too large a voltage between DC+ and BAT+ may exceed the wattage rating of resistor R10. The thermistor is identified by the serial number suffix as follows: As shipped from Benchmarq, the DV2003S1 buck-type switch-mode regulator is configured to a charging current of 2.35A. This current level is controlled by the value of sense resistor R26 by the relationship: ICHG = +VDC Input (Volts) 0.235V R26 Identifier Thermistor K1 Keystone RL0703-5744-103-S1 (blank) Philips 2322-640-63103 F1 Fenwal Type 16, 197-103LA6-A01 The value of R26 at shipment is 0.100Ω. This resistor can be changed depending on the application. Jumper-Selectable Configuration The suggested maximum ICHG for the DV2003S1 board is 3A. A location for a second sense resistor (R27) is provided on the DV2003S1 Board. R27 is electrically in parallel with R26, which assists in user modification of ICHG, if needed. The DV2003L1 must be configured as described below. DVEN (JP1): Enables/disables -∆V termination (see bq2003 data sheet). Charge current can be halted at any time via external stimulus. Connector JP5 provides a +5V DC source (+V) and an inhibit input (IN) node for this function. To inhibit charge current, the JP5 inhibit in;put (IN) is driven by +5V DC. To reinitiate charge, remove the voltage source from the inhibit input. Jumper Setting Pin State [12]3 Enabled (high) 1[23] Disabled (low) TM1 and TM2 (JP2 and JP3): Select fast charge safety time/hold-off/top-off (see bq2003 data sheet). The maximum cell voltage (MCV) setting is 1.8V. Zener diode D( is used to limit Q1 VGS per a given DC+ voltage. Benchmarq ships a 1N751A (5.1V Zener) at location D9. This voltage value was selected as an appropriate value for most development work. The user can modify this Zener diode for the application. Refer to Table 1 for suggested D9 values for DC+ voltages. 2 Jumper Setting Pin State [12]3 High 1[23] Low 123 Float DV2003S1 Number of Cells (JP4): A resistor-divider network is provided to select 2 to 16 cells (the resulting resistor value equals N – 1 cells). RB1 is a 200KΩ resistor, and RB2 (R16–R22) is jumper-selected. Closed Jumper Number of Cells R22 14 R21 12 R20 10 R19 8 R18 6 R17 5 R16 4 Setup Procedure 1. Configure DVEN, TM1, TM2, and number-of-cells (NOC) jumpers. 2. Connect the provided thermistor or a 10KΩ resistor between THERM and BAT-. Note: RT1 and RT2 match the thermistor provided and must be changed if a different thermistor type is used (see Appendix A in the application note, “Using the bq2003 to Control Fast Charge”). Temperature Disable: Connecting a 10KΩ resistor between THERM and BAT– disables temperature control. 3. If using the discharge-before-charge option, connect a current-limiting discharge load between BAT+ and DSCHG. 4. If using the INHIBIT function, connect a switch across JP5 (IN to +V) or connect IN to the controlling signal source (3–5V). 5. Attach the battery pack to BAT+ and BAT-. For temperature control, the thermistor must contact the cwlls. 6. Attach DC current source to DC+ (+) and GND (-) connections in JP6. Recommended DC Operating Conditions Symbol Description Minimum Typical Maximum Unit 2.4 A IDC+ Maximum input current - - VDC Maximum input voltage 2.0 + VBAT+ or 15 - VBAT+ BAT+ input voltage - - 30 V VTHERM THERM input signal 0 - 5 V IDSCHG Discharge load current - - 2 A Note: 18 + VBAT+ V or 35 Notes Note 1 1. The VDC+ limits consider the 5.1V Zener diode at D9. The voltage at D9 is application-specific and limits the VGS of Q1 to a safe enhancement value during Q1 conduction. See Table 1 for recommended D9 selections per VDC+. 3 DV2003S1 DV2003L1 Board Schematic JP6 D6 DC THERM DISCHG BAT+ BATGND 1 2 3 4 5 6 R10 150 2W 1N5400 C9 150UF 35V L1 MTP23P06V RB1 200K 1% 200UH D10 1N5821 Q1 R11 1K 2N3904 JP4 NUMBER OF CELLS Q2 1N4148 D1 D8 U2 +5V 78L05ACZ IN R26 0.1 1W R27 OPTIONAL 1N4148 OUT GND C1 10UF 35V 16 14 12 10 R25 13.3K 1% R24 15.4K 1% R23 18.2K 1% R22 22.1K 1% 8 R21 28.7K 1% 6 5 R20 40.2K 1% 4 R19 49.9K 1% 3 R18 66.5K 1% R17 100K 1% 2 R16 200K 1% C3 10UF 16V +5V +5V +5V JP1 DVEN 1 2 3 JP2 TM1 1 2 3 +5V +5V S1 D9 DISCHARGE_CMD 1N751A C2 JP5 1 2 D4 V+ IN RT1 4.53K 1% 1N4148 INH D5 JP3 TM2 1 2 3 4 5 6 7 8 1 2 3 R6 100K R5 CCMD VCC DCMD DIS DVEN MOD TM1 CHG TM2 TEMP TS MCV BAT TCO VSS SNS 16 15 14 13 12 11 10 9 R7 2K +5V CHARGE TEMP 1 D3 D2 RT2 3.57K 1% 0.1UF R1 63.4K 1% R2 1K 100K C7 Q3 2N7000 R4 BQ2003 1N4148 C4 C8 0.1UF R12 2K R9 2K Q4 MTP3055VL 0.1UF U1 R15 240 R8 2K 0.1UF C6 1000PF 8.87K 1% R3 26.7K 1% C5 0.1UF DV2003S1, Rev A, 4/18/97 4 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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