TI1 OPA192ID Low input bias current op amp Datasheet

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OPA192, OPA2192, OPA4192
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage,
Low Input Bias Current Op Amp with e-trim™
1 Features
3 Description
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The OPAx192 family (OPA192, OPA2192, and
OPA4192) is a new generation of 36-V, e-trim
operational amplifiers.
1
Low Offset Voltage: ±5 µV
Low Offset Voltage Drift: ±0.2 µV/°C
Low Noise: 5.5 nV/√Hz at 1 kHz
High Common-Mode Rejection: 140 dB
Low Bias Current: ±5 pA
Rail-to-Rail Input and Output
Wide Bandwidth: 10 MHz GBW
High Slew Rate: 20 V/µs
Low Quiescent Current: 1 mA per Amplifier
Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI Filtered Inputs
Differential Input Voltage Range to Supply Rail
High Capacitive Load Drive Capability: 1 nF
Industry Standard Packages:
– Single in SOIC-8, SOT-23-5, and VSSOP-8
– Dual in SOIC-8 and VSSOP-8
– Quad in SOIC-14 and TSSOP-14
These devices offer outstanding dc precision and ac
performance, including rail-to-rail input/output, low
offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ),
and 10-MHz bandwidth.
Unique features such as differential input-voltage
range to the supply rail, high output current (±65 mA),
high capacitive load drive of up to 1 nF, and high
slew rate (20 V/µs) make the OPA192 a robust, highperformance operational amplifier for high-voltage
industrial applications.
The OPA192 family of op amps is available in
standard packages and is specified from –40°C to
+125°C.
Device Information(1)
PART NUMBER
OPA192
2 Applications
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Multiplexed Data-Acquisition Systems
Test and Measurement Equipment
High-Resolution ADC Driver Amplifiers
SAR ADC Reference Buffers
Programmable Logic Controllers
High-Side and Low-Side Current Sensing
High Precision Comparator
OPA2192
OPA4192
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm x 3.90 mm
TSSOP (14)
5.00 mm x 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPA192 in a High-Voltage, Multiplexed, Data-Acquisition System
Analog Inputs
REF3140
Bridge Sensor
OPA192
Thermocouple
4:2
HV
MUX
Gain Network
Gain Network
Current Sensing
Photo
Detector
High-Voltage Multiplexed Input
RC Filter
Reference Driver
REF
OPA192
+
Gain Network
Gain Network
OPA192
LED
OPA350
+
+
Optical Sensor
RC Filter
High-Voltage Level Translation
VINP
Antialiasing
Filter
ADS8864
VINM
VCM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA192, OPA2192, OPA4192
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA192 .................................. 7
Thermal Information: OPA2192 ................................ 7
Thermal Information: OPA4192 ................................ 7
Electrical Characteristics: VS = ±4 V to ±18 V (VS =
+8 V to +36 V)............................................................ 8
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS =
+4.5 V to +8 V)......................................................... 10
6.9 Typical Characteristics ............................................ 12
6.10 Typical Characteristics .......................................... 13
7
Parameter Measurement Information ................ 21
8
Detailed Description ............................................ 23
7.1 Input Offset Voltage Drift......................................... 21
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
23
23
24
30
Application and Implementation ........................ 31
9.1 Application Information............................................ 31
9.2 Typical Applications ................................................ 31
10 Power-Supply Recommendations ..................... 35
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2015) to Revision E
Page
•
Changed PW package from product preview to production data........................................................................................... 1
•
Added PW package to test condition for input offset voltage drift.......................................................................................... 8
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Added PW package to test condition for input offset voltage drift........................................................................................ 10
•
Added PW package condition to Figure 8 ........................................................................................................................... 13
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Added PW package condition to Figure 10 ......................................................................................................................... 13
•
Added PW package condition to Figure 52 ......................................................................................................................... 22
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Changed Figure 70 to fix typos ............................................................................................................................................ 36
Changes from Revision C (March 2015) to Revision D
Page
•
Changed device status to Production Data; OPA4192 released to Production .................................................................... 1
•
Deleted footnote 2 from Device Information table ................................................................................................................. 1
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Deleted footnote 2 from Pin Configuration and Functions section ......................................................................................... 4
•
Changed ESD Ratings table: added correct OPA4192 CDM specifications ......................................................................... 6
•
Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS = ±4 V to ±18 V table ......................... 9
•
Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS = ±2.25 V to ±4 V table .................... 11
•
Changed Typical Characteristics to current standards (split curves and table of graphs into separate sections to be
SDS compliant) .................................................................................................................................................................... 12
•
Added Crosstalk vs Frequency row to Table 1 ................................................................................................................... 12
•
Added Figure 48 .................................................................................................................................................................. 20
2
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Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
OPA192, OPA2192, OPA4192
www.ti.com
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Changes from Revision B (March 2014) to Revision C
Page
•
Added CDM row for OPA2192, OPA4192 in ESD Ratings table ........................................................................................... 6
•
Changed input offset voltage values for VCM ≥ (V+) – 1.5 V test condition............................................................................ 8
•
Changed Input offset voltage parameter typical specs for VCM = (V+) – 1.5 V test conditions ............................................. 8
•
Changed test conditions for dVOS/dT parameter .................................................................................................................... 8
•
Changed input offset voltage max values and test conditions for VCM = (V+) – 3 V test condition...................................... 10
•
Changed input offset voltage values and test conditions for VCM = (V+) – 1.5 V test condition .......................................... 10
•
Changed Input offset voltage parameter typical specs for VCM = (V+) – 1.5 V test conditions ............................................ 10
•
Changed test conditions for dVOS/dT parameter ................................................................................................................. 10
•
Added text to last bullet of Layout Guidelines section.......................................................................................................... 35
Changes from Revision A (January 2014) to Revision B
Page
•
Added ESD Ratings and Recommended Operating Conditions tables, and Parameter Measurement Information,
Application and Implementation, Power-Supply Recommendations, and Device and Documentation Support
sections, and moved existing sections ................................................................................................................................... 1
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Changed all OPA192 and OPA2192 packages to production data........................................................................................ 1
•
Changed package names to latest standard; changed all MSOP to VSSOP, SO to SOIC, and SOT23 to SOT ................. 1
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Deleted DCK package pin configuration................................................................................................................................. 4
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Added thermal information for OPA192 DBV and DGK packages......................................................................................... 7
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Added OPA2192 and OPA4192 Thermal Information tables ................................................................................................ 7
•
Added rows with additional test conditions to input offset voltage parameter........................................................................ 8
•
Changed Input offset voltage drift parameter ........................................................................................................................ 8
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Changed CMRR test conditions ............................................................................................................................................ 8
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Added rows with additional test conditions to input offset voltage parameter...................................................................... 10
•
Changed Input offset voltage drift parameter ....................................................................................................................... 10
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Changed PSSR parameter .................................................................................................................................................. 10
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Changed CMRR test conditions .......................................................................................................................................... 10
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Added Output section ........................................................................................................................................................... 11
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Added typical characteristic curves to Table 1 .................................................................................................................... 12
•
Added TA = 25°C to Typical Characteristics condition line .................................................................................................. 12
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Added nine new histogram plots from Figure 2 to Figure 10 ............................................................................................... 13
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Changed Figure 11 to show more units ............................................................................................................................... 13
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Changed Figure 19 .............................................................................................................................................................. 15
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Added text to Application Information section ...................................................................................................................... 31
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Changed text in Layout Guidelines section .......................................................................................................................... 35
Changes from Original (December 2013) to Revision A
Page
•
Changed first paragraph of 16-Bit Precision Multiplexed Data-Acquisition System section ................................................ 31
•
Changed Figure 66 and title ................................................................................................................................................. 31
•
Changed TIDU181 reference design title ............................................................................................................................. 32
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
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OPA192, OPA2192, OPA4192
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
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5 Pin Configuration and Functions
DBV Package: OPA192
5-Pin SOT
Top View
OUT
1
V-
2
+IN
3
D and DGK Packages: OPA2192
8-Pin SOIC and VSSOP
Top View
V+
5
4
-IN
D and DGK Packages: OPA192
8-Pin SOIC and VSSOP
Top View
(1)
4
NC(1)
1
8
NC(1)
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
D and PW Packages: OPA4192
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
NC = No internal connection.
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Pin Functions: OPA192
PIN
OPA192
NAME
+IN
I/O
D (SOIC),
DGK (VSSOP)
DBV (SOT)
3
3
DESCRIPTION
I
Noninverting input
Inverting input
–IN
2
4
I
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V+
7
5
—
Positive (highest) power supply
V–
4
2
—
Negative (lowest) power supply
Pin Functions: OPA2192 and OPA4192
PIN
OPA2192
OPA4192
D (SOIC),
DGK (VSSOP)
D (SOIC),
PW (TSSOP)
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
—
10
I
Noninverting input, channel C
+IN D
—
12
I
Noninverting input, channel D
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
—
9
I
Inverting input,,channel C
–IN D
—
13
I
Inverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V+
8
4
—
Positive (highest) power supply
V–
4
11
—
Negative (lowest) power supply
NAME
I/O
DESCRIPTION
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Product Folder Links: OPA192 OPA2192 OPA4192
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OPA192, OPA2192, OPA4192
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Signal input pins
Common-mode
Voltage
(V–) – 0.5
V
±10
mA
Continuous
Operating range
–55
150
Junction
150
Storage, Tstg
(2)
V
(V+) – (V–) + 0.2
Current
(1)
UNIT
±20
(40, single supply)
(V+) + 0.5
Differential
Output short circuit (2)
Temperature
MAX
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
V(ESD)
VALUE
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
V
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
V
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
V
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
V
MAX
UNIT
OPA192
V(ESD)
OPA2192
V(ESD)
OPA4192
V(ESD)
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Specified temperature
6
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NOM
4.5 (±2.25)
36 (±18)
V
–40
+125
°C
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
6.4 Thermal Information: OPA192
OPA192
THERMAL METRIC (1)
D (SOIC)
DBV (SOT)
DGK (VSSOP)
8 PINS
5 PINS
8 PINS
UNIT
180.4
°C/W
RθJA
Junction-to-ambient thermal resistance
115.8
158.8
RθJC(top)
Junction-to-case(top) thermal resistance
60.1
60.7
67.9
°C/W
RθJB
Junction-to-board thermal resistance
56.4
44.8
102.1
°C/W
ψJT
Junction-to-top characterization parameter
12.8
1.6
10.4
°C/W
ψJB
Junction-to-board characterization parameter
55.9
4.2
100.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2192
OPA2192
THERMAL METRIC
(1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
107.9
158
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
53.9
48.6
°C/W
RθJB
Junction-to-board thermal resistance
48.9
78.7
°C/W
ψJT
Junction-to-top characterization parameter
6.6
3.9
°C/W
ψJB
Junction-to-board characterization parameter
48.3
77.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: OPA4192
OPA4192
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
86.4
92.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
46.3
27.5
°C/W
RθJB
Junction-to-board thermal resistance
41.0
33.6
°C/W
ψJT
Junction-to-top characterization parameter
11.3
1.9
°C/W
ψJB
Junction-to-board characterization parameter
40.7
33.1
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
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OPA192, OPA2192, OPA4192
SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
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6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = +8 V to +36 V)
At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±5
±25
±8
±50
±10
±75
±10
±40
TA = 0°C to 85°C
±25
±150
TA = –40°C to +125°C
±50
±250
TA = 0°C to 85°C
±0.1
±0.5
±0.15
±0.8
TA = 0°C to 85°C
±0.1
±0.8
TA = –40°C to +125°C
±0.2
±1.0
±0.3
±1.0
µV/V
±5
±20
pA
±5
nA
±20
pA
±2
nA
OFFSET VOLTAGE
TA = 0°C to 85°C
VOS
Input offset voltage
TA = –40°C to +125°C
VCM = (V+) – 1.5 V
D packages only
dVOS/dT
Input offset voltage drift
DBV, DGK, and PW packages only
PSRR
Power-supply rejection
ratio
TA = –40°C to +125°C
TA = –40°C to +125°C
µV
µV/°C
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
TA = –40°C to +125°C
±2
TA = –40°C to +125°C
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.30
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
4
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise
density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 100 Hz
µVPP
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
nV/√Hz
12.5
NOISE (continued)
in
Input current noise
density
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode
rejection ratio
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
120
140
114
126
100
120
86
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
8
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TA = –40°C to +125°C
TA = –40°C to +125°C
120
134
114
126
126
140
120
134
dB
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Electrical Characteristics: VS = ±4 V to ±18 V (VS = +8 V to +36 V) (continued)
At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
G = 1, 10-V step
To 0.01%
ts
Settling time
To 0.001%
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic
distortion + noise
G = 1, f = 1 kHz, VO = 3.5 VRMS
Crosstalk
10
MHz
20
V/µs
V S = ±18 V, G = 1, 10-V step
1.4
V S = ±18 V, G = 1, 5-V step
0.9
V S = ±18 V, G = 1, 10-V step
2.1
V S = ±18 V, G = 1, 5-V step
µs
1.8
200
ns
0.00008%
OPA2192 and OPA4192, at dc
150
OPA2192 and OPA4192, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
Voltage output swing
from rail
VO
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
15
95
110
RLOAD = 2 kΩ
430
500
5
15
RLOAD = 10 kΩ
95
110
RLOAD = 2 kΩ
430
500
No load
Negative rail
ISC
5
RLOAD = 10 kΩ
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, see Figure 31
Ω
375
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to +125°C, IO = 0 A
1.2
1.5
mA
TEMPERATURE
Thermal protection (1)
(1)
140
°C
For a detailed description of thermal protection, see the Thermal Protection section.
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6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = +4.5 V to +8 V)
At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±5
±25
±8
±50
±10
±75
UNIT
OFFSET VOLTAGE
VCM = (V+) – 3 V
TA = 0°C to 85°C
TA = –40°C to +125°C
VOS
Input offset voltage
(V+) – 3.5 V < VCM < (V+) – 1.5 V
VCM = (V+) – 1.5 V
dVOS/dT
PSRR
Input offset voltage drift
Power-supply rejection
ratio
See Common-Mode Voltage Range section
±10
±40
TA = 0°C to 85°C
±25
±150
TA = –40°C to +125°C
±50
±250
±0.1
±0.5
TA = –40°C to +125°C
±0.15
±0.8
TA = 0°C to 85°C
VCM = (V+) – 3 V,
DBV, DGK, and PW packages only TA = –40°C to +125°C
±0.1
±0.8
±0.2
±1.1
VCM = (V+) – 1.5 V, TA = –40°C to +125°C
±0.5
±3
VCM = (V+) – 3 V,
D packages only
µV
TA = 0°C to 85°C
TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V
±1
µV
µV/°C
µV/V
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
±5
TA = –40°C to +125°C
±2
TA = –40°C to +125°C
±20
pA
±5
nA
±20
pA
±2
nA
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
1.30
(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz
Input current noise density
µVPP
4
f = 100 Hz
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
12.5
f = 1 kHz
1.5
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode rejection
ratio
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
94
110
90
104
100
120
84
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
10
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TA = –40°C to +125°C
TA = –40°C to +125°C
110
120
100
114
110
126
110
120
dB
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = +4.5 V to +8 V) (continued)
At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
G = 1, 10-V step
ts
Settling time
To 0.01%
tOR
Overload recovery time
Crosstalk
10
MHz
20
V/µs
1
µs
VIN× G = VS
200
ns
OPA2192 and OPA4192, at dc
150
OPA2192 and OPA4192, f = 100 kHz
130
VS = ±3 V, G = 1, 5-V step
dB
OUTPUT
No load
Positive rail
Voltage output swing from
rail
VO
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
15
95
110
RLOAD = 2 kΩ
430
500
5
15
RLOAD = 10 kΩ
95
110
RLOAD = 2 kΩ
430
500
No load
Negative rail
ISC
5
RLOAD = 10 kΩ
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, see Figure 31
Ω
375
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to +125°C
1.2
1.5
mA
TEMPERATURE
Thermal protection (1)
(1)
140
°C
For a detailed description of thermal protection, see the Thermal Protection section.
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6.9 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1 to Figure 6
Offset Voltage Drift Distribution
Figure 7 to Figure 10
Offset Voltage vs Temperature
Figure 11
Offset Voltage vs Common-Mode Voltage
Figure 12 to Figure 14
Offset Voltage vs Power Supply
Figure 15
Open-Loop Gain and Phase vs Frequency
Figure 16
Closed-Loop Gain and Phase vs Frequency
Figure 17
Input Bias Current vs Common-Mode Voltage
Figure 18
Input Bias Current vs Temperature
Figure 19
Output Voltage Swing vs Output Current (maximum supply)
Figure 20
CMRR and PSRR vs Frequency
Figure 21
CMRR vs Temperature
Figure 22
PSRR vs Temperature
Figure 23
0.1-Hz to 10-Hz Noise
Figure 24
Input Voltage Noise Spectral Density vs Frequency
Figure 25
THD+N Ratio vs Frequency
Figure 26
THD+N vs Output Amplitude
Figure 27
Quiescent Current vs Supply Voltage
Figure 28
Quiescent Current vs Temperature
Figure 29
Open Loop Gain vs Temperature
Figure 30
Open Loop Output Impedance vs Frequency
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 31
Figure 32, Figure 33
No Phase Reversal
Figure 34
Positive Overload Recovery
Figure 35
Negative Overload Recovery
Small-Signal Step Response (100 mV)
Figure 36
Figure 37, Figure 38
Large-Signal Step Response
Settling Time
Figure 39
Figure 40 to Figure 43
Short-Circuit Current vs Temperature
Figure 44
Maximum Output Voltage vs Frequency
Figure 45
Propagation Delay Rising Edge
Figure 46
Propagation Delay Falling Edge
Figure 47
Crosstalk vs Frequency
Figure 48
12
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
6.10 Typical Characteristics
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
50
22
Distribution Taken From 190 Amplifiers
TA = 125 ƒC
Distribution Taken From 4715 Amplifiers
18
40
16
Amplifiers (%)
Percentage of Amplifiers (%)
20
14
12
10
8
30
20
6
10
4
Offset Voltage ( V)
Offset Voltage (µV)
C032
Figure 1. Offset Voltage Production Distribution at 25°C
Figure 2. Offset Voltage Production Distribution at 125°C
Distribution Taken From 190 Amplifiers
TA = 0ƒC
70
60
50
50
40
30
40
30
20
20
10
10
0
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Amplifiers (%)
60
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Offset Voltage (µV)
Offset Voltage (µV)
C013
Figure 3. Offset Voltage Production Distribution at 85°C
C013
Figure 4. Offset Voltage Production Distribution at 0°C
50
35
35
25
20
75
50
0
25
5
0
0
10
5
-25
15
10
-50
15
Offset Voltage (µV)
50
20
25
25
30
0
30
-75
Amplifiers (%)
40
-75
Amplifiers (%)
Distribution Taken From 190 Amplifiers
TA = -40ƒC
45
40
-25
Distribution Taken From 190 Amplifiers
TA = -25ƒC
45
-50
50
75
Amplifiers (%)
C013
Distribution Taken From 190 Amplifiers
TA = 85ƒC
70
75
50
25
0
-25
-50
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0
-75
2
Offset Voltage (µV)
C013
Figure 5. Offset Voltage Production Distribution at –25°C
C013
Figure 6. Offset Voltage Production Distribution at –40°C
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
70
60
50
Distribution Taken From 120 Amplifiers
SOIC, TA = -40ƒC to +125ƒC
Distribution Taken From 75 Amplifiers
SOT and VSSOP, TA = -40ƒC to +125ƒC
40
Amplifiers (%)
Amplifiers (%)
50
40
30
30
20
20
10
Offset Voltage Drift (µV/ƒC)
1.1
0.9
0.7
0.5
0.3
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
0.1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
Offset Voltage Drift (µV/ƒC)
C013
OPA192ID and OPA2192ID
C013
OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW
Figure 7. Offset Voltage Drift Distribution
from –40°C to +125°C
Figure 8. Offset Voltage Drift Distribution
from –40°C to +125°C
25
Offset Voltage Drift (µV/ƒC)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0
-0.3
0
-0.4
5
-0.5
10
-0.2
10
-0.3
20
15
-0.4
30
20
-0.5
40
-0.6
Amplifiers (%)
Amplifiers (%)
50
Distribution Taken From 75 Amplifiers
SOT and VSSOP, TA = 0ƒC to 85ƒC
-0.7
60
30
Distribution Taken From 120 Amplifiers
SOIC, TA = 0ƒC to 85ƒC
-0.8
70
0.8
0
-0.8
10
Offset Voltage Drift (µV/ƒC)
C013
OPA192ID and OPA2192ID
C013
OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW
Figure 9. Offset Voltage Drift Distribution
from 0°C to 85°C
Figure 10. Offset Voltage Drift Distribution
from 0°C to 85°C
100
50
190 Typical Units Shown
5 Typical Units Shown
75
25
25
VOS ( V)
VOS ( V)
50
0
±25
0
VCM = -18.1 V
±50
±25
±75
±100
±75
±50
±25
±50
0
25
50
75
100
125
Temperature (ƒC)
Figure 11. Offset Voltage vs Temperature
14
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150
±20
±15
±10
±5
0
VCM (V)
C001
5
10
15
20
C001
Figure 12. Offset Voltage vs Common-Mode Voltage
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
200
100
5 Typical Units Shown
5 Typical Units Shown
VS = ±2.25 V
150
75
VCM = +18.1 V
100
50
VOS ( V)
50
VOS ( V)
VCM = -18.1 V
25
0
0
±50
±25
P-Channel
N-Channel
±150
±75
Transition
±100
12.5
13.5
14.5
15.5
16.5
17.5
VCM (V)
Transition
P-Channel
±200
±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5
18.5
Figure 13. Offset Voltage vs Common-Mode Voltage
Gain (dB)
VOS ( V)
80.0
0
±10
±20
180
20.0
0.0
10.0 12.0 14.0 16.0 18.0 20.0
VSUPPLY (V)
Phase
±20.0
1
Figure 15. Offset Voltage vs Power Supply
10
100
1k
10k 100k
Frequency (Hz)
1M
0
10M 100M
C004
Figure 16. Open-Loop Gain and Phase vs Frequency
20
G = -100
G = +1
G = -1
G = -10
15
Input Bias Current (pA)
40.0
90
45
C001
60.0
135
40.0
±40
±50
Open-loop Gain
60.0
±30
8.0
C001
Phase (ƒ)
10
6.0
2.5
120.0
100.0
4.0
2.0
Figure 14. Offset Voltage vs Common-Mode Voltage
20
2.0
1.5
CLOAD = 15 pF
30
0.0
1.0
140.0
10 Typical Units Shown
VS = ±2.25 V to “18 V
40
N-Channel
VCM (V)
C001
50
Gain (dB)
VCM = +2.35 V
VCM = -2.35 V
±100
±50
20.0
0.0
IB-
10
5
0
IB+
±5
±10
±15
±20.0
1000
10k
100k
1M
Frequency (Hz)
±20
±18.0
10M
±9.0
Figure 17. Closed-Loop Gain and Phase vs Frequency
0.0
9.0
VCM (V)
C003
18.0
C001
Figure 18. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
6000
(V-) + 5
IB+
IB Ios
Input Bias Current (pA)
5000
(V-) + 4
+125°C
4000
(V-) + 3
Vout (V)
3000
2000
(V-) + 2
-40°C
(V-) + 1
1000
(V-)
Ios
0
±1000
(V-) - 1
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
175
0
Common-Mode Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
30
40
50
60
70
80
C001
Figure 20. Output Voltage Swing vs Output Current
(Maximum Supply)
160.0
140.0
120.0
100.0
80.0
60.0
+PSRR
CMRR
20.0
20
Iout (mA)
Figure 19. Input Bias Current vs Temperature
40.0
10
C001
-PSRR
10
8
6
4
VS = ±2.25 V, VCM = V+ - 3 V
2
0
±2
VS = ±18 V, VCM = 0 V
±4
±6
±8
±10
0.0
1
10
100
1k
10k
100k
Frequency (Hz)
1M
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
C012
Figure 21. CMRR and PSRR vs Frequency
125
150
C001
Figure 22. CMRR vs Temperature
0.8
0.6
0.4
400 nV/div
Power-Supply Rejection Ratio (µV/V)
1
0.2
0
-0.2
-0.4
-0.6
-0.8
Peak-to-Peak Noise = VRMS × 6.6 = 1.30 Vpp
-1
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
Figure 23. PSRR vs Temperature
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125
Time (1 s/div)
150
C001
C001
Figure 24. 0.1-Hz to 10-Hz Noise
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
Total Harmonic Distortion + Noise (%)
Voltage Noise Density (nV/rtHz)
VCM = V+ - 100 mV
N-Channel Input
100
10
VCM = 0 V
P-Channel Input
1
10
100
1k
G = +1 V/V, RL = 2 k
G = -1 V/V, RL = 10 k
0.01
10k
0.001
-100
0.0001
-120
VOUT = 3.5 VRMS
BW = 80 kHz
-140
10
100k
Frequency (Hz)
-80
0.001
-100
0.1
-120
1.1
1.0
0.9
-140
1
0.8
10
0
Output Amplitude (VRMS)
C007
1.2
IQ (mA)
Total Harmonic Distortion + Noise (%)
0.01
Total Harmonic Distortion + Noise (dB)
-60
G = +1 V/V, RL = 10 k
G = +1 V/V, RL = 2 k
G = -1 V/V, RL = 10 k
G = -1 V/V, RL = 2 k
10k
Figure 26. THD+N Ratio vs Frequency
f = 1 kHz
BW = 80 kHz
0.00001
0.01
1k
Frequency (Hz)
Figure 25. Input Voltage Noise Spectral Density
vs Frequency
0.0001
100
C002
0.1
-80
G = -1 V/V, RL = 2 k
0.00001
1
0.1
-60
G = +1 V/V, RL = 10 k
Total Harmonic Distortion + Noise (dB)
0.1
1000
4
8
12
16
20
24
28
32
36
Supply Voltage (V)
C008
Figure 27. THD+N vs Output Amplitude
C001
Figure 28. Quiescent Current vs Supply Voltage
3.0
1.2
Vs = 4.5 V
Vs = 36 V
2.0
1.1
AOL (µV/V)
IQ (mA)
1.0
Vs = ±18 V
1
Vs = ±2.25 V
0.0
±1.0
0.9
±2.0
±3.0
0.8
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Figure 29. Quiescent Current vs Temperature
150
RL = 10 kŸ
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 30. Open-Loop Gain vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10k
50
RII = 1NŸ
kO
R
G = -1
RFF = 1NŸ
kO
45
40
1k
Overshoot (%)
Output Impedance ( )
+ 18 V
100
±
+
35
RISO
OPA192
+
VIN
CL
±
30
± 18 V
25
20
RISO = 00
15
RISO = 2525
10
RISO = 50 50
5
10
0
0
1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
10p
100p
Figure 31. Open-Loop Output Impedance vs Frequency
1n
Capacitive Load (F)
C016
C013
Figure 32. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
50
±
40
35
OPA192
+
VIN
RL
CL
+
+
±
37 VPP ± 18 V
Sine Wave
(±18.5V)
± 18 V
±
5 V/div
30
VIN
+ 18 V
±
RISO
OPA192
+
Overshoot (%)
G = +1
+ 18 V
45
25
20
VOUT
15
VOUT
RISO = 0 0
RISO = 25
25
RISO = 50
50
10
5
0
10p
100p
Time (200 s/div)
1n
Capacitive Load (F)
C011
C013
Figure 33. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 34. No Phase Reversal
kO
RRI I = 1 NŸ
+ 18 V
VOUT
RRI = 1 kO
NŸ
I
±
+
RRF = 10 kO
NŸ
F
OPA192
OPA192
G = -10
VOUT
+
±
VOUT
± 18 V
5 V/div
5 V/div
±
±
+
VOUT
+
VIN
+ 18 V
VIN
RRFF = 10 kO
NŸ
± 18 V
G = -10
VIN
VIN
Time (200 ns/div)
Time (200 ns/div)
C009
Figure 35. Positive Overload Recovery
18
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C010
Figure 36. Negative Overload Recovery
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SBOS620E – DECEMBER 2013 – REVISED NOVEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
kO
RRI I = 1NŸ
G = -1
kO
RRF F = 1NŸ
+ 18 V
±
+
OPA192
+
±
20 mV/div
20 mV/div
VIN
G = +1
+ 18 V
±
CL
± 18 V
OPA192
+
+
VIN
RL
± 18 V
CL
±
RL = 1 kŸ
CL = 10 pF
CL = 10 pF
Time (120 ns/div)
Time (100 ns/div)
C006
C015
Figure 38. Small-Signal Step Response (100 mV)
Figure 37. Small-Signal Step Response (100 mV)
4
kO
RI RI = 1NŸ
Output Delta from Final Value (mV)
2 V/div
RL = 1 kŸ
CL = 10 pF
G = -1
kO
RFRF = 1NŸ
+ 18 V
±
+
OPA192
+
VIN
±
CL
± 18 V
G = +1
3
2
1
0
-1
0.01% Settling = ±1 mV
-2
-3
Step Applied at t = 0
-4
Time (300 ns/div)
0
0.25
0.5
0.75
C005
1.25
1.5
1.75
2
C034
Figure 40. Settling Time (10-V Positive Step)
Figure 39. Large-Signal Step Response
4
4
G = +1
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
1
Time ( s)
3
2
1
0
0.01% Settling = ±500 V
-1
-2
-3
Step Applied at t = 0
-4
G = +1
3
2
1
0
-1
0.01% Settling = ±1 mV
-2
-3
Step Applied at t = 0
-4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Time ( s)
1.8
0
0.2
0.4
0.8
1
1.2
1.4
1.6
1.8
Time ( s)
C034
Figure 41. Settling Time (5-V Positive Step)
0.6
2
C034
Figure 42. Settling Time (10-V Negative Step)
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
80
G = +1
ISC, Source
3
2
1
0
0.01% Settling = ±500 V
-1
-2
40
20
-3
Step Applied at t = 0
0
-4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Time ( s)
±75
1.8
30
0
Output Voltage (5 V/div)
VS = ±5 V
VS = ±2.25 V
1M
100
125
150
C001
tpLH = 0.97 s
VOUT Voltage
0
Time (200 ns/div)
10M
Frequency (Hz)
75
Overdrive = 100 mV
15
100k
50
Figure 44. Short-Circuit Current vs Temperature
20
10k
25
Temperature (ƒC)
25
5
±25
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
10
±50
C034
Figure 43. Settling Time (5-V Negative Step)
Output Voltage (VPP)
ISC, Sink
60
ISC (mA)
Output Delta from Final Value (mV)
4
C025
C033
Figure 45. Maximum Output Voltage vs Frequency
Figure 46. Propagation Delay Rising Edge
-100
VOUT Voltage
Crosstalk (db)
Output Voltage (1 V/div)
-80
tpLH = 1.1 s
Overdrive = 100 mV
-120
-140
-160
Time (200 ns/div)
-180
1k
10k
C026
Figure 47. Propagation Delay Falling Edge
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1M
Frequency (Hz)
Figure 48. Crosstalk vs Frequency
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7 Parameter Measurement Information
7.1 Input Offset Voltage Drift
The OPAx192 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input
offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with
input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming
internal device parameters during either wafer probing or final testing. When trimming input offset voltage drift the
systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated
with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this
concept.
Input Offset Voltage
VOS Before e-trim
VOS After e-trim
Linear component of drift
Linear component of drift
Temperature
Figure 49. Input Offset Before and After Drift Trim
A common method of specifying input offset voltage drift is the box method. The box method estimates a
maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the
corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the
box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method
works particularly well when the input offset drift is dominated by the linear component of drift, but because the
OPA192 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box
method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical
units of the OPAx192 with the box method superimposed for illustrative purposes. The boundaries of the box are
determined by the specified temperature range along the x-axis and the maximum specified input offset voltage
across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift
of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much
less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input
offset voltage drift and is not recommended when performing an error analysis.
Offset Voltage vs Temperature
100
75
Offset Voltage (PV)
50
25
0
-25
-50
-75
-100
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 50. The Box Method
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Input Offset Voltage Drift (continued)
Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input
offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along
the input offset voltage versus temperature curve. The results for the OPAx192 family are shown in Figure 51
and Figure 52.
1.1
SOIC
0.6
Input Offset Voltage Drift ( V/ƒC)
Input Offset Voltage Drift ( V/ƒC)
1
0.8
+3 1
+1
0.4
0.2
0
-0.2
-0.4
-1
-0.6
-3 1
-0.8
-1
SOT and VSSOP
0.9
+3 1
0.7
+1
0.5
0.3
0.1
-0.1
-0.3
-0.5
-1
-0.7
-0.9
-3 1
-1.1
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±75
150
±50
±25
0
25
50
75
Temperature (ƒC)
C001
Figure 51. Input Offset Voltage Drift vs Temperature
(OPA192ID and OPA2192ID)
100
125
150
C001
Figure 52. Input Offset Voltage Drift vs Temperature
(OPA192IDBV, OPA192IDGK, OPA2192IDGK, and
OPA4192IPW)
As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to
+125°C. When performing an error analysis over the full specified temperature range, use the typical and
maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced
temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error
analysis. To determine the change in input offset voltage, use Equation 1:
ΔVOS = ΔT × dVOS/dT
where
•
•
•
ΔVOS = Change in input offset voltage
ΔT = Change in temperature
dVOS/dT = Input offset voltage drift
(1)
For example, determine the amount of OPA192ID input offset voltage change over the temperature range of
25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This
input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.15 µV/°C = 7.5 µV .
For 3 σ (99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results
in a typical input offset voltage change of (75°C – 25°C) × 0.4 µV/°C = 20 µV.
Figure 53 shows six typical units.
75
6 Typical Units Shown
50
31
VOS ( V)
25
0
±25
-3 1
±50
±75
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C001
Figure 53. Input Offset Voltage Drift vs Temperature for Six Typical Units
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8 Detailed Description
8.1 Overview
The OPAx192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are
set, further communication to the trim structure is permanently disabled. The Functional Block Diagram section
shows the simplified diagram of the OPA192 with e-trim.
Unlike previous e-trim op amps, the OPAx192 uses a patented two-temperature trim architecture to achieve a
very low offset voltage of 25 µV (max) and low voltage offset drift of 0.5 µV/°C (max) over the full specified
temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for
high-impedance industrial sensors, filters, and high-voltage data acquisition.
8.2 Functional Block Diagram
OPAx192
NCH Input
Stage
IN+
36-V
Differential
Front End
Slew
Boost
High
Capacitive Load
Compensation
Output
Stage
VOUT
IN
PCH Input
Stage
t
e-trim
Package Level Trim
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8.3 Feature Description
8.3.1 Input Protection Circuitry
The OPAx192 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 54 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 55. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling
time, as shown in Figure 56.
V+
V+
VIN+
VIN+
VOUT
OPA192
36 V
VOUT
~0.7 V
VIN
VIN
V
OPA192 Provides Full 36-V
Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 54. OPA192 Input Protection Does Not Limit Differential Input Capability
Vn = +10 V
RFILT
+10 V
1
Ron_mux
Sn
1
D
2
~±9.3 V
+10 V
CFILT
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Vin±
2
Ron_mux
Sn+1
~0.7 V
CS
CFILT
Vout
Idiode_transient
±10 V
Input Low Pass Filter
Vin+
Buffer Amplifier
Simplified Mux Model
Figure 55. Back-to-Back Diodes Create Settling Issues
Output Delta From Final Value (mV)
100
Standard Input Diode Structure
Extends Settling Time
80
60
40
0.1% Settling = ±10 mV
20
0
±20
OPA192 Input Structure
Offers Fast Settling
±40
±60
±80
±100
0
5
10
15
20
25
30
35
40
45
50
55
Time ( s)
60
C040
Figure 56. OPA192 Protection Circuit Maintains Fast-Settling Transient Response
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Feature Description (continued)
The OPAx192 family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications. This patented input protection architecture does not introduce additional signal distortion or
delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.
The OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the
op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping
input signals such as multiplexed data-acquisition systems; see Figure 66.
8.3.2 EMI Rejection
The OPAx192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx192 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 57 shows the results of this testing on the OPA192. Table 2 shows the EMIRR IN+ values for the OPA192
at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in the
application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from
www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
140.0
EMIRR IN+ (dB)
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
1G
Frequency (Hz)
10G
C017
Figure 57. EMIRR Testing
Table 2. OPA192 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
44.1 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
52.8 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
61.0 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
69.5 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.7 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
105.5 dB
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8.3.3 Phase Reversal Protection
The OPAx192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx192 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 58.
VIN
+ 18 V
±
OPA192
VOUT
+
±
37 VPP ± 18 V
Sine Wave
(±18.5V)
5 V/div
+
VOUT
Time (200 s/div)
C011
Figure 58. No Phase Reversal
8.3.4 Thermal Protection
TA = 65°C
PD = 0.81W
JA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
+30 V
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx192 has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 59 shows an application example for
the OPA192 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.
The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 59 shows
how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the
output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
3V
Normal
Operation
0V
Output
High-Z
150°C
OPA192
+
±
VIN
3V
+
RL
3V
100 Ÿ ±
140ºC
Temperature
IOUT = 30 mA
Figure 59. Thermal Protection
8.3.5 Capacitive Load and Stability
The OPAx192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 60 and Figure 61. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier will be stable in operation.
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50
50
RII = 1NŸ
kO
R
G = -1
RFF = 1NŸ
kO
45
±
+
±
35
+
VIN
±
30
40
RISO
CL
± 18 V
25
35
+
VIN
RL
25
RISO = 00
15
RISO = 2525
15
10
RISO = 50 50
10
20
RISO = 0 0
RISO = 25
25
RISO = 50
50
5
0
0
10p
100p
1n
10p
Capacitive Load (F)
CL
± 18 V
±
30
20
5
RISO
OPA192
+
OPA192
Overshoot (%)
Overshoot (%)
40
G = +1
+ 18 V
45
+ 18 V
100p
1n
Capacitive Load (F)
C013
Figure 60. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
C013
Figure 61. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
(10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 62. This resistor significantly reduces
ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 62 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to
optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,
and test results.
+Vs
Vout
Riso
+
Vin
Cload
+
±
-Vs
Figure 62. Extending Capacitive Load Drive with the OPA192
Table 3. OPA192 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
VALUE
Capacitive Load
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
Phase Margin
45°
60°
45°
60°
45°
60°
45°
60°
45°
60°
RISO (Ω)
47.0
360.0
24.0
100.0
20.0
51.0
6.2
15.8
2.0
4.7
Measured
Overshoot (%)
23.2 8.6
10.4
22.5
9.0
22.1
8.7
23.1
8.6
21.0
8.6
Calculated PM
45.1°
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
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8.3.6 Common-Mode Voltage Range
The OPAx192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 63. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary
modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD
performance may be degraded compared to operation outside this region.
+Vsupply
IS1
VINPCH1
NCH4
NCH3
PCH2
VIN+
e-TrimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
-Vsupply
Figure 63. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx192 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in
Figure 64.
Transition
Region
N-Channel
Region
P-Channel
Region
200
200
100
100
Input Offset Voltage ( V)
Input Offset Voltage ( V)
P-Channel
Region
0
±100
OPA192 e-Trim
Input Offset Voltage vs Vcm
±200
Transition
Region
N-Channel
Region
0
±100
±200
Input Offset Voltage vs Vcm
without e-Trim Input
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
Figure 64. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
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8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 65 shows an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
±
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
OPA192
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 65. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
8.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx192 is approximately 200 ns.
8.4 Device Functional Modes
The OPAx192 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx192 is 36 V (±18 V).
30
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx192 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the OPAx192 a robust, highperformance operational amplifier for high-voltage industrial applications.
9.2 Typical Applications
9.2.1 16-Bit Precision Multiplexed Data-Acquisition System
Figure 66 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
Very Low Output Impedance
Input-Filter Bandwidth
±20-V,
10-kHz
Sine Wave
OPA192
+
+
OPA192
3
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
4
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Voltage
Reference
CH0+
RC Filter
Buffer
RC Filter
Reference Driver
CH0-
Gain
Network
OPA192
Gain
Network
+
4:2
Mux
REFP
+
CH3+
OPA140
Gain
Network
OPA192
VINP
+
Antialiasing
Filter
SAR
ADC
+
VINM
OPA192
CH3-
CONV
Gain
Network
±20-V,
10-kHz
Sine Wave
OPA192
+
n
16 Bits
400 kSPS
High-Voltage Level Translation
VCM
High-Voltage Multiplexed Input
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
Counter
n
Shmidtt
Trigger
Delay
Digital Counter For Multiplexer
5
Fast logic transition
Figure 66. OPA192 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs with Lowest Distortion
9.2.1.1 Design Requirements
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest
distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.
The design requirements for this block design are:
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Typical Applications (continued)
•
•
•
•
•
System Supply Voltage: ±15 V
ADC Supply Voltage: 3.3 V
ADC Sampling Rate: 400 kSPS
ADC Reference Voltage (REFP): 4.096 V
System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
9.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 66. The circuit
is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output
buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. The diagram includes the most important specifications for each
individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next
step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage
with low offset, drift, and noise contributions.
9.2.1.3 Application Curve
Integral Nonlinearity Error (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
Figure 67. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
32
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9.2.2 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx192 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 68 shows the OPA192 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 kŸ
VEE
VEE
+
R2
1.6 MŸ
VIN
OPA192
V+
OPA192
V+
VOUT
VCC
RL
10 kŸ
VCC
Figure 68. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
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9.2.3 Precision Reference Buffer
The OPAx192 features high output current drive capability and low input offset voltage, making the device an
excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the
10-µF ceramic capacitor shown in Figure 69, RISO, a 37.4-Ω isolation resistor, provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output, VOUT.
Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized
stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still
provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability
components: RF, RFx , CF , and RISO.
RF
1 kŸ
RFx
10 kŸ
CF
39 nF
RISO
37.4 Ÿ
OPA192
V+
VOUT
CL
10 µF
VREF
2.5 V
VCC
Figure 69. Precision Reference Buffer
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10 Power-Supply Recommendations
The OPAx192 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 70, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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11.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 70. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 TI Precision Designs
The
OPA192
is
featured
in
several
TI
Precision
Designs,
available
online
at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
Circuit Board Layout Techniques, SLOA089.
Op Amps for Everyone, SLOD006.
12.3 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA192
Click here
Click here
Click here
Click here
Click here
OPA2192
Click here
Click here
Click here
Click here
Click here
OPA4192
Click here
Click here
Click here
Click here
Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.5 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA192ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA192
OPA192IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUYS
OPA192IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUYS
OPA192IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUXS
OPA192IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUXS
OPA192IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA192
OPA2192ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2192
OPA2192IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OVLM
OPA2192IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OVLM
OPA2192IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2192
OPA4192ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4192
OPA4192IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4192
OPA4192IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
OPA4192
OPA4192IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
OPA4192
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
OPA192IDBVR
SOT-23
3000
180.0
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.23
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
OPA192IDBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
OPA192IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA192IDGKT
VSSOP
DGK
8
250
177.8
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA192IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2192IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2192IDGKT
VSSOP
DGK
8
250
177.8
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2192IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4192IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA192IDBVR
SOT-23
DBV
5
3000
223.0
270.0
35.0
OPA192IDBVT
SOT-23
DBV
5
250
223.0
270.0
35.0
OPA192IDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
OPA192IDGKT
VSSOP
DGK
8
250
223.0
270.0
35.0
OPA192IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2192IDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
OPA2192IDGKT
VSSOP
DGK
8
250
223.0
270.0
35.0
OPA2192IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA4192IDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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