STMicroelectronics LD49150 1.5a very low drop for low output voltage regulator Datasheet

LD49150
1.5A Very low drop for low output voltage regulator
Feature summary
■
Input voltage range:
VI = 1.4V to 5.5V
VBIAS = 3V to 6V
■
Stable with ceramic capacitor
■
±1.5% initial tolerance
■
Maximum dropout voltage (VI - VO) of 200mV
over temperature
■
Adjustable output voltage down to 0.8V
■
Ultra fast transient response (up to 10MHz
bandwidth)
■
Excellent line and load regulation
specifications
■
Logic controlled shutdown option
■
Thermal shutdown and current limit protection
■
Junction temperature range: –25°C to 125°C
PPAK
5.5V and the bias supply requires between 3V
and 6V for proper operation. The LD49150 offers
fixed output voltages from 0.8V to 1.8V and
adjustable output voltages down to 0.8V.
The LD49150 requires a minimum output
capacitance for stability, and work optimally with
small ceramic capacitors.
Applications
Description
The LD49150 is a high-bandwidth, low-dropout,
1.5A voltage regulator, ideal for powering core
voltages of low-power microprocessors. The
LD49150 implements a dual supply configuration
allowing for very low output impedance and very
fast transient response. The LD49150 requires a
bias input supply and a main input supply,
allowing for ultra-low input voltages on the main
supply rail. The input supply operates from 1.4V to
■
Graphics processors
■
PC Add-In Cards
■
Microprocessor core voltage supply
■
Low voltage digital ICs
■
High Efficiency Linear power supplies
■
SMPS post regulators
Order codes
Part number
Package
Packaging
LD49150PT08R (1)
PPAK (Tape&Reel)
2500 parts per reel
LD49150PT10R
PPAK (Tape&Reel)
2500 parts per reel
LD49150PT12R
PPAK (Tape&Reel)
2500 parts per reel
1. Adjustable Version.
April 2007
Rev. 1
1/20
www.st.com
20
LD49150
Contents
Contents
1
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
Input supply voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.2
Bias supply voltage (VBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.3
External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.4
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.5
Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.6
VIN and VBIAS power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.7
Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.8
Heatsinking PPAK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.9
Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.10
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
LD49150
1
Typical application circuits
Typical application circuits
Figure 1.
Adjustable version
Figure 2.
Fixed version with Enable
3/20
Alternative application circuits
2
Alternative application circuits
Figure 3.
Single supply voltage solution
Figure 4.
LD49150 plus DC/DC pre-regulator to reduce power dissipation
4/20
LD49150
LD49150
3
Pin configuration
Pin configuration
Figure 5.
Pin connections (top view)
Table 1.
Pin description
Pln n°
1
Symbol
Note
EN
ADJ
VIN
Enable (Input): Logic High = Enable, Logic Low = Shutdown.
Adjustable regulator feedback input. Connect to resistor voltage divider.
Input voltage which supplies current to the output power device.
Ground (TAB is connected to ground).
Regulator output.
Input bias voltage for powering all circuitry on the regulator with the exception of the output
power device.
2
3
4
GND
VOUT
5
VBIAS
5/20
LD49150
Diagram
4
Figure 6.
6/20
Diagram
Block diagram
LD49150
5
Maximum ratings
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
VIN
Supply voltage
VOUT
Output voltage
VBIAS
BIAS Supply voltage
VEN
Enable input voltage
PD
Power dissipation
TSTG
Value
Unit
-0.3 to 7
-0.3 to VIN + 0.3
-0.3 to VBIAS + 0.3
V
-0.3 to 7
V
-0.3 to 7
V
V
Internally Limited
Storage temperature range
-50 to 150
°C
Note: 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional Operation under these conditions is not implied.
2 All the values are referred to ground.
Table 3.
Operating ratings
Symbol
Parameter
Value
Unit
VIN
Supply voltage
1.4 to 5.5
V
VOUT
Output voltage
0.8 to 4.5
V
VBIAS
BIAS Supply voltage
V
VEN
Enable input voltage
3 to 6
0 to VBIAS
V
Junction temperature range
-25 to 125
°C
TJ
7/20
LD49150
Electrical characteristics
6
Electrical characteristics
Table 4.
Electrical characteristics
(TJ = -25°C to 125 °C, VBIAS = VO+2.1V (1); VI = VO+1V; VEN = VBIAS (2), IO = 10mA; CI = 1µF;
CO = 10µF; CBIAS = 1µF; unless otherwise specified. Typical values are referred to TJ = 25°C).
Symbol
VO
Parameter
Output voltage accuracy
Test conditions
VLINE
Line regulation
VDROP
Load regulation
Dropout voltage (VI - VO)
IL = 1.5A
VDROP
Dropout voltage (VBIAS- VO)
IL = 1.5A (1)
Ground pin current
IGND_SHD Ground pin current in shutdown
IVBIAS
IL
Current through VBIAS
Current limit
Enable Input
VEN
IEN
Typ.
-1.5
-3
-0.1
Over temperature range
VI = VO+1V to 5.5V
VLOAD
IGND
Min.
TJ = 25°C, fixed voltage options
IL = 0mA to 3A, VBIAS ≥ 3V
Max.
Unit
1.5
3
0.1
%/V
1
%
%
200
mV
1.5
2.1
V
IL = 0mA
4
6
IL = 1.5A
4
6
VEN ≤0.4V (2)
5
IL = 0mA
3
5
IL = 1.5A
3
5
VO = 0V
2.5
Regulator Enable
Regulator Shutdown
1.4
mA
µA
mA
A
(2)
Enable input threshold (fixed
voltage only)
Enable pin input current
0.1
0.4
1
0.8
0.8
0.812
0.824
V
µA
Reference
VREF
Reference voltage
SVR
Supply voltage rejection
TJ = 25°C
Over temperature range
VI = 2.5V±0.5V, VO = 1V,
F = 120Hz, VBIAS = 3.3V
0.788
0.776
1. For VO ≤1V, VBIAS dropout specification does not apply due to a minimum 3V VBIAS input.
2. Fixed output voltage version only.
8/20
68
V
dB
LD49150
7
Typical characteristics
Typical characteristics
Figure 7.
Reference voltage vs temperature
Figure 8.
Figure 9.
Load regulation vs temperature
Figure 10. Line regulation vs temperature
Figure 11. Output voltage vs input voltage
Output voltage vs temperature
Figure 12. Dropout voltage (VIN-VOUT) vs
temperature
9/20
Typical characteristics
LD49150
Figure 13. Dropout voltage (VIN-VOUT) vs
temperature
Figure 14. VBIAS pin current vs temperature
Figure 15. Noise vs frequency
Figure 16. Quiescent current vs temperature
Figure 17. Supply voltage rejection vs output
current
Figure 18. Stability region vs COUT & High ESR
10/20
LD49150
Typical characteristics
Figure 19. Stability region vs COUT & Low ESR Figure 20. VBIAS & VIN Start Up transient
response (VIN and VBIAS Start Up at
the same time)
VIN=VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
Figure 21. VIN Start Up transient response
(VBIAS Start Up before VIN)
Figure 22. VIN Start Up transient response
(VBIAS Start Up before VIN)
VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF
11/20
Typical characteristics
Figure 23. VIN Start Up transient response
(VBIAS Start Up before VIN and
VINH=VIN)
VIN=VINH=2.5V, VBIAS=3.1V, VOUT=1V, COUT=1µF
12/20
LD49150
LD49150
8
Application hints
Application hints
The LD49150 is an ultra-high performance, low dropout linear regulator, designed for high
current application that requires fast transient response. The LD49150 operates from two input
voltages, to reduce dropout voltage. The LD49150 is designed so that a minimum of external
component are necessary.
8.1
Input supply voltage (VIN)
VIN provides the power input current to the LD49150. The minimum input voltage can be as low
as 1.4V, allowing conversion from very low voltage supplies to achieve low output voltage levels
with very low power dissipation.
8.2
Bias supply voltage (VBIAS)
The LD49150 control circuitry is supplied the VBIAS pin which requires a very low bias current
(3mA typ.) even at the maximum output current level (1.5A). A bypass capacitor on the bias pin
is recommended to improve the performance of the LD49150 during line and load transient.
The small ceramic capacitor from VBIAS to ground reduces high frequency noise that could be
injected into the control circuitry from the bias rail. In typical applications a 1µF ceramic chip
capacitor may be used. The VBIAS input voltage must be 2.1V above the output voltage, with a
minimum VBIAS input voltage of 3V.
8.3
External capacitors
To assure regulator stability, input and output capacitors are required as shown in the typical
application circuit.
8.4
Output capacitor
The LD49150 requires a minimum output capacitance to maintain stability. A ceramic chip
capacitor of at least 1µF is required. However, specific capacitor selection could be needed to
ensure the transient response. A 1µF ceramic chip capacitor satisfies most applications but
10µF is recommended to ensure better transient performances. In applications where the VIN
level is close to the maximum operating voltage (VIN>4V), it is strongly recommended to use an
output capacitors of, at least, 10µF in order to avoid over-voltage stress on the Input/output
power pins during short circuit conditions due to parasitic inductive effect. The output capacitor
must be located as close as possible to the output pin of the LD49150. The ESR (equivalent
series resistance) of the output capacitor must be within the "STABLE" region as shown in the
typical characteristics figures. Both ceramic and tantalum capacitors are suitable.
8.5
Minimum load current
The LD49150 does not require a minimum load to maintain output voltage regulation.
13/20
Application hints
8.6
LD49150
VIN and VBIAS power sequencing
In common applications where the power on transient of VIN and VBIAS voltages are not
particularly fast (Tr>100µs), no power sequencing is required. Where voltage transient input
(Tr<100µs) is very fast, it is recommended to have the VIN voltage present before or, at least, at
the same time as the VBIAS voltage in order to avoid overvoltage spikes during the power on
transient (refer to the figures in the typical characteristics). Where VIN transient input
(Tr<<100µs) is very fast for the fixed VOUT versions, it is possible to avoid start-up overvoltage
spikes by pulling the VINH pin up to VIN voltage (refer to relative typical characteristics figures at
pages 11 and 12).
8.7
Power dissipation/heatsinking
A heatsink may be required depending on the maximum power dissipation and maximum
ambient temperature of the application. Under all possible conditions, the junction temperature
must be within the range specified under operating conditions. The total power dissipation of
the device is given by:
PD = VIN x IIN + VBIAS x IBIAS - VOUT x IOUT
Where:
●
VIN, Input supply voltage
●
VBIAS, Bias supply voltage
●
VOUT, Output voltage
●
IOUT, Load current
From this data, we can calculate the thermal resistance (θ SA) required for the heat sink using
the following formula:
θSA = (TJ - TA/PD) - (θJC + θCS)
The maximum allowed temperature rise (TRmax) depends on the maximum ambient
temperature (TAmax) of the application, and the maximum allowable junction temperature
(TJmax):
TRmax = TJmax - TAmax
The maximum allowable value for junction to ambient thermal resistance, θ JA, can be
calculated using the formula:
θJAmax = TRmax / PD
This part is available for the PPAK package.
The thermal resistance depends on the amount of copper area or heat sink, and on air flow. If
the maximum allowable value of θ JA calculated above is ≥100 °C/W for the PPAK package, no
heatsink is needed since the package can dissipate enough heat to satisfy these requirements.
If the value for allowable θ JA falls below these limits, a heat sink is required as described below.
14/20
LD49150
8.8
Application hints
Heatsinking PPAK package
The PPAK package uses the copper plane on the PCB as a heatsink. The tab of these
packages is soldered to the copper plane for heat sinking. It is also possible to use the PCB
ground plane a heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a
dual layer PCB, it can be an unbroken GND area on the opposite side where the IC is situated
with a dissipating area thermally connected through vias holes, filled by solder.
Figure 26 shows a curve for θ JA of the PPAK package for different copper area sizes, using a
typical PCB with 1/16 in thick G10/FR4.
Figure 24.
8.9
θJA vs Copper Area for PPAK package
Adjustable regulator design
The LD49150 adjustable version allows fixing output voltage anywhere between 0.8V and 4.5V
using two resistors as shown in the typical application circuit. For example, to fix the R1 resistor
value between VOUT and the ADJ pin, the resistor value between ADJ and GND (R2) is
calculated by:
R2 = R1 [0.8/(VOUT - 0.8)]
Where VOUT is the desired output voltage.
It is suggested to use R1 values lower than 10KΩ to obtain better load transient performances.
Even, higher values up to 100KΩ are suitable.
8.10
Enable
The fixed output voltage versions of LD49150 feature an active high Enable input (EN) that
allows on-off control of the regulator. The EN input threshold is guaranteed between 0.4V and
1.4V, for simple logic interfacing. The regulator is set in shut down mode when VEN<0.4V and it
is in operating mode (VOUT activated) when VEN>1.4V. If not in use, the EN pin must be tied
directly to the VIN to keep the regulator continuously activated. The En pin must not be left at
high impedance.
15/20
Package mechanical data
9
LD49150
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
16/20
LD49150
Package mechanical data
PPAK MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.4
0.6
0.015
0.023
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
D1
E
5.1
6.4
0.244
0.201
6.6
0.252
0.260
E1
4.7
0.185
e
1.27
0.050
G
4.9
5.25
0.193
0.206
G1
2.38
2.7
0.093
0.106
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.6
L5
1
L6
1
1
2.8
0.031
0.023
0.039
0.039
0.039
0.110
0078180-E
17/20
LD49150
Package mechanical data
Tape & Reel DPAK-PPAK MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MIN.
TYP.
330
13.0
13.2
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
18/20
MAX.
0.504
0.512
22.4
0.519
0.882
Ao
6.80
6.90
7.00
0.268
0.272
0.2.76
Bo
10.40
10.50
10.60
0.409
0.413
0.417
Ko
2.55
2.65
2.75
0.100
0.104
0.105
Po
3.9
4.0
4.1
0.153
0.157
0.161
P
7.9
8.0
8.1
0.311
0.315
0.319
LD49150
10
Revision history
Revision history
Table 5.
Revision history
Date
Revision
18-Apr-2007
1
Changes
Initial release.
19/20
LD49150
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