ON NVMFS6B03NLT1G Power mosfet Datasheet

NVMFS6B03NL
Power MOSFET
100 V, 4 mW, 145 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS6B03NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
4 mW @ 10 V
100 V
145 A
6 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
100
V
Gate−to−Source Voltage
VGS
±16
V
ID
145
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Pulsed Drain Current
Steady
State
ID
A
20
PD
D
TJ, Tstg
−55 to
+ 175
°C
IS
160
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 60 A)
EAS
180
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
MARKING
DIAGRAM
2.0
520
Source Current (Body Diode)
N−CHANNEL MOSFET
W
3.9
IDM
Operating Junction and Storage Temperature
S (1,2,3)
14
TA = 100°C
TA = 25°C, tp = 10 ms
W
198
99
TA = 100°C
TA = 25°C
G (4)
102
PD
D (5,6)
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 6B03NL (NVMFS6B03NL) or
XXXXXX = 6B03LW (NVMFS6B03NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
0.76
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
38
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 0
1
Publication Order Number:
NVMFS6B03NL/D
NVMFS6B03NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
100
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
40.9
VGS = 0 V,
VDS = 80 V
mV/°C
TJ = 25°C
25
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 16 V
VGS(TH)
VGS = VDS, ID = 250 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
1.0
3.0
−6.4
VGS = 10 V
ID = 20 A
VGS = 4.5 V
V
mV/°C
3.3
4.0
4.8
6.0
mW
CHARGES AND CAPACITANCES
Input Capacitance
CISS
5320
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
110
Total Gate Charge
QG(TOT)
70.7
Threshold Gate Charge
QG(TH)
9.4
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
7.4
Plateau Voltage
VGP
3.3
td(ON)
19.9
VGS = 0 V, f = 1 MHz, VDS = 25 V
VGS = 10 V, VDS = 50 V; ID = 50 A
1850
pF
nC
17.3
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 50 V,
ID = 50 A, RG = 2.5 W
tf
181.7
ns
28.7
152.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.81
TJ = 125°C
0.7
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
64.7
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 25 A
QRR
33.4
ns
31.8
99
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS6B03NL
TYPICAL CHARACTERISTICS
3.8 V
VDS = 10 V
ID, DRAIN CURRENT (A)
120
3.6 V
100
3.4 V
80
60
3.2 V
40
3.0 V
100
80
60
20
0
0
0.5
1.5
1.0
2.0
4
3
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 50 A
TJ = 25°C
8
6
4
2
0
4
5
6
8
7
9
10
VGS, GATE VOLTAGE (V)
6.0
TJ = 25°C
5.5
VGS = 4.5 V
5.0
4.5
4.0
VGS = 10 V
3.5
3.0
2.5
2.0
10
30
50
90
70
110
130
150
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.E+05
2.4
ID = 50 A
VGS = 10 V
TJ = 150°C
2.0
1.E+04
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
2
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
2.2
1
TJ = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
12
3
TJ = 125°C
0
3.0
2.5
TJ = 25°C
40
20
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
140
VGS =
140 10 V to
4V
120
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
160
1.8
1.6
1.4
TJ = 125°C
1.E+03
1.2
1.0
TJ = 85°C
1.E+02
0.8
0.6
0.4
−50 −25
1.E+01
0
25
50
75
100
125
150
175
0
10
20
30
40
50
60
70
80
90 100
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NVMFS6B03NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
1E+4
C, CAPACITANCE (pF)
Ciss
Coss
1E+3
Crss
1E+2
1E+1
VGS = 0 V
TJ = 25°C
f = 1 MHz
1E+0
0
10
20
30
40
50
60
70
80
90
9
QT
8
7
6
5
Qgd
Qgs
4
3
TJ = 25°C
VDS = 50 V
ID = 50 A
2
1
0
100
8
0
16
24
32
40
48
56
64
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
72
100
1000
IS, SOURCE CURRENT (A)
VDS = 50 V
ID = 50 A
VGS = 4.5 V
tr
tf
100
td(off)
10
td(on)
TJ = 125°C
10
TJ = 25°C
TJ = −55°C
1
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
10
100
VGS ≤ 10 V
Single Pulse
TC = 25°C
500 ms
10
1 ms
1
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.01
0.1
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFS6B03NL
TYPICAL CHARACTERISTICS
100
120
IPEAK, DRAIN CURRENT (A)
GFS, SMALL−SIGNAL FORWARD
TRANSFER CONDUCTANCE (S)
140
100
80
60
40
20
0
25°C
10
100°C
1
0
40
20
60
80
100
120
140
0.1E−3
1E−3
10E−3
ID, DRAIN CURRENT (A)
TAV, TIME IN AVALANCHE (sec)
Figure 12. GFS vs. ID
Figure 13. IPEAK vs. TAV
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
NVMFS6B03NL, 650 mm2, 2 oz, Cu Single Layer Pad
0.01 Single Pulse
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 14. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVMFS6B03NLT1G
6B03NL
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS6B03NLWFT1G
6B03LW
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS6B03NLT3G
6B03NL
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS6B03NLWFT3G
6B03LW
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS6B03NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.15
6.30
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
DETAIL A
0.495
4.560
2X
0.10
8X b
C A B
0.05
c
1.530
e/2
e
L
1
3.200
4
4.530
K
1.330
2X
E2
PIN 5
(EXPOSED PAD)
L1
0.905
M
1
0.965
4X
G
D2
1.000
4X 0.750
BOTTOM VIEW
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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NVMFS6B03NL/D