ISSI IS43R16800CC-6TL Commands entered on each positive clk edge Datasheet

IS43R16800CC
8Mx16
128Mb DDR Synchronous DRAM
FEATURES:
• Vdd =Vddq = 2.5V+0.2V (-5, -6, -75)
• Double data rate architecture; two data transfers
per clock cycle.
• Bidirectional , data strobe (DQS) is transmitted/
received with data
• Differential clock input (CLK and /CLK)
• DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
• Commands entered on each positive CLK edge;
• Data and data mask referenced to both edges of
DQS
• 4 bank operation controlled by BA0 , BA1
(Bank Address)
• /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;
Burst length -2 / 4 / 8 (programmable)
Burst type -Sequential / Interleave (programmable)
• Auto precharge/ All bank precharge controlled
by A10
• 4096 refresh cycles / 64ms (4 banks concurrent
refresh)
• Auto refresh and Self refresh
• Row address A0-11 / Column address A0-8
• SSTL_2 Interface
• Package:
66-pin TSOP II
• Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
JUNE 2009
DESCRIPTION:
IS43R16800CC is a 4-bank x 2,097,152-word x 16bit
double data rate synchronous DRAM , with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The device
achieves very high speed clock rate up to 200 MHz.
KEY TIMING PARAMETERS
Parameter
-5
-6
-75
Clk Cycle Time
CAS Latency = 3
5
6
7.5
CAS Latency = 2.5
5
6
7.5
CAS Latency = 2
7.5
7.5
7.5
Clk Frequency
CAS Latency = 3
200
167
133
CAS Latency = 2.5 200
167
133
CAS Latency = 2
133
133
133
Access Time from Clock
CAS Latency = 3
+0.70 +0.70 +0.75
CAS Latency = 2.5 +0.70 +0.70 +0.75
CAS Latency = 2
+0.75 +0.75 +0.75
Unit
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ADDRESS TABLE
Parameter
Configuration
Bank Address Pins
8M x 16
2M x 16 x 4 banks
BA0, BA1
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
A10/AP
A0 – A11
A0 – A8
4096 / 64ms
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. A
06/01/09
1
IS43R16800CC
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
VDD
1
66
VSS
DQ0
2
65
DQ15
VDDQ
3
64
VSSQ
DQ1
4
63
DQ14
DQ2
5
62
DQ13
VSSQ
6
61
VDDQ
DQ3
7
60
DQ12
DQ4
8
59
DQ11
VDDQ
9
58
VSSQ
DQ5
10
57
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VDDQ
DQ7
13
54
DQ8
NC
14
53
NC
VDDQ
15
52
VSSQ
LDQS
16
51
UDQS
NC
17
50
NC
VDD
18
49
VREF
NC
19
48
VSS
LDM
20
47
UDM
WE
21
46
CK
CAS
22
45
CK
RAS
23
44
CKE
CS
24
43
NC
NC
25
42
NC
BA0
26
41
A11
BA1
27
40
A9
A10/AP
28
39
A8
A0
29
38
A7
A1
30
37
A6
A2
31
36
A5
A3
32
35
A4
VDD
33
34
VSS
PIN DESCRIPTION:
A0-A11
Row Address Input
WE
Write Enable
A0-A8
Column Address Input
LDM, UDM
Data Write Mask
BA0, BA1
Bank Select Address
LDQS, UDQS
Data Strobe
DQ0 – DQ15
Data I/O
VDD
Power
CLK, CLK
System Clock Input
VDDQ
Power Supply for I/O Pins
CKE
Clock Enable
VSS
Ground
CS
Chip Select
VSSQ
Ground for I/O Pins
CAS
Column Address Strobe
Command
VREF
SSTL_2 reference voltage
RAS
Row Address Strobe
Command
NC
No Connection
2
Integrated Silicon Solution, Inc.
Rev. A
06/01/09
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
BA0,1
Input
D
DQ0-15
D
UDQS, LDQS
D
UDM, LDM
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by A0-8.
A10 is also used to indicate precharge option. When A10 is high at a read / write,
an auto precharge is performed. When A10 is high at a precharge command,
all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Input / Output
Data Input/Output: Data bus
Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
VDD, VSS
Power Supply
Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ
Power Supply
VDDQ, and VSSQ are supplied to the Output Buffers only.
Vref
Input
Integrated Silicon Solution, Inc.
DDR SDRAM (Rev.1.1)
Rev.
06/01/09
SSTL_2 reference voltage.
3
IS43R16800CC
DQ 0 - 15
UDQS, LD QS
I/O B uffer
DQ S Buffer
BLOCK DIAGRAM x16
DLL
Memory
Array
Bank #0
Memory
Array
Ba nk #1
Memory
Array
Ba nk #2
Memory
Array
Ba nk #3
Mode Re gister
Control C ircu itry
Addres s B uffer
Control Signal B uffer
Cl ock B uffer
A0-11
/CS /RAS /CAS
BA 0,1
CLK
4
/CLK
CKE
/WE
UDM ,
LD M
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
ISSI's 128-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
Integrated
Silicon
Solution, Inc.
DDR SDRAM
(Rev.1.1)
Rev.
06/01/09
5
Zentel Electronics Corporation
I
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
I
COMMAND TRUTH TABLE
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
H
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
H
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
H
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
H
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
H
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
H
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
H
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TERM
H
H
L
H
H
L
X
X
X
1
Mode Register Set
MRS
H
H
L
L
L
L
L
L
V
2
COMMAND
/WE BA0,1
A10
/AP
A0-9, note
11
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the
op-code to be written to the selected Mode Register.
6
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
A3S56D30/40ETP
Preliminary
IS43R16800CC
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State
IDLE
ROW ACTIVE
READ(AutoPrecharge
Disabled)
/CS /RAS /CAS /WE Address
H
X
X
X X
Action
NOP
Notes
L
L
H
H
H
H
H X
L BA
NOP
TERM
NOP
ILLEGAL
L
L
L
H
L
L
L
H
H
X BA, CA, A10
H BA, RA
L BA, A10
READ / WRITE
ACT
PRE / PREA
ILLEGAL
Bank Active, Latch RA
NOP
4
L
L
L
REFA
Auto-Refresh
5
L
L
L
MRS
Mode Register Set
5
H
L
L
X
H
H
X
H
H
H X
Op-Code, ModeL
Add
X X
H X
L BA
DESEL
NOP
TERM
L
H
L
H BA, CA, A10
READ / READA
L
H
L
L
WRITE / WRITEA
L
L
H
H BA, RA
ACT
NOP
NOP
ILLEGAL
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Bank Active / ILLEGAL
2
L
L
L
L
H
L
PRE / PREA
REFA
Precharge / Precharge All
ILLEGAL
L
L
L
MRS
ILLEGAL
H
L
X
H
X
H
L BA, A10
H X
Op-Code, ModeL
Add
X X
H X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
L
H
H
L
TERM
L
H
L
H BA, CA, A10
READ / READA
L
H
L
L
WRITE / WRITEA
Terminate Burst
Terminate Burst, Latch CA, Begin
New Read, Determine AutoPrecharge
ILLEGAL
L
L
L
L
H
H
H BA, RA
L BA, A10
ACT
PRE / PREA
Bank Active / ILLEGAL
Terminate Burst, Precharge
L
L
L
L
L
L
H X
REFA
Op-Code, ModeL
MRS
Add
Integrated
Silicon
Solution, Inc.
DDR SDRAM
(Rev.1.1)
Rev.
06/01/09
Command
DESEL
BA, CA, A10
BA
BA, CA, A10
2
2
3
2
ILLEGAL
ILLEGAL
7
Zentel Electronics Corporation
I
A3S56D30/40ETP
Preliminary
IS43R16800CC
I
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
WRITE(AutoPrecharge
Disabled)
READ with
Auto-Precharge
WRITE with
Auto-Precharge
8 DDR
/CS /RAS /CAS /WE Address
H
X
X
X X
L
H
H
H X
Command
DESEL
NOP
Action
NOP (Continue Burst to END)
NOP (Continue Burst to END)
L
H
H
L BA
TERM
L
H
L
H BA, CA, A10
READ / READA
L
H
L
L BA, CA, A10
WRITE / WRITEA
L
L
H
H BA, RA
ACT
ILLEGAL
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge
Bank Active / ILLEGAL
L
L
L
L
H
L
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
L
L
L
MRS
ILLEGAL
H
X
X
L BA, A10
H X
Op-Code, ModeL
Add
X X
DESEL
NOP (Continue Burst to END)
L
H
H
H X
NOP
NOP (Continue Burst to END)
L
L
L
L
L
H
H
H
L
L
H
L
L
H
H
L
H
L
H
L
TERM
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL
Precharge / ILLEGAL
L
L
L
ILLEGAL
L
L
L
H
X
X
H X
REFA
Op-Code, ModeL
MRS
Add
X X
DESEL
L
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
H
L
H
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL
L
L
L
L
H
L
L
L
L
L BA, A10
PRE / PREA
H X
REFA
Op-Code, ModeL
MRS
Add
SDRAM (Rev.1.1)
BA
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
BA
BA, CA, A10
BA, CA, A10
BA, RA
NOP
TERM
READ / READA
WRITE / WRITEA
ACT
Notes
3
3
2
2
2
ILLEGAL
NOP (Continue Burst to END)
Precharge / ILLEGAL
ILLEGAL
2
2
ILLEGAL
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
PRECHARGING
ROW
ACTIVATING
WRITE RECOVERING
/CS /RAS /CAS /WE Address
H
X
X
X X
Action
NOP (Idle after tRP)
Notes
L
H
H
H X
NOP
NOP (Idle after tRP)
L
L
L
H
H
L
H
L
H
L BA
X BA, CA, A10
H BA, RA
TERM
READ / WRITE
ACT
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
L
L
H
L
PRE / PREA
NOP (Idle after tRP)
4
L
L
L
L
L
L
H
X
X
H X
REFA
Op-Code, ModeL
MRS
Add
X X
DESEL
NOP (Row Active after tRCD)
L
H
H
H X
NOP
NOP (Row Active after tRCD)
L
L
L
H
H
L
H
L
H
L BA
X BA, CA, A10
H BA, RA
TERM
READ / WRITE
ACT
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
L
L
H
L
PRE / PREA
ILLEGAL
2
L
L
L
L
L
L
H
X
X
H X
REFA
Op-Code, ModeMRS
L
Add
X X
DESEL
NOP
L
H
H
H X
NOP
NOP
L
L
L
H
H
L
H
L
H
L BA
X BA, CA, A10
H BA, RA
TERM
READ / WRITE
ACT
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
L
L
H
L
PRE / PREA
ILLEGAL
2
L
L
L
L
L
L
H X
REFA
Op-Code, ModeMRS
L
Add
Integrated Silicon Solution, Inc.
DDR SDRAM (Rev.1.1)
Rev.
06/01/09
Command
DESEL
BA, A10
BA, A10
BA, A10
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
9
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
REFRESHING H
X
X
X X
MODE
REGISTER
SETTING
Command
DESEL
Action
NOP (Idle after tRC)
NOP
TERM
READ / WRITE
ACT
PRE / PREA
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
L
H
H
H
L
L
H
H
L
H
H
H
L
X
H
L
X
BA
BA, CA, A10
BA, RA
BA, A10
L
L
L
H
L
L
L
L
ILLEGAL
H
X
X
X
X
REFA
Op-Code, ModeMRS
Add
X
DESEL
L
L
L
L
L
H
H
H
L
L
H
H
L
H
H
H
L
X
H
L
X
BA
BA, CA, A10
BA, RA
BA, A10
NOP (Row Active after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
H
L
L
L
L
X
REFA
Op-Code, ModeMRS
Add
NOP
TERM
READ / WRITE
ACT
PRE / PREA
Notes
ILLEGAL
NOP (Row Active after tRSC)
ILLEGAL
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
10
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
A3S56D30/40ETP
Preliminary
IS43R16800CC
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESHING
POWER
DOWN
ALL BANKS
IDLE
ANY STATE
other than listed
above
CKE n-1
CKE n
/CS
/RAS
/CAS
/WE
Address
Action
Notes
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
L
X
ILLEGAL
1
L
H
L
H
L
X
X
ILLEGAL
1
L
H
L
L
X
X
X
ILLEGAL
1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
1
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
2
H
L
L
L
L
H
X
Enter Self-Refresh
2
H
L
H
X
X
X
X
Enter Power Down
2
H
L
L
H
H
H
X
Enter Power Down
2
H
L
L
H
H
L
X
ILLEGAL
2
H
L
L
H
L
X
X
ILLEGAL
2
H
L
L
L
X
X
X
ILLEGAL
2
L
X
X
X
X
X
X
Refer to Current State =Power Down
2
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
3
L
L
X
X
X
X
X
Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Integrated Silicon Solution, Inc.
Rev.
06/01/09
DDR SDRAM (Rev.1.1)
11
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
POWER
ON
PRE
CHARGE
ALL
PREA
SELF
REFRESH
REFS
MRS
MODE
REGISTER
SET
REFSX
MRS
AUTO
REFRESH
REFA
IDLE
CKEL
CKEH
Active
Power
Down
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
WRITE
BURST
STOP
READ
WRITEA
WRITE
READA
READ
WRITEA
READ
READ
TERM
READA
READA
WRITEA
READA
PRE
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
12DDR
SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
CLK
MODE REGISTER
/CLK
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when all banks are in idle state. After tMRD from a
MRS command, the DDR SDRAM is ready for new command.
/CS
/RAS
/CAS
/WE
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA0
BA1
0
0
0
0
Latency
Mode
0
0
0
0
0
1
1
1
1
CL
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
DR
0
LTMODE
/CAS Latency
R
R
2
3
R
R
2.5
R
BT
BL
Burst
Length
A11-A0
0
0
0
0
1
1
1
1
Burst Type
DLL Reset
0
NO
1
YES
Integrated Silicon Solution, Inc.
Rev.
06/01/09
BL
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
V
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
0
Sequential
1
Interleaved
R: Reserved for Future Use
13
IS43R16800CC
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
CLK
mode register (EMRS). The extended mode register stores these data
/CLK
until the next EMRS command, which may be issued when all banks are
in idle state. After tMRD from a EMRS command, the DDR SDRAM is
/CS
ready for new command.
/RAS
/CAS
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/WE
BA0
0
1
0
0
0
0
0
0
0
0
0
0
DS
DD
BA1
V
A11-A0
DLL Disable
Drive
Strength
14
0
1
0
1
DLL Enable
DLL Disable
Normal
Weak
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
A3S56D30/40ETP
Preliminary
IS43R16800CC
256M Double Data Rate Synchronous DRAM
/CLK
CLK
Command
Read
Write
Y
Y
Address
DQS
Q0 Q1 Q2 Q3
DQ
CL= 2
BL= 4
Initial Address
A2
Burst
Length
Burst
Length
/CAS
Latency
BL
Column Addressing
A1 A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
-
-
1
1
0
1
0
8
4
2
Integrated Silicon Solution, Inc.
DDR
SDRAM (Rev.1.1)
Rev.
06/01/09
D0 D1 D2 D3
15
IS43R16800CC
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
-0.5 ~ VDD+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VDDQ +0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25 C
1500
mW
Topr
Operating Temperature
Commercial Temperature
Industrial Temperature
0 to 70
Tstg
o
Storage Temperature
o
C
-40 to +85
o
C
-65 ~ 150
o
C
DC OPERATING CONDITIONS
(Ta=0 ~ 70oC, unless otherwise noted)
Limits
Parameter
Unit
Not es
Min.
Typ.
Max.
Supply Voltage
2.3
2.5
2.7
V
-5, -6, -75
Supply Voltage for Output
2.3
2.5
2.7
V
-5, -6, -75
Vref+0.15
Vdd+0.3
-0.3
Vref-0.15
V
V
-2
2
uA
-5
5
uA
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Any input 0V<VIN<VDD
(All other pins not under test = 0V)
Output Leakage Current:DQ are
disabled:0V<Vout<VddQ
Output Levels:
Output high Voltage (Iout=-4mA)
Output Low Voltage(Iout=4mA)
V
2.4
0.4
V
CAPACITANCE
o
(Ta=0 ~ 70 C, Vdd = VddQ = 2.5V + 0.2V Vss = VssQ = 0V, unless otherwise noted)
16
Symbol
Parameter
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
I/O Capacitance, I/O, DQS, DM pin
Test Condition
VI=1.25v
f=100MHz
VI=25mVrms
Limits
Delta
Unit Notes
Cap.(Max.)
Min. Max.
1.3 2.5
pF
0.75
1.3 2.5
pF
1.3
2.5
0.25
pF
2
4
1.3
pF
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
AVERAGE SUPPLY CURRENT from Vdd
(
o
C (Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
-5
Limits(Max.)
-6
-75
185
165
150
30
25
20
55
50
50
45
40
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
IDD3N
DQ,DM and DQS inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
95
90
75
OPERATING CURRENT: Burst =2; Read ; Continuous burst;All banks
IDD4R active; Address and control inputs changing once per clock cycle;t CK = t
CK MIN; IOUT = 0 mA
290
250
210
OPERATING CURRENT: Burst =2; Write ; Continuous burst;All banks
IDD4W active; Address and control inputs changing once per clock cycle;t CK = t
CK MIN; DQ and DQS inputs changing twice per clock cycle
290
250
210
170
160
150
5
5
Symbol
Parameter/Test Conditions
OPERATING CURRENT: One Bank; Active-Read-Precharge;Burst = 2; t
IDD1 RC = t RC MIN; t CK = t CK MIN; IOUT= 0mA; Address and control
inputs changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE <VIL (MAX); t CK = t CK MIN
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
IDD2N CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
IDD3P
ACTIVE POWER DOWN STANDBY CURRENT: One bank active;power
down mode;CKE VIL(MAX);t CK = t CK MIN
IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN)
IDD6 SELF REFRESH CURRENT: CKE < 0.2V
Integrated Silicon Solution, Inc.
Rev.
06/01/09
60
Unit
Notes
mA
5
17
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS
Symbol
tAC
-5
AC Characteristics Parameter
DQ Output access time from CLK//CLK
tDQSCK DQS Output access time from CLK//CLK
-6
-75
Min.
Max
Min.
Max
Min.
Max
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
Unit
ns
-0.6
+0.6
-0.60
+0.60
-0.75
+0.75
ns
tCH
CLK High level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
CLK Low level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
CLK cycle time
CL=3.0
5
7.5
6
12
7.5
12
ns
CL=2.5
5
12
6
12
7.5
12
ns
CL=2.0
7.5
12
7.5
12
7.5
12
ns
tDS
Input Setup time (DQ,DM)
0.4
0.45
0.5
ns
tDH
Input Hold time(DQ,DM)
0.4
0.45
0.5
ns
tIPW
Control & address input pulse width (for each input)
2.2
2.2
2.2
ns
tDIPW DQ and DM input pulse width (for each input)
tHZ
Data-out-high impedance time from CLK//CLK
tLZ
Data-out-low impedance time from CLK//CLK
1.75
1.75
+0.70
-0.70
tDQSQ DQ Valid data delay time from DQS
+0.70
1.75
+0.70
-0.70
0.40
+0.70
-0.75
0.45
ns
+0.75
ns
14
+0.75
ns
14
0.5
ns
tHP
Clock half period
tCLmin or
tCHmin
tCLmin or
tCHmin
tCLmin or
tCHmin
ns
tQH
DQ output hold time from DQS (per access)
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns
tQHS
Data hold skew factor (for DQS & associated DQ signals)
tDQSS
Write command to first DQS latching transition
0.50
0.72
1.25
0.55
0.75
1.25
Notes
20
0.75
0.75
1.25
tCK
tDQSH DQS input High level width
0.35
0.35
0.35
tCK
tDQSL DQS input Low level width
0.35
0.35
0.35
tCK
tDSS
DQS falling edge to CLK setup time
0.2
0.2
0.2
tCK
tDSH
DQS falling edge hold time from CLK
0.2
0.2
0.2
tCK
tMRD
Mode Register Set command cycle time
2
2
2
tCK
0
0
0
ns
16
tCK
15
tWPRES Write preamble setup time
tWPST Write postamble
0.4
tWPRE Write preamble
0.25
0.25
0.25
tCK
Input Setup time (address and control)
0.6
0.75
0.9
ns
19
ns
19
tIS
tIH
0.6
0.4
0.6
0.6
Input Hold time (address and control)
0.6
tRPST
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tRPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
tCK
18DDR
SDRAM (Rev.1.1)
0.75
0.4
0.9
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
AC TIMING REQUIREMENTS(Continues)
Symbol
-5
AC Characteristics Parameter
-6
-75
Min.
Max
Min.
Max
Min.
Max
120,000
42
120,000
45
120,000
Unit
tRAS
Row Active time
40
tRC
Row Cycle time(operation)
55
60
65
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
70
72
75
ns
tRCD
Row to Column Delay
15
18
20
ns
Row Precharge time
15
18
20
ns
tRRD
Act to Act Delay time
10
12
15
ns
tWR
Write Recovery time
15
15
15
ns
tWR+tRP
tWR+tRP
tWR+tRP
ns
2
1
1
tCK
tXSNR Exit Self Ref. to non-Read command
75
75
75
ns
tXSRD Exit Self Ref. to -Read command
tRP
tDAL
Auto Precharge write recovery + precharge time
tWTR
Internal Write to Read Command Delay
Notes
ns
200
200
200
tCK
tXPNR Exit Power down to command
1
1
1
tCK
tXPRD Exit Power down to -Read command
1
1
1
tCK
18
µs
17
tREFI
Average Periodic Refresh interval
15.6
15.6
15.6
Output Load Condition
VREF
DQS
DQ
VTT =V REF
VREF
50Ω
VOUT
Zo=50Ω
30pF
Integrated Silicon Solution, Inc.
Rev.
06/01/09
VREF
Output Timing
Measurement
Reference Point
19
Zentel Electronics Corporation
I
IS43R16800CC
I
Preliminary
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the
range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively
switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be
set equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level
of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) =
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE< 0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. Min (tCL,tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device.
Timing patterns:
tCK=min,tRRD=2*tCK,BL=4,tRCD=3*tCK,Read with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R3 A0 N A1 R0 – repeat the same timing with random address changing
*100% of data changing at every burst
Legend: A=Activate,R=Read,P=Precharge,N=NOP
20
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
Read Operation
tCK
/CLK
tCH
tCL
CLK
tIS
Cmd &
Add.
DQS
tIH
Valid Data
tDQSCK
tRPRE
VREF
tRPST
tQH
tDQSQ
DQ
tAC
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
tWPST
tDSS
tWPRES
DQS
tDQSL
tWPRE
tDQSH
tDS
tDH
DQ
Write Operation / tDQSS=min.
/CLK
CLK
DQS
tDSH
tDQSS
tWPST
tWPRES
tWPRE
tDQSL
tDS
tDQSH
tDH
DQ
Integrated Silicon Solution, Inc.
Rev.
06/01/09
21
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A0-11. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
Command
ACT
tRRD
A0-9,11
Xa
tRCmin
ACT READ
PRE
tRP
tRAS
Xb
ACT
Y
tRCD
Xb
BL/2
A10
Xa
Xb
0
BA0,1
00
01
00
1
Xb
01
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
22
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
I
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A0-8, and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks.
When A10 is high at a READ command, the auto-precharge (READA) is performed. Any
command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is
complete. The internal precharge starts at BL/2 after READA. The next ACT command can be
issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
ACT
READ ACT
READ PRE
tRCD
A0-9,11
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
BA0,1
00
00
10
10
00
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb7
Qb8
Burst Length
/CAS latency
Integrated
Silicon
Solution, Inc.
DDR SDRAM
(Rev.1.1)
Rev.
06/01/09
23
IS43R16800CC
READ with Auto-Precharge (BL=8, CL=2,2.5,3.0)
0
1
2
3
4
5
/CLK
CLK
Command
7
8
9
10
11
12
BL/2 + tRP
ACT
READ
tRCD
tRP
BL/2
Xa
Y
A10
Xa
1
BA0,1
00
00
A0-9,11
6
DQS
CL=2
DQ
Qa0
Qa1
Qa2
Qa3
Qa4 Qa5
Qa6
Qa7
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
DQS
CL=2.5
DQ
DQS
CL=3.0
DQ
Qa7
Internal Precharge Start Timing
24
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
I
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A0-8, and the address
sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous input data by
interleaving the multiple banks. From the last data to the PRE command, the write recovery time
(tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
Command
A0-9,11
ACT
tRCD
Xa D
WRITE ACT
Ya
Xb
WRITE
tRCD
D
PRE
PRE
Yb
A10
Xa
Xa
0
Xb
0
0
0
BA0,1
00
00
10
10
00
10
DQS
DQ
Integrated Silicon Solution, Inc.
DDR SDRAM (Rev.1.1)
Rev.
06/01/09
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
25
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
WRITE with Auto-Precharge (BL=8)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
Command
ACT
WRITE
ACT
tDAL
tRC
A0-9,11
Xa
D
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
DQS
DQ
26
DDR SDRAM (Rev.1.1)
Da0
Da1
Da2 Da3
Da4
Da5
Da6
Da7
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
READ READ
READ
READ
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
01
A0-9,11
DQS
DQ
Qai0 Qai1 Qaj0 Qaj1
Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2
Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Command
CL=2.0
Q0
READ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.
06/01/09
27
Zentel Electronics Corporation
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
IS43R16800CC
I
/CLK
CLK
Command
Read Interrupted by Precharge (BL=8)
READ
PRE
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Command
CL=3.0
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
DDR SDRAM (Rev.1.1)
28
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
READ
TERM
DQS
DQ
Command
CL=2.0
Q0
READ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
Q4
TERM
DQS
DQ
Command
READ TERM
DQS
DQ
Command
READ
TERM
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q5
TERM
DQS
DQ
Command
READ TERM
DQS
DQ
Integrated
Silicon
Solution, Inc.
DDR
SDRAM
(Rev.1.1)
Rev.
06/01/09
29
IS43R16800CC
Read Interrupted by TERM (BL=8)
/CLK
CLK
READ
Command
TERM
DQS
DQ
READ
Command
CL=3.0
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
TERM
DQS
DQ
READ TERM
Command
DQS
DQ
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
CL=2.0
READ
Command
Q0
READ
Q2
D0
Q3
D1
D2
D3
D4
D5
D6
D7
D0 D1
D2
D3
D4
D5
D0
D2
D3
D4
D5
WRITE
DQS
Command
Q0
READ
Q1
Q2
Q3
TERM
WRITE
DQS
DQ
30
Q1
TERM
DQ
CL=3.0
WRITE
DQS
DQ
CL=2.5
TERM
Q0
Q1
Q2
Q3
D1
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
Command
A0-9,11
WRITE WRITE
WRITE
WRITE
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
00
00
10
00
DQS
DQ
Dai0 Dai1 Daj0
Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0
Dal1 Dal2 Dal3 Dal4 Dal5 Dal6
Dal7
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The
input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first
positive edge after the last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
Command
A0-9,11
A10
BA0,1
WRITE
READ
Yi
Yj
0
0
00
00
DM
tWTR
QS
DQ
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Dai0
Dai1
Qaj0
Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6
Qaj7
31
Zentel Electronics Corporation
I
IS43R16800CC
I
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column
access is allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
Command
A0-9,11
A10
BA0,1
WRITE
PRE
Yi
0
00
00
tWR
DM
QS
DQ
32
DDR SDRAM (Rev.1.1)
Dai0
Dai1
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Zentel Electronics Corporation
I
IS43R16800CC
A3S56D30/40ETP
Preliminary
256M Double Data Rate Synchronous DRAM
[Initialize and Mode Register sets]
Initialize and MRS
/CLK
CLK
CKE
Command
NOP
PRE
A0-11
1
A10
BA0,1
EMRS
MRS
Code
Code
Code
Code
10
00
PRE
AR
AR
MRS
ACT
Xa
1
Code
Xa
00
Xa
DQS
DQ
tMRD
Extended Mode
Register Set
tMRD
tRP
tRFC
tRFC
tMRD
Mode Register Set,
Reset DLL
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H)
command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh
128Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing
an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum
tRFC . Any command must not be supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-12
BA0,1
Auto Refresh on All Banks
Integrated
Silicon
Solution, Inc.
DDR SDRAM
(Rev.1.1)
Rev.
06/01/09
Auto Refresh on All Banks
33
IS43R16800CC
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are
disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the
self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
X
Y
BA0,1
X
Y
tXSNR
tXSRD
Self Refresh Exit
34
Integrated Silicon Solution, Inc.
Rev.
06/01/09
IS43R16800CC
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the selfrefresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time
is NOT required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power Down
CKE
Command
PRE
NOP
NOP
Valid
tXPNR/tXPRD
Active Power Down
CKE
Command
ACT NOP
NOP
Valid
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM
to write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
WRITE
READ
DM
Don't Care
DQS
DQ
D0 D1
D3 D4
D5 D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
masked by DM=H
Integrated Silicon Solution, Inc.
Rev.
06/01/09
35
IS43R16800CC
ORDERING INFORMATION - Vdd = 2.5V
Commercial Range: 0°C to +70°C
Frequency
Speed (ns)
Order Part No.
Package
200 MHz
5
IS43R16800CC-5TL
66-pin TSOP-II, Lead-free
166 MHz
6
IS43R16800CC-6TL
66-pin TSOP-II, Lead-free
Industrial Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
200 MHz
5
IS43R16800CC-5TLI
66-pin TSOP-II, Lead-free
166 MHz
6
IS43R16800CC-6TLI
66-pin TSOP-II, Lead-free
36
Integrated Silicon Solution, Inc.
Rev. A
06/01/09
Integrated Silicon Solution, Inc.
Rev.
06/01/09
Θ
Package Outline
10/04/2006
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
3. Dimension b does not include dambar protrusion/intrusion.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
IS43R16800CC
37