STMicroelectronics M58LR128HB 128 mbit (8 mb ã 16, multiple bank, multilevel interface, burst) 1.8 v supply flash memory Datasheet

M58LR128HT
M58LR128HB
128 Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst)
1.8 V supply Flash memories
Features
■
■
Supply voltage
– VDD = 1.7 V to 2.0 V for program, erase and
read
– VDDQ = 1.7 V to 2.0 V for I/O Buffers
– VPP = 9 V for fast program
FBGA
Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 54 MHz
– Asynchronous Page Read mode
– Random access: 85 ns
■
Synchronous Burst Read Suspend
■
Programming time
– 2.5 µs typical word program time using
Buffer Enhanced Factory Program
command
■
Memory organization
– Multiple Bank memory array: 8 Mbit banks
– Parameter Blocks (top or bottom location)
■
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
■
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■
Common Flash Interface (CFI)
■
100 000 program/erase cycles per block
February 2007
VFBGA56 (ZB) 7.7 × 9 mm
■
Electronic signature
– Manufacturer code: 20h
– Top device codes:
M58LR128HT: 88C4h
– Bottom device codes
M58LR128HB: 88C5h
■
VFBGA56 package
– ECOPACK® compliant
Rev 1
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www.st.com
1
Contents
M58LR128HT, M58LR128HB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
2/112
2.1
Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13
VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.14
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.15
VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M58LR128HT, M58LR128HB
5
6
Contents
4.5
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9
Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10
Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 24
4.10.1
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10.2
Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10.3
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.12
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.13
Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.14
Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.15
Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.16
Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.17
Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
Program/Erase Controller Status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
Erase Suspend Status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3
Erase/Blank Check Status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4
Program Status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5
VPP Status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.6
Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7
Block Protection Status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.8
Bank Write/Multiple Word Program Status bit (SR0) . . . . . . . . . . . . . . . . 36
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1
Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2
X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3
Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4
Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5
Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.6
Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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M58LR128HT, M58LR128HB
6.7
Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.8
Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.9
Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2
Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.1
7.3
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8
Dual operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 48
9
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1
Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2
Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3
Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4
Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.5
Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 51
10
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 53
11
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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M58LR128HT, M58LR128HB
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5/112
List of tables
M58LR128HT, M58LR128HB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
6/112
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electronic Signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
X-Latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VFBGA56 7.7 × 9mm - 10×4 ball array, 0.50mm pitch, package mechanical data . . . . . . 73
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Top boot block addresses, M58LR128HT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Bottom boot block addresses, M58LR128HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bank and Erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Bank and Erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Bank and Erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Command Interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 105
Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 109
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
M58LR128HT, M58LR128HB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VFBGA56 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . 10
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
X-Latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Asynchronous random access Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Synchronous Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Single Synchronous Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous Burst Read Suspend AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reset and Power-up AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VFBGA56 7.7 × 9mm - 8×7 active ball array, 0.75mm pitch, bottom view
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Blank Check flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Buffer Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 96
Block Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Locking Operations flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Protection Register Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 100
Buffer Enhanced Factory Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . 101
7/112
Description
1
M58LR128HT, M58LR128HB
Description
The M58LR128HT/B are 128 Mbit (8 Mbit ×16) non-volatile Flash memories. They may be
erased electrically at block level and programmed in-system on a Word-by-Word basis using
a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the
Input/Output pins. An optional 9V VPP power supply is provided to speed up factory
programming.
The devices feature an asymmetrical block architecture. The M58LR128HT/B have an array
of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main
blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords
and 7 main blocks of 64 KWords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in
one bank, read operations are possible in other banks. Only one bank at a time is allowed to
be in program or erase mode. It is possible to perform burst reads that cross bank
boundaries. The bank architecture is summarized in Table 2, and the memory map is shown
in Figure 3. The Parameter Blocks are located at the top of the memory address space for
the M58LR128HT, and at the bottom for the M58LR128HB.
Each block can be erased separately. Erase can be suspended, in order to perform a
program or read operation in any other block, and then resumed. Program can be
suspended to read data at any memory location except for the one being programmed, and
then resumed. Each block can be programmed and erased over 100,000 cycles using the
supply voltage VDD. There is a Buffer Enhanced Factory programming command available
to speed up programming.
Program and erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports Synchronous Burst Read and Asynchronous Read from all blocks of
the memory array; at power-up the device is configured for Asynchronous Read. In
Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to
54 MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
The M58LR128HT/B features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤VPPLK all blocks are protected against
program or erase. All blocks are locked at power-up.
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64
bit segment containing a unique device number written by ST, and a 64 bit segment One-
8/112
M58LR128HT, M58LR128HB
Description
Time-Programmable (OTP) by the user. The user programmable segment can be
permanently protected. Figure 4, shows the Protection Register Memory Map.
The M58LR128HT/B are offered in a VFBGA56, 7.7 × 9 mm, 0.50 mm pitch package. They
are supplied with all the bits erased (set to ’1’).
Figure 1.
Logic diagram
VDD VDDQ VPP
16
DQ0DQ15
A0-A22
W
E
G
WAIT
M58LR128HT
M58LR128HB
RP
WP
L
K
VSS
Table 1.
VSSQ
AI12358
Signal names
A0-A22
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output Buffers
VPP
Optional Supply Voltage for Fast Program & Erase
VSS
Ground
VSSQ
Ground Input/Output Supply
NC
Not Connected Internally
DU
Do Not Use
9/112
Description
Figure 2.
M58LR128HT, M58LR128HB
VFBGA56 package connections (top view through package)
1
2
3
4
5
6
7
8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
A21
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
A22
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI09814
10/112
M58LR128HT, M58LR128HB
Table 2.
Description
Bank architecture
Parameter Bank
8 Mbits
4 blocks of 16 KWords
7 blocks of 64 KWords
Bank 1
8 Mbits
-
8 blocks of 64 KWords
Bank 2
8 Mbits
-
8 blocks of 64 KWords
Bank 3
8 Mbits
-
8 blocks of 64 KWords
----
Main blocks
----
Parameter blocks
----
Bank size
----
Number
Bank 14
8 Mbits
-
8 blocks of 64 KWords
Bank 15
8 Mbits
-
8 blocks of 64 KWords
Figure 3.
Memory map
M58LR128HB - Bottom Boot Block
Address lines A0-A22
M58LR128HT - Top Boot Block
Address lines A0-A22
000000h
00FFFFh
64 KWord
070000h
07FFFFh
64 KWord
Bank 15
600000h
60FFFFh
8 Main
Blocks
770000h
77FFFFh
780000h
78FFFFh
Parameter
Bank
7E0000h
7EFFFFh
7F0000h
7F3FFFh
7FC000h
7FFFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
170000h
17FFFFh
180000h
18FFFFh
64 KWord
8 Main
Blocks
4 Parameter
Blocks
16 KWord
64 KWord
7 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
Bank 2
64 KWord
Bank 1
16 KWord
Bank 1
64 KWord
8 Main
Blocks
00C000h
00FFFFh
010000h
01FFFFh
070000h
07FFFFh
080000h
08FFFFh
64 KWord
Bank 2
6F0000h
6FFFFFh
700000h
70FFFFh
Parameter
Bank
64 KWord
Bank 3
670000h
67FFFFh
680000h
68FFFFh
000000h
003FFFh
8 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
Bank 3
64 KWord
1F0000h
1FFFFFh
64 KWord
780000h
78FFFFh
64 KWord
7F0000h
7FFFFFh
64 KWord
64 KWord
7 Main
Blocks
64 KWord
16 KWord
4 Parameter
Blocks
Bank 15
16 KWord
8 Main
Blocks
AI12359b
11/112
Signal descriptions
2
M58LR128HT, M58LR128HB
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2
Data inputs/outputs (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the
memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 16: Lock status).
12/112
M58LR128HT, M58LR128HB
2.7
Signal descriptions
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to Table 21: DC characteristics - currents,
for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration
Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset
mode the device enters asynchronous read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to VRPH (refer to Table 22: DC characteristics - voltages).
2.8
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous
read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is
at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is high impedance when Output Enable is at VIH.
2.11
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read, Program and Erase).
2.12
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
13/112
Signal descriptions
2.13
M58LR128HT, M58LR128HB
VPP Program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case
a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in
the VPP1 range enables these functions (see Tables 21 and 22, DC Characteristics for the
relevant values). VPP is only sampled at the beginning of a program or erase; a change in its
value after the operation has started does not have any effect and program or erase
operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be
stable until the Program/Erase algorithm is completed.
2.14
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.15
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS
Note:
14/112
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package). See Figure 8: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required VPP program and erase currents.
M58LR128HT, M58LR128HB
3
Bus operations
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for
a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 23
and 24 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated when Chip Enable and Write Enable are at
VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the
rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be
latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL).
The Latch Enable must be tied to VIH during the bus write operation.
See Figures 15 and 16, Write AC Waveforms, and Tables 25 and 26, Write AC
Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
15/112
Bus operations
3.5
M58LR128HT, M58LR128HB
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the
Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory
content is no longer valid.
Table 3.
Bus operations(1)
Operation
Bus Read
WAIT(2)
E
G
W
L
RP
VIL
VIL
VIH
VIL(3)
VIH
Data Output
(3)
VIH
Data Input
Data Output or Hi-Z(4)
Bus Write
VIL
VIH
VIL
Address Latch
VIL
X
VIH
VIL
VIH
Output Disable
VIL
VIH
VIH
X
VIH
Hi-Z
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
VIL
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command.
3. L can be tied to VIH if the valid address has been previously latched.
4. Depends on G.
16/112
DQ15-DQ0
M58LR128HT, M58LR128HB
4
Command interface
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
program and erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor the progress or the result of the operation.
The Command Interface is reset to read mode when power is first applied, when exiting from
Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly.
Any invalid combination of commands will be ignored.
Refer to Table 4: Command codes, Table 5: Standard commands, Table 6: Factory
commands, and Appendix D: Command interface state tables, for a summary of the
Command Interface.
Table 4.
Command codes
Hex Code
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
40h
Program Setup
50h
Clear Status Register
60h
Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
80h
Buffer Enhanced Factory Program Setup
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
BCh
Blank Check Setup
C0h
Protection Register Program
CBh
Blank Check Confirm
D0h
Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer
Program or Buffer Enhanced Factory Program Confirm
E8h
Buffer Program
FFh
Read Array
17/112
Command interface
4.1
M58LR128HT, M58LR128HB
Read Array command
The Read Array command returns the addressed bank to Read Array mode.
One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read
Array mode, subsequent read operations will output the data from the memory array.
A Read Array command can be issued to any banks while programming or erasing in
another bank.
If the Read Array command is issued to a bank currently executing a program or erase
operation, the bank will return to Read Array mode but the program or erase operation will
continue, however the data output from the bank is not guaranteed until the program or
erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that is used to monitor program or erase operations.
The Read Status Register command is used to read the contents of the Status Register for
the addressed bank.
One Bus Write cycle is required to issue the Read Status Register command. Once a bank
is in Read Status Register mode, subsequent read operations will output the contents of the
Status Register.
The Status Register data is latched on the falling edge of the Chip Enable or Output Enable
signals. Either Chip Enable or Output Enable must be toggled to update the Status Register
data
The Read Status Register command can be issued at any time, even during program or
erase operations. The Read Status Register command will only change the read mode of
the addressed bank. The read modes of other banks are not affected. Only Asynchronous
Read and Single Synchronous Read operations should be used to read the Status Register.
A Read Array command is required to return the bank to Read Array mode.
See Table 9 for the description of the Status Register Bits.
18/112
M58LR128HT, M58LR128HB
4.3
Command interface
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer and Device
Codes, the Lock Status of the addressed bank, the Protection Register, and the
Configuration Register.
One Bus Write cycle is required to issue the Read Electronic Signature command. Once a
bank is in Read Electronic Signature mode, subsequent read operations in the same bank
will output the Manufacturer Code, the Device Code, the Lock Status of the addressed bank,
the Protection Register, or the Configuration Register (see Table 8).
The Read Electronic Signature command can be issued at any time, even during program or
erase operations, except during Protection Register Program operations. Dual operations
between the Parameter bank and the Electronic Signature location are not allowed (see
Table 15: Dual operation limitations for details).
If a Read Electronic Signature command is issued to a bank that is executing a program or
erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus
Read cycles will output the Electronic Signature data and the Program/Erase controller will
continue to program or erase in the background.
The Read Electronic Signature command will only change the read mode of the addressed
bank. The read modes of other banks are not affected. Only Asynchronous Read and Single
Synchronous Read operations should be used to read the Electronic Signature. A Read
Array command is required to return the bank to Read Array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface
(CFI).
One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in
Read CFI Query mode, subsequent Bus Read operations in the same bank read from the
Common Flash Interface.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will
output the CFI data and the Program/Erase controller will continue to program or erase in
the background.
The Read CFI Query command will only change the read mode of the addressed bank. The
read modes of other banks are not affected. Only Asynchronous Read and Single
Synchronous Read operations should be used to read from the CFI. A Read Array
command is required to return the bank to Read Array mode. Dual operations between the
Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual operation
limitations for details).
See Appendix B: Common Flash Interface, Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41
for details on the information contained in the Common Flash Interface memory area.
19/112
Command interface
4.5
M58LR128HT, M58LR128HB
Clear Status Register command
The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4
and 5) in the Status Register.
One Bus Write cycle is required to issue the Clear Status Register command. The Clear
Status Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
4.6
Block Erase command
The Block Erase command is used to erase a block. It sets all the bits within the selected
block to ’1’. All previous data in the block is lost.
If the block is protected then the erase operation will abort, the data in the block will not be
changed and the Status Register will output the error.
Two Bus Write cycles are required to issue the command.
●
The first bus cycle sets up the Block Erase command.
●
The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and
SR5 are set and the command is aborted.
Once the command is issued the bank enters Read Status Register mode and any read
operation within the addressed bank will output the contents of the Status Register. A Read
Array command is required to return the bank to Read Array mode.
During Block Erase operations the bank containing the block being erased will only accept
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored.
The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the Block Erase operation is aborted, the block must be erased again.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being erased.
Typical Erase times are given in Table 17: Program/Erase times and endurance cycles.
See Appendix C, Figure 23: Block Erase flowchart and pseudocode, for a suggested
flowchart for using the Block Erase command.
20/112
M58LR128HT, M58LR128HB
4.7
Command interface
Blank Check command
The Blank Check command is used to check whether a Main Array Block has been
completely erased. Only one Block at a time can be checked. To use the Blank Check
command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the
command and no error is shown in the Status Register.
Two bus cycles are required to issue the Blank Check command:
●
The first bus cycle writes the Blank Check command (BCh) to any address in the Block
to be checked.
●
The second bus cycle writes the Blank Check Confirm command (CBh) to any address
in the Block to be checked and starts the Blank Check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are
set to '1' and the command aborts.
Once the command is issued the addressed bank automatically enters the Status Register
mode and further reads within the bank output the Status Register contents.
The only operation permitted during Blank Check is Read Status Register. Dual Operations
are not supported while a Blank Check operation is in progress. Blank Check operations
cannot be suspended and are not allowed while the device is in Program/Erase Suspend.
The SR7 Status Register bit indicates the status of the Blank Check operation in progress:
SR7 = '0' means that the Blank Check operation is still ongoing. SR7 = '1' means that the
operation is complete.
The SR5 Status Register bit goes High (SR5 = '1') to indicate that the Blank Check
operation has failed.
At the end of the operation the bank remains in the Read Status Register mode until another
command is written to the Command Interface.
See Appendix C, Figure 20: Blank Check flowchart and pseudocode, for a suggested
flowchart for using the Blank Check command.
Typical Blank Check times are given in Table 17: Program/Erase times and endurance
cycles.
21/112
Command interface
4.8
M58LR128HT, M58LR128HB
Program command
The program command is used to program a single Word to the memory array.
If the block being programmed is protected, then the Program operation will abort, the data
in the block will not be changed and the Status Register will output the error.
Two Bus Write cycles are required to issue the Program Command.
●
The first bus cycle sets up the Program command.
●
The second latches the address and data to be programmed and starts the
Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output
the Status Register content.
During a Program operation, the bank containing the Word being programmed will only
accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query
and the Program/Erase Suspend command, all other commands will be ignored. A Read
Array command is required to return the bank to Read Array mode.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being programmed.
Typical Program times are given in Table 17: Program/Erase times and endurance cycles.
The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the Program operation is aborted, the Word must be reprogrammed.
See Appendix C, Figure 19: Program flowchart and pseudocode, for the flowchart for using
the Program command.
22/112
M58LR128HT, M58LR128HB
4.9
Command interface
Buffer Program command
The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up
programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program
command dramatically reduces in-system programming time compared to the standard nonbuffered Program command.
Four successive steps are required to issue the Buffer Program command.
1.
The first Bus Write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
After the first Bus Write cycle, read operations in the bank will output the contents of the
Status Register. Status Register bit SR7 should be read to check that the buffer is available
(SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to
update the Status Register contents.
2.
The second Bus Write cycle sets up the number of Words to be programmed. Value n
is written to the same block address, where n+1 is the number of Words to be
programmed.
3.
Use n+1 Bus Write cycles to load the address and data for each Word into the Write
Buffer. Addresses must lie within the range from the start address to the start address +
n, where the start address is the location of the first data to be programmed. Optimum
performance is obtained when the start address corresponds to a 32 Word boundary.
4.
The final Bus Write cycle confirms the Buffer Program command and starts the
program operation.
All the addresses used in the Buffer Program operation must lie within the same block.
Invalid address combinations or failing to follow the correct sequence of Bus Write cycles
will set an error in the Status Register and abort the operation without affecting the data in
the memory array.
If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not
accepted. Clear the Status Register before re-issuing the command.
If the block being programmed is protected an error will be set in the Status Register and the
operation will abort without affecting the data in the memory array.
During Buffer Program operations the bank being programmed will only accept the Read
Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being programmed.
See Appendix C, Figure 21: Buffer Program flowchart and pseudocode, for a suggested
flowchart on using the Buffer Program command.
23/112
Command interface
4.10
M58LR128HT, M58LR128HB
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where the programming time is critical.
It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device
enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any
number of times as long as the address remains within the same block. Only one block can
be programmed at a time.
If the block being programmed is protected, then the Program operation will abort, the data
in the block will not be changed and the Status Register will output the error.
The use of the Buffer Enhanced Factory Program command requires certain operating
conditions:
●
VPP must be set to VPPH
●
VDD must be within operating range
●
Ambient temperature TA must be 30°C ± 10°C
●
The targeted block must be unlocked
●
The start address must be aligned with the start of a 32 Word buffer boundary
●
The address must remain the Start Address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation
and the command cannot be suspended.
The Buffer Enhanced Factory Program Command consists of three phases: the Setup
Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 6: Factory
commands for detail information.
4.10.1
Setup phase
The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate
the command.
●
The first Bus Write cycle sets up the Buffer Enhanced Factory Program command.
●
The second Bus Write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The read Status Register command must not be issued as it will be interpreted as
data to program.
The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to
proceed to the next phase.
If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program
operation is terminated. See Status Register section for details on the error.
24/112
M58LR128HT, M58LR128HB
4.10.2
Command interface
Program and Verify phase
The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write
Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until
the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words
should be programmed with FFFFh.
Three successive steps are required to issue and execute the Program and Verify Phase of
the command.
1.
Use one Bus Write operation to latch the Start Address and the first Word to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check
that the P/E.C. is ready for the next Word.
2.
Each subsequent Word to be programmed is latched with a new Bus Write operation.
The address must remain the Start Address as the P/E.C. increments the address
location.If any address that is not in the same block as the Start Address is given, the
Program and Verify Phase terminates. Status Register bit SR0 should be read between
each Bus Write cycle to check that the P/E.C. is ready for the next Word.
3.
Once the Write Buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The Program and Verify phase can be repeated, without re-issuing the command, to
program additional 32 Word locations as long as the address remains in the same block.
4.
Finally, after all Words, or the entire block have been programmed, write one Bus Write
operation to any address outside the block containing the Start Address, to terminate
Program and Verify Phase.
Status Register bit SR0 must be checked to determine whether the program operation is
finished. The Status Register may be checked for errors at any time but it must be checked
after the entire block has been programmed.
4.10.3
Exit phase
Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer
Enhanced Factory Program operation and returned to Read Status Register mode. A full
Status Register check should be done to ensure that the block has been successfully
programmed. See the section on the Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be
limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the
internal algorithm will continue to work properly but some degradation in performance is
possible. Typical program times are given in Table 17.
See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudocode,
for a suggested flowchart on using the Buffer Enhanced Factory Program command.
25/112
Command interface
4.11
M58LR128HT, M58LR128HB
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Block Erase
operation. The command can be addressed to any bank.
The Program/Erase Resume command is required to restart the suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will
be set to ‘1’.
The following commands are accepted during Program/Erase Suspend:
–
Program/Erase Resume
–
Read Array (data from erase-suspended block or program-suspended Word is not
valid)
–
Read Status Register
–
Read Electronic Signature
–
Read CFI Query
Additionally, if the suspended operation was a Block Erase then the following commands are
also accepted:
–
Clear Status Register
–
Set Configuration Register
–
Program (except in erase-suspended block)
–
Buffer Program (except in erase suspended blocks)
–
Block Lock
–
Block Lock-Down
–
Block Unlock.
During an erase suspend the block being erased can be protected by issuing the Block Lock
or Block Lock-Down commands. When the Program/Erase Resume command is issued the
operation will complete.
It is possible to accumulate multiple suspend operations. For example: suspend an erase
operation, start a program operation, suspend the program operation, then read the array.
If a Program command is issued during a Block Erase Suspend, the erase operation cannot
be resumed until the program operation has completed.
The Program/Erase Suspend command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic signature or Read CFI
Query mode the bank remains in that mode and outputs the corresponding data.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed during Program/Erase Suspend.
During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL.
See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudocode, and
Figure 24: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using
the Program/Erase Suspend command.
26/112
M58LR128HT, M58LR128HB
4.12
Command interface
Program/Erase Resume command
The Program/Erase Resume command is used to restart the program or erase operation
suspended by the Program/Erase Suspend command. One Bus Write cycle is required to
issue the command. The command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic signature or Read CFI
Query mode the bank remains in that mode and outputs the corresponding data.
If a Program command is issued during a Block Erase Suspend, then the erase cannot be
resumed until the program operation has completed.
See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudocode, and
Figure 24: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using
the Program/Erase Resume command.
4.13
Protection Register Program command
The Protection Register Program command is used to program the user One-TimeProgrammable (OTP) segments of the Protection Register and the two Protection Register
Locks.
The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as
shown in Figure 4: Protection Register memory map.
The segments are programmed one Word at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits to ‘0’.
Two Bus Write cycles are required to issue the Protection Register Program command.
●
The first bus cycle sets up the Protection Register Program command.
●
The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
program operation has started.
Attempting to program a previously protected Protection Register will result in a Status
Register error.
The Protection Register Program cannot be suspended. Dual operations between the
Parameter Bank and the Protection Register memory space are not allowed (see Table 15:
Dual operation limitations for details)
The two Protection Register Locks are used to protect the OTP segments from further
modification. The protection of the OTP segments is not reversible. Refer to Figure 4:
Protection Register memory map, and Table 8: Protection Register locks, for details on the
Lock bits.
See Appendix C, Figure 26: Protection Register Program flowchart and pseudocode, for a
flowchart for using the Protection Register Program command.
27/112
Command interface
4.14
M58LR128HT, M58LR128HB
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration
Register.
Two Bus Write cycles are required to issue the Set Configuration Register command.
●
The first cycle sets up the Set Configuration Register command and the address
corresponding to the Configuration Register content.
●
The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles,
that is A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-A22 are ignored.
Read operations output the array content after the Set Configuration Register command is
issued.
The Read Electronic Signature command is required to read the updated contents of the
Configuration Register.
4.15
Block Lock command
The Block Lock command is used to lock a block and prevent program or erase operations
from changing the data in it. All blocks are locked after power-up or reset.
Two Bus Write cycles are required to issue the Block Lock command.
●
The first bus cycle sets up the Block Lock command.
●
The second Bus Write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 16 shows the Lock Status after issuing a Block Lock command.
Once set, the Block Lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command.
Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 25:
Locking Operations flowchart and pseudocode, for a flowchart for using the Lock command.
4.16
Block Unlock command
The Block Unlock command is used to unlock a block, allowing the block to be programmed
or erased.
Two Bus Write cycles are required to issue the Block Unlock command.
●
The first bus cycle sets up the Block Unlock command.
●
The second Bus Write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 16 shows the protection status after issuing a Block Unlock command.
Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 25:
Locking Operations flowchart and pseudocode, for a flowchart for using the Block Unlock
command.
28/112
M58LR128HT, M58LR128HB
4.17
Command interface
Block Lock-Down command
The Block Lock-Down command is used to lock-down a locked or unlocked block.
A locked-down block cannot be programmed or erased. The lock status of a locked-down
block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function
is disabled and the locked blocks can be individually unlocked by the Block Unlock
command.
Two Bus Write cycles are required to issue the Block Lock-Down command.
●
The first bus cycle sets up the Block Lock-Down command.
●
The second Bus Write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature
command.
Locked-Down blocks revert to the locked (and not locked-down) state when the device is
reset on power-down. Table 16 shows the Lock Status after issuing a Block Lock-Down
command.
Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 25:
Locking Operations flowchart and pseudocode, for a flowchart for using the Lock-Down
command.
29/112
Command interface
M58LR128HT, M58LR128HB
Standard commands(1)
Table 5.
Commands
Cycles
Bus Operations
1st Cycle
2nd Cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
BKA
70h
Read
BKA(2)
SRD
Read
BKA
(2)
ESD
Read
BKA(2)
QD
Read Electronic Signature
1+
Write
BKA
90h
Read CFI Query
1+
Write
BKA
98h
Clear Status Register
1
Write
X
50h
Block Erase
2
Write
BKA or
BA(3)
20h
Write
BA
D0h
Program
2
Write
BKA or
WA(3)
40h or
10h
Write
WA
PD
Write
BA
E8h
Write
BA
n
Write
PA1
PD1
Write
PA2
PD2
Write
PAn+1
PDn+1
Write
X
D0h
Buffer
Program(4)
n+4
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Protection Register Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration Register
2
Write
CRD
60h
Write
CRD
03h
Block Lock
2
Write
BKA or
BA(3)
60h
Write
BA
01h
Block Unlock
2
Write
BKA or
BA(3)
60h
Write
BA
D0h
Block Lock-Down
2
Write
BKA or
BA(3)
60h
Write
BA
2Fh
1. X = Don't Care, WA = Word Address in targeted bank, RD =Read Data, SRD =Status Register Data,
ESD = Electronic Signature Data, QD =Query Data, BA =Block Address, BKA = Bank Address, PD =
Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration
Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.
4. n+1 is the number of Words to be programmed.
30/112
M58LR128HT, M58LR128HB
Table 6.
Command interface
Factory commands
Command
Cycles
Bus Write Operations(1)
Phase
Blank
Check
Setup
1st
2nd
3rd
Add
Data Add Data Add Data
2
BA
BCh
BA
CBh
2
BKA or
WA(2)
80h
WA1
D0h
WA1
PD1
WA1
PD2 WA1 PD3
NOT
BA1(4)
X
Buffer
Enhanced Program/
≥32
Factory
Verify(3)
Program
Exit
1
Final -1
Add
Final
Data
Add
Data
WA1 PD31 WA1 PD32
1. WA = Word Address in targeted bank, BKA = Bank Address, PD =Program Data, BA = Block Address, X =
Don’t Care.
2. Any address within the bank can be used.
3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed
to the same block.
4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
Table 7.
Electronic Signature codes
Code
Manufacturer Code
Address (h)
Data (h)
Bank Address + 00
0020
Top
Bank Address + 01
88C4 (M58LR128HT)
Bottom
Bank Address + 01
88C5 (M58LR128HB)
Device Code
Locked
0001
Unlocked
Block Protection
0000
Block Address + 02
Locked and Locked-Down
0003
Unlocked and Locked-Down
0002
Configuration Register
Bank Address + 05
ST Factory Default
Protection Register
PR0 Lock
OTP Area Permanently
Locked
CR(1)
0002
Bank Address + 80
0000
Bank Address + 81
Bank Address + 84
Unique Device Number
Bank Address + 85
Bank Address + 88
OTP Area
Protection Register PR1 through PR16 Lock
Bank Address + 89
PRLD(1)
Protection Registers PR1-PR16
Bank Address + 8A
Bank Address + 109
OTP Area
Protection Register PR0
1. CR = Configuration Register, PRLD = Protection Register Lock Data.
31/112
Command interface
Figure 4.
M58LR128HT, M58LR128HB
Protection Register memory map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah
Protection Register Lock 89h
88h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1 0
AI07563
32/112
M58LR128HT, M58LR128HB
Table 8.
Command interface
Protection Register locks
Lock
Description
Number
Lock 1
Address
80h
Bits
Bit 0
preprogrammed to protect Unique Device Number, address
81h to 84h in PR0
Bit 1
protects 64bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 reserved
Bit 1
protects 128bits of OTP segment PR2
Bit 2
protects 128bits of OTP segment PR3
----
89h
protects 128bits of OTP segment PR1
----
Lock 2
Bit 0
Bit 13
protects 128bits of OTP segment PR14
Bit 14
protects 128bits of OTP segment PR15
Bit 15
protects 128bits of OTP segment PR16
33/112
Status Register
5
M58LR128HT, M58LR128HB
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register, refer to Read Status Register Command section for more details. To output the
contents, the Status Register is latched and updated on the falling edge of the Chip Enable
or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH.
The Status Register can only be read using single Asynchronous or Single Synchronous
reads. Bus Read operations from any address within the bank always read the Status
Register during program and erase operations if no Read Array command has been issued.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the following text descriptions.
5.1
Program/Erase Controller Status bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase
Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive,
and the device is ready to process a new command.
The Program/Erase Controller Status bit is Low immediately after a Program/Erase
Suspend command is issued until the Program/Erase Controller pauses. After the
Program/Erase Controller pauses the bit is High.
5.2
Erase Suspend Status bit (SR6)
The Erase Suspend Status bit indicates that an erase operation has been suspended in the
addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the memory is waiting for a Program/Erase
Resume command.
The Erase Suspend Status bit should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase
Suspend Latency time of the Program/Erase Suspend command being issued therefore the
memory may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
34/112
M58LR128HT, M58LR128HB
5.3
Status Register
Erase/Blank Check Status bit (SR5)
The Erase/Blank Check Status bit is used to identify if there was an error during a Block
Erase operation. When the Erase/Blank Check Status bit is High (set to ‘1’), the
Program/Erase Controller has applied the maximum number of pulses to the block and still
failed to verify that it has erased correctly.
The Erase/Blank Check Status bit should be read once the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
The Erase/Blank Check Status bit is also used to indicate whether an error occurred during
the Blank Check operation: if the data at one or more locations in the block where the Blank
Check command has been issued is different from FFFFh, SR5 is set to '1'.
Once set High, the Erase/Blank Check Status bit must be set Low by a Clear Status
Register command or a hardware reset before a new erase command is issued, otherwise
the new command will appear to fail.
5.4
Program Status bit (SR4)
The Program Status bit is used to identify if there was an error during a program operation.
The Program Status bit should be read once the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied
the maximum number of pulses to the Word and still failed to verify that it has programmed
correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the
Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the
attempt is not shown.
Once set High, the Program Status bit must be set Low by a Clear Status Register
command or a hardware reset before a new program command is issued, otherwise the new
command will appear to fail.
5.5
VPP Status bit (SR3)
The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and
erase operations. The VPP pin is only sampled at the beginning of a program or erase
operation. Program and erase operations are not guaranteed if VPP becomes invalid during
an operation
When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage.
When the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP
Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot
be performed.
Once set High, the VPP Status bit must be set Low by a Clear Status Register command or
a hardware reset before a new program or erase command is issued, otherwise the new
command will appear to fail.
35/112
Status Register
5.6
M58LR128HT, M58LR128HB
Program Suspend Status bit (SR2)
The Program Suspend Status bit indicates that a program operation has been suspended in
the addressed block. The Program Suspend Status bit should only be considered valid
when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command.
SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend
command being issued therefore the memory may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns Low.
5.7
Block Protection Status bit (SR1)
The Block Protection Status bit is used to identify if a Program or Block Erase operation has
tried to modify the contents of a locked or locked-down block.
When the Block Protection Status bit is High (set to ‘1’), a program or erase operation has
been attempted on a locked or locked-down block
Once set High, the Block Protection Status bit must be set Low by a Clear Status Register
command or a hardware reset before a new program or erase command is issued,
otherwise the new command will appear to fail.
5.8
Bank Write/Multiple Word Program Status bit (SR0)
The Bank Write Status bit indicates whether the addressed bank is programming or erasing.
In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the
device is ready to accept a new Word to be programmed to the memory array.
The Bank Write Status bit should only be considered valid when the Program/Erase
Controller Status SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low
(set to ‘0’), the addressed bank is executing a program or erase operation. When the
Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High
(set to ‘1’), a program or erase operation is being executed in a bank other than the one
being addressed.
In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to
‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High
(set to ‘1’) the device is not ready for the next Word.
For further details on how to use the Status Register, see the Flowcharts and Pseudocodes
provided in Appendix C.
36/112
M58LR128HT, M58LR128HB
Table 9.
Bit
Status Register
Status Register bits
Name
Type
SR7 P/E.C. Status
Status
SR6
SR5
Erase Suspend
Status
Status
Erase/Blank Check
Status
Error
SR4 Program Status
SR3 VPP Status
SR2
SR1
Logic
Level(1)
Definition
'1'
Ready
'0'
Busy
'1'
Erase Suspended
'0'
Erase In progress or Completed
'1'
Erase/Blank Check Error
'0'
Erase/Blank Check Success
'1'
Program Error
'0'
Program Success
'1'
VPP Invalid, Abort
'0'
VPP OK
'1'
Program Suspended
'0'
Program In Progress or Completed
'1'
Program/Erase on protected Block, Abort
'0'
No operation to protected blocks
Error
Error
Program Suspend
Status
Status
Block Protection
Status
Error
SR7 = ‘1’ Not Allowed
'1'
Bank Write Status
SR7 = ‘0’
Program or erase operation in a bank
other than the addressed bank
SR7 = ‘1’
No Program or erase operation in the
device
SR7 = ‘0’
Program or erase operation in
addressed bank
Status
'0'
SR0
SR7 = ‘1’ Not Allowed
Multiple Word
Program Status
(Buffer Enhanced
Factory Program
mode)
'1'
Status
the device is NOT ready for the next
SR7 = ‘0’ Buffer loading or is going to exit the
BEFP mode
SR7 = ‘1’ the device has exited the BEFP mode
'0'
SR7 = ‘0’
the device is ready for the next Buffer
loading
1. Logic level '1' is High, '0' is Low.
37/112
Configuration Register
6
M58LR128HT, M58LR128HB
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Read Modes section for details on read operations.
The Configuration Register is set through the Command Interface using the Set
Configuration Register command. After a reset or power-up the device is configured for
asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 11
They specify the selection of the burst length, burst type, burst X latency and the read
operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1
Read Select bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous
Read operations.
When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read
Select bit is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.
6.2
X-Latency bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of
clock cycles between the address being latched and the first data becoming available. Refer
to Figure 5: X-Latency and data output configuration example.
For correct operation the X-Latency bits can only assume the values in Table 11:
Configuration Register.
Table 10 shows how to set the X-Latency parameter, taking into account the speed class of
the device and the Frequency used to read the Flash memory in Synchronous mode.
Table 10.
38/112
X-Latency settings
fmax
tKmin
X-Latency min
30 MHz
33 ns
3
40 MHz
25 ns
4
54 MHz
19 ns
5
M58LR128HT, M58LR128HB
6.3
Configuration Register
Wait Polarity bit (CR10)
The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst
Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the
data output are valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity
bit is set to ‘1’ the Wait signal is active High.
6.4
Data Output Configuration bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either
one or two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.
The Data Output Configuration must be configured using the following condition:
●
tK > tKQV + tQVK_CPU
where
●
tK is the clock period
●
tQVK_CPU is the data setup time required by the system CPU
●
tKQV is the clock to data valid time.
If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two
clock cycles). Refer to Figure 5: X-Latency and data output configuration example.
6.5
Wait Configuration bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in
Synchronous Burst Read mode.
When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the
WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is
asserted one data cycle before the WAIT state.
6.6
Burst Type bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst
Reads.
The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses
only.
See Table 12: Burst type definition, for the sequence of addresses output from a given
starting address in sequential mode.
39/112
Configuration Register
6.7
M58LR128HT, M58LR128HB
Valid Clock Edge bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling
edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the
rising edge of the Clock is the active edge.
6.8
Wrap Burst bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the
boundary (no wrap).
When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’)
the burst read does not wrap.
6.9
Burst length bits (CR2-CR0)
The Burst Length bits are used to set the number of Words to be output during a
Synchronous Burst Read operation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words
are read sequentially. In continuous burst mode the burst sequence can cross bank
boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address,
the device asserts the WAIT signal to indicate that a delay is necessary before the data is
output.
If the starting address is shifted by 1, 2 or 3 positions from the four-Word boundary, WAIT is
asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first
16-Word boundary, to indicate that the device needs an internal delay to read the
successive Words in the array. WAIT will be asserted only once during a continuous burst
access. See also Table 12: Burst type definition.
CR14, CR5 and CR4 are reserved for future use.
40/112
M58LR128HT, M58LR128HB
Table 11.
Bit
CR15
CR14
CR13-CR11
Configuration Register
Configuration Register
Description
Value
Description
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
010
2 clock latency(1)
011
3 clock latency
100
4 clock latency
101
5 clock latency
110
6 clock latency
111
7 clock latency (default)
Read Select
Reserved
X-Latency
Other configurations reserved
CR10
CR9
CR8
CR7
CR6
CR5-CR4
CR3
CR2-CR0
0
WAIT is active Low
1
WAIT is active High (default)
0
Data held for one clock cycle
1
Data held for two clock cycles (default)(1)
0
WAIT is active during WAIT state
1
WAIT is active one data cycle before WAIT
state(1) (default)
0
Reserved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
0
Wrap
1
No Wrap (default)
001
4 Words
010
8 Words
011
16 Words
111
Continuous (default)
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Valid Clock Edge
Reserved
Wrap Burst
Burst Length
1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the
WAIT state is not supported.
41/112
Configuration Register
Wrap
Mode
Table 12.
Start
Add
M58LR128HT, M58LR128HB
Burst type definition
Sequential
Continuous Burst
4 Words
8 Words
16 Words
0
0-1-2-3
0-1-2-3-4-5-67
0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15
0-1-2-3-4-5-6...
1
1-2-3-0
1-2-3-4-5-6-70
1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0
1-2-3-4-5-6-7-...15-WAIT-16-1718...
2
2-3-0-1
2-3-4-5-6-7-01
2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1
2-3-4-5-6-7...15-WAIT-WAIT-1617-18...
3
3-0-1-2
3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122
13-14-15-0-1-2
7-4-5-6
7-0-1-2-3-4-56
3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18...
...
7
7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17...
...
42/112
12
12-13-14-15-16-17-18...
13
13-14-15-WAIT-16-17-18...
14
14-15-WAIT-WAIT-16-17-18....
15
15-WAIT-WAIT-WAIT-16-17-18...
M58LR128HT, M58LR128HB
Mode
Table 12.
Start
Add
Configuration Register
Burst type definition (continued)
Sequential
Continuous Burst
4 Words
8 Words
16 Words
0
0-1-2-3
0-1-2-3-4-5-67
0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15
1
1-2-3-4
1-2-3-4-5-6-78
1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16
2
2-3-4-5
2-3-4-5-6-7-89...
2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17
3
3-4-5-6
3-4-5-6-7-8-910
3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18
7-8-9-10
7-8-9-10-1112-13-14
7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22
12
12-13-1415
12-13-14-1516-17-18-19
12-13-14-15-16-17-1819-20-21-22-23-24-2526-27
13
13-14-15WAIT-16
13-14-15WAIT-16-1718-19-20
13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28
14
14-15WAITWAIT-1617
14-15-WAITWAIT-16-1718-19-20-21
14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29
15
15-WAITWAITWAIT-1617-18
15-WAITWAIT-WAIT16-17-18-1920-21-22
15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930
No-wrap
...
7
...
Same as for Wrap
(Wrap /No Wrap has no effect
on Continuous Burst)
43/112
Configuration Register
Figure 5.
M58LR128HT, M58LR128HB
X-Latency and data output configuration example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A22-A0(1)
VALID ADDRESS
tQVK_CPU
tK
tKQV
DQ15-DQ0
VALID DATA VALID DATA
Ai11072
1. The settings shown are X-latency = 4, Data Output held for one clock cycle.
Figure 6.
Wait configuration example
E
K
L
A22-A0
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI06972
44/112
M58LR128HT, M58LR128HB
7
Read modes
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous; if the data output is synchronized with clock, the read operation
is synchronous.
The read mode and format of the data output are determined by the Configuration Register.
(See Configuration Register section for details). All banks support both asynchronous and
synchronous read operations.
7.1
Asynchronous Read mode
In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the
data corresponding to the address latched, that is the memory array, Status Register,
Common Flash Interface or Electronic Signature depending on the command issued. CR15
in the Configuration Register must be set to ‘1’ for asynchronous operations.
Asynchronous Read operations can be performed in two different ways, Asynchronous
Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read
takes full advantage of the internal page storage so different timings are applied.
In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer.
The Page has a size of 4 Words and is addressed by address inputs A0 and A1.
The first read operation within the Page has a longer access time (tAVQV, Random access
time), subsequent reads within the same Page have much shorter access times (tAVQV1,
Page access time). If the Page changes then the normal, longer timings apply again.
The device features an Automatic Standby mode. During Asynchronous Read operations,
after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
In Asynchronous Read mode, the WAIT signal is always deasserted.
See Table 23: Asynchronous Read AC characteristics, Figure 9: Asynchronous random
access Read AC waveforms and Figure 10: Asynchronous Page Read AC waveforms for
details.
45/112
Read modes
7.2
M58LR128HT, M58LR128HB
Synchronous Burst Read mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It
is possible to perform burst reads across bank boundaries.
Synchronous Burst Read mode can only be used to read the memory array. For other read
operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single
Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that
are configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock
Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and data is output on
each data cycle after a delay which depends on the X latency bits CR13-CR11 of the
Configuration Register.
The number of Words to be output during a Synchronous Burst Read operation can be
configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0).
The data can be configured to remain valid for one or two clock cycles (Data Output
Configuration bit CR9).
The order of the data output can be modified through the Wrap Burst bit in the Configuration
Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word
boundary (Wrap) or overcome the boundary (No Wrap).
The WAIT signal may be asserted to indicate to the system that an output delay will occur.
This delay will depend on the starting address of the burst sequence and on the burst
configuration.
WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word
burst. It is only de-asserted when output data are valid or when G is at VIH. In Continuous
Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the
starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration
has no impact on the output sequence.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 24: Synchronous Read AC characteristics, and Figure 11: Synchronous Burst
Read AC waveforms, for details.
46/112
M58LR128HT, M58LR128HB
7.2.1
Read modes
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other
higher priority devices. It can be suspended during the initial access latency time (before
data is output) or after the device has output data. When the Synchronous Burst Read
operation is suspended, internal array sensing continues and any previously latched internal
data is retained. A burst sequence can be suspended and resumed as often as required as
long as the operating conditions of the device are met.
A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High.
When Output Enable, G, becomes Low again and the Clock signal restarts, the
Synchronous Burst Read operation is resumed exactly where it stopped.
WAIT being gated by E, it will remain active and will not revert to high impedance when G
goes High. So if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the M58LR128HT/B should not be directly
connected to the system’s READY signal.
WAIT will revert to high-impedance when Chip Enable, E, goes High.
See Table 24: Synchronous Read AC characteristics, and Figure 13: Synchronous Burst
Read Suspend AC waveforms, for details.
7.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations
except that the memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,
Block Protection Status, Configuration Register Status or Protection Register. When the
addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode,
the WAIT signal is asserted during the X-latency, the WAIT state and at the end of a 4, 8 and
16 Word burst. It is only de-asserted when output data are valid.
See Table 24: Synchronous Read AC characteristics, and Figure 11: Synchronous Burst
Read AC waveforms, for details.
47/112
Dual operations and Multiple Bank architecture
8
M58LR128HT, M58LR128HB
Dual operations and Multiple Bank architecture
The Multiple Bank Architecture of the M58LR128HT/B gives greater flexibility for software
developers to split the code and data spaces within the memory array. The Dual Operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The Dual Operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended.
Also if the suspended operation was erase then a program command can be issued to
another block, so the device can have one block in Erase Suspend mode, one programming
and other banks in read mode.
Bus Read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58LR128HT/B device.
Dual operations between the Parameter Bank and either of the CFI, the OTP or the
Electronic Signature memory space are not allowed. Table 15 shows which dual operations
are allowed or not between the CFI, the OTP, the Electronic Signature locations and the
memory array.
Tables 13 and 14 show the dual operations possible in other banks and in the same bank.
Table 13.
Dual operations allowed in other banks
Commands allowed in another bank
Status of bank
48/112
Read
Array
Read
Read
Read
Status
CFI Electronic
Register Query Signature
Program,
Buffer
Program
Block
Erase
Program Program
/Erase
/Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
–
–
Yes
–
Program
Suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase
Suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
M58LR128HT, M58LR128HB
Table 14.
Dual operations and Multiple Bank architecture
Dual operations allowed in same bank
Commands allowed in same bank
Status of bank
Idle
Programming
Erasing
Read
Array
Read
Read
Read
Status
CFI
Electronic
Register Query Signature
Program,
Buffer
Program
Block
Erase
Program Program
/Erase
/Erase
Suspend Resume
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(1)
Yes
Yes
Yes
–
–
Yes
–
(1)
Yes
Yes
Yes
–
–
Yes
–
–
–
Program
Suspended
Yes(2)
Yes
Yes
Yes
–
–
–
Yes
Erase
Suspended
Yes(2)
Yes
Yes
Yes
Yes(1)
–
–
Yes
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
has completed.
2. Not allowed in the Block that is being erased or in the Word that is being programmed.
Table 15.
Dual operation limitations
Commands allowed
Read Main Blocks
Read CFI / OTP /
Electronic
Signature
Read
Parameter
Blocks
No
Located in
Parameter
Bank
Not Located
in Parameter
Bank
Current Status
Programming / Erasing
Parameter Blocks
Programming /
Erasing Main
Blocks
Programming OTP
Located in
Parameter
Bank
Not Located
in Parameter
Bank
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
In Different
Bank Only
No
No
No
No
49/112
Block locking
9
M58LR128HT, M58LR128HB
Block locking
The M58LR128HT/B features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency. This locking scheme has three levels of
protection.
●
Lock/Unlock - this first level allows software only control of block locking.
●
Lock-Down - this second level requires hardware interaction before locking can be
changed.
●
VPP ≤VPPLK - the third level offers a complete hardware protection against program and
erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Locked-Down.
Table 16, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C,
Figure 25, shows a flowchart for the locking operations.
9.1
Reading a block’s lock status
The lock status of every block can be read in the Read Electronic Signature mode of the
device. To enter this mode issue the Read Electronic Signature command. Subsequent
reads at the address specified in Table 7, will output the protection status of that block.
The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock
status and is set by the Lock command and cleared by the Unlock command. DQ0 is
automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set
by the Lock-Down command. DQ1 cannot be cleared by software, only by a hardware reset
or power-down.
The following sections explain the operation of the locking system.
9.2
Locked state
The default status of all blocks on power-up or after a hardware reset is Locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any
program or erase operations attempted on a locked block will return an error in the Status
Register. The Status of a Locked block can be changed to Unlocked or Locked-Down using
the appropriate software commands. An Unlocked block can be Locked by issuing the Lock
command.
9.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
50/112
M58LR128HT, M58LR128HB
9.4
Block locking
Lock-Down state
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase
operations (as for Locked blocks) but their protection status cannot be changed using
software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the
Lock-Down command. Locked-Down blocks revert to the Locked state when the device is
reset or powered-down.
The Lock-Down function is dependent on the Write Protect, WP, input pin.
When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program,
erase and protection status changes.
When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can
be individually unlocked to the (1,1,0) state by issuing the software command, where they
can be erased and programmed.
When the Lock-Down function is disabled (WP=1) blocks can be locked (1,1,1) and
unlocked (1,1,0) as desired. When WP=0 blocks that were previously Locked-Down return
to the Lock-Down state (0,1,x) regardless of any changes that were made while WP=1.
Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked
state.
9.5
Locking operations during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock-down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the Status Register until it indicates that the erase operation has been
suspended. Next write the desired Lock command sequence to a block and the lock status
will be changed. After completing any desired lock, read, or program operations, resume the
erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase suspend of the same block, the locking
status bits will be changed immediately, but when the erase is resumed, the erase operation
will complete. Locking operations cannot be performed during a program suspend.
51/112
Block locking
M58LR128HT, M58LR128HB
Table 16.
Lock status
Current Protection Status(1)
Next Protection Status(1)
(WP, DQ1, DQ0)
(WP, DQ1, DQ0)
Current
State
Program/Erase
Allowed
After Block
Lock
Command
After Block
Unlock
Command
After Block
Lock-Down
Command
After WP
transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
no
0,0,1
0,0,0
0,1,1
1,0,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0(3)
(2)
1,0,1
(2)
0,0,1
0,1,1
1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for
a locked block) as read in the Read Electronic Signature command with DQ1 = VIH and DQ0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
52/112
M58LR128HT, M58LR128HB
10
Program and erase times and endurance cycles
Program and erase times and endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are
shown in Table 17. Exact erase times may change depending on the memory array
condition. The best case is when all the bits in the block are at ‘0’ (pre-programmed). The
worst case is when all the bits in the block are at ‘1’ (not preprogrammed). Usually, the
system overhead is negligible with respect to the erase time. In the M58LR128HT/B the
maximum number of Program/Erase cycles depends on the VPP voltage supply used.
Table 17.
Program/Erase times and endurance cycles(1) (2)
Parameter
Typ
Typical after
100kW/E
Cycles
Max
Unit
0.4
1
2.5
s
Preprogrammed
1.2
3
4
s
Not Preprogrammed
1.5
4
s
Word Program
12
180
µs
Buffer Program
12
180
µs
Condition
Min
Parameter Block (16 KWord)
Erase
Main Block (64
KWord)
VPP = VDD
Single Word
Program(3)
Buffer (32 Words) (Buffer Program)
384
µs
Main Block (64 KWord)
768
ms
Program
5
10
µs
Erase
5
20
µs
Suspend Latency
Program/Erase Cycles
(per Block)
Main Blocks
100,000
cycles
Parameter Blocks
100,000
cycles
53/112
Program and erase times and endurance cycles
M58LR128HT, M58LR128HB
Program/Erase times and endurance cycles(1) (2) (continued)
Table 17.
Parameter
Condition
Typ
Typical after
100kW/E
Cycles
Max
Unit
0.4
2.5
s
1
4
s
Word Program
10
170
µs
Buffer Enhanced
Factory Program(4)
2.5
µs
Buffer Program
80
µs
80
µs
Buffer Program
160
ms
Buffer Enhanced
Factory Program
160
ms
Buffer Program
1.28
s
Buffer Enhanced
Factory Program
1.28
s
Parameter Block (16 KWord)
Min
Erase
Main Block (64 KWord)
VPP = VPPH
Single Word
(3)
Buffer (32 Words) Buffer Enhanced
Factory Program
Program
Main Block (64
KWords)
Bank (8 Mbits)
Program/Erase Cycles
(per Block)
Main Blocks
1000 cycles
Parameter Blocks
2500 cycles
Main Blocks
16
ms
Parameter Blocks
4
ms
Blank Check
1. TA = –25 to 85 °C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
54/112
M58LR128HT, M58LR128HB
11
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 18.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature
–25
85
°C
TBIAS
Temperature Under Bias
–25
85
°C
TSTG
Storage Temperature
–65
125
°C
VIO
Input or Output Voltage
–0.5
3.8
V
VDD
Supply Voltage
–0.2
2.5
V
Input/Output Supply Voltage
–0.2
2.5
V
Program Voltage
–0.2
10
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
55/112
DC and AC parameters
12
M58LR128HT, M58LR128HB
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 19: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 19.
Operating and AC measurement conditions
M58LR128HT/B
Parameter
85
Units
Min
Max
VDD Supply Voltage
1.7
2.0
V
VDDQ Supply Voltage
1.7
2.0
V
VPP Supply Voltage (Factory environment)
8.5
9.5
V
VPP Supply Voltage (Application environment)
–0.4
VDDQ+0.4
V
Ambient Operating Temperature
–25
85
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 7.
ns
0 to VDDQ
V
VDDQ/2
V
AC measurement I/O waveform
VDDQ
VDDQ/2
0V
AI06161
56/112
pF
M58LR128HT, M58LR128HB
Figure 8.
DC and AC parameters
AC measurement load circuit
VDDQ
VDDQ
VDD
16.7kΩ
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
Table 20.
Symbol
CIN
COUT
AI06162
Capacitance(1)
Parameter
Input Capacitance
Output Capacitance
Test condition
Min
Max
Unit
VIN = 0 V
6
8
pF
VOUT = 0 V
8
12
pF
1. Sampled only, not 100% tested.
57/112
DC and AC parameters
Table 21.
Symbol
M58LR128HT, M58LR128HB
DC characteristics - currents
Parameter
Test condition
ILI
Input Leakage Current
ILO
IDD1
Max
Unit
0V ≤VIN ≤VDDQ
±1
µA
Output Leakage Current
0V ≤VOUT ≤VDDQ
±1
µA
Supply Current
Asynchronous Read (f = 5 MHz)
E = VIL, G = VIH
13
15
mA
4 Word
18
20
mA
8 Word
20
22
mA
16 Word
25
27
mA
Continuous
28
30
mA
RP = VSS ± 0.2 V
22
50
µA
Supply Current
Synchronous Read (f = 54 MHz)
IDD2
Supply Current (Reset)
IDD3
Supply Current (Standby)
E = VDD ± 0.2 V
K=VSS
22
50
µA
IDD4
Supply Current (Automatic
Standby)
E = VIL, G = VIH
22
50
µA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
Program/Erase in one Bank,
Asynchronous Read in
another Bank
23
40
mA
Program/Erase in one Bank,
Synchronous Read
(Continuous f = 54 MHz) in
another Bank
38
55
mA
E = VDD ± 0.2 V
K=VSS
22
50
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP Supply Current (Read)
VPP ≤VDD
0.2
5
µA
VPP Supply Current (Standby)
VPP ≤VDD
0.2
5
µA
Supply Current (Program)
IDD5(1)
Supply Current (Erase)
IDD6(1),(2)
IDD7(1)
Supply Current
(Dual Operations)
Supply Current Program/ Erase
Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3(1)
1. Sampled only, not 100% tested.
2. VDD Dual Operation current is the sum of read and program or erase currents.
58/112
Typ
M58LR128HT, M58LR128HB
Table 22.
Symbol
DC and AC parameters
DC characteristics - voltages
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
0
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100 µA
0.1
V
VOH
Output High Voltage
IOH = –100 µA
VDDQ –0.1
VPP1
VPP Program Voltage-Logic
Program, Erase
1.3
1.8
3.3
V
VPPH
VPP Program Voltage Factory
Program, Erase
8.5
9.0
9.5
V
VPPLK
Program or Erase Lockout
0.4
V
VLKO
VDD Lock Voltage
1
V
VRPH
RP pin Extended High Voltage
3.3
V
V
59/112
60/112
Hi-Z
Hi-Z
tGLTV
tELQX
tELTV
tGLQV
tGLQX
tELQV
tLLQV
tAVQV
tLHAX
tEHQZ
tEHQX
tEHTZ
tGHQZ
tGHQX
tAXQX
VALID
VALID
tGHTZ
Notes: 1. Write Enable, W, is High, WAIT is active Low.
2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
WAIT(1)
DQ0-DQ15
G
E
tELLH
tLLLH
tAVLH
VALID
AI09817
Figure 9.
L(2)
A0-A22
tAVAV
DC and AC parameters
M58LR128HT, M58LR128HB
Asynchronous random access Read AC waveforms
Hi-Z
tAVAV
tELTV
tELQX
tGLQX
tELQV
tLLQV
Valid Address Latch
tELLH
tLLLH
tGLQV
VALID ADDRESS
tAVLH
Note: 1. WAIT is active Low.
DQ0-DQ15
WAIT (1)
G
E
L
A0-A1
A2-A22
Enabled
Outputs
tLHGL
tLHAX
VALID DATA
VALID DATA
VALID ADDRESS
Valid Data
VALID DATA
tAVQV1
VALID ADDRESS
VALID ADDRESS
VALID DATA
VALID ADDRESS
AI14005
Standby
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 10. Asynchronous Page Read AC waveforms
61/112
DC and AC parameters
Table 23.
M58LR128HT, M58LR128HB
Asynchronous Read AC characteristics
M58LR128HT/B
Symbol
Alt
Parameter
Unit
85
tAVAV
tRC
Address Valid to Next Address Valid
Min
85
ns
tAVQV
tACC
Address Valid to Output Valid (Random)
Max
85
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
Max
25
ns
tAXQX(1)
tOH
Address Transition to Output Transition
Min
0
ns
Chip Enable Low to Wait Valid
Max
14
ns
tELTV
(2)
tCE
Chip Enable Low to Output Valid
Max
85
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
Min
0
ns
Chip Enable High to Wait Hi-Z
Max
14
ns
Read Timings
tELQV
tEHTZ
(1)
tOH
Chip Enable High to Output Transition
Min
2
ns
(1)
tHZ
Chip Enable High to Output Hi-Z
Max
14
ns
tGLQV(2)
tOE
Output Enable Low to Output Valid
Max
20
ns
tGLQX(1)
tOLZ
Output Enable Low to Output Transition
Min
0
ns
Output Enable Low to Wait Valid
Max
14
ns
tEHQX
tEHQZ
tGLTV
(1)
tOH
Output Enable High to Output Transition
Min
2
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
Max
14
ns
Output Enable High to Wait Hi-Z
Max
14
ns
tGHQX
Latch Timings
tGHTZ
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
7
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
10
ns
tLHAX
tADVHAX
Latch Enable High to Address Transition
Min
7
ns
Min
7
ns
Max
85
ns
tLLLH
tLLQV
tADVLADVH Latch Enable Pulse Width
tADVLQV
Latch Enable Low to Output Valid
(Random)
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
62/112
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLTV
tGLQX
Note 2
Note 1
VALID
Valid Data Flow
tKHTV
tKHQV
VALID
Note 2
tKHTX
tKHQX
VALID
Boundary
Crossing
Note 2
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
WAIT
G
E
K(4)
L
A0-A22
DQ0-DQ15
Data
Valid
tGHQZ
tGHQX
AI09819b
Standby
tEHTZ
tEHQZ
tEHQX
tEHEL
VALID
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 11. Synchronous Burst Read AC waveforms
63/112
DC and AC parameters
M58LR128HT, M58LR128HB
Figure 12. Single Synchronous Read AC waveforms
A0-A22
VALID ADDRESS
tAVKH
L
tLLKH
K(2)
tELKH
tKHQV
tELQV
E
tGLQV
tGLQX
G
tELQX
DQ0-DQ15
Hi-Z
VALID
tGLTV
WAIT(1)
tGHTZ
tKHTV
Hi-Z
Ai12360b
1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock
signal, K, can be configured as the active edge. Here, the active edge is the rising one.
64/112
tELKH
Hi-Z
Hi-Z
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHQV
VALID
VALID
tGHTZ
tGHQZ
Note 3
tGHQX
tEHEL
tEHQZ
AI12366
tEHTZ
NOT VALID
tEHQX
NOT VALID
Notes 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.
Here, the active edge is the rising one.
WAIT(2)
G
E
K(4)
L
A0-A22
DQ0-DQ15
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 13. Synchronous Burst Read Suspend AC waveforms
65/112
DC and AC parameters
M58LR128HT, M58LR128HB
Figure 14. Clock input AC waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
Table 24.
Synchronous Read AC characteristics(1) (2)
M58LR128HT/L
Symbol
Alt
Parameter
Unit
Clock Specifications
Synchronous Read Timings
85
tAVKH
tAVCLKH
Address Valid to Clock High
Min
7
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
7
ns
tELTV
Chip Enable Low to Wait Valid
Max
14
ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads)
Min
14
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
14
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
7
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
14
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
3
ns
tLLKH
tADVLCLKH
Latch Enable Low to Clock High
Min
7
ns
tKHKH
tCLK
Clock Period (f=54MHz)
Min
18.5
ns
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
4.5
ns
tf
tr
Clock Fall or Rise Time
Max
3
ns
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 23: Asynchronous Read AC characteristics.
66/112
K
VPP
WP
DQ0-DQ15
W
G
E
L
A0-A22
tWHDX
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tWHVPL
tWHWPL
tELKV
tWHEL
tWHGL
tWHAV
tWHAX
CMD or DATA
VALID ADDRESS
tAVWH
tWPHWH
tWHWL
tWHEH
tWHLL
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
tAVAV
Ai11073
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 15. Write AC waveforms, Write Enable controlled
67/112
DC and AC parameters
M58LR128HT, M58LR128HB
Write AC characteristics, Write Enable controlled(1)
Table 25.
M58LR128HT/B
Symbol
Alt
Unit
Parameter
85
tAVAV
Address Valid to Next Address Valid
Min
85
ns
tAVLH
Address Valid to Latch Enable High
Min
7
ns
tAVWH(2)
Address Valid to Write Enable High
Min
45
ns
Data Valid to Write Enable High
Min
45
ns
Chip Enable Low to Latch Enable High
Min
10
ns
Chip Enable Low to Write Enable Low
Min
0
ns
tELQV
Chip Enable Low to Output Valid
Min
85
ns
tELKV
Chip Enable Low to Clock Valid
Min
7
ns
tGHWL
Output Enable High to Write Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
7
ns
tLLLH
Latch Enable Pulse Width
Min
7
ns
Write Enable High to Address Valid
Min
0
ns
tDVWH
tWC
tDS
tELLH
Write Enable Controlled Timings
tELWL
tWHAV(2)
tWHAX(2)
tAH
Write Enable High to Address Transition
Min
0
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
ns
Write Enable High to Chip Enable Low
Min
20
ns
tWHGL
Write Enable High to Output Enable Low
Min
0
ns
tWHLL(3)
Write Enable High to Latch Enable Low
Min
20
ns
tWHWL
tWPH Write Enable High to Write Enable Low
Min
20
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect Low
Min
0
ns
VPP High to Write Enable High
Min
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
ns
tWHEL
Protection Timings
tCS
(3)
tVPHWH
tVPS
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. tWHEL and tWHLLhave this value when reading in the targeted bank or when reading following a Set
Configuration Register command. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing any command and to delay
the first read to any address after issuing a Set Configuration Register command. If the first read after the
command is a Read Array operation in a different bank and no changes to the Configuration Register have
been issued, tWHEL and tWHLL is 20ns.
68/112
K
VPP
WP
DQ0-DQ15
E
G
W
L
A0-A22
tGHEL
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID ADDRESS
tAVAV
tEHVPL
tEHWPL
tELKV
tWHEL
tEHGL
tQVVPL
Ai11074
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 16. Write AC waveforms, Chip Enable controlled
69/112
DC and AC parameters
M58LR128HT, M58LR128HB
Write AC characteristics, Chip Enable controlled(1)
Table 26.
M58LR128HT/B
Symbol
Alt
Parameter
Unit
85
Chip Enable Controlled Timings
tAVAV
Address Valid to Next Address Valid
Min
85
ns
tAVEH
Address Valid to Chip Enable High
Min
45
ns
tAVLH
Address Valid to Latch Enable High
Min
7
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
45
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
20
ns
Chip Enable High to Output Enable Low
Min
0
ns
Chip Enable High to Write Enable High
Min
0
ns
Chip Enable Low to Clock Valid
Min
7
ns
Chip Enable Low to Chip Enable High
Min
45
ns
tELLH
Chip Enable Low to Latch Enable High
Min
10
ns
tELQV
Chip Enable Low to Output Valid
Min
85
ns
tGHEL
Output Enable High to Chip Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
7
ns
tLLLH
Latch Enable Pulse Width
Min
7
ns
Write Enable High to Chip Enable Low
Min
20
ns
Write Enable Low to Chip Enable Low
Min
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
ns
VPP High to Chip Enable High
Min
200
ns
Write Protect High to Chip Enable High
Min
200
ns
tEHGL
tEHWH
tCH
tELKV
tELEH
tWHEL
tCP
(2)
tWLEL
Protection Timings
tWC
tVPHEH
tWPHEH
tCS
tVPS
1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration
Register command. System designers should take this into account and may insert a software No-Op
instruction to delay the first read in the same bank after issuing any command and to delay the first read to
any address after issuing a Set Configuration Register command. If the first read after the command is a
Read Array operation in a different bank and no changes to the Configuration Register have been issued,
tWHEL is 0ns.
70/112
M58LR128HT, M58LR128HB
DC and AC parameters
Figure 17. Reset and Power-up AC waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 27.
Symbol
Reset and Power-up AC characteristics
Parameter
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
tPHWL
tPHEL
tPHGL
tPHLL
tPLPH(1),(2)
tVDHPH(3)
Test Condition
85
Unit
During Program
Min
25
µs
During Erase
Min
25
µs
Other Conditions
Min
80
ns
Reset High to
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
Min
30
ns
RP Pulse Width
Min
50
ns
Supply Voltages High to Reset
High
Min
150
µs
1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
71/112
Package mechanical
13
M58LR128HT, M58LR128HB
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 18. VFBGA56 7.7 × 9mm - 8×7 active ball array, 0.75mm pitch, bottom view
package outline
D
D1
FD
FE
E
SD
E1
ddd
BALL "A1"
e
e
b
A
A2
A1
BGA-Z38
1. Drawing is not to scale.
72/112
M58LR128HT, M58LR128HB
Table 28.
Package mechanical
VFBGA56 7.7 × 9mm - 10×4 ball array, 0.50mm pitch, package mechanical
data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.000
A1
Max
0.0394
0.200
0.0079
A2
0.660
0.0260
b
0.350
0.300
0.400
0.0138
0.0118
0.0157
D
7.700
7.600
7.800
0.3031
0.2992
0.3071
D1
5.250
–
–
0.2067
–
–
ddd
0.080
0.0031
e
0.750
–
–
0.0295
–
–
E
9.000
8.900
9.100
0.3543
0.3504
0.3583
E1
4.500
–
–
0.1772
–
–
FD
1.225
–
–
0.0482
–
–
FE
2.250
–
–
0.0886
–
–
SD
0.375
–
–
0.0148
–
–
73/112
Part numbering
14
M58LR128HT, M58LR128HB
Part numbering
Table 29.
Ordering information scheme
Example:
M58LR128HT
85 ZB 5
E
Device Type
M58
Architecture
L = Multi-Level, Multiple Bank, Burst Mode
Operating Voltage
R = VDD = 1.7V to 2.0V, VDDQ = 1.7V to 2.0V
Density
128 = 128 Mbit (x16)
Technology
H = 90nm technology
Parameter Location
T = Top Boot
B = Bottom Boot
Speed
85 = 85ns
Package
ZB = VFBGA56, 7.7 x 9mm, 0.50mm pitch
Temperature Range
5 = –25 to 85°C
Packing Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
74/112
M58LR128HT, M58LR128HB
Appendix A
Block address tables
Block address tables
Table 30.
Top boot block addresses, M58LR128HT
Bank 3
Bank 2
Bank 1
Parameter Bank
Bank(1)
#
Size (KWord)
Address Range
0
16
7FC000-7FFFFF
1
16
7F8000-7FBFFF
2
16
7F4000-7F7FFF
3
16
7F0000-7F3FFF
4
64
7E0000-7EFFFF
5
64
7D0000-7DFFFF
6
64
7C0000-7CFFFF
7
64
7B0000-7BFFFF
8
64
7A0000-7AFFFF
9
64
790000-79FFFF
10
64
780000-78FFFF
11
64
770000-77FFFF
12
64
760000-76FFFF
13
64
750000-75FFFF
14
64
740000-74FFFF
15
64
730000-73FFFF
16
64
720000-72FFFF
17
64
710000-71FFFF
18
64
700000-70FFFF
19
64
6F0000-6FFFFF
20
64
6E0000-6EFFFF
21
64
6D0000-6DFFFF
22
64
6C0000-6CFFFF
23
64
6B0000-6BFFFF
24
64
6A0000-6AFFFF
25
64
690000-69FFFF
26
64
680000-68FFFF
27
64
670000-67FFFF
28
64
660000-66FFFF
29
64
650000-65FFFF
30
64
640000-64FFFF
31
64
630000-63FFFF
32
64
620000-62FFFF
33
64
610000-61FFFF
34
64
600000-60FFFF
75/112
Block address tables
M58LR128HT, M58LR128HB
Table 30.
Top boot block addresses, M58LR128HT (continued)
Bank 7
Bank 6
Bank 5
Bank 4
Bank(1)
76/112
#
Size (KWord)
Address Range
35
64
5F0000-5FFFFF
36
64
5E0000-5EFFFF
37
64
5D0000-5DFFFF
38
64
5C0000-5CFFFF
39
64
5B0000-5BFFFF
40
64
5A0000-5AFFFF
41
64
590000-59FFFF
42
64
580000-58FFFF
43
64
570000-57FFFF
44
64
560000-56FFFF
45
64
550000-55FFFF
46
64
540000-54FFFF
47
64
530000-53FFFF
48
64
520000-52FFFF
49
64
510000-51FFFF
50
64
500000-50FFFF
51
64
4F0000-4FFFFF
52
64
4E0000-4EFFFF
53
64
4D0000-4DFFFF
54
64
4C0000-4CFFFF
55
64
4B0000-4BFFFF
56
64
4A0000-4AFFFF
57
64
490000-49FFFF
58
64
480000-48FFFF
59
64
470000-47FFFF
60
64
460000-46FFFF
61
64
450000-45FFFF
62
64
440000-44FFFF
63
64
430000-43FFFF
64
64
420000-42FFFF
65
64
410000-41FFFF
66
64
400000-40FFFF
M58LR128HT, M58LR128HB
Table 30.
Block address tables
Top boot block addresses, M58LR128HT (continued)
Bank 11
Bank 10
Bank 9
Bank 8
Bank(1)
#
Size (KWord)
Address Range
67
64
3F0000-3FFFFF
68
64
3E0000-3EFFFF
69
64
3D0000-3DFFFF
70
64
3C0000-3CFFFF
71
64
3B0000-3BFFFF
72
64
3A0000-3AFFFF
73
64
390000-39FFFF
74
64
380000-38FFFF
75
64
370000-37FFFF
76
64
360000-36FFFF
77
64
350000-35FFFF
78
64
340000-34FFFF
79
64
330000-33FFFF
80
64
320000-32FFFF
81
64
310000-31FFFF
82
64
300000-30FFFF
83
64
2F0000-2FFFFF
84
64
2E0000-2EFFFF
85
64
2D0000-2DFFFF
86
64
2C0000-2CFFFF
87
64
2B0000-2BFFFF
88
64
2A0000-2AFFFF
89
64
290000-29FFFF
90
64
280000-28FFFF
91
64
270000-27FFFF
92
64
260000-26FFFF
93
64
250000-25FFFF
94
64
240000-24FFFF
95
64
230000-23FFFF
96
64
220000-22FFFF
97
64
210000-21FFFF
98
64
200000-20FFFF
77/112
Block address tables
M58LR128HT, M58LR128HB
Table 30.
Top boot block addresses, M58LR128HT (continued)
Bank 15
Bank 14
Bank 13
Bank 12
Bank(1)
#
Size (KWord)
Address Range
99
64
1F0000-1FFFFF
100
64
1E0000-1EFFFF
101
64
1D0000-1DFFFF
102
64
1C0000-1CFFFF
103
64
1B0000-1BFFFF
104
64
1A0000-1AFFFF
105
64
190000-19FFFF
106
64
180000-18FFFF
107
64
170000-17FFFF
108
64
160000-16FFFF
109
64
150000-15FFFF
110
64
140000-14FFFF
111
64
130000-13FFFF
112
64
120000-12FFFF
113
64
110000-11FFFF
114
64
100000-10FFFF
115
64
0F0000-0FFFFF
116
64
0E0000-0EFFFF
117
64
0D0000-0DFFFF
118
64
0C0000-0CFFFF
119
64
0B0000-0BFFFF
120
64
0A0000-0AFFFF
121
64
090000-09FFFF
122
64
080000-08FFFF
123
64
070000-07FFFF
124
64
060000-06FFFF
125
64
050000-05FFFF
126
64
040000-04FFFF
127
64
030000-03FFFF
128
64
020000-02FFFF
129
64
010000-01FFFF
130
64
000000-00FFFF
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;
Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
78/112
M58LR128HT, M58LR128HB
Table 31.
Block address tables
Bottom boot block addresses, M58LR128HB
Bank 12
Bank 13
Bank 14
Bank 15
Bank(1)
#
Size (KWord)
Address Range
130
64
7F0000-7FFFFF
129
64
7E0000-7EFFFF
128
64
7D0000-7DFFFF
127
64
7C0000-7CFFFF
126
64
7B0000-7BFFFF
125
64
7A0000-7AFFFF
124
64
790000-79FFFF
123
64
780000-78FFFF
122
64
770000-77FFFF
121
64
760000-76FFFF
120
64
750000-75FFFF
119
64
740000-74FFFF
118
64
730000-73FFFF
117
64
720000-72FFFF
116
64
710000-71FFFF
115
64
700000-70FFFF
114
64
6F0000-6FFFFF
113
64
6E0000-6EFFFF
112
64
6D0000-6DFFFF
111
64
6C0000-6CFFFF
110
64
6B0000-6BFFFF
109
64
6A0000-6AFFFF
108
64
690000-69FFFF
107
64
680000-68FFFF
106
64
670000-67FFFF
105
64
660000-66FFFF
104
64
650000-65FFFF
103
64
640000-64FFFF
102
64
630000-63FFFF
101
64
620000-62FFFF
100
64
610000-61FFFF
99
64
600000-60FFFF
79/112
Block address tables
M58LR128HT, M58LR128HB
Table 31.
Bottom boot block addresses, M58LR128HB (continued)
Bank 8
Bank 9
Bank 10
Bank 11
Bank(1)
80/112
#
Size (KWord)
Address Range
98
64
5F0000-5FFFFF
97
64
5E0000-5EFFFF
96
64
5D0000-5DFFFF
95
64
5C0000-5CFFFF
94
64
5B0000-5BFFFF
93
64
5A0000-5AFFFF
92
64
590000-59FFFF
91
64
580000-58FFFF
90
64
570000-57FFFF
89
64
560000-56FFFF
88
64
550000-55FFFF
87
64
540000-54FFFF
86
64
530000-53FFFF
85
64
520000-52FFFF
84
64
510000-51FFFF
83
64
500000-50FFFF
82
64
4F0000-4FFFFF
81
64
4E0000-4EFFFF
80
64
4D0000-4DFFFF
79
64
4C0000-4CFFFF
78
64
4B0000-4BFFFF
77
64
4A0000-4AFFFF
76
64
490000-49FFFF
75
64
480000-48FFFF
74
64
470000-47FFFF
73
64
460000-46FFFF
72
64
450000-45FFFF
71
64
440000-44FFFF
70
64
430000-43FFFF
69
64
420000-42FFFF
68
64
410000-41FFFF
67
64
400000-40FFFF
M58LR128HT, M58LR128HB
Table 31.
Block address tables
Bottom boot block addresses, M58LR128HB (continued)
Bank 4
Bank 5
Bank 6
Bank 7
Bank(1)
#
Size (KWord)
Address Range
66
64
3F0000-3FFFFF
65
64
3E0000-3EFFFF
64
64
3D0000-3DFFFF
63
64
3C0000-3CFFFF
62
64
3B0000-3BFFFF
61
64
3A0000-3AFFFF
60
64
390000-39FFFF
59
64
380000-38FFFF
58
64
370000-37FFFF
57
64
360000-36FFFF
56
64
350000-35FFFF
55
64
340000-34FFFF
54
64
330000-33FFFF
53
64
320000-32FFFF
52
64
310000-31FFFF
51
64
300000-30FFFF
50
64
2F0000-2FFFFF
49
64
2E0000-2EFFFF
48
64
2D0000-2DFFFF
47
64
2C0000-2CFFFF
46
64
2B0000-2BFFFF
45
64
2A0000-2AFFFF
44
64
290000-29FFFF
43
64
280000-28FFFF
42
64
270000-27FFFF
41
64
260000-26FFFF
40
64
250000-25FFFF
39
64
240000-24FFFF
38
64
230000-23FFFF
37
64
220000-22FFFF
36
64
210000-21FFFF
35
64
200000-20FFFF
81/112
Block address tables
M58LR128HT, M58LR128HB
Table 31.
Bottom boot block addresses, M58LR128HB (continued)
Parameter Bank
Bank 1
Bank 2
Bank 3
Bank(1)
#
Size (KWord)
Address Range
34
64
1F0000-1FFFFF
33
64
1E0000-1EFFFF
32
64
1D0000-1DFFFF
31
64
1C0000-1CFFFF
30
64
1B0000-1BFFFF
29
64
1A0000-1AFFFF
28
64
190000-19FFFF
27
64
180000-18FFFF
26
64
170000-17FFFF
25
64
160000-16FFFF
24
64
150000-15FFFF
23
64
140000-14FFFF
22
64
130000-13FFFF
21
64
120000-12FFFF
20
64
110000-11FFFF
19
64
1F0000-1FFFFF
18
64
0F0000-0FFFFF
17
64
0E0000-0EFFFF
16
64
0D0000-0DFFFF
15
64
0C0000-0CFFFF
14
64
0B0000-0BFFFF
13
64
0A0000-0AFFFF
12
64
090000-09FFFF
11
64
080000-08FFFF
10
64
070000-07FFFF
9
64
060000-06FFFF
8
64
050000-05FFFF
7
64
040000-04FFFF
6
64
030000-03FFFF
5
64
020000-02FFFF
4
64
010000-01FFFF
3
16
00C000-00FFFF
2
16
008000-00BFFF
1
16
004000-007FFF
0
16
000000-003FFF
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;
Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
82/112
M58LR128HT, M58LR128HB
Appendix B
Common Flash Interface
Common Flash Interface
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query Command is issued the device enters CFI Query mode and the
data structure is read from the memory. Tables 32, 33, 34, 35, 36, 37, 38, 39, 40 and 41
show the addresses used to retrieve the data. The Query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Figure 4: Protection Register memory map). This area can be accessed only
in Read mode by the final user. It is impossible to change the security number after it has
been written by ST. Issue a Read Array command to return to Read mode.
Table 32.
Query structure overview
Offset
Sub-section Name
Description
000h
Reserved
Reserved for algorithm-specific information
010h
CFI Query Identification String
Command set ID and algorithm data offset
01Bh
System Interface Information
Device timing & voltage information
027h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended
Query table
Additional information specific to the Alternate
Algorithm (optional)
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in Tables 33, 34, 35 and 36. Query data is always presented on the
lowest order data outputs.
83/112
Common Flash Interface
Table 33.
84/112
M58LR128HT, M58LR128HB
CFI query identification string
Offset
Sub-section Name
Description
000h
0020h
Manufacturer Code
001h
88C4h
88C5h
Device Code
002h-00Fh
Reserved
010h
0051h
011h
0052h
012h
0059h
013h
0001h
014h
0000h
015h
offset = P = 000Ah
016h
0001h
017h
0000h
018h
0000h
019h
value = A = 0000h
01Ah
0000h
Value
ST
M58LR128HT
M58LR128HB
Top
Bottom
Reserved
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control
Interface ID code 16 bit ID code defining a specific
algorithm
Address for Primary Algorithm extended Query table
(see Table 36)
p = 10Ah
Alternate Vendor Command Set and Control
Interface ID Code second vendor - specified
algorithm supported
NA
Address for Alternate Algorithm extended Query
table
NA
M58LR128HT, M58LR128HB
Table 34.
Common Flash Interface
CFI query system interface information
Offset
Data
01Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7V
01Ch
0020h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2V
01Dh
0085h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5V
01Eh
0095h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
9.5V
01Fh
0004h
Typical time-out per single byte/word program = 2n µs
16µs
020h
0009h
Description
Value
n
Typical time-out for Buffer Program = 2 µs
512µs
021h
000Ah
Typical time-out per individual block erase =
022h
0000h
Typical time-out for full chip erase = 2n ms
023h
024h
0004h
0004h
2n
ms
NA
n
Maximum time-out for word program = 2 times typical
Maximum time-out for Buffer Program =
2n
1s
256µs
times typical
8192µs
n
025h
0002h
Maximum time-out per individual block erase = 2 times typical
4s
026h
0000h
Maximum time-out for chip erase = 2n times typical
NA
85/112
Common Flash Interface
Table 35.
Device geometry definition
Data
027h
0018h
Device Size = 2n in number of bytes
028h
029h
0001h
0000h
Flash Device Interface Code description
02Ah
02Bh
0006h
0000h
Maximum number of bytes in multi-byte program or page = 2n
02Ch
0002h
Number of identical sized erase block regions within the
device
bit 7 to 0 = x = number of Erase Block Regions
02Dh
02Eh
007Eh
0000h
Erase Block Region 1 Information
Number of identical-size erase blocks = 007Eh+1
02Fh
030h
0000h
0002h
Erase Block Region 1 Information
Block size in Region 1 = 0200h * 256 Byte
031h
032h
0003h
0000h
Erase Block Region 2 Information
Number of identical-size erase blocks = 0003h+1
033h
034h
0080h
0000h
Erase Block Region 2 Information
Block size in Region 2 = 0080h * 256 Byte
TOP DEVICES
Offset
BOTTOM DEVICES
035h
038h
Description
Reserved Reserved for future erase block region information
02Dh
02Eh
0003h
0000h
Erase Block Region 1 Information
Number of identical-size erase block = 0003h+1
02Fh
030h
0080h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0080h * 256 bytes
031h
032h
007Eh
0000h
Erase Block Region 2 Information
Number of identical-size erase block = 007Eh+1
033h
034h
0000h
0002h
Erase Block Region 2 Information
Block size in Region 2 = 0200h * 256 bytes
035h
038h
86/112
M58LR128HT, M58LR128HB
Reserved Reserved for future erase block region information
Value
16 MBytes
x16
Async.
64 Bytes
2
127
128 KByte
4
32 KByte
NA
4
32 KBytes
127
128 KBytes
NA
M58LR128HT, M58LR128HB
Table 36.
Common Flash Interface
Primary algorithm-specific extended query table
Offset
Data
(P)h = 10Ah
0050h
0052h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string
“PRI”
0049h
"R"
"I"
(P+3)h =10Dh
0031h
Major version number, ASCII
"1"
(P+4)h = 10Eh
0033h
Minor version number, ASCII
"3"
(P+5)h = 10Fh
00E6h
Extended Query table contents for Primary Algorithm. Address
(P+5)h contains less significant byte.
0003h
(P+7)h = 111h
(P+8)h = 112h
0000h
0000h
bit 0 Chip Erase supported(1 = Yes, 0 = No)
bit 1 Erase Suspend supported(1 = Yes, 0 = No)
bit 2 Program Suspend supported(1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4 Queued Erase supported(1 = Yes, 0 = No)
bit 5 Instant individual block locking supported(1 = Yes, 0 = No)
bit 6 Protection bits supported(1 = Yes, 0 = No)
bit 7 Page mode read supported(1 = Yes, 0 = No)
bit 8 Synchronous read supported(1 = Yes, 0 = No)
bit 9 Simultaneous operation supported(1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then
another 31 bit field of optional features follows at the end of the
bit-30 field.
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
(P+9)h = 113h
0001h
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 114h
0003h
(P+B)h = 115h
0000h
Yes
Block Protect Status
Defines which bits in the Block Status Register section of the
Query are implemented.
bit 0 Block protect Status Register Lock/Unlock
bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes,
0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
(P+C)h = 116h
1.8V
0018h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
VPP Supply Optimum Program/Erase voltage
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9V
87/112
Common Flash Interface
Table 37.
Protection Register information
Offset
Data
(P+E)h = 118h
0002h
(P+F)h = 119h
(P+12)h = 11Ch
0080h Protection Field 1: Protection Description
0000h Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
0003h
Bits 16-23 2n bytes in factory pre-programmed region
0003h Bits 24-31 2n bytes in user programmable region
(P+13)h = 11Dh
0089h
(P+10)h = 11Ah
(P+ 11)h = 11Bh
(P+14)h = 11Eh
0000h
(P+15)h = 11Fh
0000h
(P+16)h = 120h
0000h
(P+17)h = 121h
0000h
(P+18)h = 122h
0000h
(P+19)h = 123h
0000h
(P+1A)h = 124h
0010h
(P+1B)h = 125h
0000h
(P+1C)h = 126h
0004h
Table 38.
Description
Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available.
Value
2
80h
00h
8 Bytes
8 Bytes
89h
Protection Register 2: Protection Description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower
byte)
Bits 40-47 n number of factory programmed regions (upper
byte)
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower
byte)
Bits 64-71 n number of user programmable regions (upper
byte)
Bits 72-79 2n bytes in user programmable region
00h
00h
00h
0
0
0
16
0
16
Burst Read information
Offset
88/112
M58LR128HT, M58LR128HB
Data
Description
Value
(P+1D)h = 127h
Page-mode read capability
bits 0-7 n’ such that 2n HEX value represents the number of
0003h
read-page bytes. See offset 0028h for device word width to
determine page-mode data output width.
(P+1E)h = 128h
0004h
(P+1F)h = 129h
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear
0001h
bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space.
This field’s 3-bit value can be written directly to the read
configuration register bit 0-2 if the device is configured for its
maximum word width. See offset 0028h for word width to
determine the burst data output width.
4
(P+20)h = 12Ah
0002h Synchronous mode read capability configuration 2
8
(P-21)h = 12Bh
(P+22)h = 12Ch
0003h Synchronous mode read capability configuration 3
0007h Synchronous mode read capability configuration 4
16
Number of synchronous mode read configuration fields that
follow.
8 Bytes
4
Cont.
M58LR128HT, M58LR128HB
Table 39.
Common Flash Interface
Bank and Erase block region information(1) (2)
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+23)h = 12Dh
02h
(P+23)h = 12Dh
02h
Number of Bank Regions within the device
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 and Table 31.
Table 40.
Bank and Erase block region 1 information
M58LR128HT (top)
M58LR128HB
(bottom)
Offset
Data
Offset
Data
(P+24)h = 12Eh
0Fh
(P+24)h = 12Eh
01h
(P+25)h = 12Fh
00h
(P+25)h = 12Fh
00h
Description
Number of identical banks within Bank Region 1
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
11h
00h
00h
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
11h
Number of program or erase operations allowed
in Bank Region 1:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations allowed
in other banks while a bank in same region is
programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations allowed
in other banks while a bank in this region is
erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
Types of erase block regions in Bank Region 1
n = number of erase block regions with
contiguous same-size erase blocks.
Symmetrically blocked banks have one blocking
region(2).
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h
07h
(P+2A)h = 134h
03h
(P+2B)h = 135h
00h
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2C)h = 136h
80h
(P+2D)h = 137h
02h
(P+2D)h = 137h
00h
(P+2E)h = 138h
64h
(P+2E)h = 138h
64h
(P+2F)h = 139h
00h
(P+2F)h = 139h
00h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
89/112
Common Flash Interface
Table 40.
M58LR128HT, M58LR128HB
Bank and Erase block region 1 information (continued)
M58LR128HT (top)
Offset
(P+30)h = 13Ah
(P+31)h = 13Bh
Data
01h
03h
M58LR128HB
(bottom)
Offset
Description
Data
01h
Bank Region 1 (Erase Block Type 1): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+31)h = 13Bh
03h
Bank Region 1 (Erase Block Type 1): Page
mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+32)h = 13Ch
06h
Bank Region 1 Erase Block Type 2 Information
(P+33)h = 13Dh
00h
(P+34)h = 13Eh
00h
(P+35)h = 13Fh
02h
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
(P+36)h = 140h
64h
(P+37)h = 141h
00h
(P+30)h = 13Ah
(P+38)h = 142h
(P+39)h = 143h
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
01h
Bank Regions 1 (Erase Block Type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 1 (Erase Block Type 2): Page
mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 to Table 31.
90/112
M58LR128HT, M58LR128HB
Table 41.
Common Flash Interface
Bank and Erase block region 2 information
M58LR128HT (top)
M58LR128HB (bottom)
Description
Offset
Data
Offset
Data
(P+32)h = 13Ch
01h
(P+3A)h = 144h
0Fh
(P+33)h = 13Dh
00h
(P+3B)h = 145h
00h
Number of identical banks within Bank Region 2
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
11h
00h
00h
(P+3C)h = 146h
(P+3D)h = 147h
(P+3E)h = 148h
11h
Number of program or erase operations allowed
in Bank Region 2:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations allowed
in other banks while a bank in this region is
programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations allowed
in other banks while a bank in this region is
erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
Types of erase block regions in Bank Region 2
n = number of erase block regions with
contiguous same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(2)
(P+37)h = 141h
02h
(P+3F)h = 149h
01h
(P+38)h = 142h
06h
(P+40)h = 14Ah
07h
(P+39)h = 143h
00h
(P+41)h = 14Bh
00h
(P+3A)h = 144h
00h
(P+42)h = 14Ch
00h
(P+3B)h = 145h
02h
(P+43)h = 14Dh
02h
(P+3C)h = 146h
64h
(P+44)h = 14Eh
64h
(P+3D)h = 147h
00h
(P+45)h = 14Fh
00h
(P+3E)h = 148h
01h
(P+46)h = 150h
01h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
91/112
Common Flash Interface
Table 41.
M58LR128HT, M58LR128HB
Bank and Erase block region 2 information (continued)
M58LR128HT (top)
M58LR128HB (bottom)
Description
Offset
Data
(P+3F)h = 149h
03h
(P+40)h = 14Ah
03h
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h = 14Eh
64h
(P+45)h = 14Fh
00h
(P+46)h = 150h
(P+47)h = 151h
Offset
(P+47)h = 151h
Data
03h
Bank Region 2 (Erase Block Type 1):Page mode
and Synchronous mode capabilities (defined in
Table 38)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
01h
Bank Region 2 (Erase Block Type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 2 (Erase Block Type 2): Page mode
and Synchronous mode capabilities (defined in
Table 38)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 and Table 31.
92/112
M58LR128HT, M58LR128HB
Appendix C
Flowcharts and pseudocodes
Flowcharts and pseudocodes
Figure 19. Program flowchart and pseudocode
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
Write 40h or 10h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
93/112
Flowcharts and pseudocodes
M58LR128HT, M58LR128HB
Figure 20. Blank Check flowchart and pseudocode
Start
blank_check_command (blockToCheck) {
writeToFlash (blockToCheck, 0xBC);
Write Block
Address & BCh
writeToFlash (blockToCheck, 0xCB);
/* Memory enters read status state after
the Blank Check Command */
Write Block
Address & CBh
do {
status_register = readFlash (blockToCheck);
/* see note (1) */
/* E or G must be toggled */
Read
Status Register (1)
} while (status_register.SR7==0);
SR7 = 1
NO
YES
SR4 = 1
SR5 = 1
SR5 = 0
YES
NO
Command Sequence
Error (2)
if (status_register.SR4==1) && (status_register.SR5==1)
/* command sequence error */
error_handler () ;
Blank Check Error (2)
if (status_register.SR5==1)
/* Blank Check error */
error_handler () ;
End
}
ai10520c
1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
94/112
M58LR128HT, M58LR128HB
Flowcharts and pseudocodes
Figure 21. Buffer Program flowchart and pseudocode
Start
Buffer Program E8h
Command,
Start Address
status_register=readFlash (Start_Address);
Read Status
Register
SR7 = 1
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/* buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
do {writeToFlash (Start_Address, 0xE8) ;
NO
} while (status_register.SR7==0);
YES
writeToFlash (Start_Address, n);
Write n(1),
Start Address
Write Buffer Data,
Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
X=0
X=n
x = 0;
YES
while (x<n)
NO
Write Next Buffer Data,
Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++;
X=X+1
}
Program
Buffer to Flash
Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status
Register
SR7 = 1
do {status_register=readFlash (Start_Address);
NO
} while (status_register.SR7==0);
YES
Full Status
Register Check(3)
full_status_register_check();
}
End
AI08913b
1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
buffer_Program[].address
3. Routine for Error Check by reading SR3, SR4 and SR1.
95/112
Flowcharts and pseudocodes
M58LR128HT, M58LR128HB
Figure 22. Program Suspend & Resume flowchart and pseudocode
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
YES
Read Data
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
96/112
M58LR128HT, M58LR128HB
Flowcharts and pseudocodes
Figure 23. Block Erase flowchart and pseudocode
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
Read Status
Register (2)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI10976
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
97/112
Flowcharts and pseudocodes
M58LR128HT, M58LR128HB
Figure 24. Erase Suspend & Resume flowchart and pseudocode
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
YES
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from another block,
Program,
Set Configuration Register or
Block Protect/Unprotect/Lock
}
else
Write D0h
Write FFh
Erase Continues
Read Data
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
AI13893
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
98/112
M58LR128HT, M58LR128HB
Flowcharts and pseudocodes
Figure 25. Locking Operations flowchart and pseudocode
Start
locking_operation_command (address, lock_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
/* see note (1) */
Write 60h (1)
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI06176b
1. Any address within the bank can equally be used.
99/112
Flowcharts and pseudocodes
M58LR128HT, M58LR128HB
Figure 26. Protection Register Program flowchart and pseudocode
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
100/112
M58LR128HT, M58LR128HB
Flowcharts and pseudocodes
Figure 27. Buffer Enhanced Factory Program flowchart and pseudocode
Start
NO
writeToFlash (start_address, 0x80) ;
Write D0h to
Address WA1
writeToFlash (start_address, 0xD0) ;
Read Status
Register
do {
do {
status_register = readFlash (start_address);
SR7 = 0
Initialize count
X=0
SR4 = 1
Read Status Register
SR3 and SR1for errors
Write PDX
Address WA1
Exit
Increment Count
X=X+1
NO
Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
Write 80h to
Address WA1
YES
NO
SETUP PHASE
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */
PROGRAM AND }
VERIFY PHASE while (status_register.SR7==1)
x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
X = 32
NO
YES
}while (x<32)
do {
Read Status
Register
status_register = readFlash (start_address);
SR0 = 0
}while (status_register.SR0==1)
YES
NO
Last data?
} while (not last data)
YES
Write FFFFh to
Address = NOT WA1
Read Status
Register
NO
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
do {
status_register = readFlash (start_address)
SR7 = 1
}while (status_register.SR7==0)
YES
Full Status Register
Check
full_status_register_check();
End
}
AI07302a
101/112
Command interface state tables
Appendix D
Table 42.
M58LR128HT, M58LR128HB
Command interface state tables
Command Interface states - modify table, next state(1)
Command Input
Current CI State
Ready
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Ready
Program
Setup
Lock/CR Setup
BP
Setup
Erase
Setup
BEFP
Setup
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
confirm Erase Register
setup
(5)
CFI Query
BEFP
(CBh) Suspend (70h)
(BCh)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Blank
Check
setup
Ready (unlock
block)
Ready (Lock Error)
Setup
Busy
OTP
OTP
Busy
IS in OTP
Busy
OTP Busy
Program Busy
IS in
Program
Program
Program
Busy
Busy
Busy
IS in Program
Busy
IS in
Program
Busy
Program Busy
Program
Suspend
Program Busy
Program Busy
PS
IS in PS
PS
IS in Program
Suspend
PS
Program Busy
Program Suspend
IS in PS
Program Suspend
Setup
Buffer Program Load 1 (give word count load (N-1));
Buffer
Load 1
if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load)
Buffer
Load 2
Buffer Program Confirm when count =0; Else Buffer Program Load 2
(note: Buffer Program will fail at this point if any block address is different from the first address)
Busy
IS in BP
Busy
Suspend
IS in BP
Suspend
102/112
IS in OTP Busy
Setup
Confirm
Buffer
Program
OTP
busy
OTP Busy
Suspend
Ready (Lock Error)
OTP Busy
IS in
OTP
busy
Busy
Program
Ready
Ready (error)
BP Busy IS in BP
Busy
BP Busy
BP Busy
BP Busy
IS in BP Busy
Ready (error)
BP
Suspend
Buffer Program Busy
Buffer Program Busy
BP
BP
IS in BP
BP
IS in BP Suspend
Suspend
Suspend Suspend Suspend
BP busy
Buffer Program Suspend
Buffer Program Suspend
M58LR128HT, M58LR128HB
Table 42.
Command interface state tables
Command Interface states - modify table, next state(1) (continued)
Command Input
Current CI State
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Setup
Busy
Erase
Erase
Busy
IS in
Erase
Busy
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
setup
confirm Erase Register
(5)
CFI Query
BEFP
(BCh)
(CBh) Suspend (70h)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Ready (error)
Erase Busy
Erase
Busy
Erase Busy
IS in Erase Busy
IS in
Erase
Busy
Suspend
Erase
Suspend
Erase Busy
Erase Busy
Erase
Program
BP in ES
Suspend
in ES
IS in Erase
Suspend
ES
Erase Busy
IS in ES
Erase Suspend
Setup
Program Busy in Erase Suspend
Busy
Ready (error)
IS in
Program
Program
Busy in
Busy in
ES
ES
Program
Busy in
ES
IS in Program
Busy in ES
Program IS in
in Erase Program
Suspend busy in
ES
Erase Suspend
Program Busy in ES
PS in ES
Program Busy in Erase
Suspend
Program busy in Erase Suspend
Suspend PS in ES
IS in PS in
PS in ES
ES
IS in Program
Suspend in ES
PS in ES
Program Busy
in ES
Program Suspend in Erase Suspend
IS in PS
in ES
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N ≠ 0) go to
Buffer Program Load 2
Buffer
Load 1
Buffer Program Load 2 in Erase Suspend (data load)
Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program
Load 2
will fail at this point if any block address is different from the first address)
Confirm
Buffer
Program
in Erase
Suspend
Busy
IS in BP
busy in
ES
Erase Suspend (sequence error)
BP Busy
in ES
IS in BP
Busy in
ES
BP busy
in ES
BP Busy in ES
IS in BP busy in
ES
BP
Suspend
in ES
BP Busy in ES
Buffer Program Busy in ES
Buffer Program Busy in Erase Suspend
BP
BP
IS in BP
BP
IS in BP Suspend Suspend
Suspend Suspend Suspend Suspend in
Erase Suspend
in
ES
in
ES
in ES
in ES
IS in BP
Suspend
in ES
Erase Suspend (sequence error)
BP Busy in
Erase
Suspend
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
103/112
Command interface state tables
Table 42.
M58LR128HT, M58LR128HB
Command Interface states - modify table, next state(1) (continued)
Command Input
Current CI State
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Setup
Blank
Check
Busy
Lock/CR Setup in
Erase Suspend
Buffer
EFP
Setup
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
setup
confirm Erase Register
(5)
CFI Query
BEFP
(BCh)
(CBh) Suspend (70h)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Blank
Check
busy
Ready (error)
Blank IS in Blank
Check
Check
busy
busy
Blank
Check
busy
IS in Blank Check
busy
Ready (error)
Blank Check busy
Erase Suspend (Lock Error)
Erase
Suspend
Erase Suspend (Lock Error)
Ready (error)
BEFP Busy
Ready (error)
Busy
BEFP Busy(6)
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend.
2. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E C is active, both cycles are ignored.
5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
104/112
M58LR128HT, M58LR128HB
Table 43.
Command interface state tables
Command Interface states - modify table, next output state(1) (2)
Command Input
Current CI State
Erase Confirm
Block
Blank P/E Resume,
Buffer Erase, BEFP
Block Unlock
(4)
Setup Check
Program Setup
(5)
setup confirm, BEFP
(5)
(E8h)
(80h) (BCh) Confirm(4)(5)
(10/40h)
(20h)
(D0h)
Read Program
Array Setup(4)
(3)
(FFh)
Blank
Clear
Program/ Read
Check
Status
Status
Erase
confir
Suspend Register Register
m
(B0h)
(70h)
(50h)
(CBh)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
Program Setup
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program
Setup
Buffer Program
Load 1
Buffer Program
Load 2
Buffer Program
Confirm
Status Register
Buffer Program
Setup in Erase
Suspend
Buffer Program
Load 1 in Erase
Suspend
Buffer Program
Load 2 in Erase
Suspend
Buffer Program
Confirm in Erase
Suspend
Blank Check setup
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
105/112
Command interface state tables
Table 43.
M58LR128HT, M58LR128HB
Command Interface states - modify table, next output state(1) (2) (continued)
Command Input
Current CI State
Erase Confirm
Block
Blank P/E Resume,
Buffer Erase, BEFP
Block Unlock
(4)
Setup Check
Program Setup
(5)
setup confirm, BEFP
(5)
(E8h)
(80h) (BCh) Confirm(4)(5)
(10/40h)
(20h)
(D0h)
Read Program
Array Setup(4)
(3)
(FFh)
Blank
Clear
Program/ Read
Check
Status
Status
Erase
confir
Suspend Register Register
m
(B0h)
(70h)
(50h)
(CBh)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
Status
Register
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program
Busy
Program/Erase
Suspend
Buffer Program
Suspend
Array
Status Register
Output Unchanged
Program Busy in
Erase Suspend
Status
Output
Register Unchanged Electronic
Signature/
CFI
Buffer Program
Busy in Erase
Suspend
Program Suspend
in Erase Suspend
Buffer Program
Suspend in Erase
Suspend
Blank Check busy
Illegal State
Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/E.C. is active, both cycles are ignored.
106/112
M58LR128HT, M58LR128HB
Command interface state tables
Command interface states - lock table, next state(1)
Table 44.
Command Input
Current CI State
Ready
Lock/CR Setup
Lock/CR Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Lock/CR Setup
OTP Setup
Busy
Block
Address
(WA0)(3)
(XXXXh)
Illegal
Command(4)
Ready
P/E C
operation
completed
(5)
N/A
Ready (Lock error)
OTP Busy
N/A
N/A
IS in OTP Busy
Ready
OTP Busy
IS in OTP
busy
OTP Busy
IS Ready
Setup
Program Busy
N/A
Busy
Program
Set CR
Confirm
(03h)
Ready
Ready (Lock error)
Setup
OTP
Block
LockDown
Confirm
(2Fh)
Block
Lock
Confirm
(01h)
IS in Program Busy
IS in Program
busy
Suspend
Ready
Program Busy
Program busy
IS in PS
IS Ready
Program Suspend
N/A
IS in PS
Program Suspend
Setup
Buffer Program Load 1 (give word count load (N-1));
Buffer Program Load 2(6)
see note (6)
N/A
Buffer Load 2
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at
this point if any block address is different from the first address)
N/A
Confirm
Ready (error)
N/A
Buffer Load 1
Buffer
Program
Busy
Suspend
Exit
IS in BP Busy
IS in Buffer
Program
busy
Buffer Program Busy
Buffer Program Busy
IS in BP Suspend
Buffer Program Suspend
N/A
Buffer Program Suspend
Setup
Ready (error)
IS in Erase Busy
IS in Erase
busy
Suspend
IS in ES
Ready
IS Ready
IS in BP
Suspend
Busy
Erase
N/A
N/A
Erase Busy
Erase Busy
Lock/CR Setup in
ES
IS in ES
Ready
IS ready
Erase Suspend
N/A
Erase Suspend
107/112
Command interface state tables
Table 44.
M58LR128HT, M58LR128HB
Command interface states - lock table, next state(1) (continued)
Command Input
Current CI State
Lock/CR Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Setup
Busy
Program
in Erase
Suspend
Block
LockDown
Confirm
(2Fh)
Block
Address
(WA0)(3)
(XXXXh)
Set CR
Confirm
(03h)
Illegal
Command(4)
P/E C
operation
completed
Program Busy in Erase Suspend
IS in Program busy in ES
ES
Program Busy in Erase Suspend
IS in PS in ES
(5)
N/A
Program Busy in Erase Suspend
IS in Program
busy in ES
Suspend
Block
Lock
Confirm
(01h)
IS in ES
Program Suspend in Erase Suspend
N/A
IS in PS in ES
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1))
Buffer Load 1
Buffer
Program
in Erase
Suspend
Buffer Program Load 2 in Erase Suspend(7)
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase
Suspend (note: Buffer Program will fail at this point if any block address is different from the first
address)
Confirm
Erase Suspend (sequence error)
Busy
IS in BP busy in ES
Buffer Program Busy in Erase Suspend
IS in BP busy
in ES
Suspend
Blank
Check
see note (7)
Exit
BP busy in ES
IS in BP suspend in ES
Buffer Program Suspend in Erase Suspend
N/A
Buffer Program Suspend in Erase Suspend
Setup
Ready (error)
Lock/CR Setup in ES
ES
IS in ES
IS in BP
Suspend in
ES
Blank Check
busy
N/A
IS in Blank Check busy
N/A
Blank Check busy
Erase Suspend (Lock error)
Setup
Erase Suspend
Ready
Erase Suspend (Lock error)
Ready (error)
N/A
N/A
BEFP
Busy
BEFP Busy(8)
Exit
BEFP Busy(8)
N/A
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP
address.
2. If the P/E C is active, both cycle are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. N/A: not available. In this case the state remains unchanged.
6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load)
7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend.
8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
108/112
M58LR128HT, M58LR128HB
Table 45.
Command interface state tables
Command interface states - lock table, next output state (1) (2)
Command Input
Current CI State
Lock/CR
Setup(3)(
60h)
Blank
Check
setup
(BCh)
OTP
Setup(3)
(C0h)
Blank
Check
confirm
(CBh)
P. E./C.
Illegal
Block Lock Block Lock- Set CR BEFP
Confirm
Down
Confirm Exit(4) Command Operation
(5)
Completed
(01h)
Confirm (2Fh) (03h) (FFFFh)
Program Setup
Erase Setup
OTP Setup
Program Setup in Erase
Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Status Register
Buffer Program Load 2
Output
Unchanged
Buffer Program Confirm
Buffer Program Setup in
Erase Suspend
Buffer Program Load 1 in
Erase Suspend
Buffer Program Load 2 in
Erase Suspend
Buffer Program Confirm in
Erase Suspend
Blank Check setup
Lock/CR Setup
Lock/CR Setup in Erase
Suspend
Status Register
Array
Status Register
109/112
Command interface state tables
Table 45.
M58LR128HT, M58LR128HB
Command interface states - lock table, next output state (continued)(1) (2)
Command Input
Current CI State
Lock/CR
Setup(3)(
60h)
Blank
Check
setup
(BCh)
OTP
Setup(3)
(C0h)
Blank
Check
confirm
(CBh)
P. E./C.
Block Lock Block Lock- Set CR BEFP
Illegal
Confirm
Down
Confirm Exit(4) Command Operation
(5)
Completed
(01h)
Confirm (2Fh) (03h) (FFFFh)
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Buffer Program Suspend
Status Register
Output Unchanged
Array
Output Unchanged
Program Busy in Erase
Suspend
Buffer Program Busy in
Erase Suspend
Program Suspend in Erase
Suspend
Buffer Program Suspend in
Erase Suspend
Blank Check busy
Illegal State
Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank's output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. If the P/E.C. is active, both cycles are ignored.
4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
5. Illegal commands are those not defined in the command set.
110/112
M58LR128HT, M58LR128HB
Revision history
Revision history
Table 46.
Document revision history
Date
Revision
17-Feb-2006
0.1
Initial release.
0.2
Document status promoted from Target Specification to Preliminary
data. Small text changes.
By default CR10 = 1 and CR8 = 1 (see Table 11: Configuration
Register). Table 12: Burst type definition modified.
Figure 5: X-Latency and data output configuration example modified.
Section 7.1: Asynchronous Read mode and Section 7.3: Single
Synchronous Read mode modified.
In Table 17: Program/Erase times and endurance cycles:
– Main Block Program at VPP = VDD modified
– Buffer, Main Block and Bank Program modified, and Blank Check
timings added at VPP = VPPH
tVDHPH changed in Table 27: Reset and Power-up AC characteristics.
tWHLL and Note 3 modified in Table 25: Write AC characteristics,
Write Enable controlled.
1
Document status promoted from Preliminary data to full Datasheet.
Address lines corrected in Figure 3: Memory map. Set Configuration
Register is not accepted during Program Suspend but it is accepted
during Erase Suspend (see Figure 24: Erase Suspend & Resume
flowchart and pseudocode).
Figure 10: Asynchronous Page Read AC waveforms modified.
Appendix D: Command interface state tables modified.
30-Jun-2006
26-Feb-2007
Changes
111/112
M58LR128HT, M58LR128HB
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112/112