A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation FEATURES AND BENEFITS DESCRIPTION • • • • • • • • • • • The A8652/53 is a high output current synchronous buck regulator that provides tight load regulation over a wiring harness without the need for remote sense lines. This remote load regulation is achieved with an integrated open-loop correction scheme that, given a known wiring harness resistance, adjusts the output voltage based on the measured load current and a user-programmable gain, achieving ±2% accuracy at 500 mV of correction. The Remote Load Regulation control includes a 115% regulated voltage clamp in conjunction with a dynamic overvoltage protection, with OVP threshold changing with the correction voltage. The A8652/53 includes a user-configurable load-side current limit to fold back the output voltage during an output overcurrent condition. The A8652/53 regulates nominal input voltages from 4 to 36 V and remains operational when VIN drops as low as 2.6 V. When the input voltage approaches the output voltage, the duty cycle is maximized to maintain the output voltage. • • • • Automotive AEC-Q100 qualified Cable and wiring drop compensation Dynamic voltage correction with controller Integrated high-side and low-side switching MOSFETs Programmable load-side current limit Maximized duty cycle for low dropout operation Operating input voltage range: 4 V to 36 V UVLO STOP threshold is at 2.6 VTYP Withstands surge voltages up to 40 V Continuous loading: 2.6 A for A8653; 1 A for A8652 Adjustable switching frequency (fSW): 100 kHz to 2.2 MHz Synchronization to external clock: 100 kHz to 2.2 MHz Frequency dithering for lower EMI signature External adjustable compensation network Stable with ceramic output capacitors Continued on next page... The A8652/53 features include externally set soft-start time, external compensation network, an EN input to enable VOUT, a SYNC/FSET input to synchronize or set the PWM switching PACKAGES: 16-Pin eTSSOP (suffix LP) with exposed thermal pad Continued on next page... APPLICATIONS • • • • Not to scale VIN CIN 2 × 4.7 µF Automotive USB Power Ports Rear Seat Entertainment Navigation Systems Motorcycle Clusters BOOT VIN CBOOT 100 nF GND LO RSEN VOUT RWIRE/2 SW CO RGADJ EN RWIRE/2 GADJ SYNC/FSET A8652/3 ISEN+ CF (optional) RFSET SS ISENRIADJ CSS 22 nF IADJ COMP CP RPU 10 kΩ RZ CZ RF (optional) FB POK Typical Application Diagram 1 A8652/53-DS, Rev.2 RFB1 24.9 kΩ RFB2 4.75 kΩ VLOAD CLOAD A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation FEATURES AND BENEFITS (continued) • Pre-bias startup compatible • Power OK (POK) output • Dynamic overvoltage protection, pulse-by-pulse current limit, hiccup mode short-circuit, and thermal protections • Open-circuit and adjacent pin short-circuit tolerant • Short-to-ground tolerant at every pin • USB3 charging capability: 2.6 A (A8653) • USB2 capability: 1 A (A8652) DESCRIPTION (continued) frequency, and a Power OK output to indicate when VOUT is within regulation and there is no load-side current limit condition. Protection features include VIN undervoltage lockout, pulse-by-pulse current limit, hiccup mode short-circuit protection, dynamic overvoltage protection, and thermal shutdown. The A8652/53 provides opencircuited, adjacent pin short-circuit, and short-to-ground protection at every pin to satisfy the most demanding automotive and nonautomotive applications. The A8652/53 device is available in a 16-pin eTSSOP package with exposed pads for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte-tin lead frame plating. The maximum junction temperature (TJ(max)) is 150ºC. VIN CIN 2 × 4.7 µF BOOT VIN CBOOT 100 nF GND RSEN 20 mΩ LO 10 µH VOUT RWIRE/2 62.5 mΩ SW CO 2 × 22 µF RIADJ 20 kΩ EN RWIRE/2 62.5 mΩ IADJ SYNC/FSET A8653 RFSET 52.3 kΩ ISEN+ CF (optional) RF (optional) RGE CSS 22 nF VG GADJ RGADJ 20 kΩ COMP 5V RFB1 24.9 kΩ RPU 10 kΩ RZ POK FB CZ CLOAD 100 µF ISEN- SS CP VLOAD RFB2 4.75 kΩ Typical Application Diagram 2 with Dynamic Voltage Correction Control at Pin GADJ Selection Guide Part Number A8652KLPTR-T A8653KLPTR-T Packing Package 4000 pieces per 13-inch reel 4.4 mm × 5 mm, 1.2 mm nominal height 16-pin eTSSOP with exposed thermal pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation SPECIFICATIONS Absolute Maximum Ratings1 Characteristic Symbol Notes Rating VIN, EN, SS Unit –0.3 to 40 V –0.3 to VIN + 0.3 V VIN ≤ 36 V, t < 50 ns –1 to VIN + 2 V Continuous VSW – 0.3 to VSW + 5.5 V < 1 ms VSW – 0.3 to VSW + 7 V –0.3 to 6.5 V ISEN+ to ISEN– Differential Voltage –0.3 to 0.3 V All other pins –0.3 to 5.5 V TJ(max) 150 ºC Tstg –55 to 150 ºC SW to GND 2 BOOT Pin Above SW Pin VSW VBOOT ISEN+ and ISEN– Pins Maximum Junction Temperature Storage Temperature Range Continuous ISEN+ and ISEN– Pins 1 Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability 2 SW has internal clamp diodes to GND and VIN. Applications that forward bias these diodes should take care not to exceed the IC package power dissipation limits. Thermal Characteristics Characteristic Package Thermal Resistance 3 Additional Symbol RθJA Test Conditions3 LP Package, 4-layer PCB based on JEDEC standard Value Unit 34 ºC/W thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation PINOUT DIAGRAM AND TERMINAL LIST TABLE EN 1 16 BOOT VIN 2 15 SW SS 3 14 PGND GADJ 4 FB 5 PAD 13 PGND 12 ISEN+ IADJ 6 11 ISEN– SGND 7 10 POK COMP 8 9 SYNC/FSET Package LP, 16-Pin eTSSOP Pinout Diagram Terminal List Table Symbol Number Function EN 1 Enable input. This pin is used to turn the converter on or off: set this pin high to turn the converter on or set this pin low to turn the converter off. May be connected to VIN. VIN 2 Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. A high quality ceramic capacitor should be placed very close to this pin. SS 3 Soft-Start pin. Connect a capacitor, CSS, from this pin to GND to set the soft-start time. This capacitor also determines the hiccup period during overcurrent. GADJ 4 This pin is used to set the gain of the differential current sense amplifier with ISEN+/ISEN– pins. A resistor from this pin to GND set the amplifier gain. Together with load sense resistor, it sets the desired voltage correction at the specified load condition. Grounding GADJ disables Remote Load Regulation function. FB 5 Feedback (negative) input to the error amplifier. Connect a resistor divider from the converter output node (VOUT) to this pin to program the output voltage. IADJ 6 Active current limit adjust pin. A resistor from this pin to GND sets the current limit. When the load current exceeds this limit, the output voltage will decrease at the predefined slope. SGND 7 Signal (quiet) GND. COMP 8 Output of the error amplifier and compensation node for the control loop. Connect a series RC network from this pin to GND for loop compensation. SYNC/FSET 9 Frequency setting and synchronization pin. A resistor, RFSET, from this pin to GND sets the PWM switching frequency. POK 10 Power OK output signal. This pin is an open-drain output that transitions from low impedance to high impedance when the output is within the final regulation voltage and no load side current limit exists. ISEN– 11 Negative current-sensing pin to the internal current sense amplifier, connected to the load side of the external current sensing resistor. ISEN+ 12 Positive current-sensing pin to the internal current sense amplifier, connected to the inductor side of the external current sensing resistor. PGND 13, 14 SW 115 The source of the high-side N-channel MOSFET. The output inductor (LO) should be connected to this pin. LO should be placed as close as possible to this pin and connected with relatively wide traces. BOOT 16 High-side gate drive boost input. Connect a 100 nF ceramic capacitor from BOOT to SW. PAD – Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad. Power GND. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation VIN BOOT REG VIN Regulator VREF VREG UVLO EN BOOT Current Sense Amp TSD Isen OCP 500 nA EN SYNC/FSET Protection & Fault OVP OSC SW Adj 5 µs CLK 80 mV 80 mΩ FB PWM Control Logic PWM COMP Error Amp VREG 55 mΩ Σ COMP Slope Comp PGND Ramp Offset 20 µA 5 µA HICCUP LOGIC 400 mV 2 kΩ FAULT SS REF_ADJ POK UV 920 mV OV VREF 800 mV Sense Amp ISEN+ ISEN– Adj GADJ SGND IADJ Functional Block Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation ELECTRICAL CHARACTERISTICS: Valid at 4 V ≤ VIN ≤ 36 V; TA = 25ºC; • indicates specifications guaranteed –40°C ≤ TA = TJ ≤ 150°C (unless noted otherwise). Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT VOLTAGE SPECIFICATIONS Operating Input Voltage Range 2 4 – 36 V UVLO Start Threshold VUVLO(START) VIN VIN rising ● – 3.4 3.7 V UVLO Stop Threshold VUVLO(STOP) VIN falling – 2.6 2.9 V UVLO Hysteresis VUVLO(HYS) – 800 – mV – 3 6.5 mA VIN = 12 V, VEN ≤ 0.4 V, –40°C < TA = TJ < 85°C – 1 240 µA VIN = 12 V, VEN ≤ 0.4 V, TA = TJ = 125°C – 40 900 µA 792 800 808 mV INPUT CURRENTS Input Quiescent Current 1 Input Sleep Supply Current 1 IQ IQSLEEP VEN = 5 V, VFB = 1 V, no PWM switching ● VOLTAGE REGULATION Feedback Voltage Accuracy 3 Feedback Voltage Accuracy with Cable Compensation 3 Error Amp Clamp Voltage 3 Output Voltage Setting Range 3 VFB VFB = VCOMP, VGADJ = 0 V, –40°C < TA = TJ < 125°C VFB = VCOMP, VGADJ = 0 V ● 788 800 812 mV VFB(ACC) VFB = VCOMP, VISEN+ – VISEN– = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ ● 808 825 842 mV VFB(CLAMP) VFB = VCOMP, VISEN+ – VISEN– = 55 mV, VOUT =5 V, RGADJ = 7.5 kΩ, RIADJ = 20 kΩ 900 920 940 mV 3.3 – 5.75 V VOUT VIN = 5.7 V, IO = 2.6 A, fSW = 500 kHz Output Dropout Voltage 3 VO(PWM) VIN = 7.3 V, IO = 2.6 A, fSW = 2 MHz VIN = 5.5 V, IO = 1 A, fSW = 500 kHz VIN = 6.8 V, IO = 1 A, fSW = 2 MHz A8653 A8652 ● 4.9 – – V ● 4.9 – – V ● 4.9 – – V ● 4.9 – – V ERROR AMPLIFIER Feedback Input Bias Current 1 IFB Open-Loop Voltage Gain AVOL Transconductance gmEA Output Current IEA –100 – –8 nA VCOMP = 1.2 V – 65 – dB 400 mV < VFB 550 750 950 0 V < VFB < 400 mV 275 375 475 – ±75 – VCOMP = 1.2 V µA/V µA INTERNAL MOSFET PARAMETERS High-Side MOSFET On-Resistance 3 SW Node Rising Slew Rate RDSON(HS) dV/dt TA = 25°C, IDS = 100 mA – 80 – mΩ 12 V < VIN < 16 V – 0.75 – V/ns –10 0 10 µA – 55 – mΩ SW Leakage 1 ISW(LEAK) VEN ≤ 0.4 V, VSW = 5 V, VIN = 12 V, TJ = 25°C Low-Side MOSFET On-Resistance 3 RDSON(LS) TA = 25°C, IDS = 100 mA Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ VIN ≤ 36 V; TA = 25ºC; • indicates specifications guaranteed –40°C ≤ TA = TJ ≤ 150°C (unless noted otherwise). Characteristics Symbol Test Conditions Min. Typ. Max. Unit RFSET = 261 kΩ – RFSET = 61.9 kΩ 375 100 – kHz 415 457 kHz OSCILLATOR PWM Switching Frequency fSW RFSET = 10.5 kΩ – 2000 – kHz PWM Frequency Dithering fDITHER No dithering with FSET synchronization – ±13 – % Minimum Controllable On-Time tON(MIN) VIN = 12 V, IOUT = 1 A – 95 135 ns Minimum Switch Off-Time tOFF(MIN) VIN = 12 V, IOUT = 1 A – 100 135 ns FSET SYNCHRONIZATION TIMING Synchronization Frequency Range fSW_MULT 100 – 2200 kHz Synchronization Input Off-Time tSYNC_OFF 0.2 – 1.3 µs tr(SYNC) – 10 15 ns tf(SYNC) – 10 15 ns Synchronization Input Rise Time3 Synchronization Input Fall Time3 Synchronization Rising Threshold VSYNC(HI) VSYNC rising Synchronization Falling Threshold VSYNC(LO) VSYNC falling – – 2 V 0.5 – 0.7 V 3.3 4 4.62 A CURRENT LOOP Peak Inductor (Pulse-by-Pulse) Current Limit Load-Side Current Limit COMP to SW Current Gain IPK_LIM(MINON) tON = tON(MIN) IPK_LIM(MINOFF) tON = 1/fSW – tOFF(MIN), No Sync IOUT_LIM RIADJ = 20 kΩ, RSEN = 20 mΩ, VOUT = 5 V gmPOWER A8653 A8652 ● 1.5 1.8 2.1 A A8653 ● 2.4 3.2 4 A A8652 ● 0.9 1 1.5 A A8653 2.5 3 3.3 A A8652 1 1.2 1.4 A A8653 – 6.3 – A/V A8652 – 3.2 – A/V – 0.056 – A/µs A8653 0.09 0.24 0.43 A/µs RFSET = 261 kΩ, 100 kHz RFSET = 61.9 kΩ, 415 kHz Slope Compensation SE ● RFSET = 10.5 kΩ, 2 MHz – 1.3 – A/µs RFSET = 261 kΩ, 100 kHz – 0.035 – A/µs 0.07 0.15 0.23 A/µs – 0.8 – A/µs RFSET = 61.9 kΩ, 415 kHz RFSET = 10.5 kΩ, 2 MHz A8652 Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ VIN ≤ 36 V; TA = 25ºC; • indicates specifications guaranteed –40°C ≤ TA = TJ ≤ 150°C (unless noted otherwise). Characteristics Symbol Test Conditions Min. Typ. Max. Unit – 200 275 mV – 3.3 – V –30 –20 –10 µA 1 2.2 5 µA SOFT-START SS FAULT/HICCUP Reset Voltage VSS(RST) SS Maximum Charge Voltage VSS(MAX) SS Startup (Source) Current 1 VSS falling due to RSS(FLT) ISS(SU) HICCUP = FAULT = 0 SS Hiccup (Sink) Current 1 ISS(HIC) HICCUP = 1 SS Pull-Down Resistance RSS(FLT) FAULT = 1 or EN = 0 – 2 – kΩ 0 V < VFB < 200 mV – fSW/4 – – 200 mV < VFB < 400 mV – fSW/2 – – 400 mV < VFB – fSW – – SS Switching Frequency fSS HICCUP MODE Hiccup OCP Enable Threshold VHIC(EN) VSS rising – 2.3 – V Hiccup, OCP Count OCPLIM VSS > 2.3 V, OCP pulses – 240 – counts BOOTUV – 64 – counts BOOTOPEN – 7 – counts – – 0.4 V Hiccup, BOOT Shorted Count Hiccup, BOOT Open Count POWER OK (POK) OUTPUT POK Output Voltage POK Leakage VPOK IPOK = 4 mA IPOK(LEAK) VPOK = 5 V ● – – 5 µA POK UV Threshold VPOK(UV) VFB falling ● 715 740 760 mV POK UV Hysteresis VPOK(UV,HYS) 1 POK OV Threshold POK OV Hysteresis ISEN+ OV Threshold ISEN+ OV Hysteresis POK Delay VPOK(OV) – 10 – mV VFB rising, VGADJ = 0 V 840 880 920 mV VFB rising, VISEN+ – VISEN– = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ 865 905 950 mV VFB rising, VISEN+ – VISEN– = 55 mV, VOUT = 5 V, RGADJ = 7.5 kΩ, RIADJ = 20 kΩ – 1 – V – 10 – mV ISEN+ rising, VGADJ = 0 V 5.4 5.65 6 V ISEN+ rising, VISEN+ – VISEN– = 25 mV, VOUT = 5 V, RGADJ = 20 kΩ, RIADJ = 20 kΩ 5.6 5.8 6.1 V ISEN+ rising, VISEN+ – VISEN– = 55 mV, VOUT = 5 V, RGADJ = 7.5 kΩ, RIADJ = 20 kΩ – 6.45 – V – 60 – mV VPOK(OV,HYS) VISEN(OV) VISEN(OV,HYS) td(POK) VFB rising only – 7 – PWM cycles 155 170 185 ºC – 20 – ºC THERMAL PROTECTION TSD Rising Threshold TSD Hysteresis 3 TSD TSDHYS PWM stops immediately and COMP is pulled low and SS is reset Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ VIN ≤ 36 V; TA = 25ºC; • indicates specifications guaranteed –40°C ≤ TA = TJ ≤ 150°C (unless noted otherwise). Characteristics Symbol Test Conditions Min. Typ. Max. Unit EN INPUT THRESHOLDS EN High Threshold VEN(H) EN rising – 1.41 2 V EN Low Threshold VEN(L) EN falling 0.7 1.36 – V EN Delay td(EN) EN transitioning low, VOUT < 25% – 60 – PWM cycles EN = 5 V – 500 – nA EN Input Bias Current 1 IEN_BIAS 1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin or node. 2 Thermally limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow. 3 Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation 815 4.05 810 4.00 3.95 805 IPK_LIM(MINON) (A) Reference Voltage, VREF (mV) TYPICAL PERFORMANCE CHARACTERISTICS 800 3.90 3.85 795 3.80 790 3.75 3.70 -50 785 -50 -25 0 25 50 75 100 125 150 175 -25 0 25 50 75 100 125 150 175 Temperature (ºC) Temperature (ºC) Pulse-by-Pulse Current Limit at tON(MIN) (IPK_LIM(MINON)) versus Temperature Reference Voltage versus Temperature 3.50 1.6 EN Rising Threshold EN Falling Threshold 3.25 1.4 START, UVLOSTART EN Thresholds (V) VIN UVLO Thresholds (V) 1.5 STOP, UVLOSTART 3.00 2.75 1.3 1.2 1.1 1.0 2.50 0.9 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Temperature (ºC) VIN UVLO START and STOP Thresholds versus Temperature 75 100 125 150 175 EN Rising and Falling Thresholds versus Temperature 8.3 925 8.2 900 8.1 875 8.0 850 825 POK Overvoltage 800 POK Undervoltage POK Delay (µs) POK OV & UV Thresholds at FB (mV) 50 Temperature (ºC) 7.9 7.8 7.7 7.6 775 7.5 750 7.4 725 7.3 7.2 700 -50 -25 0 25 50 75 Temperature (ºC) 100 125 150 175 POK Overvoltage and Undervoltage Thresholds at FB versus Temperature (POK OV test with VGADJ = 0 V) -50 -25 0 25 50 75 100 125 150 175 Temperature (ºC) POK Delay Time versus Temperature Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation 6.00 2.5 5.95 5.5 Input Quiescent Current (mA) ISEN+ OV Thresholds (V) 5.90 5.85 5.80 5.75 5.70 5.65 5.60 5.0 4.5 4.0 3.5 5.55 5.50 3.0 -50 0 -25 25 75 50 125 100 150 175 -50 0 -25 25 100 125 94 4.00 92 3.50 90 Efficiency (%) 96 4.50 3.00 2.50 2.00 88 86 84 VIN = 8 V 82 1.50 VIN = 12 V 80 1.00 VOUT 0.50 78 VLOAD VIN = 16 V 0 0.5 1.5 1.0 Load (A) 0.00 3.0 3.5 4.5 4.0 175 Quiescent Current IQ versus Temperature 5.00 2.5 150 Temperature (ºC) ISEN+ Overvoltage Thresholds versus Temperature (test with VGADJ = 0 V) Voltage (V) 75 50 Temperature (ºC) 5.0 5.5 6.0 2.0 2.5 3.0 Efficiency versus Output Current (Typical Design A in Table 3) VIN (V) Low VIN Dropout Operation at 5 Ω Load 5.2 V 5.2 V VOUT VOUT 5.1 V 5.1 V VLOAD 5.0 V 4.9 V 4.9 V 25 mA/µs 1 A/div VLOAD 5.0 V 25 mA/µs 1 A/div IOUT IOUT C4 C2 100 µs/div 100 µs/div Transient Response 0 to 1 A Load Step Transient Response 1 to 2 A Load Step (Typical Design A in Table 3) (Typical Design A in Table 3) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation FUNCTIONAL DESCRIPTION Overview The A8652/53 is a synchronous PWM buck regulator that integrates low RDS(on) high-side and low-side N-channel MOSFETs. It is designed to remain operational when input voltage falls as low as 2.6 V. The A8652/53 employs peak current mode control to provide superior line and load regulation, pulse-by-pulse current limit, fast transient response and simple compensation. The A8652/53 incorporates a Cable Drop Compensation (Remote Load Regulation) function in its current mode control architecture to adjust the output voltage according to the load current, offsetting the voltage drop introduced by the wiring harness. The reference voltage in the feedback loop is adjusted relative to the voltage across the sensing resistor at the load side. When the load current increases, it causes the reference voltage at the error amplifier to increase and the output voltage to follow. The gain of the voltage correction is configurable using the GADJ and IADJ pins. Such features provide flexibility in setting the amount of output voltage correction and the load current limit. The features of the A8652/53 include Remote Load Regulation, an internal precision reference, an adjustable switching frequency, a transconductance error amplifier, an enable input, integrated top and bottom switching MOSFETs, adjustable softstart time, pre-bias startup, and a Power OK output. Protection features of A8652/53 include VIN undervoltage lockout, pulse-bypulse overcurrent protection, BOOT overvoltage and undervoltage protection, hiccup mode short-circuit protection, dynamic overvoltage protection, and thermal shutdown. In addition, the A8652/53 provides open-circuit, adjacent pin short-circuit, and pin-to-ground short-circuit protection. Reference Voltage The A8652/53 incorporates an internal precision reference that allows output voltages as low as 0.8 V. The accuracy of the internal reference is ±1% from –40°C to 125°C and ±1.5% across from –40°C to 150°C when the Remote Load Regulation is disabled. The output voltage of the regulator is programmed with a resistor divider between VOUT and the FB pin of the A8652/53. Oscillator/Switching Frequency and Synchronization The PWM switching frequency of the A8652/53 is adjustable from 100 kHz to 2.2 MHz and has an accuracy of about ±10% over the operating temperature range. Connecting a resistor from the FSET/SYNC pin to GND, as shown in the Applications Schematic, sets the switching frequency. An FSET resistor with ±1% tolerance is recommended. A graph of switching frequency versus FSET resistor value is shown in the Component Selection section of this datasheet. The A8652/53 will suspend operation if the FSET pin is shorted to GND or left open. FSET/SYNC pin also can be used as a synchronization input that accepts an external clock to switch the A8652/53 from 100 kHz to 2.2 MHz and scales the slope compensation according to the synchronization frequency. When being used as a synchronization input, the applied clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics shown in this datasheet. Remote Load Regulation Control and Transconductance Error Amplifier The Remote Load Regulation control in the A8652/53 provides improved load regulation at the remote load by increasing the voltage reference of the error amplifier to correct for the voltage drop introduced by wiring harness to the load. The amount of voltage correction is user-programmable with external configuration resistors, allowing the A8652/53 to be applied to wiring harnesses that have up to 750 mV IR drops at full load. The Remote Load Regulation controller has a variety of protection features, including a load-side current limit, a maximum regulation voltage, and protection in the event of open pin or shorted pin conditions. The Remote Load Regulation voltage correction and protection features interface with the error amplifier, which is a four-terminal input device with three positive inputs and one negative input, as shown in Figure 1. The negative input is simply connected to the FB pin and is used to sense the feedback voltage for regulation. The error amplifier performs an “analog OR” selection between its positive inputs, operating according to the positive input with the lowest potential. The three positive inputs are used for soft-start, steady-state regulation, and the 15% maximum regulation voltage. The error amplifier regulates to the soft-start pin voltage minus 400 mV during startup, the sum of A8652/53 internal reference (VREF) and the Remote Load Regulation correction (REF_ADJ) during normal operation, or the 920 mV maximum. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation The gain of the current sense to the REF_ADJ (GADJ) signal is set by the ratio of resistance to GND on the GADJ pin and the IADJ pin in conjunction with Rsen: 400 mV SS GADJ = Error Amp COMP 920 mV REF_ADJ VREF 800 mV REF_ADJ Rsen × RIADJ = RGADJ IOUT (1) This allows the user to calibrate the voltage correction to the IR drop of the wiring harness, as shown in Figure 3. This calibration results in improved load regulation at the end of the wiring harness. Larger Rsen × RIADJ / RGADJ VOUT FB 5.5 V Figure 1: A8652/53 Error Amplifier 5.0 V Current Sense Amp ISEN+ VREF 800 mV Smaller Rsen × RIADJ / RGADJ 920 mV Error Amp ISEN- REF_ADJ Σ Σ IOUT Gain Adj GADJ 0A 1.0 A Figure 3: Voltage Correction Gain Adjustment RGADJ IADJ RIADJ Figure 2: Remote Load Regulation Control The amount of the voltage correction for the wiring harness is generated by the Remote Load Regulation control circuit and fed to the error amplifier via the REF_ADJ signal, as shown in Figures 1 and 2. The Remote Load Regulation controller generates REF_ADJ according to the load current sensed by ISEN+ and ISEN– and the gain set by the configuration resistors. The current sense resistor (Rsen) is connected on the load side between the regulator output capacitor and the load terminal and can have a value between 20 and 50 mΩ. To configure the voltage correction gain, the load-side current limit (IOUT_LIM) must first be set by the following equation (also referring to Table 1): RIADJ = 1200 IOUT_LIM × Rsen (2) The voltage correction gain is based on RWIRE, which is the sum of the wiring harness supply and return resistive paths as detailed in the typical application diagram. Given the gain of the FB pin voltage divider (AFB = VOUT/VFB), RWIRE and RIADJ the desired voltage correction gain is set by the following equation (referring to Figure 4): RGADJ = Rsen × AFB × RIADJ RWIRE Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com (3) 13 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation For example, for a 5 V application with a 20 mΩ current sense resistor and a 3 A load side current limit the IADJ configuration resistor would be 20 kΩ. To correct for a 125 mV wire harness drop at 1 A (RWIRE =125 mΩ) given RIADJ = 20 kΩ, the GADJ configuration resistor should be 20 kΩ. Rsen = 50 mΩ, RIADJ = 20 kΩ (1.2 A) RWIRE (mΩ) Table 1: RIADJ Resistor Selection vs. IOUT_LIM 800 700 Rsen = 50 mΩ, RIADJ = 23.7 kΩ (1.0 A) 600 Rsen = 50 mΩ, RIADJ = 30.1 kΩ (0.8 A) 500 400 RIADJ (kΩ) Rsen = 20 mΩ Rsen = 50 mΩ 15.8 3.80 1.52 16.9 3.55 1.42 200 100 3.45 1.38 3.37 1.35 18.2 3.30 1.32 18.7 3.21 1.28 19.1 3.14 1.26 19.6 3.06 1.22 20.0 3.00 1.20 20.5 2.93 1.17 21.0 2.86 1.14 21.5 2.79 1.12 22.1 2.71 1.09 22.6 2.65 1.06 23.2 2.59 1.03 23.7 2.53 1.01 24.3 2.47 0.99 26.7 2.25 0.90 30.1 1.99 0.80 34.8 1.72 0.69 40.2 1.49 0.60 As will be discussed in further detail below, altering the GADJ resistance with an external voltage proportionally adjusts the voltage correction gain (Method 1, refer to Typical Application Diagram 2). On the other hand, altering the IADJ resistance with an external voltage proportionally adjusts the load-side current limit, and inversely proportionally adjusts the voltage correction gain (Method 2). 0 0 10 20 30 RGADJ (kΩ) 40 50 60 300 Rsen = 20 mΩ, RIADJ = 20 kΩ (3.0 A) Rsen = 20 mΩ, RIADJ = 23.7 kΩ (2.5 A) 250 Rsen = 20 mΩ, RIADJ = 30.1 kΩ (2.0 A) 200 RWIRE (mΩ) 17.4 17.8 300 150 100 50 0 0 10 20 30 RGADJ (kΩ) 40 50 60 Figure 4: RGADJ Selection vs RWIRE for Given Rsen, RIADJ This can be very useful, for instance when one “universal” design is created for multiple platforms, where the expected wiring resistance can vary widely. The design can use this method in conjunction with the system controller such that the degree of voltage correction can be set via software. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation The minimum and maximum voltage correction can be adjusted with the ratio of RGADJ and RG_E for a given controlling voltage (VG) range. 1.0 V A8652/53 Similarly, as shown in Figure 7, Method 2 can inversely proportionally adjust the voltage correction gain for a fixed GADJ resistance, at the same time proportionally adjusts the load side current limit (IOUT_LIM) by applying the control voltage (VI) to the IADJ pin. The equivalent resistance RIADJ at pin IADJ is: ig 1 GADJ VG RI_eqv = RG_E (R1 IADJ RGADJ Figure 5: Dynamic Voltage Correction Adjustment at Pin GADJ Figure 5 above illustrates how to adjust the amount of voltage correction by controlling VG. The equivalent resistance RG_eqv at pin GADJ with respect to GND now becomes: – ) VI – 1 RI_E (6) Thus the voltage correction gain can be kept the same by applying a separate control voltage to the GADJ pin to keep the GADJ and IADJ resistor ratio the same if only load-side current limit needs to be adjusted. 1.0 V A8652/53 1 RG_eqv = (R 1 GADJ – ) VG – 1 RG_E (4) ia The voltage correction gain (GADJ) then varies linearly with the applied VG for given RGADJ and RG_E. Normalizing this gain to the case with only RGADJ connecting to pin GADJ results in: Gnorm = 1 + RGADJ R – GADJ VG RG_E RG_E IADJ RI_E (5) VI RIADJ Gnorm Figure 7: Simultaneous Voltage Correction and LoadSide Current Limit Adjustment at Pin IADJ 1 + RGADJ / RG_E If a fixed load-side current limit is desired it is simpler to use GADJ pin to dynamically control the amount of voltage correction because of linear control and only altering the voltage correction gain. 1 The GADJ and IADJ pins are designed for a resistance range of 10 to 34 kΩ, and therefore the controlling voltage VG and VI must be limited as follows: 0 0 1 VG(V) 10 kΩ < RG_eqv < 34 kΩ (7) 10 kΩ < RI_eqv < 34 kΩ (8) and Figure 6: Normalized Gain Gnorm vs. VG Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation In addition to the voltage correction circuitry, Figure 2 also details the load-side current limit (IOUT_LIM), which is configured independently by the resistance to GND on the IADJ pin. As shown by Figure 8 and 9, when the load current exceeds IOUT_LIM, POK is pulled low to flag the condition, and the output voltage is decreased at the same rate as the voltage correction (set by Rsen, RGADJ and RIADJ) to protect against unstable behavior. Figure 8 and 9 also details the operation of peak inductor current limit (IPK_LIM), which monitors the inductor current and will enter into hiccup mode after 240 counts of exceeding IPK_LIM for robust protection and against the output voltage shorted to GND. 2.6 V – UVLOfall 5.75 V VOUT 5.0 V 5.5 V IPK_LIM 4.0 A IOUT_LIM 2.5 A 2.0 A IOUT 0 1A 1.5 A SS 12 V VIN 12 V VIN 2.6 V – UVLOfall VOUT 5.0 V 5.75 V POK IPK_LIM 4.0 A Figure 9: Excessive Voltage Correction Gain IOUT_LIM The Remote Load Regulation controller is also robust against pin faults, such as adjacent pins shorting, shorting pins to GND, or pin open faults. When a pin fault is detected, either the IADJ or GADJ pin, the A8652/53 will default to the 800 mV reference, not applying any voltage correction to the output voltage. Given this, the GADJ pin can be connected to GND to disable the Remote Load Regulation function. 3.0 A IOUT 0 1A SS POK t 5.25 V t Figure 8: POK and Load-Side Current Limit Timing In addition to current protection, the A8652/53 also includes a 115% (5.75 V) regulation voltage limit on the error amplifier. This protection feature prevents the excessive output voltages during fault conditions, and is therefore set above the operating range of the Remote Load Regulation. However, if the voltage correction gain is too high, the 115% voltage limit will impede the Remote Load Regulation operation, as shown in Figure 9. The VOUT waveform shows the operation point of the Remote Load Regulation controller set by REF_ADJ, but as illustrated, the 115% voltage regulation limit at the error amplifier clips the output voltage to 5.75 V. Compensation Components To stabilize the regulator, a series RC compensation network (RZ and CZ) must be connected from the error amplifier output (COMP pin) to GND as shown in the applications schematic. In most instances, an additional low-value capacitor (CP) should be connected in parallel with the RZ-CZ compensation network to reduce the loop gain at very high frequencies. However, if the CP capacitor is too large, the phase margin of the converter may be reduced. How to calculate RZ, CZ and CP is covered in the Component Selection section of this datasheet. When selecting the compensation components, the load decoupling capacitance and the wiring resistance must be taken into consideration. If a fault occurs or the regulator is disabled, the COMP pin is pulled to GND via the approximately 1 kΩ internal resistor and PWM switching is inhibited. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Slope Compensation Power MOSFETs The A8652/53 incorporates internal slope compensation to allow PWM duty cycles above 50% for a wide range of input/output voltages, switching frequencies, and inductor values. As shown in the functional block diagram, the slope compensation signal is added to the sum of the current sense and PWM Ramp Offset. The amount of slope compensation is scaled with the switching frequency when programming the frequency with a resistor or with an external clock. The A8652/53 includes an 80 mΩ, high-side N-channel MOSFET capable of delivering up to 4 A typical. The A8652/53 also includes a 55 mΩ, low-side N-channel MOSFET to provide synchronous rectification. The value of the output inductor should be chosen such that slope compensation rate SE is between 0.5× and 1× the falling slope of the inductor current (SF). Pulse-Width Modulation (PWM) Mode Current Sense Amplifier The A8652/53 incorporates a high-bandwidth current sense amplifier to monitor the current through the top MOSFET. This current signal is used to regulate the peak current when the top MOSFET is turned on. The current signal is also used by the protection circuitry for the pulse-by-pulse current limit (IPK_LIM) and hiccup mode short-circuit protection. Low Dropout Operation and Undervoltage Lockout The Undervoltage Lockout behavior is described in the following Protection Features section. The A8652/53 is designed to allow operation when input voltage drops as low as 2.6 V, which is the UVLO STOP threshold. When the input voltage falls towards the nominal output voltage, the high-side switch can remain on for maximum on-time to keep regulating the output. This is accomplished by decreasing the fSW switching frequency. In this way, the dropout from the input to output voltage is minimized. Sleep Mode with Enable input The A8652/53 provides a shutdown function via the EN pin. When this pin is low, the A8652/53 is shut down and the A8652/53 will enter a “sleep mode” where the internal control circuits will be shut off and draw less current from VIN. If EN goes high, the A8652/53 will turn on and provided there are no fault conditions, soft-start will be initiated and VOUT will ramp to its final voltage in a time set by the soft-start capacitor (CSS). To automatically enable the A8652/53, the EN pin may be connected directly to VIN. When the A8652/53 is disabled via the EN input being low or a Fault condition, the A8652/53 output stage is tri-stated by turning off both the upper and lower MOSFETs. The A8652/53 employs fixed-frequency, peak current mode control to provide excellent load and line regulation, fast transient response, and simple compensation. A high-speed comparator and control logic is included in A8652/53. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation signal, and a DC PWM Ramp offset voltage (VPWM(OFFSET)). At the beginning of each PWM cycle, the CLK signal sets the PWM flip-flop, the bottom MOSFET is turned off, the top MOSFET is turned on, and the inductor current increases. When the voltage at the non-inverting of PWM comparator rises above the error amplifier output COMP, the PWM flip-flop is reset and the top MOSFET is turned off, the bottom MOSFET is turned on and the inductor current decreases. The PWM flip-flop is reset-dominant, so the error amplifier may override the CLK signal in certain situations. BOOT Regulator The A8652/53 includes a regulator to charge its boot capacitor. The voltage across the boot capacitor is typically 5 V. If the boot capacitor is missing, the A8652/53 will detect a boot overvoltage. Similarly, if the boot capacitor is shorted, the A8652/53 will detect a boot undervoltage. Also, the boot regulator has a current limit to protect itself during a short-circuit condition. Soft-Start (Startup) and Inrush Current Control The soft-start function controls the inrush current at startup. The soft-start pin, SS, is connected to GND via a capacitor. When the A8652/53 is enabled and all faults are cleared, the soft-start pin will source the charging current ISS(SU), and the voltage on the Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation soft-start capacitor, CSS, will ramp upward from 0 V. When the voltage at the soft-start pin exceeds the Soft-Start COMP Release Threshold (VSS(RELEASE), typically 400 mV) the error amplifier will ramp up its output voltage above the PWM Ramp Offset. At that instant, the top and bottom MOSFETs will begin switching. There is a small delay (td(SS)) between the moments of EN pin transitioning high and the soft-start voltage reaching 400mV to initiate PWM switching. Once the A8652/53 begins PWM switching, the error amplifier will regulate the voltage at the FB pin to the soft-start pin voltage minus approximately 400 mV. During the active portion of softstart, the voltage at the SS pin will rise from 400 mV to 1.2 V (a difference of 800 mV), the voltage at the FB pin will rise from 0 V to 800 mV, and the regulator output voltage will rise from 0 V to the setpoint determined by the feedback resistor divider. During startup, the PWM switching frequency is reduced to 25% of fSW while VFB is below 200 mV. If VFB is above 200 mV but below 400 mV, the switching frequency is 50% of fSW. At the same time, the transconductance of the error amplifier, gmEA, is reduced to 1/2 of nominal value when VFB is below 400 mV. When VFB is above 400 mV, the switching frequency will be fSW and the error amplifier gain will be the nominal value. The reduced switching frequencies and error amplifier gain are necessary to help improve output regulation and stability when VOUT is at very low voltage. When VOUT is very low, the PWM control loop requires on-time near the minimum controllable on-time and extra low duty cycles that are not possible at the nominal switching frequency. When the voltage at the soft-start pin reaches approximately 1.2 V, the error amplifier will “switch over” and begin regulating the voltage at the FB pin to the A8652/53 adjusted reference voltage. The voltage at the soft-start pin will continue to rise to the internal LDO regulator output voltage. If the A8652/53 is disabled or a fault occurs, the internal fault latch is set and the capacitor at the SS pin is discharged to ground very quickly through a 2 kΩ pull-down resistor. The A8652/53 will clear the internal fault latch when the voltage at the SS pin decays to approximately 200 mV. However, if the A8652/53 enters hiccup mode, the capacitor at the SS pin is slowly discharged through a current sink, ISS(HIC). Therefore, the soft-start capacitor CSS not only controls the startup time but also the time between soft-start attempts in hiccup mode. Pre-Biased Startup If the output of the buck regulator is pre-biased at certain output voltage level, the A8652/53 will modify the normal startup routine to prevent discharging the output capacitors. As described in the Soft-Start (Startup) and Inrush Current Control section, the error amplifier usually becomes active when the voltage at the soft-start pin exceeds 400 mV. If the output is pre-biased, the voltage at the FB pin will be non-zero. The A8652/53 will not start switching until the voltage at SS pin rises to approximately VFB + 400 mV. From then on, the error amplifier becomes active, the voltage at the COMP pin rises, PWM switching starts, and VOUT will ramp upward from the pre-bias level. Power OK (POK) Output The Power OK (POK) output is an open-drain output, so an external pull-up resistor must be connected. POK remains high when the voltage at the FB pin is within regulation and the loadside current limit Iout_LIM is not triggered. The POK output is pulled low under the conditions below: 1. VFB(RISING) < 92.5% of the reference voltage VREF 2. VFB(RISING) is larger than the sum of the adjusted reference voltage (i.e. VREF + VREF_ADJ or 920 mV, whichever is lower) and 80 mV 3. Load current exceeds the load-side current limit Iout_LIM 4. EN is low for more than 32 PWM cycles 5. VIN UVLO event occurs 6. Thermal shutdown event occurs Once the load-side current limit is triggered, POK will go low even if the output voltage has not yet dropped due to the current limit. If the A8652/53 is running and EN is kept low for more than 32 PWM cycles, POK will fall low and remain low only as long as the internal circuitry is able to enhance the open-drain output device. Once VIN fully collapses, POK will return to the high-impedance state. Hysteresis is included in POK comparators to prevent chattering due to the ripple effects on comparators’ input terminals. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation PROTECTION FEATURES The A8652/53 was designed to satisfy the most demanding automotive and nonautomotive applications. In this section, a description of each protection feature is described and Table 2 summarizes the protections and their operation. Undervoltage Lockout Protection (UVLO) An Undervoltage Lockout (UVLO) comparator in the A8652/53 monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the START threshold (VUVLO(START), VIN rising) or the STOP threshold (VUVLO(STOP), VIN falling). The UVLO comparator incorporates some hysteresis, VUVLO(HYS), to help reduce ON/OFF cycling of the regulator due to the resistive or inductive drops in the VIN path during heavy loading or during startup. Pulse-by-Pulse Overcurrent Protection (OCP) The A8652/53 monitors the current in the upper MOSFET, and if this current exceeds the pulse-by-pulse overcurrent threshold (IPK_LIM), then the upper MOSFET is turned off. Normal PWM operation resumes on the next clock pulse from the oscillator. The A8652/53 includes leading-edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the upper MOSFET is turned on. 4.4 4.2 4.0 3.8 ILIM (A) Figure 10 shows the typical and worst case pulse-by-pulse current limits versus duty cycles at 2 MHz, 550 kHz, and 100 kHz. The exact current the buck regulators can support is heavily dependent on duty cycle (VIN, VOUT), ambient temperature, thermal resistance of the PCB, airflow, component selection, and nearby heat sources. Overcurrent Protection (OCP) and Hiccup Mode An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when the load current is too high. When the voltage at the SS pin is below the Hiccup OCP Threshold, the hiccup mode counter is disabled. Two conditions must be met for the OCP counter to be enabled and begin counting: 1. VSS > VHIC(EN) (2.3 V) and 2. VCOMP clamped at its maximum voltage (OCL = 1) As long as these two conditions are met, the OCP counter remains enabled and will count pulses from the overcurrent comparator. If the COMP voltage decreases (OCL = 0) the OCP counter is cleared. If the OCP counter reaches OCPLIM counts (240), a hiccup latch is set and the COMP pin is quickly pulled down by a relatively low resistance (1 kΩ). 4.6 3.6 3.4 3.2 3.0 MAX_550 kHz TYP_550 kHz MIN_550 kHz MAX_100 kHz TYP_100 kHz MIN_100 kHz MAX_2 MHz TYP_2 MHz MIN_2 MHZ 2.8 2.6 2.4 2.2 Because of the addition of the slope compensation ramp to the inductor current, the A8652/53 can deliver more current at lower duty cycles than at higher duty cycles to activate pulse-by-pulse overcurrent protection. Also the slope compensation is not a perfectly linear function of switching frequency, so the current limit at lower switching frequency is larger compared with the limit at higher switching frequency for a given duty cycle. 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Duty Cycle (%) Figure 10: Pulse-by-Pulse Current Limit vs. Duty Cycle at 100 kHz (long dashed lines), 550 kHz (solid lines) and 2 MHz (short dashed lines) The hiccup latch also enables a small current sink connected to the SS pin (ISS(HIC)). This causes the voltage at the soft start pin to slowly ramp downward. When the voltage at the soft-start pin decays to a low-enough level (VSS(RST), 200 mVTYP), the hiccup latch is cleared and the small current sink turned off. At that instant, the SS pin will begin to source current (ISS(SU)) and the voltage at the SS pin will ramp upward. This marks the beginning of a new, normal soft-start cycle as described earlier. When the voltage at the soft-start pin exceeds the error amp voltage by approximately 400 mV, the error amp will force the voltage at the COMP pin to quickly slew upward and PWM switching will resume. If the short circuit at the regulator’s output remains, Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation another hiccup cycle will occur. Hiccups will repeat until the short circuit is removed or the converter is disabled. If the short circuit is removed, the A8652/53 will soft-start normally and the output voltage will automatically recover to the desired level. Thus Hiccup mode is a very effective protection for the overload condition. It can avoid false trigger for a short-term overload. On the other hand, for the extended overload, the average power dissipation during Hiccup operation is very low to keep the controller cool and enhance the reliability. Note that OCP is the only fault that results in Hiccup mode being ignored while VSS < 2.3 V. BOOT Capacitor Protection The A8652/53 monitors the voltage across the BOOT capacitor to detect if the capacitor is missing or short-circuited. If the BOOT capacitor is missing, the regulator will enter Hiccup mode after 7 PWM cycles. If the BOOT capacitor is short-circuited, the regulator will enter Hiccup mode after 64 PWM cycles. For a BOOT fault, Hiccup mode will operate virtually the same as described previously for an output short-circuit fault (OCP), with SS ramping up and down as a timer to initiate repeated soft-start attempts. BOOT faults are nonlatched condition, so the A8652/53 will automatically recover when the fault is corrected. Dynamic Overvoltage Protection (OVP) In addition to the error amp regulation voltage clamp (VEA(CLAMP)) at 115%, the A8652/53 includes a dynamic overvoltage protection feature where the overvoltage threshold changes with the correction voltage. As shown in Figure 11 below, the A8652/53 also includes an overvoltage comparator that monitors the FB pin and the sum of the adjusted reference voltage (i.e. VREF + VREF_ADJ or 920 mV, whichever is lower) and 80 mV. In this way, the overvoltage threshold will dynamically change with the amount of the correction voltage and the threshold is always 0.5 V above the output voltage. For example, OVP threshold is 5.5 V when VOUT = 5 V at IOUT = 0 A; the OVP threshold will be 5.75 V when VOUT = 5.25 V at IOUT = 1 A; if VOUT = 5.75 V at certain load, the OVP threshold will become 6.25 V. When the Remote Load Regulation function is disabled due to some reason (e.g., IADJ or GADJ pin fault or general non- FB OV 5 µs 80 mV 800 mV VREF 920 mV REF_ADJ Figure 11: Dynamic Overvoltage Protection USB buck application), the OVP threshold will be 5.5 V; when the output voltage reaches the 115% regulation limit, the OVP threshold will reach the maximum value of 6.25 V. When the voltage at the FB pin exceeds the overvoltage threshold (VPOK(OV)), A8652/53 will stop PWM switching, i.e. both high and side switches will be turned off, and POK will be pulled low. In most cases, the error amplifier will be able to maintain regulation since the synchronous output stage has excellent sink and source capability. However the error amplifier and its regulation voltage clamp are not effective when the FB pin is disconnected or when the output is shorted to the input supply. When the FB pin is disconnected from the feedback resistor divider, a tiny internal current source will force the voltage at the FB pin to rise above VPOK(OV) and disable the regulator, preventing the load from being significantly overvoltage. If a higher external voltage is accidently shorted to the A8652/53’s output, VFB will rise above the overvoltage threshold, triggering an OVP event and thus protecting the low-side switch. In either case, if the conditions causing the overvoltage are corrected, the regulator will automatically recover. To provide additional protection when the battery is shorted to the load terminal, a 40 V Schottky diode (D) can be inserted after sensing resistor Rsen to block the high voltage entering into IC, and a Zener diode is placed at FB pin, as shown in Figure 12. The test result was shown in Figure 12b when Battery = 36 V was shorted to VOUT. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Rsen 20 mΩ LO 10 µH CO 2 × 22 µF VOUT D RWIRE/2 62.5 mΩ RWIRE/2 62.5 mΩ VLOAD CLOAD 100 µF ISEN+ ISENRFB1 FB 5.1 V RFB2 Figure 12a: Protection Circuitry for Load Short-to-Battery FB VOUT Thermal Shutdown (TSD) The A8652/53 monitors its junction temperature and will stop PWM switching and pull POK low if it becomes too hot. Also, to prepare for a restart, the SS and COMP pins will be pulled low until VSS < VSS(RST). TSD is a non-latched fault so the A8652/53 will automatically recover if the junction temperature decreases by approximately 20°C. Pin-to-Ground and Pin-to-Pin Short Protections The A8652/53 was designed to satisfy the most demanding automotive and nonautomotive applications. For example, the A8652/53 was carefully designed “up front” to withstand a short circuit to ground at each pin without suffering damage. In addition, care was taken when defining the A8652/53’s pinouts to optimize protection against pin-to-pin adjacent short-circuits. For example, logic pins and high-voltage pins were separated as much as possible. Inevitably, some low-voltage pins were located adjacent to high-voltage pins. In these instances, the low-voltage pins were designed to withstand increased voltages, with clamps and/or series input resistance, to prevent damage to the A8652/53. POK Figure 12b: Test Results when Battery = 36 V is Shorted to VOUT Ch1: VOUT (10 V/div); Ch2: VFB (2 V/div); Ch4: VPOK (5 V/div); 50 ms/div Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Table 2: Summary of A8652/53 Fault Modes and Operation During Fault Count, before Hiccup Dropout Foldback POK BOOT Charging LATCH RESET CCM according to COMP fSW/4 or fSW/2 based on VFB Depends on VOUT and ISEN Not affected No Auto, remove short CCM according to COMP CCM according to COMP Not affected Pulled Low immediately Not affected No Auto Pulled low only by hiccup Forced off Immediately Forced off Immediately Dropout Foldback Reset Depends on VOUT and ISEN Not affected No Auto, remove short Hiccup at the end of blankOn Pulled low only by hiccup Forced off Immediately One Shot Diode Emulation Dropout Foldback Reset Depends on VOUT and ISEN Not affected No (option avail able) Auto, remove short Die is too hot Pulled Low Immediately & latched until VSS < VSS(RST) Pulled Low Immediately & latched until VSS < VSS(RST) Forced off Immediately Forced off Immediately Dropout Foldback Reset Pulled Low Immediately Off No Auto, Cool Down Boot Capacitor Greater than 7V BOOT capacitor Open Hiccup, after 7 latched faults Pulled low by hiccup CCM according to COMP CCM according to COMP Dropout Foldback Disabled by Hiccup Depends on VOUT and ISEN Off for rest of period – – Boot Capacitor On Fault BOOT Capacitor Open Hiccup, after 7 latched faults Pulled low by hiccup CCM according to COMP CCM according to COMP Dropout Foldback Disabled by Hiccup Depends on VOUT and ISEN Off only during hiccup No Auto, replace capacitor Boot Capacitor Overcurrent BOOT to GND Short Not affected Not affected Not affected Pulsed at minOff Not affected Depends on VOUT and ISEN Off until fault clears – – Boot Capacitor Low Voltage Normal Low VIN Operation Not affected Not affected Not affected Active during minOff period Not affected Depends on VOUT and ISEN On – – Boot Capacitor Undervoltage BOOT Capacitor Short Not affected Not affected Forced Off Immediately Active during minOff period Dropout Foldback Reset Depends on VOUT and ISEN On – – Low-Side Switch Undervoltage Low VIN Not affected Not affected Forced Off Immediately Forced Off Immediately Dropout Foldback Reset Depends on VOUT and ISEN Not affected – – VREG Undervoltage Low VIN Pulled Low Immediately & latched until VSS < VSS(RST) Pulled Low Immediately & latched until VSS < VSS(RST) Forced Off Immediately Forced Off Immediately Dropout Foldback Reset Pulled Low Immediately Off No Auto VIN Undervoltage Low VIN Pulled Low Immediately & latched until VSS < VSS(RST) Pulled Low Immediately & latched until VSS < VSS(RST) Forced Off Immediately One Shot Diode Emulation Dropout Foldback Reset Depends on VOUT and ISEN Off No Auto Fault Mode Fault Cases VSS Positive Overcurrent Protection 1. Excessive IOUT 2. VOUT Shorted to GND 3. SW Soft Short To GND Load-Side Current Limit Excessive IOUT Negative Overcurrent Protection SW Hard Short to GND VCOMP High-Side Switch Low-Side Switch Hiccup, after 240 faults of OCL Clamped to achieve ILIM, and pulled low only by hiccup CCM according to COMP Not affected Not affected 1. Excessive Negative IOUT 2. Inductor Short Hiccup, after 1 fault of LSOC SW to GND hard Short Thermal Shutdown Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Table 2: Summary of A8652/53 Fault Modes and Operation (continued) During Fault Count, before Hiccup Fault Mode Hiccup Delay (after fault count is reached) Hiccup Restart or Startup (after VSS returns to VSS(RST)) Fault Cases Hiccup Startup Hiccup FB Overvoltage 1. VOUT to VIN Short 2. FB pin Open ISENP Overvoltage 1. VOUT to VIN short 2. FB to GND short VSS VCOMP High-Side Switch Low-Side Switch Dropout Foldback POK BOOT Charging LATCH RESET – – Discharged with ISS(HIC) until VSS < VSS(RST) Pulled Low until VSS < VSS(RST) Forced Off at Start of Period One Shot Diode Emulation Dropout Foldback Reset Depends on VOUT and ISEN Not affected, (off only for boot capacitor faults) (sleep opt available) Charged with ISS(SU) Released from 0 V, then responds to VSS↑ CCM after VCOMP > 400 mV CCM after VCOMP > 400 mV (pulsed at minOff) Dropout Foldback Reset Depends on VOUT and ISEN Not affected – – Not affected Not affected Forced Off Immediately One Shot Diode Emulation Dropout Foldback Reset Pulled Low Immediately Off No Auto, VFB to normal range Not affected Not affected Forced Off Immediately One Shot Diode Emulation Dropout Foldback Reset Pulled Low Immediately Off No Auto, VFB to normal range FB Undervoltage Startup Not affected Not affected CCM according to COMP CCM according to COMP Not affected Pulled Low Immediately Not affected No Auto, VFB to normal range Feedback Less Than 400 mV Startup Not affected Not affected fSW/2 CCM according to COMP Not affected Pulled Low Not affected – – Feedback Less Than 200 mV Startup VOUT to GND Short Not affected Not affected fSW/4 CCM according to COMP fSW already at 1/4 Pulled Low Not affected – – Pulled Low Immediately & latched until VSS < VSS(RST) Pulled Low Immediately & latched until VSS < VSS(RST) Forced Off Immediately One Shot Diode Emulation Not affected Depends on VOUT and ISEN Off – – FSET Resistor Fault 1.FSET to GND short 2.FSET pulled high 3.Low R 4.High R GADJ or IADJ Resistor Fault ADJ to GND short ADJ pulled high Low R High R Not affected Not affected CCM according to COMP CCM according to COMP Not affected Depends on VOUT and ISEN Not affected – – SS shorted to VIN SS to VIN short Clamped to Zener voltage internally Not affected CCM according to COMP CCM according to COMP Not affected Depends on VOUT and ISEN Not affected – – SS shorted to GND SS to GND short At GND Loop response only CCM according to COMP CCM according to COMP Not affected Depends on VOUT and ISEN Not affected – – COMP shorted to GND COMP to GND short Not affected At GND CCM according to COMP CCM according to COMP Not affected Depends on VOUT and ISEN Not affected – – Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation DESIGN AND COMPONENT SELECTION Setting the Output Voltage The output voltage of the regulator is determined by connecting a resistor divider from the output node (VOUT) to the FB pin as shown in Figure 13. There are tradeoffs when choosing the value of the feedback resistors. If the series combination (RFB1 + RFB2) is too low, then the light load efficiency of the regulator will be reduced. To maximize the efficiency, it is best to choose higher values of resistors. On the other hand, if the parallel combination (RFB1//RFB2) is too high, then the regulator may be susceptible to noise coupling onto the FB pin. 1% resistors are recommended to maintain the output voltage accuracy. 1.8 × 10 3 1.6 × 10 3 1.4 × 10 3 1.2 × 103 1 × 10 3 800 600 400 CFB FB Pin Frequency (kHz) 2.0 × 103 200 VOUT 0 10 RFB1 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 RFSET (kΩ) RFB2 Figure 14: PWM Switching Frequency versus RFSET the FSET resistor, RFSET (x-axis). For a desired switching frequency (fSW), the FSET resistor can be calculated using equation 11, where fSW is in kHz and RFSET is in kΩ. Figure 13: Connecting a Feedback Divider to Set the Output Voltage The feedback resistors must satisfy the ratio shown in equation below to produce a desired output voltage, VOUT. VOUT RFB1 –1 RFB2 = 0.8 V RFSET = (9) A phase lead capacitor (CFB) can be connected in parallel with RFB1 to increase the phase and gain margins. It adds a zero and pole to the compensation network and boosts the loop phase at the crossover frequency. In general, CFB should be less than 25 pF. If CFB is too large, it will have no effect. If CFB is used, CFB can be calculated from equation 10: CFB = 1 2πRFB1fc (10) where fc is crossover frequency. PWM Switching Frequency (fSW, RFSET) The PWM switching frequency is set by connecting a resistor from the FSET pin to ground. Figure 14 is a graph showing the relationship between the typical switching frequency (y-axis) and 26000 – 2.2 fSW (11) When the PWM switching frequency is chosen, the designer should be aware of the minimum controllable on-time, tON(MIN), of the A8652/53. If the system’s required on-time is less than the minimum controllable on-time, pulse skipping will occur and the output voltage will have increased ripple or oscillations. The PWM switching frequency should be calculated using equation 12, where VOUT is the output voltage, tON(MIN) is the minimum controllable on-time of the A8652/53 (See EC table), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). fSW < VOUT tON(MIN) × VIN(MAX) (12) If the A8652/53 synchronization function is employed, the base switching frequency should be chosen such that pulse skipping will not occur at the maximum synchronized switching frequency according to equation 12 (i.e. 1.5 × fSW is less than the result from equation 12). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Output Inductor (LO) For a peak current mode regulator, it is common knowledge that without adequate slope compensation, the system will become unstable when the duty cycle is near or above 50%. However, the slope compensation in the A8652/53 is a fixed value (SE). Therefore, it is important to calculate an inductor value so the falling slope of the inductor current (SF) will work well with the A8652/53 slope compensation. Equations 13 and 14 can be used to calculate a range of values for the output inductor based on the well-known approach of providing slope compensation that matches 50% to 100% of the down slope of the inductor current. In equation 13, use the slope compensation (SE), which is a function of switching frequency according to equation 14. VOUT VOUT ≤ L O ≤ 2 × SE SE 2 SE = 0.0445 × fSW + 0.5612 × fSW 2 SE = 0.0237 × fSW + 0.3529 × fSW (13) (14a for A8653) (14b for A8652) SE is in A/µs, fSW is in MHz, and LO will be in µH. If equations 13 or 14 yield an inductor value that is not a standard value, then the next highest available value should be used. The final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. The saturation current of the inductor should be higher than the peak current capability of the A8652/53. Ideally, for output shortcircuit conditions, the inductor should not saturate at the highest pulse-by-pulse current limit at minimum duty cycle. This may be too costly. At the very least, the inductor should not saturate at the peak operating current according to equation 15. In equation 15, VIN(MAX) is the maximum continuous input voltage. IPEAK = 4.62 – SE × VOUT 1.15 × fSW × VIN(MAX) (15a) for A8653 IPEAK = 2.1 – SE × VOUT 1.15 × fSW × VIN(MAX) (15b) for A8652 Subtracting half of the inductor ripple current from equation 15 gives an interesting equation to predict the typical DC load capability of the regulator at a given duty cycle (D), IOUT(DC)≤ 4.62 – V × (1 – D) SE × D – OUT fSW 2 × fSW × LO (16a) for A8653 IOUT(DC)≤ 2.1 – SE × D V × (1 – D) – OUT fSW 2 × fSW × LO (16b) for A8652 After an inductor is chosen, it should be tested during output short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. Output Capacitors The output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (ΔVOUT) is a function of the output capacitors parameters: CO, ESRCO, ESLCO. VOUT = IL × ESRCO + IL VIN – VOUT × ESLCO + LO 8fSWCO (17) The type of output capacitors will determine which terms of equation 17 are dominant. For ceramic output capacitors, the ESRCO and ESLCO are virtually zero, so the output voltage ripple will be dominated by the third term of equation 17. VOUT = IL 8fSWCO (18) To reduce the voltage ripple of a design using ceramic output capacitors, simply increase the total capacitance, reduce the inductor current ripple (i.e. increase the inductor value), or increase the switching frequency. For electrolytic output capacitors, the value of capacitance will be relatively high, so the third term in equation 17 will be very small and the output voltage ripple will be determined primarily by the first two terms of equation 17. VOUT = IL × ESRCO + VIN – VOUT × ESLCO LO Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com (19) 25 A8652, A8653 To reduce the voltage ripple of a design using electrolytic output capacitors, simply decrease the equivalent ESRCO and ESLCO by using a high(er) quality capacitor, or add more capacitors in parallel, or reduce the inductor current ripple (i.e. increase the inductor value). The ESR of some electrolytic capacitors can be quite high so Allegro recommends choosing a quality capacitor for which the ESR or the total impedance is clearly documented in the datasheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambients, as much as 10×, which increases the output voltage ripple and in most cases reduces the stability of the system. The transient response of the regulator depends on the quantity and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount: VOUT = ILOAD × ESRCO + di ESLCO dt (20) After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. The speed at which the error amplifier will bring the output voltage back to its setpoint mainly depends on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, with a higher bandwidth system, it may be more difficult to obtain acceptable gain and phase margins. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the Compensation Components section of this datasheet. Input Capacitors Three factors should be considered when choosing the input capacitors. First, they must be chosen to support the maximum expected input surge voltage with adequate design margin. Second, the capacitor RMS current rating must be higher than the expected RMS input current to the regulator. Third, they must have enough capacitance and a low enough ESR to limit the input voltage dV/dt to something much less than the hysteresis of the IRMS / IOUT Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 10 20 30 60 40 50 Duty Cycle (%) 70 80 90 100 Figure 15: Input Capacitor Ripple vs. Duty Cycle VIN pin UVLO circuitry (VUVLO(HYS), nominally 800 mV for the A8652/53) at maximum loading and minimum input voltage. The input capacitors must deliver the RMS current according to: IRMS = IO D × (1 – D) (21) where the duty cycle D is D ≈ VOUT / VIN. Figure 15 shows the normalized input capacitor RMS current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output current multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 2.6 A of steady-state load current, the input capacitor(s) must support 0.40 × 2.6 A or 1.04 ARMS. The input capacitor(s) must limit the voltage deviations at the VIN pin to something significantly less than the A8652/53 UVLO hysteresis during maximum load and minimum input voltage. The minimum input capacitance can be calculated as follows: CIN ≥ IOUT × D × (1 – D) 0.85 × fSW × ΔVIN(MIN) (22) where ΔVIN(MIN) is chosen to be much less than the hysteresis of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recommended), and fSW is the nominal PWM frequency. The D × (1 – D) term in equation 20 has an absolute maximum value of 0.25 at 50% duty cycle. So, for example, a very conservative design based on IOUT = 2.6 A, fSW = 85% of 425 kHz, D × (1 – D) = 0.25, and ΔVIN = 150 mV, CIN ≥ 2.6 A × 0.25 = 12 µF 361 kHz × 150 mV Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation A good design should consider the DC bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as 90% reduction) so these types should be avoided. The X5R and X7R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. To avoid prematurely triggering Hiccup mode, the soft-start capacitor (CSS) should be calculated according to equation below, } ILIM ILOAD Output Capacitor Current (ICO) For all ceramic capacitors, the DC bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size (i.e. 1206 or 1210). Also, it is advisable to select input capacitors with plenty of design margin in the voltage rating to accommodate the worst-case transient input voltage (such as a load dump as high as 40 V for automotive applications). tSS Bootstrap Capacitor A bootstrap capacitor must be connected between the BOOT and SW pins to provide the floating gate drive to the high-side MOSFET. Usually, 100 nF is an adequate value. This capacitor should be a high-quality ceramic capacitor, such as an X5R or X7R, with a voltage rating of at least 16 V. Soft-Start and Hiccup Mode Timing (CSS) The soft-start time of the A8652/53 is determined by the value of the capacitance at the soft-start pin (CSS). When the A8652/53 is enabled, the voltage at the soft-start pin will start from 0 V and will be charged by the soft-start current (ISS(SU)). However, PWM switching will not begin instantly because the voltage at the soft-start pin must rise above 400 mV. The soft-start delay (td(SS)) can be calculated using equation below, td(SS) = C SS × (400I mV) SS(SU) (23) If the A8652/53 is starting with a very heavy load, a very fast soft-start time may cause the regulator to exceed the pulse-bypulse overcurrent threshold. This occurs because the sum of the full load current, the inductor ripple current, and the additional current required to charge the output capacitors, ICO = CO × VOUT / tSS is higher than the pulse-by-pulse current threshold, as shown in Figure 16. This phenomena is more pronounced when using highvalue electrolytic type output capacitors. Figure 16: Output Current (ICO) During Startup CSS ≥ ISS(SU) × VOUT × CO 0.8 V × ICO (24) where VOUT is the output voltage, CO is the output capacitance, ICO is the amount of current allowed to charge the output capacitance during soft-start (recommend 0.1 A < ICO < 0.3 A). Higher values of ICO result in faster soft-start times. Howewer, lower values of ICO ensure that Hiccup mode is not falsely triggered. Allegro recommends starting the design with an ICO of 0.1 A and increasing it only if the soft-start time is too slow. If a nonstandard capacitor value for CSS is calculated, the next larger value should be used. The output voltage ramp time (tSS) can be calculated by using either of the following methods: COUT CSS tSS = VOUT × I or 0.8 V × I SS(SU) CO (25) When the A8652/53 is in hiccup mode, the soft-start capacitor is used as a timing capacitor and sets the hiccup period. The soft-start pin charges the soft-start capacitor with ISS(SU) during a startup attempt and discharges the same capacitor with ISS(HIC) between startup attempts. Because the ratio of ISS(SU)/ISS(HIC) is approximately 4:1, the time between hiccups will be about four times as long as the startup time. Therefore, the effective duty cycle will be very low and the junction temperature will be kept low. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Remote Load Regulation Control Components Compensation Components (RZ, CZ, CP) To compensate the voltage drop across the wiring harness, the wire resistance RWIRE must be know as a priori. The current sense resistor Rsen,which is connected in series with the load after the output capacitor CO, is recommended to have a value between 20 and 50 mΩ, considering the tradeoff between measurement accuracy and power dissipation. When the load side current limit IOUT_LIM is set, the resistor RIADJ at pin IADJ can be calculated from the equation below: 1,200 RIADJ = IOUT_LIM × Rsen The needed amount of voltage correction should be equal to the voltage drop across the wiring harness: IOUT × RWIRE = IOUT × Rsen × RIADJ × AFB RGADJ Thus for given Rsen, RIADJ, RWIRE, the resistance RGADJ at pin GADJ can be determined from the equation above: Rsen × RIADJ RGADJ = × AFB RWIRE Where AFB = VOUT / VFB is the gain of the FB pin voltage divider. If the dynamic voltage correction adjustment at pin GADJ is desired (refer to Figure 5), then RGADJ in the equation above should be replaced with the equivalent resistance RG_eqv at pin GADJ: RG_eqv = (R 1 GADJ 1 V –1 – G RG_E ) Similarly the equivalent resistance RIADJ at pin IADJ can be calculated below if an external voltage VI is applied at pin IADJ as shown in Figure 7: RI_eqv = ( 1 1 V –1 – I RIADJ RI_E ) The GADJ and IADJ pins are designed for a resistance range of 10 to 34 kΩ, and therefore the controlling voltage VG and VI must be limited as follows: 10 kΩ < RG_eqv < 34 kΩ and, To compensate the system, it is important to understand where the buck power stage, load resistance, and output capacitance form their poles and zeroes in frequency. Also, it is important to understand that the (Type II) compensated error amplifier introduces a zero and two more poles and where these should be placed to maximize system stability, provide a high bandwidth, and optimize the transient response. First, consider the power stage of the A8652/53, the output capacitors, and the load resistance. This circuitry is commonly referred as the “control to output” transfer function. The low frequency gain of this section depends on the COMP to SW current gain (gmPOWER), and the value of the load resistor (RL). The DC gain (GCO(0 HZ)) of the control-to-output is GCO(0 Hz) = gmPOWER × RL (26) The control to output transfer function has a pole (fP1) formed by the output capacitance (COUT) and load resistance (RL) at fP1 = 1 2π × RL × COUT (27) The control to output transfer function also has a zero (fZ1) formed by the output capacitance (COUT) and its associated ESR fZ1 = 1 2π × ESR × COUT (28) For a design with very low ESR type output capacitors (i.e. ceramic or OSCON output capacitors), the ESR zero, fZ1, is usually at a very high frequency, so it can be ignored. On the other hand, if the ESR zero falls below or near the 0 dB crossover frequency of the system (as is the case with electrolytic output capacitors), then it should be cancelled by the pole formed by the CP capacitor and the RZ resistor (discussed and identified later as fP3). Next, consider the feedback resistor divider, (RFB1 and RFB2), the error amplifier (gmEA), and its compensation network RZ/CZ/CP. It greatly simplifies the transfer function derivation if RO >> RZ, and CZ >> CP (where RO is the error amplifier output impedance). In most cases, RO > 2 MΩ, 1 kΩ < RZ < 100 kΩ, 220 pF < CZ < 47 nF, and CP < 50 pF, so the following equations are very accurate. The low frequency gain of the control section (GC(0 Hz)) is formed by the feedback resistor divider and the error amplifier. It can be calculated using equation 29: 10 kΩ < RI_eqv < 34 kΩ Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation RFB2 × gmEA × RO RFB1 + RFB2 VFB = × gmEA × RO VOUT VFB × AVOL = VOUT A Generalized Tuning Procedure GC(0 Hz) = (29) where VOUT is the output voltage, VFB is the reference voltage (0.8 V), gmEA is the error amplifier transconductance (750 µA/V), and RO is the error amplifier output impedance (AVOL/gmEA) The transfer function of the Type-II compensated error amplifier has a (very) low frequency pole (fP2) dominated by the output error amplifier’s output impedance RO and the CZ compensation capacitor, 1 fP2 = 2π × RO × CZ (30) The transfer function of the Type-II error amplifier also has a low frequency zero (fZ2) dominated by the RZ resistor and the CZ capacitor. fZ2 = 1 2π × RZ × CZ (31) Lastly, the transfer function of the Type-II compensated error amplifier has a (very) high frequency pole (fP3) dominated by the RZ resistor and the CP capacitor fP3 = 1 2π × RZ × CP (32) Placing fZ2 just above fP1 will result in excellent phase margin, but relatively slow transient recovery time. The magnitude and phase of the entire system are simply the sum of the error amplifier response and the control-to-output response. 1. Choose the system bandwidth, fC, the frequency at which the magnitude of the gain will cross 0 dB. Recommended values for fC based on the PWM switching frequency are fSW/20 < fC < fSW/7.5. A higher value of fC will generally provide a better transient response while a lower value of fC will be easier to obtain higher gain and phase margins. 2. Calculate the RZ resistor value to set the desired system bandwidth (fC), VOUT 2 × π × COUT RZ = fC × × (33) VFB gmPOWER × gmEA 3. Determine the frequency of the pole (fP1) formed by COUT and RL by using equation 27 (repeated here). 1 fP1 = 2π × RL × COUT 4. Calculate a range of values for the CZ capacitor, 4 1 < CZ < 2 × π × RZ × fc 2 × π × RZ × 1.5 × fP1 (34) To maximize system stability (i.e. have the most gain margin), use a higher value of CZ. To optimize transient recovery time at the expense of some phase margin, use a lower value of CZ. 5. Calculate the frequency of the ESR zero (fZ1) formed by the output capacitor(s) by using equation 28 (repeated here). 1 fZ1 = 2π × ESR × COUT A. If fZ1 is at least 1 decade higher than the target crossover frequency (fC), then fZ1 can be ignored. This is usually the case for a design using ceramic output capacitors. Use equation 32 to calculate the value of CP by setting fP3 to either 5 × fC or fSW/2, whichever is higher. B. On the other hand, if fZ1 is near or below the target crossover frequency (fC) then use equation 32 to calculate the value of CP by setting fP3 equal to fZ1. This is usually the case for a design using high ESR electrolytic output capacitors. Referring to Typical Application Diagram 1 on page 1, several typical designs are provided in Table 3 with VLOAD = 5 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Table 3: Recommended Components Values for Several Typical Designs Design fSW RFSET LO CO RZ + CZ // CP Rsen RGADJ RIADJ A8653 (set IOUT_LIM = 2.75 A, RWIRE = 125 mΩ) A 500 kHz 52.3 kΩ 10 µH (74437368100) 44 µF 14 kΩ + 2.7 nF//33 pF 20 mΩ 20.0 kΩ 20.0 kΩ B 1 MHz 23.7 kΩ 6.8 µH (74437368068) 44 µF 14 kΩ + 2.7 nF//33 pF 20 mΩ 20.0 kΩ 20.0 kΩ C 2 MHz 10.5 kΩ 6.8 µH (74437368068) 32 µF 37.4 kΩ + 1.8 nF//4.7 pF 20 mΩ 20.0 kΩ 20.0 kΩ A8652 (set IOUT_LIM = 1.2 A, RWIRE = 200 mΩ) D 500 kHz 52.3 kΩ 33 µH (74437368330) 20 µF 14 kΩ + 2.7 nF//33pF 50 mΩ 31.6 kΩ 20.0 kΩ E 2 MHz 10.5 kΩ 10 µH (74437368100) 20 µF 24.3 kΩ + 2.2 nF//4.7 pF 50 mΩ 31.6 kΩ 20.0 kΩ Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation POWER DISSIPATION AND THERMAL CALCULATIONS The power dissipated in the A8652/53 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the high-side power MOSFET (PSW1), the power dissipated due to the RMS current being conducted by the high-side MOSFET (PCOND1) and low-side MOSFET (PCOND2), and the power dissipated by both gate drivers (PDRIVER). The power dissipated from the VIN supply current can be calculated using equation 35, PIN = VIN × IQ + (VIN – VGS ) × (QG1 + QG2 ) × fSW (35) where Similarly, the conduction losses dissipated by the low-side MOSFET while it is conducting can be calculated by the following equation: PCOND2 = I 2 RMS,FET ( × R DS(ON)LS = 1 – VOUT I 2 × I OUT + L × R DS(ON)LS VIN 12 (38) 2 )( ) where IOUT is the regulator output current, ΔIL is the peak-to-peak inductor ripple current, RDS(ON)HS is the on-resistance of the high-side MOSFET, VIN is the input voltage, IQ is the input quiesent current drawn by the A8652/53 (see EC table), VGS is the MOSFET gate drive voltage (typically 5 V), QG1 and QG2 is the internal high-side and low-side MOSFET gate charges (approximately 5.8 nC and 10.4 nC, respectively), and fSW is the PWM switching frequency. The power dissipated by the high-side MOSFET during PWM switching can be calculated using equation 36, VIN × IOUT × (tr + tf ) × fSW PSW1 = 2 (36) where RDS(ON)LS is the on-resistance of the low-side MOSFET The RDS(ON) of the both MOSFETs have some initial tolerance plus an increase from self-heating and elevated ambient temperatures. A conservative design should accomodate an RDS(ON) with at least a 15% initial tolerance plus 0.39%/°C increase due to temperature. The power dissipated from the low-side MOSFET body diode during the non-overlap time can be calculated as follows: PNO = VSD × IOUT × 2 × tNO × fSW (39) where VSD is the source-to-drain voltage of the low-side MOSFET (typically 0.60 V), and tNO is the non-overlap time (15 ns(typ)) VIN is the input voltage, IOUT is the regulator output current, The sum of the power dissipated by the internal gate driver can be calculated using equation 40, fSW is the PWM switching frequency, and tr and tf are the rise and fall times measured at the SW node. where The exact rise and fall times at the SW node will depend on the external components and PCB layout, so each design should be measured at full load. Approximate values for both tr and tf range from 10 to 20 ns. The power dissipated by the high-side MOSFET while it is conducting can be calculated using equation 37, PCOND1 = I 2 RMS,FET × R DS(ON)HS = VOUT I 2 × I OUT + L × R DS(ON)HS VIN 12 (37) ( )( 2 ) PDRIVER = (QG1 + QG2) × VGS × fSW (40) VGS is the gate drive voltage (typically 5 V), QG1 and QG2 is the gate charges to drive high-side and low-side MOSFETs to VGS = 5 V (about 5.8 nC and 10.4 nC respectively), and fSW is the PWM switching frequency. Finally, the total power dissipated by the A8652/53 (PTOTAL) is the sum of the previous equations, PTOTAL = PIN + PSW1 + PCOND1 + PCOND2 + PNO + PDRIVER (41) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation The average junction temperature can be calculated with the equation below, TJ = PTOTAL × RθJA + TA (42) where PTOTAL is the total power dissipated from equation 40, RθJA is the junction-to-ambient thermal resistance (34°C/W on a 4-layer PCB), and TA is the ambient temperature. The maximum junction temperature will be dependent on how efficiently heat can be transferred from the PCB to the ambient air. It is critical that the thermal pad on the bottom of the IC should be connected to at least one ground plane using multiple vias. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are tradeoffs between ambient operating temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow will reduce the junction temperature considerably. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation PCB COMPONENT PLACEMENT AND ROUTING A good PCB layout is critical for the A8652/53 to provide clean, stable output voltages. Follow these guidelines to ensure a good PCB layout. Figure 17 shows a typical buck converter schematic with the critical power paths/loops. Figure 18 shows an example PCB component placement and routing with the same critical power paths/loops from the schematic. 1. The current sensing traces from ISEN+ and ISEN– are most sensitive to noise. A Kelvin connection is strongly recommended for the low ohmic current sensing resistor. The loop formed by ISEN+ and ISEN– traces should be minimal. The loop should be away from the noisy switching areas and can be placed on the bottom layer of PCB where it is away from the high di/dt and dv/dt areas. This critical loop is shown as trace 1 in Figure 17 and 18. 2. Place the ceramic input capacitors as close as possible to the VIN pin and GND pins to make the loop area minimal, and the traces of the input capacitors to VIN pin should be short and wide to minimize the inductance. This critical loop is shown as trace 2 in Figure 17 and 18. The larger input capacitor can be located further away from VIN pin. The input capacitors and A8652/53 IC should be on the same side of the board with traces on the same layer. 3. The loop from the input supply and capacitors, through the high-side MOSFET, into the load via the output inductor, and back to ground should be minimized with relatively wide traces. 4. When the high-side MOSFET is off, free-wheeling current flows from ground, through the synchronous low-side MOSFET, into the load via the output inductor, and back to ground. This loop should be minimized and have relatively wide traces, shown as trace 4 in Figure 17 and 18. 5. Place the output capacitors relatively close to the output inductor (LO) and the A8652/53. Ideally, the output capacitors, output inductor and the controller IC A8652/53 should be on the same layer. Connect the output inductor and the output capacitors with a fairly wide trace. The output capacitors must use a ground plane to make a very low-inductance connection to the GND. 6. Place the output inductor (LO) as close as possible to the SW pin with short and wide traces. This critical trace is shown as 7. 8. 9. 10. 11. 12. 13. 14. 15. trace 3 in Figure 17 and 18. The SW node voltage transitions from 0 V to VIN and with a high dv/dt rate. This node is the root cause of many noise issues. It is suggested to minimize the SW copper area to minimize the coupling capacitance between SW node and other noise-sensitive nodes. However, the SW node area cannot be too small in order to conduct high current. A ground copper area can be placed beneath the SW node to provide additional shielding. Also, keep low level analog signals (like FB, COMP) away from the SW polygon. Place the feedback resistor divider (RFB1 and RFB2) very close to the FB pin. Make the ground side of RFB2 as close as possible to the A8652/53. Place the compensation components (RZ, CZ, and CP) as close as possible to the COMP pin. Also make the ground side of CZ and CP as close as possible to the A8652/53. Place the FSET resistor as close as possible to the SYNC/ FSET pin. Place the soft-start capacitor CSS as close as possible to the SS pin. The output voltage sense trace (from VOUT to RFB1) should be connected as close as possible to the load to obtain the best load regulation. Place the bootstrap capacitor (CBOOT) near the BOOT pin and keep the routing from this capacitor to the SW polygon as short as possible. When connecting the input and output ceramic capacitors, use multiple vias to GND and place the vias as close as possible to the pads of the components. Do not use thermal reliefs around the pads for the input and output ceramic capacitors. To minimize PCB losses and improve system efficiency, the input and output traces should be as wide as possible and be duplicated on multiple layers, if possible. The thermal pad under the A8652/53 IC should be connected to the GND plane (preferably on the top and bottom layer) with as many vias as possible. Allegro recommends vias with an approximately 0.25 to 0.30 mm hole and a 0.13 and 0.18 mm ring. EMI/EMC issues are always a concern. Allegro recommends having locations for an RC snubber from SW to ground. The resistor should be 0805 or 1206 size. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 33 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation 2 VIN 1 ISENRFB1 1 ISEN+ CIN FB LO SW SS Rsen 3 VOUT Load VREG SYNC/FSET CO COMP CSS RFB2 4 CP RFSET CZ RZ SGND PGND 2 Figure 17: Typical Synchronous Buck Regulator with Current Sensing Resistor for Remote Load Regulation A single-point ground is recommended, which could be the exposed thermal pad under the IC. Figure 18a: Example PCB Component Placement and Routing, Top Layer Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 34 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Figure 18b: Example PCB Component Placement and Routing, Bottom Layer Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 35 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use (Reference MO-153 ABT) Dimensions in millimeters. NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0.65 0.45 8º 0º 5.00 ±0.10 16 16 0.20 0.09 1.70 B 3 NOM 4.40 ±0.10 6.40 ±0.20 A 1 3.00 6.10 0.60 ±0.15 1.00 REF 2 3 NOM 1 2 0.25 BSC Branded Face C 16X 0.10 C 0.30 0.19 3.00 SEATING PLANE GAUGE PLANE C PCB Layout Reference View SEATING PLANE 1.20 MAX 0.65 BSC NNNNNNN 0.15 0.00 YYWW LLLL A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Branding scale and appearance at supplier discretion 1 D Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W= Week of manufacture L = Characters 5-8 of lot number Figure 19: Package LP, 16-Pin eTSSOP with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 36 A8652, A8653 Wide Input Voltage, Synchronous USB Buck Regulator with Remote Load Regulation Revision Table Number Date – February 6, 2015 1 March 2, 2016 2 April 7, 2016 Description Initial Release Corrected Output Voltage Accuracy symbol (page 6), Synchronization Input Rise and Fall Time units and Threshold symbols (page 7), SS Maximum Charge Voltage (page 8), and miscellaneous editorial changes. Test specifications changed. Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 37