L9663
PSI5 Transceiver IC
Datasheet - production data
Short to ground tolerant with ±1.5 V ground
shift
32-bit SPI interface with address multiplexing
Operating voltage: VB = 4.8 V (5.2 V for sync
pulses with 3.5 V step) to 35 V
Ambient temperature range: -40°C to 140 °C
Package: VFQFPN28 or TQFP32EP
*$3*36
*$3*36
VFQFPN28
TQFP32
(Exposed pad down)
Description
The Peripheral Sensor Interface (PSI5) is an
interface for automotive sensor applications. PSI5
is an open standard based on existing sensor
interfaces for peripheral sensors and offers a
universal and flexible solution for multiple sensor
applications.
Features
2-channel PSI5 transceiver compatible with
rev. 1.3 and rev. 2.1
The PSI5 interface allows asynchronous or
synchronous operations and different bus modes.
The device is compatible with both v1.3 and v2.1
PSI5 revisions (limitations are specified inside this
document). It operates with a wide range of
sensor supply current and variable data word
length (8 to 28 bit).
Manchester coded digital data transmission
High data transmission speed of 125 kbps
(optional 83.3 kbps and 189 kbps)
High EMC robustness and low emission
Bootstrap circuits for sync pulses
Current limitation and voltage clamp on
interface pins
Integrated charge pump stage for preregulation with spread spectrum approach
Integrated FLL module for high accuracy timing
control
Reverse voltage protection structure
The sensors are connected to the ECU using the
same line for power supply and data
transmission. The transceiver IC provides a preregulated voltage to the sensors and reads in the
transmitted sensor data.
The PSI5 interface allows either point to point
connection or bussed mode.
Table 1. Device summary
Order code
L9663
L9663-TR
L9663-1
L9663-TR-1
January 2016
This is information on a product in full production.
Package
TQFP32 (Exposed pad)
VFQFPN28
DocID028693 Rev 1
Packing
Tray
Tape & Reel
Tray
Tape & Reel
1/104
www.st.com
Contents
L9663
Contents
1
2
3
2/104
Overall description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Main functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
VQFPN28 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4
TQFP32 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6
Detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7
Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1
Internal supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2
VAS supply and pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3
2.4
Voltage supply for synchronous pulse generation VSYNCx . . . . . . . . . . . . . . . . 19
Power supply for PSI5 sensor line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
Frequency references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6
Reset handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Satellite interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1
Receiver with digital sampling and filtering . . . . . . . . . . . . . . . . . . . . . . . 25
3.2
Manchester decoder and error detection . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3
Receive block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1
PSI5 receive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2
Sensor data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.3
Interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.4
Automatic storage of sensor initialization data . . . . . . . . . . . . . . . . . . . . 33
3.4
Upstream data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5
Trigger pulse generator for synchronous pulses . . . . . . . . . . . . . . . . . . . 36
3.6
Synchronous pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7
Safety concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.7.1
Voltage monitoring check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.7.2
Sensor data consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.7.3
Buffer empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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4
5
Contents
DOUTx path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.5
Cross coupling test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1
PSIx output voltage clamping circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2
PSIx output under voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3
PSIx short circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4
PSIx reverse voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5
VAS under/over voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6
Monitoring of Synchronous Pulse amplitude . . . . . . . . . . . . . . . . . . . . . . 45
Communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.1
Device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3
6
3.7.4
5.2.1
Physical layer and signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.2
Clock and data characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2.3
Frame definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2.4
Communication frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Direct interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9
8.1
TQFP32 (7x7x1.0 mm exp. pad down) package information . . . . . . . . . . 99
8.2
VFQFPN-28 (5x5x1.0 mm) package information . . . . . . . . . . . . . . . . . . 101
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DocID028693 Rev 1
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List of tables
L9663
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/104
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
VQFPN28 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TQFP32 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Time (t0-t2) vs SensorData. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error codes in sensor communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Faults priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Time (t0-t7) vs SensorData. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doutx test mode bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VINTx internal supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VAS supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
VAS external MOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
VAS pre regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
VSYNCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PSI5 output supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PSI5 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Sync generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VAS under/over voltage monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Synchronous pulse amplitude monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Time slot monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Frequency references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI communication timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Direct interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TQFP32 (7x7x1.0 mm exp. pad down) package mechanical data . . . . . . . . . . . . . . . . . . 100
VFQFPN-28 (5x5x1.0 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DocID028693 Rev 1
L9663
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VQFPN28 pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TQFP32 pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply line model for PSI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-up sequence of transceiver IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal power supply and reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input structure of supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VAS application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block diagram Transceiver 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal oscillator vs external clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FLL clock error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block diagram of incoming data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PSI5 v1.3 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PSI5 v2.0 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sensor buffer in synchronous mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Sensor buffer in asynchronous mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagram with interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ECU to sensor communication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Short (in case 1 μs < tw < 5 μs) Sync Pulse trigger, compliant to PSI5 standard . . . . . . . . 38
Timing for PSIx under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timing for PSIx reverse voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing for VAS under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing for sync pulse voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Operation on internal register (with upstream data buffer) . . . . . . . . . . . . . . . . . . . . . . . . . 84
Init data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Sensor data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Sync generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI communication timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TQFP32 (7x7x1.0 mm exp. pad down) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 99
VFQFPN-28 (5x5x1.0 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DocID028693 Rev 1
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5
Overall description
L9663
1
Overall description
1.1
Simplified block diagram
Figure 1. Simplified block diagram
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6/104
DocID028693 Rev 1
L9663
1.2
Overall description
Main functionality
The transceiver IC can be used in two different modes (Mode 1 or Mode 2)(a) . The system
configuration called Mode 1 performs the decoding effort of sensor signals in the IC. The
system configuration called Mode 2 is a frontend to a PSI5 decoder contained in an external
device (typically a μC with a dedicated module).
The transceiver IC can monitor all internally generated relevant voltages, such as VSYNCx
VAS and V_PSIx.
The PSI5 interfaces inside the IC are supplied by a separate input pin VAS. If only
asynchronous mode is required, the VAS voltage is sufficient for the sensor power supply.
When synchronous mode is required, a higher voltage than VAS is needed in order to
generate the synchronous pulses. This voltage VSYNCx is generated by a dedicated
bootstrap circuit for each channel.
For direct supply from battery, the transceiver IC includes a VAS pre-regulator supplied by
VASSUP-pin: the pre-regulator can drive an external FET to regulate the VAS voltage to
7.6 V or 5.3 V. In case of low voltage level at VASSUP, an integrated charge pump is
implemented, with supply from VASSUP.
The internal analog and digital circuits are supplied by VB. The external voltage on VDD pin
is used to supply the digital output pins; VDD pin can be used to switch the digital outputs
from 5 V output level (default) to 3.3 V output level.
The PSI5 transceiver is functional in the whole VDD, VB, VASSUP and VAS power supply
range.
The internal voltage supplies (VSYNCx) are automatically activated by the transceiver IC
depending on the operating mode whenever they are needed.
Each transceiver interface can be activated and deactivated by an SPI command. At startup, the interfaces are off by default.
The communication interface block includes two different interfaces. In mode 1, SPI is used
for data transfer. In mode 2, the direct interface is used. The data from and to the sensors
will be transmitted bit-wise between the transceiver IC and the μC. The data evaluation and
error handling for frame errors will be done in the PSI5 controller which is integrated in the
μC.
Transceiver 1 and 2 supply the sensors and generate the synchronous pulses for
synchronous data transfer (if required) from the sensors to the transceiver and for data
transfer from the ECU to the sensors.
A data transfer from the ECU to the sensors can be performed:
by using sync pulses with different duration (PSI5 2.x standard)
by masking of sync pulses (PSI5 1.3 and 2.x standard)
The sync pulse trigger can be generated by an SPI command, by a dedicated pin (for
connection to the Synchronous Pulse Output Block included in the microcontroller) or by an
integrated automatic timer.
a. Mode 1 and Mode 2 are two system architectures which relate on the way L9663 communicates with the
microcontroller. Depending on the chosen architecture, the μC must configure the IC with the correct setup.
DocID028693 Rev 1
7/104
103
Overall description
L9663
The Transceivers 1 and 2 limit the current and the PSIx voltage (PSI5-requirement when
VAS is too high because of failure in the VAS power supply, less than 11 V in data
transmission or less than 16.5 V in sync pulse).
The current modulated signal received from sensor is detected and digitally converted. This
sensor data will then either be:
First Manchester decoded by the Manchester Decoder block with mark space error
correction and then transferred to the "receive data buffer" module (Mode 1). The data
from the new sensor frames will be saved in a buffer and then will be transferred to the
μC via SPI.
Transferred directly to the μC (Mode 2). In this case the output of the transceiver is a
Manchester-coded signal without error correction that falls under microcontroller
responsibility.
8/104
DocID028693 Rev 1
L9663
VQFPN28 pins description
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Table 2. VQFPN28 pin-out
Pin
Name
Description
1
SYNC1
Direct interface sync pulse trigger 1
I
local
2
DOUT1
Direct interface 1/Interrupt 1
O
local
3
CLKIN
External clock input
I
local
4
SYNC2
Direct Interface sync pulse trigger 2
I
local
5
DOUT2
Direct interface 2/Interrupt 2
O
local
6
NC(1)
-
-
-
7
BH1
Bootstrap capacitor pin 1 or SYNC voltage supply
(from ECU), transceiver 1
I/O
local
8
BL1
Bootstrap capacitor pin 2, transceiver 1
I/O
local
9
GND1
supply
local
10
PSI1
PSI5 Interface 1
I/O
global
11
VAS
PSI5 Interface pre-regulated voltage supply
supply
local
12
PSI2
PSI5 Interface 2
I/O
global
13
GND2
supply
local
14
BL2
Bootstrap capacitor pin 2, transceiver 2
I/O
local
15
BH2
Bootstrap capacitor pin 1 or SYNC voltage supply
(from ECU), transceiver 2
I/O
local
Ground return for PSI5 interface (analog ground and
substrate ground)
Ground return for PSI5 interface (analog ground and
substrate ground)
DocID028693 Rev 1
Pin type
9/104
103
Overall description
L9663
Table 2. VQFPN28 pin-out (continued)
10/104
Pin
Name
16
VB
17
VASSUP
18
VGS
(2)
Description
Pin type
Input voltage supply
supply
global
VAS pre-regulator and charge pump voltage supply
supply
global
I/O
local
-
-
-
Gate driver for VAS pre-regulator
19
NC
20
MOSI
SPI input
I
local
21
SCLK
SPI Clock
I
local
22
CS
SPI Chip Select
I
local
23
RESETN
Reset
I
local
I
local
(3)
24
TM
Test-mode pin
25
VINTD
Internal digital supply voltage
supply
local
26
DGND
Digital ground
supply
local
27
VDD
Digital I/O supply
supply
local
28
MISO
O
local
SPI output
1.
Not connected internally, must be left open.
2.
Not connected internally, it can be connected to GND externally.
3.
It must be connected to GND, for safety reasons.
DocID028693 Rev 1
L9663
1.4
Overall description
TQFP32 pins description
Note:
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The exposed pad is electrically shorted to the substrate and to pins GND1 and GND2.
These three nodes have to be kept shorted on the application.
Table 3. TQFP32 pin-out
Pin
Name
1
SYNC1
Direct interface sync pulse trigger 1
I
local
2
DOUT1
Direct interface 1/Interrupt 1
O
local
3
CLKIN
External clock input
I
local
-
-
-
2
Description
Pin type
4
NC
5
SYNC2
Direct Interface sync pulse trigger 2
I
local
6
DOUT2
Direct interface 2/Interrupt 2
O
local
-
-
(1)
7
NC
-
8
BH1
Bootstrap capacitor pin 1 or SYNC voltage
supply (from ECU), transceiver 1
I/O
local
9
BL1
Bootstrap capacitor pin 2, transceiver 1
I/O
local
DocID028693 Rev 1
11/104
103
Overall description
L9663
Table 3. TQFP32 pin-out (continued)
Pin
Name
10
GND1
11
PSI1
PSI5 Interface 1
12
VAS
PSI5 Interface pre-regulated voltage supply
(2)
Description
Ground return for PSI5 interface (analog
ground and substrate ground)
supply
local
I/O
global
supply
local
-
-
I/O
global
13
NC
-
14
PSI2
PSI5 Interface 2
15
GND2
Ground return for PSI5 interface (analog
ground and substrate ground)
supply
local
16
BL2
Bootstrap capacitor pin 2, transceiver 2
I/O
local
17
BH2
Bootstrap capacitor pin 1 or SYNC voltage
supply (from ECU), transceiver 2
I/O
local
18
NC(1)
-
-
-
19
VB
Input voltage supply
supply
global
20
VASSUP
VAS pre-regulator and charge pump voltage
supply
supply
global
21
VGS
I/O
local
22
NC
2
-
-
-
23
MOSI
SPI input
I
local
24
SCLK
SPI Clock
I
local
25
CS
SPI Chip Select
I
local
26
RESETN
Reset
I
local
27
TM
Test-mode pin(3)
I
local
-
-
(2)
Gate driver for VAS pre-regulator
28
NC
-
29
VINTD
Internal digital supply voltage
supply
local
30
DGND
Digital ground
supply
local
31
VDD
Digital I/O supply
supply
local
32
MISO
O
local
SPI output
1. Not connected internally, must be left open.
2. Not connected internally, it can be left open or connected to GND externally.
3. It must be connected to GND, for safety reasons.
12/104
Pin type
DocID028693 Rev 1
L9663
1.5
Overall description
Maximum ratings
Within the maximum ratings, no damage to the component shall occur. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
All maximum ratings can occur at the same time.
All analog voltages are related to the potential at substrate ground (GND1 and GND2,
internally shorted), all digital voltages are related to DGND.
Operative voltage conditions are specified in Section 6.
Table 4. Pin maximum ratings
Symbol
Description
Min
Max
Unit
-0.3
40
V
Power supply
VB, VASSUP Input voltage range
VAS
Pre-regulated voltage range
-0.3
40
V
VDD
Supply voltage range for digital I/O pins
-0.3
6.5
V
Internal digital supply voltage
-0.3
4.6
V
Voltage range of bootstrap capacitor or SYNC
voltage supply (from ECU)
-0.3
40
V
-1.5
40
V
Pre-regulator gate voltage range
-0.3
40
V
Reset input pin range
-0.3
6.5
V
Test mode input pin range
-0.3
6.5
V
Clock input pin range
-0.3
6.5
V
-0.3
6.5
V
VINTD
BHx, BLx
Other pins
PSI1, PSI2 Voltage of sensor interface
VGS
RESETN
TM
CLKIN
CS, SCLK,
SPI communication pin range
MOSI
MISO
SPI communication pin range
-0.3
VDD+0.3≤6.5
V
DOUT1,
DOUT2
Direct interface pin range
-0.3
VDD+0.3≤6.5
V
SYNC1,
SYNC2
Sync pulse trigger input range
-0.3
6.5
V
ESD robustness
-
ESD according to Human Body Model (HBM),
Q100-002 for pins PSIx, VB, VASSUP;
(100 pF/1.5 kΩ)
±4000
-
V
-
ESD according to Human Body Model (HBM),
Q100-002 for all other pins; (100 pF/1,5 kΩ)
±2000
-
V
-
ESD according to Charged Device Model (CDM),
Q100-011 Corner pins
±750
-
V
-
ESD according to Charged Device Model (CDM),
Q100-011 Non-corner pins
±500
-
V
DocID028693 Rev 1
13/104
103
Overall description
L9663
Table 4. Pin maximum ratings (continued)
Symbol
Description
Min
Max
Unit
Temperature
Ta
Ambient operating temperature range
-40
140
°C
Tj
Junction operating temperature range
-40
175
°C
45
°C/W
Rthja
Package thermal resistance (on PCB JEDEC
2s2p)
The device offers a high level of flexibility on power supply configuration. The calculated
maximum power dissipation can reach 1.6 W considering the worst case configuration.
1.6
Detailed block diagram
Figure 4. Detailed block diagram
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14/104
DocID028693 Rev 1
L9663
Overall description
The high supply voltage of the IC can be a battery or a regulated voltage provided by the
ECU.
To reduce disturbances on the voltage supply which might have a negative influence on the
PSIx interface and therefore lead to bit errors, a PI filter can be employed in the supply line.
Possible power supply configurations(b) are:
VB, VASSUP connected to VSUP, VAS and VSYNCx generated by the IC with external
components (as in the above figure);
VAS, VB, VASSUP connected to VSUP, VSYNCx generated by bootstrap, no external
MOS, VGS pin open;
VB, VASSUP, BH1, BH2 connected to VSUP, no external capacitors CBx, VAS
generated by IC pre-regulator and external MOS;
VB connected to VSUP, VASSUP connected to 0V (charge pump off), VAS supplied by
an external source and VSYNCx generated by the IC with external components.
The values of the external components RE2_x, CE_x and CL_x are specified in PSI5
standard.
The assumed line model for the PSI5 interface on which the transceiver IC operates is as
follows:
Figure 5. Supply line model for PSI5
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b. The high supply voltage VSUP must be in the correct operative range of connected pins.
DocID028693 Rev 1
15/104
103
Overall description
1.7
L9663
Power up sequence
When VDD is higher than the startup threshold and VB is available the IC is switched on.
To reduce disturbances on its voltage supply, the transceiver IC does a staggered startup of
its internal voltage supplies.
While RESETN is low, the PSIx lines are deactivated to reduce power consumption and to
increase system safety.
The transceiver IC can be configured to operate in the standard current mode (4 mA up to
19 mA) or in the extended current mode (4 mA up to 35 mA). Moreover, both channels can
be configured to allow the extension to a maximum quiescent current of 45 mA, only in case
of asynchronous mode.
The synchronous sensors send data only after a synchronous pulse is triggered via the
dedicated pin or by SPI.
The following figure shows a power-up example.
Figure 6. Power-up sequence of transceiver IC
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16/104
DocID028693 Rev 1
L9663
Power supply
2
Power supply
2.1
Internal supply
The internal analog and digital part is supplied by the supply voltage VB. The necessary
power supply for the internal digital and analog parts is generated internally by the
transceiver IC. The generated voltage is monitored. In case of under/over voltage, the
transceiver IC performs a power on reset (POR).
Figure 7. Internal power supply and reset generation
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Basic features:
Voltage regulator
Under / Over voltage monitoring
Reset generation of the IC in case of under / over voltage
Figure 8. Input structure of supply
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DocID028693 Rev 1
17/104
103
Power supply
L9663
A ceramic capacitor with a typical capacitance of 100 nF is required as a blocking capacitor
close to the pins VDD and VB.
The internal supply voltages VINTD (supply voltage for digital part) and VINTA (supply voltage
for analog part) are monitored for under voltage and over voltage to prevent the transceiver
IC from malfunction. The reference for the voltage monitoring is a bandgap voltage, supplied
by VINTA. The device integrates two separated instances of bandgap voltage regulators; one
of these bandgaps is used as voltage reference for the internal regulators, while the other
one is used for monitoring the voltage levels. In case of under or over voltage, the
transceiver IC is set into reset: outside reset thresholds full functionality is granted.
The functionality of the digital part only depends on the voltages on VINTD. In order to
improve noise emissions and stability of the regulator, the digital supply line needs an
external decoupling 100 nF ceramic capacitor to be connected between VINTD and DGND
and close to them.
DGND ground line is protected against ground loss scenarios. In case DGND line would be
at least DGNDOPEN above the reference ground lines GND1/2, a POR is asserted.
The transceiver IC returns to normal operation with full functionality as soon as the POR is
released.
2.2
VAS supply and pre-regulator
The VAS pre-regulator sets the VAS voltage if no regulated voltage with the necessary value
is available in the ECU.
The pre-regulator is designed for two different regulated voltages at VAS: 5.3 V or 7.6 V,
selectable by a SPI command. The supply of external FET can be chosen at application
level according to the required voltage at VAS pin.
Two possible applications are:
VAS typical of 5.3 V; external FET supplied by ECU internal voltage, typically 6 V .
VAS typical of 7.6 V; external FET directly supplied from battery, from 8 V to 35 V.
Basic features:
Gate control for an external n-ch FET transistor with integrated charge pump stage
Gate control is switched on if no power on reset condition is present
Configurable output voltage: either 5.3 V or 7.6 V.
18/104
DocID028693 Rev 1
L9663
Power supply
Figure 9. VAS application diagram
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When POR is active, the VGS output pin is driven low to keep external N-ch switched off.
The VAS pre-regulator is automatically activated with a soft start at POR and automatically
switched off, after a filter time, if VAS falls below VVASU_off. It can be later controlled off or on
by means of a dedicated VAS_EN bit. To protect the external component from exceeding
maximum allowed gate to source voltage if VAS is shorted to ground by a fault, an internal
passive clamp is implemented on VGS.
The integrated charge pump, supplied by VASSUP, assures proper voltage regulation in
case of low voltage conditions. It is automatically switched off in case the voltage on VASSUP
is high enough to allow proper regulation.
If the pre-regulator is not needed, the VAS_EN bit can be set to '0' to switch off the preregulator itself. The pin VGS can be left open, and the VAS pin directly connected to the
regulated voltage in the ECU.
The pre-regulator is active independently of RESETN input pin if the supply voltage of the
internal analog/digital circuits is available.
2.3
Voltage supply for synchronous pulse generation VSYNCx
To use synchronous PSI5 sensors and for ECU-to-sensor communication, the transceiver
IC needs to generate synchronization pulses. These require a voltage which is higher than
VAS.
This module generates the necessary voltage VSYNCx by two bootstrap circuits. Two
capacitors with two transceiver IC pins each are used as external components of this
module.
The bootstrap blocks start pre-charging the external capacitors after POR (with a 2 ms time
gap between the first and second block).
The bootstrap circuits are enabled by default, activated by internal logic with timing sync
pulses dependent, and can be disabled later on through a dedicated SPI command. The
bootstrap block can recharge the capacitor so that subsequent sync pulses are allowed with
a minimum period of 200 μs.
A useful option is the possibility to connect the BHx pin directly to a high voltage rail. In this
configuration, VB has also to be connected to the same high voltage rail and the bootstrap
DocID028693 Rev 1
19/104
103
Power supply
L9663
circuit can be bypassed by disabling it through the dedicated SPI command (bit 12 of
CH1_CR2, CH2_CR2, writable during PROG phase).
The bootstrap blocks are automatically switched off in case the voltage on VB is high
enough to allow proper regulation. In this case both CBx capacitors should be omitted.
The VSYNCx voltage can supply a 2.5 V minimum sync pulse as per PSI5 v2.x low power
mode down to VB = 4.8 V and a 3.5 V minimum sync pulse down to VB = 5.2 V, with a
maximum quiescent current level of 35mA and down to minimum 200 μs period between
sync pulses. The block is protected against reverse feeding to VB.
The bootstrap module is fully functional while VB and VDD are all inside their specified
voltage ranges.
2.4
Power supply for PSI5 sensor line
Basic features:
Reverse voltage protection structure
Voltage limitation and current limitation for PSIx input/output
Protection against negative voltages on PSIx transceiver pin due to ground shifts
Disconnection of PSIx from VAS in failure cases
The PSI5 transceiver IC is supplied directly from the pin VAS. It includes blocks with the
following functionalities:
Reverse voltage protection structure and gate driver block for
–
Voltage clamp on PSIx in case of VAS fault
–
Backward voltage supply blocking mechanism from PSIx to VAS
–
Sensor supply by switching VAS to the PSIx pin
–
Disconnection of PSIx from the VAS if required or in failure cases
Under voltage detection block to implement cross coupling test between the two
channels (see Section 3.7.5 and 4.2)
Receiver block for Sensor Data receive (see Section 3.1 for details).
The reverse voltage protection structure is also used to switch off the PSIx transceiver
channel, if:
the local junction temperature exceeds its maximum rating and the channel is in
overcurrent
an overcurrent condition on PSIx is detected (STG)
a short to battery is detected
it is requested via SPI or RESETN pin.
In case of short to battery on the PSIx lines, there is no interference to any other IC
pin/supply including SPI.
The two interfaces can be enabled by SPI command, and the enable has effect only if VAS
under voltage signals are not asserted.
If an over temperature condition (OT) occurs, the interface that is also in overcurrent
condition is switched off and a failure bit is set. The fault bit is latched and cleared only when
a SPI switch off command is sent for confirmation on the line that was automatically
switched off. The shutoff of one interface does not affect the second interface.
20/104
DocID028693 Rev 1
L9663
Power supply
If an overcurrent condition on PSIx is detected, the current limitation is active and after a
filter time tfilt a fault bit is set and the interface is shut off. In order to switch on again, the
interface must be first switched off by SPI and then switched on, as for over temperature.
The channels’ switch off by overcurrent can be disabled if the corresponding bits
STG_MASK for every channel are set in the SPI registers.
During start up, a configurable blanking time is implemented (128 μs/5 ms/10 ms, see
BLANKING_SEL bits in SPI register); during this time current limitation is active, even
though the interface will not shut off for overcurrent, thermal shutdown is always active, the
PSI5 receiver is disabled, and some fault flags are masked (short to battery, under voltage,
leakage to ground).
The quiescent current is monitored for minimum and maximum value, depending on the
range selected by SPI (CH1_CR1, QC_SEL bits). In failure case the corresponding bit in the
diagnostic register is set (SR2).
The voltage at PSIx is compared with VAS to monitor short to battery condition: if an over
voltage occurs PSIx is disconnected from VAS and the corresponding bit in diagnostic
register is set (STBx in SR2), In over voltage condition also low quiescent current bit is set
(OLx in SR2) after a transient time.
Figure 10. Block diagram Transceiver 1
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Frequency references
The device comes with an integrated accurate oscillator, used for any of the internal
circuitry, with no need of external connections or components. The nominal clock frequency
is 16 MHz with a ±5% accuracy.
Should the application need some more accurate timing reference, a discrete pin CLKIN is
provided. An external clock reference can be connected to this pin. The PSI5 transceiver IC
offers an integrated FLL module that tracks this input to provide a high accurate clock
reference (±1%). This feature can be used especially if accurate timeslot control needs to be
achieved.
External signal on CLKIN can be configured as follows (see CLKIN_CFG bits in GCR1 SPI
register):
1 MHz square signal
4 MHz square signal
No signal (Not connected pin)
Pin CLKIN can be grounded when not used. The pin input circuit implements a pull-down
structure.
The FLL module tracking the CLKIN signal is off by default.
The PSI5 transceiver IC implements a safety function for monitoring the device clock
reference, both in case it is derived from the CLKIN signal through the FLL module or
internally generated. In the first condition the monitoring is always activated, while in the
second condition it can be enabled by programming in ST (storing a '1' in a dedicated
OTP(c) bit) and another oscillator generator is used for monitoring.(d)
When the CLKIN_CFG is set, the FLL tries to close the LOOP and a mask counter of
T_CKMSK (16 ms MAX) is used to count the maximum transient time.
During this time, regardless the CLK frequency the CKER_DETECT is masked, i.e the
device doesn't detect a clock error.
After this time, if the CLKIN frequency is in the correct range, the loop is closed and the CLK
frequency is inside the 1% tolerance; if the CLKIN frequency is outside the malfunction
detecting range, a clock error is detected after a detection time T_CKERD, the device is
reset and the CLK_FLT is set so that the μC can read the reset source.
The T_CKERD and the transient during detection time depend on the CLKIN frequency
behavior; the figure below shows the behavior of the internal oscillator as function of the
external one.
c. One Time Programmable bit: it can be programmed by ST only.
d. For clock error detection by internal monitor oscillator see errata n.3367, Section 7: Errata.
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Figure 11. Internal oscillator vs external clock frequency
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If the CLKIN is stuck the device behavior is shown in the figure below: in this case during the
detection time the tolerance is still inside the 1% tolerance until the device enters reset
(T_CKERD max 260 μs).
Figure 12. FLL clock error detection
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Reset handling
Four different sources are considered in resetting the IC:
POR (Power On Reset, see Section 2.1)
RESETN pin
SW_RESET
CKER_DETECT
All these sources of reset, when asserted, will switch off the PSIx lines and reset to default
value the device registers (including those registers for configuration).
Additionally to the hardware resets (by pin/POR), a reset can also be initiated by software
(SW_RESET).
The command SW_RESET initiates a soft reset-sequence if all of the following conditions
are fulfilled (see also the DCR register in SPI section):
unlocked state: it means that if the UNLOCK command is not received the command
SW_RESET has no effect;
The command SW_RESET is sent in next SPI communication of the unlock command.
A SW_RESET initiates soft reset-sequence and resets all digital parts of the device, except
POR and RST flag that is set in SR3 register.
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3
Satellite interface
3.1
Receiver with digital sampling and filtering
This module has the following features:
The output current signal is mirrored and converted to the digital domain
Automatic synchronization on entire PSI5 frames
Fast DAC digital conversion of sensed currents with digital filtering
Static DC current set point tracking of PSI5 quiescent current.
Tracking of modulated PSI5 current signal
The quiescent current tracking can be configured to work in two ways (reg. ADVSET1,
ADVSET3, bits FREEZE_DIS): continuous mode tracking or tracking between consecutive
frames till the first edge of a new frame is recognized. In the second case, the quiescent
current is frozen till the end of the frame.
To recognize the PSI5 current signal level the receiver compares the digitally converted and
filtered current with a threshold. This threshold can be fixed or dynamic, depending on the
configuration selected by SPI (reg. ADVSET).
In fixed threshold mode the user must program the right delta current threshold, according
to the application requirements. The threshold is obtained as tracked quiescent current plus
the programmed threshold.
In dynamic threshold mode, the threshold is dynamically adapted considering the PSI5
current input signal.
For detailed explanation on all the possible configurations refer to ADVSET registers
section.
Depending on the selected configuration, the threshold for the sensor signal can be
permanently tracked, separately for each PSI5 interface. The IC is designed to compensate
erratic changes of the quiescent current in the bus according to PSI5 standard
requirements.
The v2.x standard low power mode is not supported with dynamic threshold mode.
Micro cuts up to 10μs do not affect the DC current tracking in a way that more than one
frame will be lost.
The PSI5 Receiver is designed to operate at:
83.3 Kbps typical (slow mode)
125 Kbps typical (standard mode)
189 Kbps typical (fast mode).
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Manchester decoder and error detection
Basic features:
Detection of start bits "00"
Synchronization with sensor to ECU frame
Manchester decoding according to PSI5 specification (v 1.3 or v 2.x, depending on the
chosen configuration)
The Manchester decoder takes the bit stream which the receiver has as its output and
decodes the incoming data frames from this bit stream.
It can be programmed to measure the period of start bits sent by the sensors and doublecheck the timing of the following data bits with respect to the synchronization given by the
start bits or to validate the data bits according to the PSI5 protocol baud rate configured by
the microcontroller. The tolerance for timing checks is 20%: in case of timing error a
Manchester error is reported.
A Manchester Decoder Error occurs if one or more of the following are true:
Start bit error outside of selected operating range
Data length error or stop bit error
Bit time error (a data bit edge is not received inside the expected time window)
Timing violation on slot when standard timeslot monitor is enabled
In case a Manchester error is detected the corresponding error code is set [v. Error codes
table, Section 3.3.2].
3.3
Receive block
This block includes the buffer for incoming sensor data and diagnostic results. It includes:
PSI5 receive registers
Sensor data buffer
Interrupt generation for the microcontroller
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Satellite interface
PSI5 receive register
This module includes the sensor data storage and diagnostic.
Basic features:
Storage of Sensor data
Error handling
Figure 13. Block diagram of incoming data buffer
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PSI5 Receive Register
The transceiver IC has a PSI5 Receive Register for each PSI5 transceiver.
Each PSI5 Receive Register can store up to 28Bit data and up to 3Bit error check (CRC or
parity) for each of the incoming frames. According to the PSI5 powertrain substandard, up to
6 frames can be sent between two synchronous pulses. For every frame, a frame
configuration register is available which defines:
Data Region 8 … 28 bit
CRC or Parity Bit (3 or 1 bit)
Depending on the desired configuration (SPI bit CRC_CK of GCR1 register), the parity/CRC
bits handling can be done in the following ways:
Parity/CRC bits are generated by the sensor; the transceiver IC simply passes
data+parity/CRC bits to the μC via SPI and the μC performs parity/CRC check
Parity/CRC bits are calculated by the transceiver IC and in case of a correct parity
bit/checksum, the payload of the frame is stored in the receive buffer; otherwise, if the
CRC calculation shows a wrong result, the Parity Error code is stored.
The SPI register bit CRC_CK is valid for all sensors of both interfaces.
After all bits have been received the data will be transmitted into the corresponding part of
the receive buffer.
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Each PSI5 data frame consists of a total p bits containing:
two start bits (S1 and S2),
one parity bit (P) with even parity or alternatively 3 CRC bits (C0, C1, C2), and
a data region (D0 … D[k-1]) with k = 8…28 bit.
The total length of a PSI5 frame is p=k+3 data bits (in case of frames with parity bit) or
p=k+5 data bits (in case of frames with CRC).
Data bits are transmitted LSB first. The parity or CRC check bits cover the bits of the entire
data region.
Figure 14. PSI5 v1.3 frame
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L9663
Satellite interface
In case of PSI5 v2.x, the length of the data region can vary between k = 10 … 28 bits, with
1-bit granularity. The data region can be split into the following fields and regions:
Signal payload region 1 with data bits A0 … A[n-1] (scalable n = 10…24 with 1-bit
granularity)
Signal payload region 2 with data bits B0 … B[m-1] (scalable m = 0…12 with 1-bit
granularity)
Sensor status E0.. E[r-1] (optional r = 0, 1 or 2 bit)
–
This optional status bit can be used to show that the data of the current frame are
faulty.
Frame control, type of frame F0, …F[q-1] (optional q = 0, 1, 2, 3 or 4 bit)
–
This frame control can be used to number the frames which are sent after a sync
pulse.
Serial (slow) messaging channel (optional) M0, M1 (optional 0 or 2 bit)
Time slot monitoring
The time slot monitoring is active only in synchronous mode.
The time slot monitoring is required to check if the sensors connected to the transceiver
work properly in terms of timing, i.e. if they are sending data frames within their defined time
slot.
Basic features:
3 configurable modes
Failure bit
During a synchronous pulse period (TSYNC), a maximum number of 6 frames can be
configured. Each frame has its own time slot, to be configured through dedicated
configuration registers. The registers contain the reference time needed to check if the
sensor data is transmitted during the defined time slot.
The resolution of time slots is 1 μs. The time slot monitoring timings are applied starting
from the internal sync pulse trigger. This internal trigger falls td_SPI (or td_SYNC, depending
on sync pulse trigger configuration) after the external one (via SPI or SYNC pin).
Three different configurations for the time slot monitoring are available:
Standard configuration: monitoring the correct start and end time of a unique frame
within a time slot
Simple configuration: monitoring only the end time of a frame within a time slot
No monitoring configuration: monitoring is disabled and data are stored in successive
slots.
The time slot monitoring can be activated/deactivated separately for each interface
(registers CHx_CR1, bits TSMx_SEL).
In case of standard configuration, the IC accepts as valid frame in a timeslot only a frame
which starts and ends within its timeslot; if more than one valid frame is received within its
timeslot, only the last one received is kept.
On the other side, in case frames span across slots, the frame is discarded and the error
code 1FC (timing violation) is stored in the correspondent buffer; in this case the decoder is
reset at every slot start. After this reset if a frame was being decoded, a slot error is set in
the previous slot but no slot error is set. Then the Manchester FSM after reset checks again
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for two valid start bits and so a new incoming frame can be stored without error in the new
timeslot.
In the simple configuration, the last valid message which ends in a timeslot is stored in the
buffer of the slot (so if a frame is currently stored in a timeslot and an incoming frame ends
in this timeslot, the old data are overwritten). In this mode slot error is never set.
It is also possible to disable the time slot monitoring and in this case, no timing check is
done: the first frame is assigned to the first buffer, the second to the second, and so on. This
means that the buffer index is incremented every time a frame is received both valid and
invalid (Manchester communication error).
After reset, the default mode for the time slot monitoring is "monitoring disabled".
3.3.2
Sensor data buffer
To avoid loss of data, a data buffer for each PSI5 transceiver is necessary. While the data
buffer is being read by SPI, at the beginning of the sensor data transfer the data register is
cleared and a new data frame can be accepted.
The incoming PSI5 sensor data, together with CRC and SID/GBIT (if selected) are written
into a receive buffer, which is large enough to hold the data of one sync pulse cycle (i.e. up
to six sensors). In order to avoid data-mixing between different cycle times the data must be
fetched by the μC before the next transmission cycle starts.
The figure below shows how sensor buffers are updated in synchronous mode.
At t0 the buffers contain no data; then a sync pulse is sent and data are received and stored
in each register during the cycle time; so at t1/t2 the buffers contain sensors data of the
current cycle time.
Figure 16. Sensor buffer in synchronous mode diagram
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Table 5. Time (t0-t2) vs SensorData
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Time/Sensor
t0
t1
t2
SensorData1
Buffer Empty
D11
D12
SensorData2
Buffer Empty
D21
D22
SensorData3
Buffer Empty
D31
D32
SensorData4
Buffer Empty
D41
D42
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Table 5. Time (t0-t2) vs SensorData (continued)
Time/Sensor
t0
t1
t2
SensorData5
Buffer Empty
D51
D52
SensorData6
Buffer Empty
D61
D62
In case of sensor or channel fault conditions, the following codes are sent in the first 10 bits
of the data field. The lower 10 bits are filled with '0'.
Table 6. Error codes in sensor communication
Error Code
Definition
1FC
Manchester error (non-valid start bits, incorrect number of bits
received, timing violation)
1F8
Parity / CRC error(1)
1F1
Physical layer error (short to ground, leakage to GND, overtemperature, open load)
1F0
Data buffer empty
1F2
Short to battery
1F9
Sync pulse error
1. Used only in case the CRC check computation is assigned to the IC (CRC_CK bit set to 1); otherwise the
sensor data will be written in the buffer.
If more than one data is present, the faults are handled with this priority scale:
Table 7. Faults priority
Priority
1 (highest)
Data
Valid data
Fault type
Code
-
-
2
Over Temperature
channel
1F1
3
Short To Ground
channel
1F1
4
Short To Battery
channel
1F2
5
Leakage To Ground
channel
1F1
6
Open Load
channel
1F1
7
Manchester Error
Sensor related
1FC
8
CRC/Parity Error
Sensor related
1F8
9
Sync Pulse under voltage
(both Slow Vsync detection
and sync UV faults)
channel
1F9
10
Data Buffer Empty
Sensor related
1F0
In synchronous communication mode each sensor (time slot) has its own range in the data
buffer. The buffer range content is overwritten if new data arrives before the old data has
been read out.
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If a channel fault occurs, the content of every sensor buffer is affected regardless the
moment inside the timeslots cycle in which the fault occurs. This value will be held until the
fault is cleared (reading the appropriate bit in the Status Register) or a fault with higher
priority occurs.
In asynchronous communication mode a six stages FIFO is implemented: the newest data
is always in the data buffer range corresponding to sensor no. 1, the oldest data is in the
data buffer range corresponding to sensor no. 6. When the buffer is full, the FIFO shifts the
incoming data to keep always the newest data. As soon as the first data is read by SPI, the
FIFO will be locked to writing, until it is emptied(e). This situation is reported through SPI bit
FIFO_LCK.
Figure 17. Sensor buffer in asynchronous mode diagram
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Table 8. Time (t0-t7) vs SensorData
Time/Sensor
t0
t1
t2
t3
t4
t5
t6
t7
SensorData1
Buffer Empty
D1
D2
D3
D4
D5
D6
D7
SensorData2
Buffer Empty
Buffer
Empty
D1
D2
D3
D4
D5
D6
SensorData3
Buffer Empty
Buffer
Empty
Buffer
Empty
D1
D2
D3
D4
D5
SensorData4
Buffer Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
D1
D2
D3
D4
SensorData5
Buffer Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
D1
D2
D3
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Buffer Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
Buffer
Empty
D1
D2
If a fault occurs and FIFO is unlocked, the correspondent code is written in the FIFO buffer
at the current position; if more than one fault occurs at the same time the fault with the
highest priority is written in the FIFO.
In both synchronous and asynchronous mode, when a valid data is read, the buffer empty
code 1F0 is written in the buffer.
e. For the lock of the FIFO see errata n.1526, Section 7: Errata.
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As safety feature, the IC always checks that after a valid data read the code 1F0 is written in
the buffer.
If this check fails a Buffer Empty Fault is latched (BEx bits in SR2 register) and it's cleared
after SPI read. Buffer empty fault asserts also Global Status Bit.
In order to allow the μC to test this feature a test of buffer empty check is implemented (see
Section 3.7.3 and STSR register for details).
3.3.3
Interrupt generator
The microcontroller interrupt module describes the function of the interrupt pins to generate
a microcontroller interrupt if the data buffers are filled with sensor data.
Basic features:
Configurable interrupt pins
Interrupt generation when data buffer is full
The interrupt pins generate an interrupt for the microcontroller if the receive buffer
corresponding to a transceiver interface is filled completely: the interrupt pin is then reset
when the receive buffer is empty.
Asynchronous operation:
The interrupt pin is set to high when the number of received data since the last reading of
register is as large as the size of the receive buffer. The interrupt pin is set to low when all
the buffers are empty.
Synchronous operation:
The interrupt pin is set to high when all the buffers configured by SPI are full. The interrupt
pin is set to low when all the buffers are empty.
Figure 18. Block diagram with interrupt pins
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After reset, the output pin is configured as DOUTx.
3.3.4
Automatic storage of sensor initialization data
If the sensor uses a data range initialization procedure and the PSI5 payload is 20 bit with 3
frame control bits, 1 status bit, 16 bit data, the device can be configured so that the
initialization data is stored in the transceiver IC and can be read via SPI.
In case of serial messaging method, the data must be extracted at application layer.
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Basic features:
Registers for initialization data (up to 8 init data buffer by 16 word available)
Automatic detection of init data
Reading via SPI
Figure 19. Timing diagram
After the activation of an interface, the transceiver IC can check for incoming sensor
initialization data on that interface and store the data for further processing. This behavior is
triggered by the configuration bit READ_INIT_DATA on that channel.
If the bit is set, an internal FSM checks for IDn and data blocks Dn in the incoming payload
data on that interface and stores data in the init buffer id (init_buf_id) of the corresponding
frame id at address n-1 in the following format:
RegAddr
n-1
15 (MSB)
10
additional data from blockid
message (6 bits --- 0 bits)
9
6
data block ( 4 bits )
5
0 (LSB)
additional data from data
message (6 bits --- 0 bits)
The frame control bits allow using up to 8 init data buffers when automatic storage of init
data is activated and both interfaces are used (READ_INIT_DATA1 = READ_INIT_DATA2 =
1). In case only one interface is active, the IC can store up to 6 init data on that interface.
As specified in PSI5, data nibbles D2 and D3 contain the number of datablock expected for
the all init procedure for each particular frame id; when all the init data are received for the
engaged sensors (i.e. for the sensors which had sent at least one correct data blocks) on
both the interfaces, the init_data_rdy is set and the μC can read all the init data by SPI.
During reset, the incoming data buffer is cleared and the counters for each initialization data
block are set to "00".
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The interface can be configured both in asynchronous and synchronous mode (in the
second case, the number of bits must be the same for all the timeslots). The accepted
configuration for init data is based on 20 total bits, as follows:
16 data bits
1 status bit
3 frame control
3.4
Upstream data buffer
Basic features:
Adapts the signals delivered by Sync Pulse Timer block in order to make possible a
bidirectional communication ECU to sensor
Generates the trigger signal necessary for an event triggered sync pulse
Provides the Sync Pulse Trigger signal to the Sync Pulse Generator
Figure 20. ECU to sensor communication diagram
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The synchronization bits in the ECU to sensor communication must be programmed in the
upstream data buffer by the microcontroller.
The upstream data buffer has 64 bits. The clock for the register is the output of the Sync
Pulse Timer together with the trigger commands via SPI. After each request for a sync
pulse, the register is shifted by one and the last bit is fed into the sync pulse trigger
generator.
Depending on the data length, only a part of the upstream data buffer is used. After the
writing of the relevant part of the buffer, the μC writes the upstream data confirm bit in the
UDBCR register (bit UDBx_RDY). After this confirmation, the trigger source can start the
communication. If these data are sent, the upstream data buffer is ready for new data. This
is indicated by the SPI flag UDBx_BUSY='0'. If new data is written to the buffer while
UDBx_BUSY is still '1', the write command is ignored and the error flag UDBx_FLT is set.
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Besides if a new trigger is sent while the buffer is busy, again the command is ignored and
the fault bit is set.
The buffer register can be reset by writing 0x00FF for channel 1 (respectively 0xFF00 for
channel 2) to the SPI register DCR. After such a reset, the module will flag that it is ready for
new data.
The behaviour of the sync pulse trigger generator then depends on the configuration of the
transceiver IC:
In PSI5 1.3 and 2.x mode (tooth gap method), it will mask out (i.e. ignore) the incoming
sync pulse trigger if the bit is '0'. The resulting gap is defined to be a '0' in the ECU-tosensor communication.
In PSI5 2.x mode (pulse length method), it will generate a long sync pulse if the bit is '1'
and a standard sync pulse otherwise.
The transceiver IC provides a transparent interface for ECU-to-sensor communication. This
means that any data in the upstream data buffer will directly be transmitted onto the PSIx
interface. The CRC calculation and data layer handling are done by the microcontroller.
3.5
Trigger pulse generator for synchronous pulses
This module generates the trigger signals for the transceiver interfaces. It has the following
sub-modules:
SPI-programmable sync pulse timer
SPI command triggering
2 pins named SYNC1, SYNC2
The module contains the sync pulse trigger generators (one for each transceiver).
Basic features:
Generates the sync pulse trigger at the configured time intervals
Generates the sync pulse trigger upon the corresponding command via SPI or discrete
SYNCx pins.
The trigger pulse generator generates the trigger signal which the sync pulse generator
uses as its input.
The trigger pulse generator has five different configurations, which can be properly selected
via SPI command:
Triggering via SPI without upstream data buffer. The microcontroller sends the
corresponding SPI command for a sync pulse. The sync pulse trigger generator then
internally generates the appropriate sync pulses, based on the specific SPI command
sent.
Triggering via SPI with upstream data buffer. The microcontroller sends the
corresponding SPI command for a sync pulse. Then the sync pulse trigger generator
internally generates the appropriate sync pulses, depending on the value in the
upstream data buffer.
Triggering via SYNCx pins without upstream data buffer. When the SYNCx pin is
triggered, the sync pulse trigger generator internally generates the appropriate sync
pulses, based on the type of trigger (length) received on the input pin.
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L9663
Satellite interface
Triggering via SYNCx pins with upstream data buffer. When the SYNCx pin is
triggered, the sync pulse trigger generator internally generates the appropriate sync
pulses, depending on the value in the upstream data buffer.
Triggering via trigger pulse timer: the transceiver IC automatically generates the sync
pulses at fixed time intervals, depending on the value in the upstream data buffer.
The default configuration at startup is to use the triggering via SYNCx pins without upstream
data buffer.
If the triggering with upstream data buffer is used and there aren't data to be sent to the
sensor, a short pulse is sent.
The switch matrix is configurable by an SPI command. It determines whether the sync
pulses are triggered via SPI by the trigger generator (transceiver IC in mode 1) or by the
external trigger pins (transceiver IC in mode 2).
If the trigger pulse timer is used to generate the sync pulse trigger, the interval between two
pulses on interface x is configured by the SPI register SYNC Pulse Timer (SPT). It's
possible also to program the delay between interface 1 and interface 2 sync pulses through
the SYNC_DELAY_PSI1_PSI2 bits in ADVSET2 register. In case the sync pulse trigger
comes from SPI commands or SYNCx pins, the programmed pulse timer still has the
functionality of a filtering time with respect to those triggering commands.
If full flexibility for the sync pulse interval is required, use direct triggering either via SPI or
direct interface.
3.6
Synchronous pulse generator
The Synchronous Pulse Generator is designed to generate synchronous pulses conform to
PSI5 rev. 1.3 (min Vt2 = 3.5 V) as well PSI5 rev. 2.x (min Vt2 = 2.5 V).
The sync pulse is granted according to PSI5 standard with the Ibase current range up to
35 mA.
If the pulse trigger generation is configured with an external trigger and without the
upstream data buffer, the external source must manage the encoding via SPI CHCNT
register (for tooth gap and pulse width methods) or via PIN (tooth gap method only), for what
concerns the duration of the sync pulse (i.e. ECU to sensor communication), otherwise the
IC manages the encoding (tooth gap or pulse width methods, specified in register GCR1, bit
PSIx_TGAP_PW).
An automatic hardware based slew rate control (SRC) ensures PSI5 compliant slew rates
for the rising and falling edge of the sync pulse for an overall capacitive bus load of 15 to
107 nF. The Sync Pulse is shaped like raised cosine instead of trapezoidal to reduce EMC
emission.
During the duration of the sync pulse, the corresponding PSI5 receiver is frozen to avoid
erroneous data detection.
VDD, VAS and VB and other supply voltages are protected against reverse feeding from the
sync pulse.
The pulse length at PSIx will be generated using the Sync Pulse Trigger Generator.
In case of trigger by pin without UDB, the Sync Pulse Generator starts the sync pulse with
the positive edge of the trigger signal, after SYNCx pin filter. The duration of the sync pulse
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Satellite interface
L9663
is compliant to PSI5 standard (short pulse only) if the duration of the trigger is shorter than
5μs.(f)
Figure 21. Short (in case 1 μs < tw < 5 μs) Sync Pulse trigger, compliant to PSI5
standard
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3.7
Safety concepts
The IC design is optimized concerning functional safety requirements, thanks to the
following implementations.
3.7.1
Voltage monitoring check
Internal and external voltage critical monitoring structures are automatically tested run-time
while the device is operated. This feature covers the voltage monitors on:
VINTA/D (under/over voltage monitoring)
GNDD loss
VAS (under/over voltage monitoring)
VASSUP over voltage for charge pump disable
VB over voltage for bootstrap disable
PSIx under voltage
PSIx over-temperature
The tests automatically running can highlight a condition of real fault on the application or a
fault within the IC.
3.7.2
Sensor data consistency
Sensor data handling implements a particular safe concept intended to work with the SPI
formats related to passive restraint application (i.e. 10-bit to 16-bit payloads): SID bits and G
bit.
A 5-bit code (SID) can be used to identify sensor data. The external MCU can program a
SID via SPI to be associated to each time slot of a physical interface. When the MCU
performs a sensor data read operation via SPI, the L9663 returns the SID code to the MCU,
along with the requested sensor data, for the MCU to check.
f.
38/104
For sync pulse triggering via pin see errata n.1822, Section 7: Errata.
DocID028693 Rev 1
L9663
Satellite interface
If the SID is used, a diagnostic bit (G bit) is also present in the SPI frame sent to the MCU.
This bit signals the occurrence of specific faults, namely an under voltage on the VAS
supply, or a parity check fault on a critical register(g) .
The data register containing SID bits and PSI5 sensor data is written with one single access:
data from the Manchester decoder is identified with reference to the time slot counter and
written in the same access when the information of the transmitting sensor is written.
Each failure case, CRC checksum and SID identification mismatch, can be forced via test
SPI commands through STS and STSR register after a special "self test" mode is entered
through an SPI command (see DCR (PROG) register for details).
3.7.3
Buffer empty check
As described in Section 3.3.2, the IC always checks that, after a valid data read, the code
1F0 is written in the buffer.
This feature is the "Buffer Empty check", implemented for safety: if the check fails a Buffer
Empty Fault is asserted and latched (BEx bits in SR2 register) and it is cleared after reading
through SPI.
In order to allow the μC to test this feature at startup or during normal operation, a Test of
buffer empty check is provided in the STSR register (bit0).
If this bit is set, after a read operation the old data is left in the buffer; in this way a buffer
empty fault is set and the μC can test the safety feature.
3.7.4
DOUTx path check
DOUTx paths can be checked against fault conditions through dedicated test SPI register
(STS register).
In order to test the input structures of the connected microcontroller, the L9663 features a
DOUTx test mode that allows test patterns to be applied on the two outputs DOUT1DOUT2. The test mode can be entered via SPI and the test patterns can also be controlled
via SPI commands. Test patterns can be composed only of static high or low signals, which
can be selected via SPI. For failsafe reasons only one channel at a time can be switched
into test mode.
Table 9. Doutx test mode bit value
Bit
10
9:5
Name
Description
DOUTTP
Test Pattern:
1: Static output set to high on DOUTx, for which test mode is enabled
0: Static output set to low on DOUTx, for which test mode is enabled
DOUTSEL
Dout Test Mode Selection Bits:
10101: DOUT Test Mode Enabled for DOUT1 Output
10110: DOUT Test Mode Enabled for DOUT2 Output
All other bit patterns: DOUT Test Mode Disabled
g. The fault "clock error" is not included in the G bit because in this case the device enters immediately reset
state, if the bit REACTTIME of ADVSET2 register is '0' (default).
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3.7.5
L9663
Cross coupling test
An automatic hardware based cross-coupling test (XCT) for the PSI interfaces is
implemented and can be triggered by SPI command (Self-Test Setting (STS) Register). Aim
of the test is to monitor the status of PSIx interfaces both in master and slave mode; slave
mode simply checks that when PSIx are switched off the under voltage flag is set, while
master mode implements a Finite State Machine able to schedule several steps (see
description below).
XCT test both in master and slave mode is triggered only if both PSIx interfaces are off.
In case one of the PSI-IFs is already switched on, starting of a XCT will not be possible
and in this case the XCT results register will be reset.
Once XCT test is running, commands to switch the channel on or disable VAS regulator
are ignored by the device.
Once XCT test is running, it cannot be interrupted or stopped by any SPI instruction
except by stop bit within "Abort cross-coupling test" command: in this case, only in
master mode, an "abort" flag will be set (XCT_ABT bit).
While XCT test is running a "busy" flag will be asserted (XCT_RUN bit).
Once XCT test is finished a "done" flag will be asserted (XCT_COMPL).
Flag "busy" is only asserted while XCT test both master and slave mode is ongoing
while "done", "abort", XCTx_R, STB, XCT_STG results are cleared when read via SPI
or when a new XCT start request occurs (both valid or invalid). Please note that
XCT_STG bits are mapped in bits 0 and bit 8 of SR2 register. These bits normally are
real time bits but, as soon as a Master XCT test is completed (and the XCT_COMPL
flag is asserted) the bits 0 and 8 contain the results of the XCT test and keep this value
until results are cleared by reading or by new test start)
Slave Mode (PSIx switched off)
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A pulldown current (IXCT) is turned ON for both channels for a 512 μs time in order to
be sure to discharge PSI5 lines
Once PSI5 line is supposed to be discharged (512 μs time elapsed), pull-down current
is switched off on each channel
Check psi1_uv=psi2_uv='1':
–
Xcoupling_slave PSI1 ok if psi1_uv='1' (test failed otherwise)
–
Xcoupling_slave PSI2 ok if psi2_uv='1' (test failed otherwise)
DocID028693 Rev 1
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Satellite interface
Master Mode
Short to battery test
–
Enable PSI1 channel
–
Wait for a 512 μs time in order to reach steady state condition (short to ground
and overcurrent masked in this phase)
–
Check psi1_stb='0': in case psi1_stb='1' the fault flag is asserted and the channel
1 is not involved in the following tests
–
Switch off PSI1 channel and switch on IXCT pull down current for a 128 μs time on
PSI1 interface
–
Once PSI5 line is supposed to be discharged (128 μs time elapsed), pull-down
current is switched OFF
–
Enable PSI2 channel
–
Repeat the above flow for PSI2 channel
X coupling test phase 1 (only if channel 1 was not excluded in previous short to battery
test)
–
Enable PSI1 channel, PSI2 channel switched off
–
Wait for 512 μs time in order to reach steady state condition and allow PSI under
voltage filter time to elapse (short to ground and overcurrent masked in this phase)
–
Check psi1_uv='0' and psi2_uv='1': in case of psi1_uv='1' a short to GND on PSI1
is detected while in case psi2_uv='0' a cross coupling is detected and XCT2_R bit
is set (h)
–
Switch off PSI1 channel and switch on IXCT pull down current for a 128 μs time
–
Once PSI5 line is supposed to be discharged (128 μs time elapsed), pull-down
current is switched off.
X coupling test phase 2 (only if channel 2 was not excluded in previous short to battery
test)
–
Enable PSI2 channel, PSI1 channel switched off
–
Wait for 512us time in order to reach steady state condition and allow PSI under
voltage filter time to expire (short to ground and overcurrent masked in this phase)
–
Check psi2_uv='0' and psi1_uv='1': in case of psi2_uv='1' a short to GND on PSI2
is detected while in case psi1_uv='0' a cross coupling is detected and XCT1_R bit
is set
–
Switch off PSI2 channel and switch on IXCT pull down current for a 128 μs time
–
Once PSI5 line is supposed to be discharged (128 μs time elapsed), pull-down
current is switched off
Short to battery test in master mode is executed in two phases for the two channels to avoid
enabling simultaneously PSIx interfaces and avoid overloading ECU supply line.
Cross coupling test in master mode stops automatically when the time required by this test
is elapsed. Cross coupling test in slave mode can be stopped with "Abort cross coupling
test" command; only in this case, the flag "cross-coupling test aborted" is not set, because
this is not a faulty condition.
h. Cross coupling test flags swapped in master mode, see errata n.1830, Section 7: Errata.
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Diagnosis
4
L9663
Diagnosis
The PSIx output voltage is monitored to detect and protect against failures:
Under voltage on PSI5x outputs
Short to ground (STG)
Leakage to ground (LTG)
Open load (OL)
Short to battery (STB)
Short between channels (through cross coupling test) and to protect the transceiver IC
in case of negative voltages or excessive voltage on the PSIx outputs.
This module consists of the following sub modules:
PSIx output voltage clamping circuit
PSIx short circuit detection and current limitation
PSIx reverse voltage monitoring
PSIx under voltage monitoring
VAS under voltage monitoring
Sync pulse voltage monitoring
4.1
PSIx output voltage clamping circuit
The clamping circuit allows control of the maximum voltage level on the PSIx output, despite
a possible over voltage fault on the VAS line.
The Transceivers clamp the PSIx voltage to less than 11 V in data transmission or less than
16.5 V in sync pulse with a 50 mA typical sink current.
4.2
PSIx output under voltage monitoring
The under voltage monitoring detects a low voltage level of the sensor supply line PSIx.
Basic features:
Under voltage monitoring with filter time
Figure 22. Timing for PSIx under voltage detection
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L9663
Diagnosis
The PSIx lines (sensor supply lines) are monitored for under voltage if the PSIx line is
switched on.
The current status of the under voltage comparators is shown in the SPI register SR2.
The logical state of the voltage comparator is debounced internally by a filter.
While any reset is active (POR, RESETN or SW_RESET), the PSIx lines are switched off.
After reset is released, the failure bits are reset and the voltage supply at PSIx lines kept off.
4.3
PSIx short circuit detection
The short circuit monitoring detects a short of the sensor supply line PSIx to GND, limits the
current to ISTG (max 130mA) for tIfilt and then switches off the affected PSIx line.
Basic features:
Short to ground circuit monitoring with filter time
Automatic deactivation of the PSIx line in case of a short to GND
Readable via SPI
The PSIx lines (sensor supply lines) are monitored to detect a short circuit to GND if the
PSIx line is switched on. In this case, the corresponding fault SPI bit STGx in SR2 register
is set to '1' and the PSIx line is switched off (the status of the interfaces is reported in SR3
register). The fault bit is latched and cleared only when a SPI switch off command for
confirmation is sent on the line that was under short to ground condition. The current status
(on/off) of the PSI interfaces can be read via SPI.
The line can be switched on again by switching off and on via SPI.
The logical state of the short to ground monitoring is debounced internally by a filter. The
monitoring is deactivated during a configurable blanking time after startup of the interface.
This time is selectable through BLANKING_SEL parameter in SPI register ADVSET1
(default value is 128 μs)
During reset is active, the PSIx lines are switched off. After reset is released, the failure bits
are reset and the voltage supply at PSIx lines can be switched on by SPI command. It is
possible to reset the transceiver IC by sending an SPI command (SW Reset).
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103
Diagnosis
4.4
L9663
PSIx reverse voltage monitoring
The PSIx sensor supply lines are monitored to detect a short circuit to battery if the PSIx line
is switched on.
Basic features:
Reverse voltage monitoring with respect to VAS (or VBH during sync pulse) voltage
with filter time
Readable via SPI
Figure 23. Timing for PSIx reverse voltage detection
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In case of a detected failure, a failure bit STBx in SR2 register is set to '1' (latched and
cleared upon reading via SPI).
After reset, the failure bit is reset to '0'
4.5
VAS under/over voltage monitoring
The VAS voltage is monitored for under voltage and over voltage.
Basic features:
Under voltage comparator with filter time
Over voltage comparator with filter time
Readable via SPI
Figure 24. Timing for VAS under voltage detection
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L9663
Diagnosis
If the VAS voltage is lower than the under voltage threshold for longer than the filter time, the
SPI bit VAS_UV in SR1 reg is set to '1' and it is latched and cleared upon read.
If the VAS voltage is higher than the over voltage threshold for longer than the filter time, the
SPI bit VAS_OV in SR1 reg is set to '1' (NOT latched). In addition to that, in case of further
lower under voltage condition (VVASU_off), VAS is switched off to protect the external nchannel FET component from high current flow when external pin is shorted to ground. The
fault bit VAS_UVL (SR1) is latched and gets cleared only when a SPI switch off command
for confirmation is sent. The current status (on/off) can be read via SPI (SR3).
The regulator can be switched on again by switching off and on via SPI.
When POR is de-asserted, under voltage is masked for the time needed by soft start circuit
to switch on the regulator (1 ms).
During reset, the under/over voltage bits are set to 0.
4.6
Monitoring of Synchronous Pulse amplitude
To detect possible communication problems due to sync pulses which do not conform to the
standard, this module monitors the parameters of the sync pulse and registers any deviation
from the standard.
Basic features:
Comparator
Evaluation block
Flag readable via SPI
Figure 25. Timing for sync pulse voltage monitoring
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Diagnosis
L9663
The sync pulses(i) are monitored for under voltage, duration and rising edge transient
speed. The circuit evaluates the output voltage versus internal sync trigger signal and sets
the corresponding bit(s) in Status Register 1 (SR1):
Bit SYNCx_SLOW if a delayed sync pulse or pulse with Vt2< 2.5V /3.5V was generated
(slow Vsync rising time)
Bit SYNCx_UV if the sync pulse amplitude goes below 2.5V/3.5V for a time longer than
the specified filtering time (spec parameter tAsync_V).
STB is detected by the over voltage monitoring (see Section 4.4).
i.
46/104
For sync pulse triggering via pin see errata n.1822, Section 7: Errata
DocID028693 Rev 1
L9663
5
Communication interface
Communication interface
As interface to the microcontroller, either the SPI interface or the direct interface shall be
used.
The following pins are used for SPI communication:
MOSI
MISO
SCLK
CS
5.1
Device registers
The following registers are available for writing configuration data and reading information
data. Registers can be of 4 different types:
WO: writeable only
RO: readable only
R/W: both readable and writeable
RC : readable and cleared upon reading
Device configuration registers are marked with "PROG". These registers can only be written
before the microcontroller sends an EOP (End Of Programming) command through the
Direct Command Register (DCR).
The registers which have a special safety importance contain a parity bit (PAR) which must
be written by the μC with an odd parity. A periodic check (every 150 us) is done and if a
parity error is found on one of these registers the GBIT is set.
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5
0
0
4
3
2
1
0
VAS_SEL
0
6
CRC_CK
0
7
SIDG_EN
8
CLKIN_CFG
9
RESERVED
10
PSI1_TGAP_PW
PSI2_EXT_UDB
11
PSI1_TRIG_SEL
DIS_ADD_MUX
12
PSI1_EXT_UDB
13
PSI2_TGAP_PW
14
General Configuration Register 1
PSI2_TRIG_SEL
15
PAR
GCR1 (PROG)
0
0
0
Default value:
1
0
0
0
0
0
0
0
0
R/W
Address:
000001
Type:
R/W
Description:
[15] PAR: Register parity
Odd parity bit for register bits [15:0]
[14] DIS_ADD_MUX: SPI address multiplexing disable
0: address multiplexing enabled
1: address multiplexing disabled
[13] PSI2_EXT_UDB: SYNC pulse generation for PSI5 interface 2
0: the trigger on SYNC2 pin or the SPI command determine the SYNC pulse length
1: the contents of UDB2 determine the SYNC pulse length (always true if timer enabled
bit[12:11]=10)
[12:11] PSI2_TRIG_SEL: SYNC pulse trigger source for PSI5 interface 2
00: SYNC pulse generated by SYNC2 pin
11: SYNC pulse generated by SYNC2 pin
01: SYNC pulse generated by SPI command
10: automatic SYNC pulse generation
[10] PSI2_TGAP_PW: SYNC pulse method for PSI5 interface 2
This bit takes effect only in case bit [13] = 1
0: tooth gap method
1: pulse width method
[9] PSI1_EXT_UDB: SYNC pulse generation for PSI5 interface 1
0: the trigger on SYNC1 pin or the SPI command determine the SYNC pulse length
1: the contents of UDB1 determine the SYNC pulse length(always true if timer enabled
bit[8:7]=11)
[8:7] PSI1_TRIG_SEL: SYNC pulse trigger source for PSI5 interface 1
00: SYNC pulse generated by SYNC1 pin
11: SYNC pulse generated by SYNC1 pin
01: SYNC pulse generated by SPI command
10: automatic SYNC pulse generation
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Communication interface
[6] PSI1_TGAP_PW: SYNC pulse method for PSI5 interface 1
This bit takes effect only in case bit [9]=1
0: tooth gap method
1: pulse width method
[5] RESERVED
[4:3] CLKIN_CFG: Clock input configuration
00: no external clock used
11: no external clock used
01: 1MHz external clock
10: 4MHz external clock
[2] SIDG_EN: SID and Gbit
This bit takes effect only in case of payload of 10 or 16 bits
0: SID bits and G bit not used
1: SID bits and G bit used
[1] CRC_CK: CRC / parity check on sensor data
0: the CRC bits on SPI MISO are those from the sensor
1: the CRC bits on SPI MISO are calculated by the transceiver
[0] VAS_SEL: VAS voltage regulator output
0: 5.3 V
1: 7.6 V
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RESERVED
VAS_EN
0
1
7
6
5
0
1
0
4
3
2
1
0
PSI1_EN
RESERVED
0
8
MASK_SYNC1
RESERVED
0
9
RESERVED
10
SPI_SYNC_TRIG1
11
PSI2_EN
12
MASK_SYNC2
13
RESERVED
14
SPI_SYNC_TRIG2
15
RESERVED
Channel Control
RESERVED
CHCNT
0
1
0
Default value:
0
0
0
0
0
0
R/W
Address:
000010
Type:
R/W
Description:
[15:11] RESERVED
[10] PVAS_EN: Enable / disable VAS regulator
0: disabled
1: enabled
[9:8] SPI_SYNC_TRIG2: SPI SYNC pulse trigger for PSI5 interface 2
00, 11: no SYNC pulse generated
01: short SYNC pulse
10: long SYNC pulse
Notes:
if interface 2 is off, these bits are ignored and no sync pulse is generated bits are evaluated
only once, after writing;
If upstream data buffer is used, both codes "01" and "10" are equivalent. Information on sync
pulse length is provided by the UDB
[7] RESERVED
[6] MASK_SYNC2: SYNC pulse enable / disable for PSI5 interface 2
0: SYNC pulse disabled
1: SYNC pulse enabled (if in synchronous mode, otherwise ignored)
[5] PSI2_EN: Enable PSI5 interface 2
0: interface off
1: interface on
[4:3] SPI_SYNC_TRIG1: SPI SYNC pulse trigger for PSI5 interface 100: no external clock used
00: no SYNC pulse generated
11: no SYNC pulse generated
01: short SYNC pulse
10: long SYNC pulse
Notes:
if interface 1 is off, these bits are ignored and no sync pulse is generated.
if interface 1 is on, these bits are evaluated only once, after writing;
If upstream data buffer is used, both codes "01" and "10" are equivalent. Information on sync
pulse length is provided by the UDB
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Communication interface
[2] RESERVED
[1] MASK_SYNC1: SYNC pulse enable / disable for PSI5 interface 1
0: SYNC pulse disabled
1: SYNC pulse enabled (if in synchronous mode, otherwise ignored)
[0] PSI1_EN: Enable PSI5 interface 1
0: interface off
1: interface on
NOPR
No Operation Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Default value:
0
0
R/W
Address:
000011
Type:
R/W
Description:
Write into this register to perform no operation and read the Global Status Bits.
XCT_RUN
SPI_FLT
OTP_CRC_ERR
VAS_UV
VAS_OV
VAS_UVL
-
-
-
-
-
-
7
6
5
4
3
2
1
0
SYNC1_UV
8
SYNC1_SLOW
9
UDB1_FLT
10
SYNC1_TOUT
11
SYNC2_UV
12
SYNC2_SLOW
13
UDB2_FLT
14
SYNC2_TOUT
15
XCT_ABT
Status Register 1
XCT_COMPL
SR1
-
-
-
-
-
-
-
-
Default value:
-
-
RC
Address:
000100
Type:
RC (latched and cleared on read, except if otherwise specified)
Description:
[15] XCT_COMPL: Cross-coupling test completed
[14] XCT_ABT: Cross-coupling test aborted
[13] XCT_RUN: Cross-coupling test running [realtime]
[12] SPI_FLT: SPI fault (CRC error, clock cycles, wrong H/L read operation on sensor data, register
address not valid)
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[11] OTP_CRC_ERR: Error from OTP trimming bits [realtime]
[10] VAS_UV: Under voltage detected on VAS. Latched bit
[9] VAS_OV: Over voltage detected on VAS [realtime]
[8] VAS_UVL: Under voltage detected on VAS. When below VVASU_off, VAS is switched off.
Latched bit. Cleared upon VAS_EN=’0’ confirmation from MCU
[7] SYNC2_TOUT: Exceeded tw timeout of 100 μs on SYNC2 pin during sync pulse (sync pulse
driven by pin source)
[6] UDB2_FLT: Write operation on Upstream Data Buffer 2 occurred while buffer is busy (i.e.
UDB2_BUSY=1)
[5] SYNC2_SLOW: No SYNC pulse generated, delayed SYNC pulse or SYNC voltage <
2.5V/3.5V on PSI5 interface 2
[4] SYNC2_UV: SYNC pulse < 2.5V/3.5V for a time longer than specified on PSI5 interface 2
[3] SYNC1_TOUT: Exceeded tw timeout of 100 μs on SYNC1 pin during sync pulse (sync pulse
driven by pin source)
[2] UDB1_FLT: Write operation on Upstream Data Buffer 1 occurred while buffer is not empty (i.e.
UDB1_BUSY=1)
[1] SYNC1_SLOW: No SYNC pulse generated, delayed SYNC pulse or SYNC voltage < 2.5V/3.5V
on PSI5 interface 1
[0] SYNC1_UV: SYNC pulse < 2.5V/3.5V for a time longer than specified on PSI5 interface 1
OL2
STB2
LKG2
STG2
OT2
UV2/XCT_STG2
-
-
-
-
-
-
7
6
5
4
3
2
1
0
UV1/XCT_STG1
8
OT1
9
STG1
10
LKG1
11
STB1
12
OL1
13
BE1
14
XCT1_R
15
BE2
Status Register 2
XCT2_R
SR2
-
-
-
-
-
-
-
-
Default value:
-
-
RC
Address:
000101
Type:
RC (latched and cleared on read, except if otherwise specified)
Description:
[15] XCT2_R(1): Result of cross-coupling test on PSI5 interface 2
[14] BE2: Buffer empty fault on PSI5 interface 2
[13] OL2: Open load on PSI5 interface 2
[12] STB2Short to VBAT on PSI5 interface 2
Masked towards FSR2 status bit during cross coupling test
[11] LKG2: Leakage to GND on PSI5 interface 2
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Communication interface
[10] STG2: Short to GND on PSI5 interface 2
Cleared upon PSI2_EN='0' confirmation from MCU
[9] OT2: Over temperature on PSI5 interface 2
Cleared upon PSI2_EN='0' confirmation from MCU
[8] UV2/XCT_STG2: Under voltage on PSI5 interface 2
Masked towards FSR2 status bit during cross coupling test
[real time bit except when XCT test is used]
[7] XCT1_R: Result of cross-coupling test on PSI5 interface 1
[6] BE1: Buffer empty fault on PSI5 interface 1
[5] OL1: Open load on PSI5 interface 1
[4] STB1: Short to VBAT on PSI5 interface 1
Masked towards FSR2 status bit during cross coupling test
[3] LKG1: Leakage to GND on PSI5 interface 1
[2] STG1: Short to GND on PSI5 interface 1
Cleared upon PSI1_EN='0' confirmation from MCU
[1] OT1: Over temperature on PSI5 interface 2
Cleared upon PSI1_EN='0' confirmation from MCU
[0] UV1/XCT_STG1: Under voltage on PSI5 interface 1
Masked towards FSR2 status bit during cross coupling test
[real time bit except when XCT test is used]
1. Cross coupling test flags swapped in master mode, see errata n.1830, Section 7: Errata.
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INITDATA_RDY
VAS_ON
FIFO_LCK
RESERVED
RESERVED
SYNC2_STAT
UDB2_BUSY
PSI2_ON
RESERVED
SYNC1_STAT
UDB1_BUSY
PSI1_ON
RESERVED
CLK_FLT
RST
Status Register 3
STS_EN
SR3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default value:
-
-
R
Address:
000110
Type:
R (except if otherwise specified)
Description:
[15] STS_EN: Enable self test status
0: disabled: STS/STSR register not WR (depending on PROG state STS will not be enabled)
1: enabled: STS/STSR register WR
[14] INITDATA_RDY: Initialization data ready
0: not ready
1: ready
[13] VAS_ON: VAS regulator status
0: disabled
1: enabled
[12] FIFO_LCK: FIFO locked status
Note:
This bit is set to '1' when first data is read after FIFO has been filled up
Cleared to '0' as soon as FIFO gets emptied
[11:10] RESERVED
[9] SYNC2_STAT: SYNC2 pin status
0: SYNC2 pin is low
1: SYNC2 pin is high for more than pin filter time.
It can be used to detect short condition on this pin.
Cleared upon read.
[8] UDB2_BUSY: Upstream data buffer 2 is busy with data to be sent
Not cleared upon read
0: not busy
1: busy
[7] PSI2_ON: PSI 2 interface status
0: disabled
1: enabled
[6] RESERVED
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Communication interface
[5] SYNC1_STAT: SYNC1 pin status
0: SYNC1 pin is low,
1: SYNC1 pin is high for more than pin filter time.
It can be used to detect short condition on this pin.
Cleared upon read.
[4] UDB1_BUSY: Upstream data buffer 1 is busy with data to be sent
0: not busy
1: busy
[3] PSI1_ON: PSI 1 interface status
0: disabled
1: enabled
[2] RESERVED
[1] CLK_FLT:
0: no CLK fault
1: reset by internal CLK fault
Cleared upon read.
[0] RST: Reset occurred via internal POR, SW reset (via SPI) or HW reset (via RESET pin)
0: no reset
1: reset occurred
Cleared upon read.
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11
0
0
0
10
9
8
0
0
0
7
6
0
0
5
4
3
0
0
0
2
1
0
0
0
0
UDB1_NOB
12
UDB1_RDY
UDB2_RDY
13
RESERVED
14
Upstream Data Buffer Configuration Register
UDB2_NOB
15
RESERVED
UDBCR
Default value:
0
0
R/W
Address:
000111
Type:
R/W
Description:
[15] RESERVED
[14] UDB2_RDY: Upstream data confirmation.
0: NOP.
1: UDB2 data are ready for sending, and are sent based on the trigger source.
Note:
This bit is used only once, after writing
[13:8] UDB2_NOB: Number of bits in UDB2 to be sent on the PSI5 interface 2.
000000: 1 bit
000001: 2 bits
…
111111: 64 bits
[7] RESERVED
[6] UDB1_RD: Upstream data confirmation.
0: NOP.
1: UDB1 data are ready for sending and are sent based on the trigger source.
Note:
This bit is used only once, after writing.
[5:0] UDB1_NOB: Number of bits in UDB1 to be sent on the PSI5 interface 1
000000: 1 bit
000001: 2 bits
…
111111: 64 bits
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Communication interface
UDB1_X (X = 1…4)
14
13
12
11
10
9
8
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
UDB1_X
15
Upstream Data Buffer 1
Default value:
0
0
R/W
Address:
001000 (UDB1_1) .. 001011 (UDB1_4)
Type:
R/W
Description:
[15:0] UDB1_X (X = 1…4)
The Upstream Data Buffer 1 (4x 16 bits = 64 bits) contains the bits to be sent to sensors as
SYNC pulses on the PSI5 interface 1. The Upstream Data Buffer 1 is formed by the
concatenation of UDB1_1, UDB1_2, UDB1_3 and UDB1_4:UDB1_1 (bits [63:48]), UDB1_2
(bits [47:32]), UDB1_3 (bits [31:16]), UDB1_4 (bits [15:0]). Data are sent on the interface with
LSB first.
If the upstream data buffer is empty (UDBx_BUSY flag is set to '0'), when the trigger source
(SPI, SYNCx pin or timer) is active, a short sync pulse is generated on the interface by default
(independently from tooth gap or pulse width method selection).
UDB2_X (X = 1…4)
14
13
12
11
10
9
8
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
UDB2_X
15
Upstream Data Buffer 2
Default value:
0
0
R/W
Address:
001100 (UDB2_1) .. 001111 (UDB2_4)
Type:
R/W
Description:
[15:0] UDB2_X (X = 1…4)
The Upstream Data Buffer 2 (4x 16 bits = 64 bits) contains the bits to be sent to sensors as
SYNC pulses on the PSI5 interface 2. The Upstream Data Buffer 2 is formed by the
concatenation of UDB2_1, UDB2_2, UDB2_3 and UDB2_4: UDB2_1 (bits [63:48]), UDB2_2
(bits [47:32]), UDB2_3 (bits [31:16]), UDB2_4 (bits [15:0]). Data are sent on the interface with
LSB first.
If the upstream data buffer is empty (UDBx_BUSY flag is set to '0'), when the trigger source
(SPI, SYNCx pin or timer) is active, a short sync pulse is generated on the interface by default
(independently from tooth gap or pulse width method selection).
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SPT (PROG)
13
12
0
0
11
10
9
8
1
0
0
1
7
6
5
4
0
0
0
0
3
2
1
0
1
0
0
1
SPT2
14
SPT1
15
SYNC Pulse Timer
Default value:
0
0
R/W
Address:
010000
Type:
R/W
Description:
[15:8] SPT1 Sync pulse timer 1:
Period for automatic SYNC pulse generation on PSI5 interface 2 (if automatic SYNC pulse
generation is selected).
Minimum allowed period (if SYNC pulse trigger is generated by PIN or SPI).
00000000: 200 μs
…
00001001: 488 μs (default)
…
11111111: 8360 μs
Steps of 32 μs.
[7:0] SPT2 Sync pulse timer 2:
Period for automatic SYNC pulse generation on PSI5 interface 1 (if automatic SYNC pulse
generation is selected)
Minimum allowed period (if SYNC pulse trigger is generated by PIN or SPI).
00000000: 200 μs
…
00001001: 488 μs (default)
…
11111111: 8360 μs
Steps of 32 μs.
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0
0
8
7
6
5
4
3
2
1
0
SYNC1_EN
DOUT1_SEL
9
BR1
VT2_SYNC1_SEL
0
10
RESERVED
RESERVED
0
11
NOTS1
12
READ_INIT_DATA1
13
QC1_SEL
14
Channel 1 Configuration Register 1
TSM1_SEL
15
PAR
CH1_CR1 (PROG)
Default value:
0
0
0
1
0
0
0
0
0
0
0
1
R/W
Address:
010001
Type:
R/W
Description:
[15] PAR: Register parity
Odd parity bit for register bits [15:0]
[14] RESERVED
[13] VT2_SYNC1_SEL: Sync pulse voltage selector for channel 1
0: 2.5 V (PSI5 ver. 2.x common and low power mode)
1: 3.5 V (PSI5 ver. 2.x common mode only, and PSI5 ver. 1.3)
[12] DOUT1_SE: Configuration of DOUT1 pin
0: DOUT1 transmits PSI5 data
1: DOUT1 is an interrupt output
[7] RESERVED
[11:10] TSM1_SEL: Time slot monitoring on PSI5 channel 1
00: monitoring disabled
11: monitoring disabled
01: standard monitoring enabled
10: simple monitoring enabled
[9:8] QC1_SEL: Quiescent current limit on PSI5 interface 1
00: standard current (19 mA)
01: extended current (35 mA)
11: extended current (35 mA)
10: extended current (45 mA)
[6:4] NOTS1: Number of time slots on PSI5 interface 1
001: 1 time slot
…
110: 6 time slots
others: default (3 slots)
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[3] RESERVED
[2:1] BR1: Baud rate of PSI5 interface 1
00: 125 kb/s
11: 125 kb/s
01: 189 kb/s
10: 83.3 kb/s
[0] SYNC1_EN: Asynchronous or synchronous mode on PSI5 interface 1
0: asynchronous mode (SYNC pulse disabled, FIFO data buffer)
1: synchronous mode
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Communication interface
12
11
RESERVED
CH1_BT1_DIS1
CH1_CRCP2
0
0
0
10
9
1
0
8
7
6
0
0
5
4
3
1
0
2
1
0
0
0
CH1_NOB1
13
CH1_CRCP1
14
CH1_NOB2
15
RESERVED
Channel 1 Configuration Register 2
RESERVED
CH1_CR2 (PROG)
Default value:
0
0
1
0
1
R/W
Address:
010010
Type:
R/W
Description:
[15:13] RESERVED
[12] CH1_BT1_DIS1: Bootstrap ch1 disable
0: enabled
1: disabled
[11] CH1_CRCP2: Parity or CRC in time slot 2
0: CRC
1: parity
[10:6] CH1_NOB2: Number of data bits in time slot 2
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
[5] CH1_CRCP1: Parity or CRC in time slot 1
0: CRC
1: parity
[4:0] CH1_NOB1: Number of data bits in time slot 1
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
Settings programmed for time slot 1 are automatically applied to the other time slots in case at least one of the
following conditions in CH1_CR1 register is verified:
– READ_INIT_DATA1='1'
– TSM1_SEL="10" (simple configuration)
– SYNC1_EN='0' (asynchronous mode)
Although the settings of time slot 1 are automatically applied by the logic to other time slots, these are not written in
corresponding configuration registers: so, reading by SPI the configuration of other time slots (TS2 to TS6) would not
give correct values. In above conditions programming on the other time slots would be ignored.
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12
11
RESERVED
RESERVED
CH1_CRCP6
0
0
0
10
9
1
0
8
7
6
0
0
5
4
3
1
0
2
1
0
0
0
CH1_NOB5
13
CH1_CRCP5
14
CH1_NOB6
15
RESERVED
Channel 1 Configuration Register 3
RESERVED
CH1_CR3 (PROG)
Default value:
0
0
1
R/W
Address:
010011
Type:
R/W
Description:
[15:12] RESERVED
[11] CH1_CRCP6: Parity or CRC in time slot 6
0: CRC
1: parity
[10:6] CH1_NOB6: Number of data bits in time slot 6
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
[5] CH1_CRCP5: Parity or CRC in time slot 5
0: CRC
1: parity
[4:0] CH1_NOB5: Number of data bits in time slot 5
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
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1
L9663
Communication interface
SID1 (PROG)
11
10
9
8
1
1
0
1
7
SID1_3
12
6
5
4
3
1
0
0
1
2
1
0
0
1
SID1_1
13
SID1_2
14
RESERVED
15
SID1 Configuration Register
Default value:
0
0
1
0
0
0
R/W
Address:
010101
Type:
R/W
Description:
[15] RESERVED
[14:10] SID1_3: SID bits for time slot 3 of PSI5 interface 1
[19:5] SID1_2: SID bits for time slot 2 of PSI5 interface 1
[4:0] SID1_1: SID bits for time slot 1 of PSI5 interface 1
SID2 (PROG)
11
10
9
8
1
0
0
1
7
SID1_6
12
6
5
4
3
0
1
0
1
2
1
0
0
0
SID1_4
13
SID1_5
14
RESERVED
15
SID2 Configuration Register
Default value:
0
0
1
1
1
1
R/W
Address:
010110
Type:
R/W
Description:
[15] RESERVED
[14:10] SID1_6: SID bits for time slot 6 of PSI5 interface 1
[19:5] SID1_5: SID bits for time slot 5 of PSI5 interface 1
[4:0] SID1_5: SID bits for time slot 4 of PSI5 interface 1
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TSM1_ESn, n=1…6 (PROG)
13
12
11
10
9
8
-
-
-
-
-
7
6
-
-
5
4
3
2
1
0
-
-
-
-
-
-
ST_CH1_n
RESERVED
14
PAR
15
Time Slot Monitoring Channel 1, Earliest Start of Slot n
Default value:
-
-
-
R/W
Address:
010111 (TSM1_ES1) .. 011100 (TSM1_ES6)
Type:
R/W
Description:
default values: TSM1_TES1=0x002c , TSM1_TES2=0x00b5, TSM1 _TES3=0x8149,
TSM1_ES4,5,6= 0x8000.
[15] PAR: Odd parity bit for register bits [15:0]
[14:12] RESERVED
[11:0] ST_CH1_n: Start time of time slot n on PSI5 channel 1
The start time for the given time slot after the rising edge of the SYNC pulse
Steps of 1 μs
TSM1_END (PROG)
13
12
11
10
9
8
0
0
0
0
1
7
6
1
1
5
4
3
2
1
0
1
0
1
1
0
0
ET_CH1_n
RESERVED
14
PAR
15
Time Slot Monitoring Channel 1, End of last Slot
Default value:
1
0
0
R/W
Address:
011101
Type:
R/W
Description:
default value:
[15] PAR: Odd parity bit for register bits [15:0]
[14:12] RESERVED
[11:0] ET_CH1_n: End time of time slot on PSI5 channel 1
The end time of the last given slot after the rising edge of the SYNC pulse
Steps of 1 μs
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Communication interface
DCR (PROG)
14
13
12
11
10
9
8
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
DCR
15
Direct Command Register
Default value:
-
-
WO
Address:
011110
Type:
WO
Description:
A write operation on this register carries out specific actions, depending on the bits
written.
1) In order to perform a software reset of the L9663, the hexadecimal value 0x5555
("unlock reset" command) has first to be written into this register, followed by the
hexadecimal value 0xA5A5 ("reset" command) in the next SPI cycle. If this condition
is not met, no software reset will occur.
2) In order to reset the UDB1 (Upstream Data Buffer 1) for ECU-to-sensor
communication on the PSI5 channel 1, 0x00FF has to be written to this register. This
also resets the UDB1_RDY bit in the UDBCR register to 0.
3) In order to reset the UDB2 (Upstream Data Buffer 2) for ECU-to-sensor
communication on the PSI5 channel 2, 0xFF00 has to be written to this register. This
also resets the UDB2_RDY bit in the UDBCR register to 0.
4) Writing the hexadecimal value 0x1111 into this register locks the configuration
registers (EOP, End Of Programming), i.e. it is no longer possible to write the
configuration registers (marked with PROG). The PROG bit in the SPI Status bits is '0'
after the EOP command has been sent. This bit is reset to '1' at device reset (POR,
RESETN, SW_RESET or clock error).
5) If value 0x9999 is written into this register the writing of STS or STSR registers is
allowed. This is intended to grant a safety enabler for writing these couple of
registers. If value 0x9999 is written in PROG phase, then both STS and STSR
registers are allowed to be written, otherwise only STSR is allowed. To disable writing
these two registers, value 0x9090 has to be written here. The status of the
configuration (STS and STSR registers writeable or not) is shown with the STS_EN
bit in the SR3 register.
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0
0
8
7
6
5
4
3
2
1
0
SYNC2_EN
DOUT2_SEL
9
BR2
VT2_SYNC2_SEL
0
10
RESERVED
RESERVED
0
11
NOTS2
12
READ_INIT_DATA2
13
QC2_SEL
14
Channel 2 Configuration Register 1
TSM2_SEL
15
PAR
CH2_CR1 (PROG)
Default value:
0
0
0
1
1
0
0
0
0
R/W
Address:
011111
Type:
R/W
Description:
[15] PAR: Odd parity bit for register bits [15:0]
[14] RESERVED
[13] VT2_SYNC2_SEL: Sync pulse voltage selector for channel 2
0: 2.5 V (PSI5 ver. 2.x common and low power mode)
1: 3.5 V (PSI5 ver. 2.x common mode only, and PSI5 ver. 1.3)
[12] DOUT2_SEL: Configuration of DOUT2 pin
0: DOUT1 transmits PSI5 data
1: DOUT1 is an interrupt output
[11:10] TSM2_SEL: Time slot monitoring on PSI5 channel 2
00: monitoring disabled
11: monitoring disabled
01: standard monitoring enabled
10: simple monitoring enabled
[9:8] QC2_SEL: Quiescent current limit (extended+ current) on PSI5 interface 2
00: standard current (19 mA)
01: extended current (35 mA)
11: extended current (35 mA)
10: extended+ current (45 mA)
[7] READ_INIT_DATA2: Read sensor initialization data on ch 2
0: init data not stored
1:init data stored in dedicated buffer.
[6:4] NOTS2: Number of time slots on PSI5 interface 2
001: 1 time slot
…
110: 6 time slots
others: default (3 slots)
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0
1
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Communication interface
[3] RESERVED
[2:1] BR2: Baud rate of PSI5 interface 2
00: 125 kb/s
11: 125 kb/s
01: 189 kb/s
10: 83.3 kb/s
[0] SYNC2_EN: Asynchronous or synchronous mode on PSI5 interface 2
0: asynchronous mode (SYNC pulse disabled, FIFO data buffer)
1: synchronous mode
12
11
RESERVED
CH2_BT_DIS2
CH2_CRCP2
0
0
0
10
9
1
0
8
7
6
0
0
5
4
3
1
0
2
1
0
0
0
CH2_NOB1
13
CH2_CRCP1
14
CH2_NOB2
15
RESERVED
Channel 2 Configuration Register 2
RESERVED
CH2_CR2 (PROG)
Default value:
0
0
1
0
1
R/W
Address:
010000
Type:
R/W
Description:
[15:13] RESERVED
[12] CH2_BT_DIS2: Bootstrap ch2 disable
0: enabled
1: disabled
[11] CH2_CRCP2: Parity or CRC in time slot 2
0: CRC
1: parity
[10:6] CH2_NOB2: Number of data bits in time slot 2
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
[5] CH2_CRCP1: Parity or CRC in time slot 1
0: CRC
1: parity
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[4:0] CH2_NOB1: Number of data bits in time slot 1
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
Settings programmed for time slot 1 are automatically applied to the other time slots in case at least one of the
following conditions in CH2_CR2 register is verified:
– READ_INIT_DATA2 = '1'
– TSM2_SEL = ‘10’ (simple configuration)
– SYNC2_EN = '0' (asynchronous mode)
Although the settings of time slot 1 are automatically applied by the logic to other time slots, these are not written in
corresponding configuration registers: so, reading by SPI the configuration of other time slots (TS2 to TS6) would not
give correct values. In above conditions programming on the other time slots would be ignored.
12
11
RESERVED
RESERVED
CH2_CRCP4
0
0
0
10
9
1
0
8
7
6
0
0
5
4
3
1
0
2
1
0
0
0
CH2_NOB3
13
CH2_CRCP3
14
CH2_NOB4
15
RESERVED
Channel 2 Configuration Register 3
RESERVED
CH2_CR3 (PROG)
Default value:
0
0
1
R/W
Address:
100001
Type:
R/W
Description:
[15:12] RESERVED
[11] CH2_CRCP4: Parity or CRC in time slot 4
0: CRC
1: parity
[10:6] CH2_NOB4: Number of data bits in time slot 4
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
[5] CH2_CRCP3: Parity or CRC in time slot 3
0: CRC
1: parity
[4:0] CH2_NOB3: Number of data bits in time slot 3
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
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Communication interface
12
11
RESERVED
RESERVED
CH2_CRCP6
0
0
0
10
9
1
0
8
7
6
0
0
5
4
3
1
0
2
1
0
0
0
CH2_NOB5
13
CH2_CRCP5
14
CH2_NOB6
15
RESERVED
Channel 2 Configuration Register 4
RESERVED
CH2_CR4 (PROG)
Default value:
0
0
1
0
1
R/W
Address:
100010
Type:
R/W
Description:
[15:12] RESERVED
[11] CH2_CRCP6: Parity or CRC in time slot 6
0: CRC
1: parity
[10:6] CH2_NOB6: Number of data bits in time slot 6
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
[5] CH2_CRCP5: Parity or CRC in time slot 5
0: CRC
1: parity
[4:0] CH2_NOB5: Number of data bits in time slot 5
01000: 8 data bits
…
11100: 28 data bits
others: default (20 bit)
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SID3 (PROG)
11
10
9
8
1
1
1
0
7
6
5
4
3
1
0
1
0
2
1
0
0
1
SID_CH2_S1
12
SID_CH2_S2
13
SID_CH2_S3
14
RESERVED
15
SID3 Configuration Register
Default value:
0
1
0
0
0
0
R/W
Address:
100011
Type:
R/W
Description:
[15] RESERVED
[14:10] SID_CH2_S3: SID bits for time slot 3 of PSI5 interface 2
[19:5] SID_CH2_S2: SID bits for time slot 2 of PSI5 interface 2
[4:0] SID_CH2_S1: SID bits for time slot 1 of PSI5 interface 2
SID4 (PROG)
11
10
9
8
1
0
1
0
7
6
5
4
3
0
1
1
0
2
1
0
0
0
SID_CH2_S4
12
SID_CH2_S5
13
SID_CH2_S6
14
RESERVED
15
SID4 Configuration Register
Default value:
0
1
0
1
1
R/W
Address:
100011
Type:
R/W
Description:
[15] RESERVED
[14:10] SID_CH2_S6: SID bits for time slot 6 of PSI5 interface 2
[19:5] SID_CH2_S5: SID bits for time slot 5 of PSI5 interface 2
[4:0] SID_CH2_S4: SID bits for time slot 4 of PSI5 interface 2
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TSM2_ESn, n=1…6 (PROG)
13
12
11
10
9
8
0
0
0
0
0
7
6
0
0
5
4
3
2
1
0
0
0
0
0
0
0
ST_CH2_n
RESERVED
14
PAR
15
Time Slot Monitoring Channel 2, Earliest Start of Slot n
Default value:
1
0
0
R/W
Address:
100101 (TSM1_ES1) .. 101010 (TSM1_ES6)
Type:
R/W
Description:
default values: TSM2_TES1=0x002c, TSM2_TES2=0x00b5, TSM2 _TES3=0x8149,
TSM2_ES4,5,6= 0x8000.
[15] PAR: Odd parity bit for register bits [15:0]
[14:12] RESERVED
[11:0] ST_CH2_n: Start time of time slot n on PSI5 channel 2
The start time for the given time slot after the rising edge of the SYNC pulse
Steps of 1 μs
TSM2_END (PROG)
13
12
11
10
9
8
0
0
0
0
1
7
6
1
1
5
4
3
2
1
0
1
0
1
1
0
0
ET_CH2_n
RESERVED
14
PAR
15
Time Slot Monitoring Channel 2, End of last Slot
Default value:
1
0
0
R/W
Address:
101011
Type:
R/W
Description:
[15] PAR: Odd parity bit for register bits [15:0]
[14:12] RESERVED
[11:0] ET_CH2_n: End time of time slot on PSI5 channel 2
The end time of the last given slot after the rising edge of the SYNC pulse
Steps of 1 μs
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STS (PROG)
11
0
0
9
8
0
0
7
DOUTTP
10
6
5
4
3
0
0
0
0
2
1
0
0
0
RESERVED
12
DOUTSEL
13
RESERVED
14
FCRCM
15
Self-Test Setting - prog time
Default value:
0
0
0
0
0
R/W
Address:
101100
Type:
R/W
Description:
[15] FCRCM: Force CRC mismatch on MISO
0: NOP
1: the least significant bit of CRC is inverted
[14:11] RESERVED
[10] DOUTTP
Value ('0' or '1') to be output on DOUTx pin
[9:5] DOUTSEL: DOUTx channel activation
10101: DOUT1
10110: DOUT2
others: ignored
[4:0] RESERVED
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10
0
0
0
9
8
7
6
0
0
5
4
3
2
0
0
1
0
TBEC
11
RESERVED
FTSIDM
12
SCCT
13
ACCT
14
RESERVED
15
FSIDM
Self-Test Setting - run time
RESERVED
STRS
Default value:
0
0
0
0
0
0
0
0
0
R/W
Address:
101101
Type:
R/W
Description:
[15] RESERVED
[14] FSIDM: Force SID mismatch
0: NOP
1: the behavior of the MUX which selects SID, CRC/parity and Number of bits, is changed
according to the following table:
slot1 <-->slot2
slot3<-->slot4
slot6<-->slot5
[13] FTSIDM: Force TSID mismatch
0: NOP
1: the behavior of MUX that selects sensor data (and SID) for each time slot is modified in this
way:
– slot2 sensor data -> slot1 sensor data
– slot4 sensor data ->slot3 sensor data
– slot6 sensor data ->slot5 sensor data
Sensor data of time slots 1, 3 and 5 keep a buffer empty value.
[12:6] RESERVED
[5] ACCT: Abort cross-coupling test
0: NOP
1: Stop cross-coupling test immediately
[4:3] SCCT: Start cross-coupling test
11: ignored
11: ignored
01: start cross-coupling test in master mode
10: start cross-coupling test in slave mode
[2:1] RESERVED
[0] TBEC: Test buffer empty check
0 : after a read operation 1F0 is written into the buffer (normal operation)
1 : after a read operation old data are left In the buffer
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1
0
7
6
5
0
0
0
4
3
0
0
2
1
0
FIXED_THR
8
RESERVED
0
9
FREEZE_DIS
0
10
DATA_FILT_SEL
11
BLANKING_SEL
12
TRACKING_SEL
13
FIXED_THR_SEL
14
STG_MASK
15
Advanced Settings 1
RESERVED
ADVSET1 (PROG)
0
0
0
Default value:
0
1
0
0
R/W
Address:
101110
Type:
R/W
Description:
Advanced settings for interface 1
[15] STG_MASK: Short to ground does not switch off channel
0: short to ground switches off the channel after filter time
1: short to ground does NOT switch off the channel
[14:11] FIXED_THR_SEL: Fixed threshold setting for PSI5 channel 1
Ibase + 5.5mA + (15-5.5)/16*bits[14:11]mAIbase + 5.5mA + (15-5.5)/[16*bits[14:11]]mA(1)
[10] RESERVED
[9] TRACKING_SEL
0: Standard threshold tracking algorithm (default, recommended)
1: Fast tracking algorithm
[8:7] BLANKING_SEL: Blanking time selector at sensor startup:
00/11 : 128 μs
01 : 5 ms
10: 10 ms
[6:3] DATA_FILT_SEL: Deglitch filter adjust
Baud rate = 189K: filter time = (16 + <DATA_FILT_SEL>) * Tosc
Baud rate = 125K or 83.3K: filter time = (24 + <DATA_FILT_SEL>) * Tosc
Note:Tosc is the period of the 16 MHz oscillator
[2] FREEZE_DIS: Freezing of base current tracking after start bits are detected
0: frozen
1: not frozen
[1] RESERVED
[0] FIXED_THR: Adaptive / fixed threshold
0: adaptive threshold
1: fixed threshold
1. The selectable threshold is in the range: Ibase+5.5 mA to Ibase+14.4 mA
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0
0
0
0
7
6
5
4
3
0
0
0
0
2
1
0
SYNC_DELAY_PSI1_PSI2
9
STBITERR_RST_CNT1
10
STBIT_DC_CK_DIS1
11
PERIOD_M_DIS1
12
BITTIME_H_DET1
RESERVED
13
RESERVED
14
REACTTIME
15
STBITERR_RST_CNT2
Advanced Settings 2
STBIT_DC_CK_DIS2
ADVSET2 (PROG)
PERIOD_M_DIS2
Communication interface
BITTIME_H_DET2
L9663
Default value:
0
0
0
0
0
0
0
0
R/W
Address:
101111
Type:
R/W
Description:
Advanced settings for interface 2
[15] REACTTIME: Reaction time for FLL module reset after error detection
0: 0ms
1: 20ms
[14:13] RESERVED
[12] BITTIME_H_DET2: Manchester decoder Bit time error detect on PSI2
0: bittime too high error is not detected as error
1: bittime too high error is detected as error
[11] PERIOD_M_DIS2: Disable bit time Period measurement for frame decoding on PSI2
0: measurement of start bits period enabled
1: measurement of start bits period disabled
[10] STBIT_DC_CK_DIS2: Duty cycle check (DC>0.25) on start bits
0: duty cycle check enabled
1: duty cycle check disabled
[9] STBITERR_RST_CNT2: Manchester decoder Bit counter reset upon start bit error
0: start bit error does not reset the counter
1: start bit error resets the counter
[8:7] RESERVED
[6] BITTIME_H_DET1: Manchester decoder Bit time error detect on PSI1
0: bittime too high error is not detected as error
1: bittime too high error is detected as error
[5] PERIOD_M_DIS1: Disable bittime Period measurement for frame decoding on PSI1
0: measurement of start bits period enabled
1: measurement of start bits period disabled
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[4] STBIT_DC_CK_DIS1: Duty cycle check (DC>0.25) on start bits
0: duty cycle check enabled
1: duty cycle check disabled
[3] STBITERR_RST_CNT1: Manchester decoder Bit counter reset upon start bit error
0: start bit error does not reset the counter
1: start bit error resets the counter
[2:0] SYNC_DELAY_PSI1_PSI2: SYNC pulse time delay between PSI5 interface 1 and 2 in case of
automatic SYNC pulse generation
This bit takes effect only in case of automatic generation on both interfaces
000: no delay
001 - 111: 2μs/LSB
1
0
7
6
5
0
0
0
4
3
0
0
2
1
0
FIXED_THR
8
RESERVED
0
9
FREEZE_DIS
0
10
DATA_FILT_SEL
11
BLANKING_SEL
12
TRACKING_SEL
13
FIXED_THR_SEL
14
STG_MASK
15
Advanced Settings 3
RESERVED
ADVSET3 (PROG)
0
0
0
Default value:
0
1
0
0
R/W
Address:
110000
Type:
R/W
Description:
Advanced settings for interface 3
[15] STG_MASK: Short to ground does not switch off channel
0: short to ground switches off the channel after filter time
1: short to ground does NOT switch off the channel
[14:11] FIXED_THR_SEL: Fixed threshold setting for PSI5 channel 2
Ibase + 5.5mA + (15-5.5)/16*bits[14:11]mA (1)
[10] RESERVED
[9] TRACKING_SEL:
0: Standard threshold tracking algorithm (default, recommended)
1: Fast tracking algorithm
[8:7] BLANKING_SEL: Blanking time selector at sensor startup:
00 : 128 μs
11: 128 μs
01: 5 ms
10: 10 ms
[9] TRACKING_SEL:
0: Standard threshold tracking algorithm (default, recommended)
1: Fast tracking algorithm
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[8:7] BLANKING_SEL: Blanking time selector at sensor startup:
00 : 128 μs
11: 128 μs
01: 5 ms
10: 10 ms
[6:3]] DATA_FILT_SEL: Deglitch filter adjust
Baud rate = 189K: filter time = (16 + <DATA_FILT_SEL>) * Tosc
Baud rate = 125K or 83.3K: filter time = (24 + <DATA_FILT_SEL>) * Tosc
Note: Tosc is the period of the 16 MHz oscillator
[2] FREEZE_DIS: Freezing of base current tracking after start bits are detected
0: frozen
1: not frozen
[1] RESERVED
[0] FIXED_THR: Adaptive / fixed threshold
0: adaptive threshold
1: fixed threshold
1. The selectable threshold is in the range: Ibase+5.5 mA to Ibase+14.4 mA.
ADVRD1
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
BASE1
RESERVED
15
Advanced Read 1
Default value:
-
-
-
R/W
Address:
110010
Type:
RO
Description:
[15:10] RESERVED
[9:0] BASE1: Base current level on PSI5 channel 1
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ADVRD2
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
DELTA1
RESERVED
15
Advanced Read 2
Default value:
-
-
-
RO
Address:
110011
Type:
RO
Description:
[15:10] RESERVED
[9:0] DELTA1: Delta current level I(threshold) - I(base) on PSI5 channel 1
ADVRD3
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
THRESH1
RESERVED
15
Advanced Read 3
Default value:
-
-
-
RO
Address:
110100
Type:
RO
Description:
[15:10] RESERVED
[9:0] THRESH1: Threshold current level on PSI5 channel 1 (absolute value)
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ADVRD4
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
BASE2
RESERVED
15
Advanced Read 4
Default value:
-
-
-
RO
Address:
110101
Type:
RO
Description:
[15:10] RESERVED
[9:0] BASE2: Base current level on PSI5 channel 2
ADVRD5
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
DELTA2
RESERVED
15
Advanced Read 5
Default value:
-
-
-
RO
Address:
110110
Type:
RO
Description:
[15:10] RESERVED
[9:0] DELTA2: Delta current level I(threshold) - I(base) on PSI5 channel 2
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ADVRD6
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
THRESH2
RESERVED
15
Advanced Read 6
Default value:
-
-
-
RO
Address:
110111
Type:
RO
Description:
[15:10] RESERVED
[9:0] THRESH2: Threshold current level on PSI5 channel 2 (absolute value)
DEVID
14
13
12
11
10
9
8
-
-
-
-
-
7
6
5
-
-
-
4
3
2
1
0
-
-
-
-
-
VER_ID
RESERVED
15
Device Version ID
Default value:
-
-
-
RO
Address:
111000
Type:
RO
Description:
[15:10] RESERVED
[9:0] VER_ID: Device Version ID
Static value for silicon version.
b<9:6>: ST reserved
b<5:3>: mask set reference "000"=A,"001"=B,…
b<2:0>: mask set revision "000"=A,"001"=B,…
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5.2
SPI interface
5.2.1
Physical layer and signal description
Figure 26. SPI interface
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63,0DVWHU
63,6ODYH
0,62
*$3*36
Chip Select (CS)
The communication interface is deselected when this input signal is logically high. A falling
edge on CS enables and starts the communication, while a rising edge finishes the
communication and the command is executed if a valid frame has been sent. During
communication start and stop, the Serial Clock (SCLK) has to be logically low. The MISO
line is in high impedance when CS is high.
In order to considerably reduce the number of CS lines and pins on the system, while still
allowing connecting different devices, an address multiplexing approach is implemented in
the device with cabled address "00".
This means that if CS is low the device is not selected unless the MOSI bits 31 and 30 of the
frame matches the device address.
This feature can be disabled by SW, writing a dedicated SPI bit.
The default state after reset (sw, hw or by internal clock fault) is in the address multiplexing
mode.
Serial Clock (SCLK)
This SCLK provides the clock of the SPI. Data present on the MOSI line is latched on the
rising edge of Serial Clock (SCLK) into the internal shift registers, while data from the
internal shift registers are shifted out on the MISO line on the falling edge.
MOSI
This input is used to transfer data serially into the device. Data is latched on the rising edge
of Serial Clock (SCLK).
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MISO
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (SCLK). MISO is in high impedance under POR condition.
5.2.2
Clock and data characteristics
A microcontroller with its SPI peripheral running in the following mode can drive the SPI:
CPOL = '0' and CPHA = '1'.
The communication frame starts with the falling edge of the CS (Communication Start).
SCLK has to be low.
The MOSI data are then latched on all following falling SCLK edges into the internal shift
registers.
After Communication Start, the MISO will leave tri-state and shift the MSB of the output data
on MISO. On all following rising SCLK edges data are shifted out through the internal shift
registers to MISO.
The communication frame is finished with the rising edge of CS. If a valid communication
took place (e.g. correct number of SCLK cycles), the operation requested will be performed
(Write or Clear operation).
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5.2.3
Communication interface
Frame definition
Global status bits (standard mode)
31
30
29
28
27
26
SPIE
FSR1
FSR2
RSTB
PROG
GSB
Global status bits (address multiplexing mode)
31
30
29
28
27
26
-
-
-
RSTB
PROG
GSB
Type: R
Bit Description
[31] SPIE: SPI error
The SPIE bit is a logical OR combination of errors related to wrong SPI communication (wrong
SCLK count, wrong CRC, wrong SPI operation). It is also reported as SR1[12] bit and it is
automatically cleared when this register is read.
[30] FSR1: Fault status register 1 flag
The FSR1 bit is set to '1' if at least one of the bits SR1[11:0] is active.
[29] FSR2: Fault status register 2 flag
The FSR2 bit is set to '1' if at least one of the bits SR2[14:8] or SR2[6:0] is active.
[28] RSTB: Reset bit
The RSTB bit indicates a device reset (POR, RESETN or SW_RESET). In case this bit is set,
all internal Control Registers are set to their default values and kept in that state until the bit is
cleared. It is automatically cleared by any valid SPI communication.
[27] PROG: End of programming
The EOP bit indicates the end of the device programming phase (PROG registers).
[26] GSB: Global Status Bit
The GSB bit is a logical OR combination of Bit 31 to Bit 27 and buffer empty error bit. This
stands also for address multiplexing mode.
The global status bits are shifted out on the MISO line on every SPI access. They provide
information about the current device status.
5.2.4
Communication frames
In the following frames, all fields are written with MSB at left side and 'X' represents a "don't
care" value.
The bit RW is used to select the operation type on the internal register: read (RW=0), write
(RW=1).
CRC on MOSI is calculated over bits 31:5. CRC on MISO is:
a) CRC from the sensor
b) CRC calculated over bits 26:3
depending on GCR1[1].
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CRC generation is based on the same calculation scheme used for PSI5 sensor data
(generator polynomial g(x)=1+x+x3, initialization value "111") with MSB passed first.
Register Address out on MISO is checked internally with the register decoded address; a
CRC error is generated in case of mismatch (last two bits are inverted)
Figure 27. Operation on internal register (with upstream data buffer)
Figure 28. Init data reading
Sensor data Reading:
Timeslot coding: Timeslot1=001, …, timeslot6=110
SID and Gbit are supported only for 10 - 16 bit and enabled by 1 single configuration bit =
GCR1(2)
Two kinds of transfer are possible:
1. No SID, payload ≤ 20 bit; SID and GBIT, payload ≤ 16 bit: one transfer needed
2. No SID, payload > 20 bit: two transfers are needed.
In case 1) the L/H bit must be L (0); if a H (1) is requested on a sensor which fits in 1 SPI
frame a SPIE is generated and a CRC error is generated.
In case 2) the device expects a sequence H - L on the L/H bit to transmit first the MSB part
of the data and then the LSB. If the sequence is not the one above, a SPI error is generated
and a CRC error is generated.
To guarantee a safe communication with two SPI transfers:
if CRC is the one from the sensor (GCR1(1)=0) , CRC is the same on both transfers
and it's the one from the sensor;
if CRC is calculated on SPI (GCR1(1)=1), CRC is calculated over bits 26:3 in each
frame.
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Communication interface
Figure 29. Sensor data reading
In case of sensor fault conditions, error codes are sent in the first 10 bits of the data field
(see Table 6 on page 31). The lower 10 bits are filled with '0'.
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103
Communication interface
L9663
SPI error handling
The SPI message from the external microcontroller is monitored. The following errors are
detected:
the CRC on the MOSI line is not correct;
incorrect SPI operation (e.g. an attempt to write a read-only register);
the number of SPI clock cycles is not equal to 32.
In case any of the above-mentioned errors is detected, the MOSI message is rejected, the
SPI failure bit in the SR1 register is set and the SPIE status bit in the next MISO message is
set to '1'.
5.3
Direct interface
The direct interface has the following features:
DOUTx output for Manchester-coded sensor data
SYNCx input for synchronous pulse voltage trigger
Deglitch filter for SYNCx input of PSI5 transceiver
The reference voltage for the threshold levels of DOUTx pins is VDD.
The direct interface is only used in transceiver IC mode 2 (data decoding in the μC).
To use direct mode slot monitor should be disabled on the channel.
In order to have good device functionality all registers, except the ones listed below, must be
configured if default values do not match the application.(j)
The registers that do not need a configuration are the following: SIDx, TSMx_ESy,
TSMx_END.
Optional configuration: SPT (if sync pulse period is smaller than 500 μs), ADVSET1/2/3 if a
particular set of tracking is required, UDBCR, UDBx_y to use tooth gap method, DCR, STS,
STSR.
j.
86/104
Registers needing a configuration: CHCNT, CHx_CR1, CHx_CR2, CHx_CR3, CHx_CR4, GCR1.
DocID028693 Rev 1
L9663
6
Electrical characteristics
Electrical characteristics
Table 10. Operating conditions
Parameter / Condition(1)
Symbol
VVB
VVASSUP
VVDD
Tj
Min
Typ
Max
Unit
VB input voltage
4.8
–
35
V
VASSUP input voltage (in case VAS pre-regulator is
used)
4.8
–
35
V
3
–
6
V
-40
–
175
°C
VDD input voltage
Junction temperature
1. Unless otherwise specified.
Table 11. VINTx internal supply
Symbol
Parameter / Condition
Min
Typ
Max
Unit
VDDwu_H
VDD voltage level for power up
2.3
2.5
2.7
V
VDDwu_L
VDD voltage level for power down
1.5
1.8
2.3
V
VINTDuv
VINTD under voltage threshold
2.7
–
2.9
V
VINTDov
VINTD over voltage threshold
3.47
–
3.66
V
VINTAuv
VINTA under voltage threshold
2.97
–
3.13
V
VINTAov
VINTA over voltage threshold
3.47
–
3.66
V
100
200
300
mV
DGNDOPEN
DGND ground loss threshold
GND1 = GND2 = 0
TPOR
Filter time for power on reset output (vintx ov/uv,
dgnd open)
5
–
45
μs
TWAKE
Start-up time in no fault conditions (from VDD=3V
to internal power on reset set to ‘1’) (Design info)
–
–
250
μs
IlimVINTD
VINTD current limitation
80
–
150
mA
CVINTD
VINTD filter capacitance (Test info)
60
100
140
nF
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Electrical characteristics
L9663
Table 12. VAS supply
Symbol
Min
Typ
Max
Unit
Supply voltage VAS normal operation (Test info)
4.3
–
16
V
Max. voltage ripple on VAS (1) (Test info)
-1.5
–
1
V
Slew rate of the voltage ripple on VAS
(Test info)
–
–
50
mV/μs
I_VAS,eff
Effective current for VAS: (Design info)
2 * 60 mA (effective for 45 mA supply current;
30mA data current)
+ 5mA current for all included Transceiver blocks
supplied from VAS.
–
–
125
mA
I_VAS,peak
Dynamic current for VAS: (Design info)
1 * 75 mA (45 mA supply current; 30mA data
current)
+ 130 mA (STG on 2nd IF)
+ 5 mA current for all included Transceiver blocks
supplied from VAS.
–
–
210
mA
VAS
VAS,rip
SR_VAS,rip
Parameter / Condition
1. This voltage ripple, that will anyhow not exceed minimum VAS voltage value, does not lead to corrupted
data reception.
Table 13. VAS external MOS
Symbol
Parameter / Condition(1)
Min
Typ
Max
Unit
-20
–
20
V
1
–
2.5
V
-10
–
10
μA
Drain to Source on state resistance at
VGS = 4.5 V, ID = 2.6 A (Test info)
–
–
150
mΩ
Ciss_ext
Input Capacitance at VGS=0V, VDS=25V f=1MHz
(Test info)
–
–
1100
pF
Coss_ext
Output Capacitance at VGS=0V, VDS=25V
f=1MHz (Test info)
–
–
170
pF
tdon_ext
Turn on delay time at VDS=30V, VGS=4.5V,
ID=2.6A, RG=16Ω (Test info)
–
–
20
ns
Vgs_ext
Vgsth_ext
Vgl_ext
Rdson_ext
Gate to Source voltage (Test info)
Gate threshold voltage, with VDS = VGS,
ID = 250 μA (Test info)
Gate leakage current at VGS = 20 V, VDS = 0 V
(Test info)
1. Main parameters for choice of external component.
88/104
DocID028693 Rev 1
L9663
Electrical characteristics
Table 14. VAS pre regulator
Symbol
Parameter / Condition
Min
Typ
Max
Unit
-2.5%
5.3
+2%
V
VAS5DC
Regulated VAS voltage
5.3 V output selection
VSUP ≥ 5.8 V (supply of external NFET)
VASSUP ≥ 5.3 V
Static load condition: 4 mA ≤ Iload ≤ 210 mA
VAS7DC
Regulated VAS voltage
7.6 V output selection
VSUP > 8 V (supply of external NFET)
VASSUP ≥ 7.6V
Static load condition 4 mA ≤Iload ≤210 mA
-4%
7.6
4%
V
VAS5LS
Maximum ripple on VAS output in load step
condition
5.3 V output selection
VSUPR ≥ 5.8 V (supply of external NFET)
VASSUP ≥ 5.3 V
Transient load: 0 mA to 210 mA and 210 mA
to 0 mA in 0.5 μs
-5%
VAS5DC
+5%
V
VAS7LS
Maximum ripple on VAS output in load step
condition
7.6 V output selection
VSUP > 8V (supply of external NFET)
VASSUP ≥ 7.6 V
Transient load: 0 mA to 210 mA and 210 mA
to 0 mA in 0.5 μs
-5%
VAS7DC
5%
V
VAS
Maximum ripple voltage on the transceiver
during current modulation (dI/dt = ±60mA/ μs)
–
–
|2|
%
VGS passive pull-down clamping structure
(device off)
Test condition: Isink = 100 μA
–
–
1.5
V
VGS active pull-down current (regulator
disabled, VAS_EN=0, device on)
–
1
1.2
mA
VGS to VAS passive clamp (VAS shorted to
ground, regulator switched on)
8
12
16
V
1.7
4.7
6.3
μF
0
–
0.2
Ω
11.82
–
13
V
–
–
1
ms
VVGS_RPD
IVGS_IPD
–
C2
ESRC2
VASSUPuv
VASton
Decoupling capacitor (Test info)
ESR of decoupling capacitor (Test info)
VASSUP under voltage threshold for enabling
of internal charge pump
VAS startup timing after VAS_EN=’1’ (on by
default at POR release)
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Electrical characteristics
L9663
Table 15. VSYNCx
Symbol
Min
Typ
Max
Unit
Voltage limitation on CB
V(BHx)-V(BLx)
–
–
8
V
VCBov
VB over voltage threshold for bootstrap disabling
18
–
21
V
tch_ini
Initial time interval necessary to charge CB =
10μF from 0V to 4V@VB = 4.8V
–
–
2
ms
Recharge time for bootstrap capacitor
min. sync pulse amplitude = 2.5 V; all sync pulses
are long (for logical 1, pulse width); VB = 5.2 V.
–
–
tch_reset1
Start of CB1 charging after release of internal
POR
–
–
1
μs
tch_reset2
Delay between start of CB2 charging with respect
to start of CB1 charging (staggered charging)
–
2
–
ms
VCBclamp
tch
Parameter / Condition
130
μs
VB
VB voltage for full functionality
5.2
–
35
V
VB
VB voltage for full functionality (low power mode)
4.8
–
5
V
5
10
15
μF
CBx
Capacitor value
Table 16. PSI5 output supply
Symbol
Min
Typ
Max
Unit
IPSIx
Interface quiescent current (standard
current)
-19
–
-4
mA
IPSIx
Interface quiescent current (extended
current)
-35
–
-4
mA
IPSIx
Interface quiescent current (extended+
current)
-45
–
-4
mA
VPSIx,max
Max. output voltage excluding sync.
pulse (internal regulation, VAS=16V)
–
–
11
V
VPSIxsync,max
Max. output voltage including sync.
pulse (internal regulation, VAS=16V)
–
–
16.5
V
Static short to ground current limitation
for each transceiver output PSIx
-130
–
-80
mA
Filter time for current limitation
detection
128
–
–
μs
tIblank
Blanking time on current limitation
detection (active at PSIx output startup in addition to the filter time)
Selectable by SPI: 128 μs/5ms/10ms
128
–
–
μs
RINT
Internal resistance of complete path
(from input pin VAS to output pin PSIx,
Iload=<75mA) VAS from
4
–
8.5
W
TOT
Over temperature detection
175
–
200
°C
ISTG
tIfilt
90/104
Parameter / Condition
DocID028693 Rev 1
L9663
Electrical characteristics
Table 16. PSI5 output supply (continued)
Symbol
Parameter / Condition
Min
Typ
Max
Unit
ILTG_std
Leakage to ground detection (standard
current)
-9%
-23
+13%
mA
ILTG_ext
Leakage to ground detection
(extended current)
-9%
-42
+9%
mA
ILTG_ext+
Leakage to ground detection
(extended+ current)
-9%
-54
+9%
mA
Open load detection
-4
-2.5
-1
mA
VSTB
Short to battery reverse voltage
detection
10
100
mV
tSTB
Short to battery reverse voltage filter
time
7
10
16.5
μs
ISTB
Static reverse current into PSIx pin
VPSIx > VAS
–
–
20
mA
IBO
Base current
Default value of receiver
-9%
15
+9%
mA
Trigger point for signal current
threshold (fixed threshold mode,
assuming a nominal programming of
IBO + 6 mA for low power mode, see
ADVSETx(FIXED_THR_SEL))
IBO + 5.14
IBO + 6
IBO + 6.86
Trigger point for signal current
threshold (fixed threshold mode,
assuming a nominal programming of
IBO + 12mA for common mode, see
ADVSETx(FIXED_THR_SEL))
IBO + 10.29
IBO + 12
IBO + 13.71
IOL
IPSIxTH
mA
VPSIxU
PSIx under voltage monitoring
threshold
3.1
3.3
3.5
V
tPSIxU
PSIx under voltage monitoring filter
time
200
–
–
μs
–
32
–
mA
IXCT
PSIx pull down current for cross
coupling test
Table 17. PSI5 receiver
Symbol
Parameter / Condition
Typ
Max
Unit
-
kbps
fslow
PSI5 baud rate (slow)
-
83.3
fstd
PSI5 baud rate (standard)
-
125
ffast
PSI5 baud rate (fast)
-
189
-
kbps
8/10
-
28
bit
Data frame length (without overhead)
1.
Min
(1)
kbps
Also 8 bit compatibility according to PSI5 v1.3.
DocID028693 Rev 1
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Electrical characteristics
L9663
Figure 30. Sync generator
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Table 18. Sync generator
Symbol
Min
Typ
Max
Unit
1
-
5
μs
tw
Trigger signal duration to generate a
short Sync Pulse (std PSI5) (1)
Vt2
Voltage increase of sync pulse
normal operation (Ibase ≤ 35 mA,
VB ≥ 4.8 V)
2.5
-
-
V
Vt2
Voltage increase of sync pulse
normal operation (Ibase ≤ 35 mA,
VB ≥ 5.2 V
2.5/3.5
-
-
V
SRrise
Slew rate of rising sync slope
0.43
-
1.5
V/μs
SRfall
Slew rate of falling sync slope
-1.5
-
-
V/μs
-
0
-
μs
-3.25
-
-
μs
-
-
7
μs
16/43
-
-
μs
10
-
14
μs
-
-
35/62
μs
44/71
-
-
μs
t0
Reference time (@ 0.5 V on top of
VCEbase)
t1
Sync signal earliest start
Delta current less than 2 mA
t2
Sync signal sustain start (@ Vt2)
t3
Sync signal sustain time (short/long
pulse)
tsync_slow
t4
tSlot 1 Start
92/104
Parameter / Condition
Slow Vsync detection time
Discharge time limit (short/long pulse)
Start of first sensor data word
(short/long pulse)
DocID028693 Rev 1
L9663
Electrical characteristics
Table 18. Sync generator (continued)
Symbol
Parameter / Condition
Min
Typ
Max
Unit
ILimit
Static current limitation for each
transceiver output PSIx (only for sync
pulse generator)
-280
-
-110
mA
td_SPI
Delay between end of SPI trigger
command and start of sync pulse (t1)
-
-
2.2
μs
td_SYNC
Delay between SYNC pin command
filtered (tdeglitch not included) and start
of sync pulse (t1)
-
-
1
μs
1. Only the short sync pulse can be triggered by PIN (tw ≤5 μs), see errata 1822, Section 7.
Table 19. Reset
Symbol
Parameter / Condition
Min
Typ
Max
Unit
VRESETN_THR_High
Input high threshold of RESETN pin
-
-
2
V
VRESETN_THR_Low
Input low threshold of RESETN pin
1
-
-
V
Hysteresis of RESETN pin thresholds
100
150
-
mV
IRESETN
Input Pull-Down current source
30
45
60
μA
tRESETN
Reset detection filter time
1-
-
4
μs
Min
Typ
Max
Unit
VRESETN_HYS
Table 20. VAS under/over voltage monitoring
Symbol
Parameter / Condition
VVASU_low
VAS under voltage monitoring threshold
(low voltage mode)
4.5
-
4.85
V
VVASU_inc
VAS under voltage monitoring threshold
(increased voltage mode)
6.5
-
6.95
V
VVASO_low
VAS over voltage monitoring threshold
(low voltage mode)
6.5
-
6.95
V
VVASO_inc
VAS over voltage monitoring threshold
(increased voltage mode)
8.2
-
8.8
V
VVASU_off
VAS low under voltage monitoring threshold (both
increased and low voltage modes)
When below this threshold, VAS is switched off
1
-
1.4
V
tVASU
VAS under/over voltage monitoring filter time
3
-
4
μs
tVASblk1
VAS under voltage switch-off blanking time (at
VAS activation)
-
1
-
ms
tVASuoff2
VAS automatic switch-off filter time (after VAS
activation)
9
-
12
μs
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Electrical characteristics
L9663
Table 21. Synchronous pulse amplitude monitoring
1.
Symbol
Parameter / Condition
Min
Typ
Max
Unit
VAsync_l
Sync pulse amplitude under voltage monitoring
threshold (if VT2_SYNCx_SEL bit is set to 0) (1)
2
-
2.8
V
VAsyncU
Sync pulse amplitude under voltage monitoring
threshold (if VT2_SYNCx_SEL bit is set to 1)
3.5
-
3.85
V
tAsync_V
Filter time for insufficient sync pulse amplitude
-
2
-
μs
The sync pulse amplitude and the diagnostic threshold voltage level are referred to the inputs of the
difference amplifier, i.e. VAsync = V(PSIx-VAS).
Table 22. Time slot monitoring
Symbol
Parameter / Condition
tTSM
Min
Typ
Max
Unit
Resolution of the time slots
-
1
-
μs
Required register size for each time slot
-
12
-
bit
Table 23. Digital I/O
Symbol
Parameter / Condition
Min
Typ
Max
Unit
Vin_High
Input high threshold
-
-
2
V
Vin_Low
Input low threshold
0.8
-
-
V
Vin_HYS
Hysteresis
100
150
-
mV
Iin_pu
Input pull up current (pins CS, MOSI, SCLK)
-30
-45
-60
μA
Iin_pd
Input pull down current (pins SYNC1, SYNC2,
CLKIN)
30
45
60
μA
VDD-0.4
-
VDD
V
-
-
0.4
V
Vout_High Output high level (Isource = 2 mA)
Vout_Low
Output low level (Isink = 2 mA)
Table 24. Frequency references
Symbol
Parameter / Condition
Min
Typ
Max
Unit
fCLK
Internal oscillator frequency (FLL
disabled)
15.2
16
16.8
MHz
fCLK
Internal oscillator frequency (FLL enabled,
normal CLKIN frequency)
15.84
16
16.16
MHz
fCLKIN-normal
Normal CLKIN input frequency (1MHz or
4MHz) (Test info)
-0.5%
1/4
+0.5%
MHz
tT_CKMSK
FLL Mask time
-
-
16
ms
tT_CKERD
Clock error detection time (if FLL is
enabled and CLKIN is stuck)
-
-
260
μs
Clock error reaction time (if bit
REACTTIME=1)
-
20
-
ms
treaction
94/104
DocID028693 Rev 1
L9663
Electrical characteristics
Table 24. Frequency references (continued)
Parameter / Condition
Min
Typ
Max
Unit
fCLKMONERR_H
High frequency error detection by internal
clock monitor (clock error, monitor enabled
by ST)
16.1
-
20.3
MHz
fCLKMONERR_L
Low frequency error detection by internal
clock monitor (clock error, monitor enabled
by ST)
12.5
-
15.68
MHz
fCLKERR_H
High frequency error detection by FLL
(clock error, FLL enabled)
16.16
-
20.1
MHz
fCLKERR_L
Low frequency error detection by FLL
(clock error, FLL enabled)
11.9
-
-
MHz
SPI interface
Figure 31. SPI communication timing diagram
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DocID028693 Rev 1
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103
Electrical characteristics
L9663
Table 25. SPI communication timing
Symbol
Min
Typ
Max
Unit
-
10
-
MHz
SCLK high/low time
30
-
-
ns
tlead
CS to SCLK delay
180
-
-
ns
tlag
SCLK to CS delay
45
-
-
ns
tdisablelead
SCLK disable lead time
10
-
-
ns
tdisablelag
SCLK disable lag time
10
-
-
ns
tMOSI-set
MOSI to SCLK delay
10
-
-
ns
tMOSI-hold
SCLK to MOSI delay
10
-
-
ns
tMISO-delay
SCLK to MISO delay, CL≤ 90 pF
-
-
30
ns
tMISO-delay
SCLK to MISO delay, CL = 25 pF (Design info)
-
-
21
ns
tMISO-delay
SCLK to MISO delay, CL = 200 pF (Design info)
-
-
75
ns
tMISO-active
CS to MISO active delay, CL≤ 90 pF
-
-
30
ns
tMISO-tristate
CS to MISO tristate delay, CL≤ 90 pF
-
-
30
ns
tSPICS-high
CS high time
200
-
-
ns
MISO leakage current
-10
-
10
μA
fSPICLK
Parameter / Condition
SCLK frequency
tCLK-high/low
IMISO_tristate
Table 26. Direct interface
Symbol
Parameter / Condition
Typ
Max
Unit
VSYNCx-H
SYNCx high threshold
-
-
2
V
VSYNCx-L
SYNCx low threshold
0.8
-
-
V
∆VSYNCx
SYNCx Hysteresis
100
150
-
mV
tdeglitch
Deglitch filter for SYNCx path
-
500
-
ns
VDout-L
DOUTx Low level (Isink=2mA)
-
-
0.4
V
VDout-H
DOUTx High level (Isource=2mA)
VDD0.45
-
-
V
tDOUTx-delay
DOUTx output buffer delay, CL≤ 50pF (Design
info)
-
-
90
ns
-
DOUTx rising and falling edge delay difference,
CL≤ 50pF
-50
-
+50
ns
-
-
3.05
μs
Latency time between receiving sensor data @
PSIx pin and reaching threshold high level of
tLatency_DOUTx_HF_IIR DOUTx pin (trigger point: 80% of PSIx
modulated current, @189kBps, deglitch filter
with default value).
96/104
Min
DocID028693 Rev 1
L9663
Electrical characteristics
Table 26. Direct interface (continued)
Symbol
Parameter / Condition
Min
Typ
Max
Unit
Latency time between receiving sensor data @
PSIx pin and reaching threshold high level of
tLatency_ DOUTx_MF_IIR DOUTx pin (trigger point: 80% of PSIx
modulated current, @125kBps or 83.3kBps,
deglitch filter with default value.
-
-
3.6
μs
tdeglitch
Additional delay on DOUTx for deglitch filter
configuration by SPI (DATA_FILT_SEL bits with
value from “0000” to “1111”)
-
-
1
μs
tLatency_Jitter_ DOUTx
Latency jitter between receiving sensor data @
PSIx pin and reaching threshold high level of
DOUTx pin (trigger point: 80% of PSIx
amplitude)
-
-
125
Ns
DocID028693 Rev 1
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103
Errata
7
L9663
Errata
Table 27. Errata
BugID#
1526
Component
Revision
L9663BA
Category /
Function
Asynchronous
Mode
1822
L9663BA
Sync Pulse
1830
L9663BA
Cross coupling
test
3367
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Issue Description
FIFO_LOCK could still stay set even after clearing of the data
buffer registers of the 2 PSI5 channels.
Assuming a low data rate from sensor compared to SPI readout,
the proposed workaround is to read both FIFOs in the following
sequence:
– Ch 1, slot 6
– Ch 2, slot 6
– Ch 1, slot 5
– Ch 2, slot 5
–…
– Ch 2, slot 1
Afterwards, if the FIFO_LOCK bit is still high, the following read
commands are needed:
– Ch 1, slot 1
– Ch 2, slot 1
If the IC is configured to control the sync pulse length via pin
(PSIx_EXT_UDB=0 and PSIx_TRIG_SEL=00/11, x=1 or 2) the
generated sync pulse could be not compliant with the PSI5
standard, depending on the trigger pulse duration tw.
– 1μs ≤ tw ≤ 5μs ≥ a short pulse is generated, PSI5 standard
compliant; ≥ Correct short pulse
– tw > 5μs ≥ the pulse could be not compliant with PSI5 standard,
two consecutive pulses could be generated instead of a single
pulse. ≥ Wrong pulse
XCTRSLT1/2 fault flags are swapped in master mode
The internal clock monitor (disabled by default) is not accurate
enough: fCLKERR_H/L thresholds overlap the main oscillator
Clock monitor by operating range.
internal oscillator This function is disabled by default, it can be enabled by ST only
(burning a dedicated OTP bit).
If enabled it could detect false errors. => Activation is forbidden.
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8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8.1
TQFP32 (7x7x1.0 mm exp. pad down) package information
Figure 32. TQFP32 (7x7x1.0 mm exp. pad down) package outline
*$3*36
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Package information
L9663
Table 28. TQFP32 (7x7x1.0 mm exp. pad down) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.2
-
-
0.0472
A1
0.05
-
0.15
0.0020
-
0.0059
A2
0.95
1
1.05
0.0374
0.0394
0.0413
b
0.3
0.37
0.45
0.0118
0.0146
0.0177
c
0.09
-
0.2
0.0035
-
0.0079
D
8.8
9
9.2
0.3465
0.3543
0.3622
D1
6.8
7
7.2
0.2677
0.2756
0.2835
D2
2
-
-
0.0787
-
-
D3
-
5.6
-
-
0.2205
-
E
8.8
9
9.2
0.3465
0.3543
0.3622
E1
6.8
7
7.2
0.2677
0.2756
0.2835
E2
2
-
-
0.0787
-
-
E3
-
5.6
-
-
0.2205
-
e
-
0.8
-
-
0.0315
-
L
0.45
0.6
0.75
0.0177
0.0236
0.0295
L1
-
1
-
-
0.0394
-
k
-
3.5
7
-
0.1378
0.2756
ccc
-
-
0.1
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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L9663
VFQFPN-28 (5x5x1.0 mm) package information
Figure 33. VFQFPN-28 (5x5x1.0 mm) package outline
,1'(;$5($
H
'
$
'
-
/
$
E
(
'(7$,/$
/
/
$
'(7$,/$
/
8.2
Package information
/
Table 29. VFQFPN-28 (5x5x1.0 mm) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.85
0.95
1.05
0.0335
0.0374
0.0413
A1
-
-
0.05
-
-
0.0020
A3
-
0.2
-
-
0.0079
-
D
4.85
5
5.15
0.1909
0.1969
0.2028
E
4.85
5
5.15
0.1909
0.1969
0.2028
D2
3.25
3.4
3.55
0.1280
0.1339
0.1398
E2
3.25
3.4
3.55
0.1280
0.1339
0.1398
e
-
0.5
-
-
0.0197
-
J
-
0.3
-
-
0.0118
-
L
0.4
0.5
0.6
0.0157
0.0197
0.0236
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Table 29. VFQFPN-28 (5x5x1.0 mm) package mechanical data (continued)
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
L2
-
0.05
-
-
0.0020
-
L3
-
0.2
-
-
0.0079
-
L4
-
0.075
-
-
0.0030
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Revision history
Revision history
Table 30. Document revision history
Date
Revision
19-Jan-2016
1
Changes
Initial release.
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