STMicroelectronics M24C16-DFCU 16-kbit serial iâ²c bus eeprom 4 balls csp Datasheet

M24C16-DFCU
16-Kbit serial I²C bus EEPROM 4 balls CSP
Datasheet - preliminary data
Features
 Package:
– RoHS compliant and halogen free
WLCSP(ECOPACK2®)
 Compatible with all I2C bus modes
– 1 MHz
– 400 kHz
WLCSP (CU)
 Memory array:
– 16 Kbits (2 Kbytes) of EEPROM
– Page size: 16 bytes
– Additional Write lockable
page(Identification page)
 Supply voltage range:
– 1.6 V to 5.5 V
 Operating temperature range
– VCC = 1.7 V : -40°C / +85°C
– VCC = 1.6 V : -40°C (Read) / 0°C (Write) /
+85°C
 Schmitt trigger inputs for noise filtering
 Write
– Byte Write within 5 ms
– Page Write within 5 ms
 Random and sequential read modes
 ESD protection
– Human Body Model: 4 kV
 Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
 More than 200-years data retention
December 2014
DocID026468 Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/35
www.st.com
Contents
M24C16-DFCU
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
2/35
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3
Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4
Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.5
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Contents
5.2.4
Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.5
Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.6
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
6.2
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Error correction code (ECC x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of tables
M24C16-DFCU
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
4/35
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Significant address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M24C16-DF CU WLCSP 4-bump package related mechanical data . . . . . . . . . . . . . . . . . 32
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Maximum Rbus value versus bus parasitic capacitance (Cbus) 
for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
WLCSP 4-bump wafer-level chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M24C16-DF CU WLCSP 4-bump recommended land pattern . . . . . . . . . . . . . . . . . . . . . . 32
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Description
1
M24C16-DFCU
Description
The M24C16-DFCU is a 16-Kbit I2C-compatible EEPROM assembled in a four balls ultra
thin chip scale package (WLCSP).
The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.
The M24C16-DFCU memory array is based on advanced true EEPROM technology
(Electrically Erasable Programmable Memory), organized as 128 pages of 16 bytes, with a
data integrity improved with an embedded Error Correction Code logic.
The M24C16-DFCU offers an additional Identification Page (16 bytes) in which the ST
device identification can be read. This page can also be used to store sensitive application
parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
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Table 1. Signal names
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Signal name
Function
Direction
SDA
Serial Data
I/O
SCL
Serial Clock
Input
VCC
Supply voltage
VSS
Ground
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Description
Figure 2. WLCSP connections
(top view, marking side, with balls on the underside)
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Signal description
M24C16-DFCU
2
Signal description
2.1
Serial Clock (SCL)
SCL is an input. The signal applied on the SCL input is used to strobe the data available on
SDA(in) and to output the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 9
indicates how to calculate the value of the pull-up resistor).
2.3
VSS (ground)
VSS is the reference for the VCC supply voltage.
2.4
Supply voltage (VCC)
2.4.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually from10 nF to
100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.4.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 9: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.4.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 9: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 9: DC and AC
parameters).
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M24C16-DFCU
Signal description
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.4.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
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Memory organization
3
M24C16-DFCU
Memory organization
The memory is organized as shown below.
Figure 3. Block diagram
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4
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 4. I2C bus protocol
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Device operation
4.1
M24C16-DFCU
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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M24C16-DFCU
4.5
Device operation
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier(1)
Chip Enable address
b7
b6
b5
b4
b3
b2
b1
b0
When accessing the memory
1
0
1
0
A10
A9
A8
RW
When accessing the identification page
1
0
1
1
X
X
X
RW
1. The most significant bit, b7, is sent first.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time.
If the device does not match the device select code, the device deselects itself from the bus,
and goes into Standby mode (therefore will not acknowledge the device select code).
Address byte
Most
significant
address bits
Table 3. Significant address bits
Memory
Identification page
(Device type identifier = 1010b)
(Device type identifier = 1011b)
Read
Write
Lock
Identification Identification Identification Read lock status
page
page
page
Random
Address Read
Write
b3 (1)
A10
A10
X
X
X
b2 (1)
A9
A9
X
X
X
(1)
A8
A8
X
X
X
b7
A7
A7
0
0
1
b6
A6
A6
X
X
X
b5
A5
A5
X
X
X
b4
A4
A4
X
X
X
b3
A3
A3
A3
A3
X
b2
A2
A2
A2
A2
X
b1
A1
A1
A1
A1
X
b0
A0
A0
A0
A0
X
b1
see Chapter 5.2.4
1. Address bits defined inside the DeviceSelect code (see Table 2).
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Device operation
4.6
M24C16-DFCU
Identification page
The M24C16-DFCU offers an Identification Page (16 bytes) in addition to the 16-Kbit
memory. The Identification page contains two fields:
Note:

Device identification code: the first three bytes are programmed by STMicroelectronics
with the Device identification code, as shown in Table 4.

Application parameters: the bytes after the Device identification code are available for
application specific data.
If the end application does not need to read the Device identification code, this field can be
overwritten and used to store application-specific data. Once the application-specific data
are written in the Identification page, the whole Identification page should be permanently
locked in Read-only mode.
The instructions Read, Write and Lock Identification Page are detailed in Section 5:
Table 4. Device identification code
Address in
Identification page
00h
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Content
ST manufacturer code
2C
family code
01h
I
02h
Memory density code
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Value
20h
E0h
0Bh(16-Kbit)
M24C16-DFCU
Instructions
5
Instructions
5.1
Write operations
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send the address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
Byte Write
After the device select code and the address bytes, the bus master sends one data byte.
The device replies with Ack, as shown in . The bus master shall terminate the transfer by
generating a Stop condition.
Figure 5. Write mode sequence (data write enabled)
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5.1.1
DocID026468 Rev 2
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34
Instructions
5.1.2
M24C16-DFCU
Page Write
The Page Write mode allows up to N(a) bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A10/A4, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
Note:
After each byte is transferred, the internal byte address counter is incremented. The transfer
is terminated by the bus master generating a Stop condition.
5.1.3
Write Identification Page
The Identification Page (16 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:

Device type identifier = 1011b

Most significant address bits A10/A4 are don't care, except for address bit A7 which
must be “0”. Least significant address bits A3/A0 define the byte location inside the
Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4
Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
16/35

Device type identifier = 1011b

Address bit A7 must be ‘1’; all other address bits are don't care

The data byte must be equal to the binary value xxxx xx1x, where x is don't care
DocID026468 Rev 2
M24C16-DFCU
5.1.5
Instructions
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 9: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 6, is:

Initial condition: a Write cycle is in progress.

Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 6. Write cycle polling flowchart using ACK
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1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
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34
Instructions
5.2
M24C16-DFCU
Read operations
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 7. Read mode sequences
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Random Address Read
The Random Address Read is a sequence composed of a truncated Write sequence (to
define a new address pointer value, see Table 3) followed by a current Read.
Therefore the Random Address Read sequence is the sum of [Start + Device Select code
with R/W=0 + address byte] (without Stop condition, as shown in Figure 7) and [Start
condition + Device Select code with R/W=1]. The memory device acknowledges the
sequence and then outputs the contents of the addressed byte. To terminate the data
18/35
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Instructions
transfer, the bus master does not acknowledge the last data byte and then issues a Stop
condition.
5.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 9, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the Identification page byte location, when accessing the memory, it is
safer to always use the Random Address Read instruction (this instruction loads the
address counter with the byte location to read in the memory) instead of the Current
Address Read instruction.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.2.4
Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The most significant address bits A10/A4
are don't care except bit A7 which must be 0, the least significant address bits A3/A0 define
the byte location inside the Identification page. The number of bytes to read in the ID page
must not exceed the page boundary.
5.2.5
Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction plus one data byte] to the
device. The device returns an acknowledge bit after the data byte if the Identification page is
unlocked, otherwise a NoAck bit if the Identification page is locked. After this, it is
recommended to transmit to the device a Start condition followed by a Stop condition, so
that:

Start: the truncated command is not executed because the Start condition resets the
device internal logic,

Stop: the device is then set back into Standby mode by the Stop condition.
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Instructions
5.2.6
M24C16-DFCU
Acknowledge in Read mode
For all Read instructions, after each byte sent out, the device waits for an acknowledgment
from the bus master during the “9th bit” time slot. If the bus master does not send the
Acknowledge (the master drives SDA high during the 9th bit time), the device terminates the
data transfer and enters its Standby mode.
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Application design recommendations
6
Application design recommendations
6.1
Supply voltage
6.1.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 6).
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
6.1.2
Power-up conditions
When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up
to the minimum VCC operating voltage defined in see Table 6.
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC reaches the internal
threshold voltage (this threshold is defined in the DC characteristic Table 11 as VRES).
When VCC passes over the POR threshold, the device is reset and in the following state:

in the Standby power mode

deselected
As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)]
range (defined in Table 6), the device is ready for operation.
6.1.3
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 6), the device must be in Standby power mode (that
is after a STOP condition or after the completion of the Write cycle tW if an internal Write
cycle is in progress).
6.2
Error correction code (ECC x 1)
The error correction code (ECC x 1) is an internal logic function which is transparent for the
I2C communication protocol.
The ECC x 1 logic is implemented on each byte of the memory array. If a single bit out of the
byte happens to be erroneous during a Read operation, the ECC x 1 detects this bit and
replaces it with the correct value. The read reliability is therefore much improved.
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Initial delivery state
7
M24C16-DFCU
Initial delivery state
The device is delivered as follows:
• The memory array is set to all 1s (each byte = FFh).
• Identification page: the first three bytes define the Device identification code (value defined
in Table 4). The content of the following bytes is Don’t Care.
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8
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
°C
–0.50
6
V
-
5
mA
–0.50
6
V
-
4000
V
Lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
note(1)
Electrostatic pulse (Human Body
model)(2)
see
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 ).
DocID026468 Rev 2
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DC and AC parameters
9
M24C16-DFCU
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Operating conditions
Symbol
VCC
TA
fC
Parameter
Min.
Supply voltage
1.6
1.7
Ambient operating temperature: Read
–40
-40
Ambient operating temperature: Write
0
-40
Max.
Unit
5.5
V
85
°C
Operating clock frequency @1.6 V
-
400
Operating clock frequency @1.7 V
-
1000
kHz
Table 7. AC measurement conditions
Symbol
Cbus
Parameter
Min.
Load capacitance
Max.
Unit
100
-
pF
-
SCL input rise/fall time, SDA input fall time
50
ns
-
Input levels
0.2 VCC to 0.8 VCC
V
-
Input and output timing reference levels
0.3 VCC to 0.7 VCC
V
Figure 8. AC measurement I/O waveform
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Table 8. Input parameters
Symbol
Parameter (1)
Min.
Max.
Unit
CIN
Input capacitance (SDA)
-
-
8
pF
CIN
Input capacitance (other pins)
-
-
6
pF
VIN < 0.3 VCC
30
-
k
VIN > 0.7 VCC
500
-
k
ZL
ZH
Input impedance (WC)
1. Characterized only, not tested in production.
24/35
Test condition
DocID026468 Rev 2
M24C16-DFCU
DC and AC parameters
Table 9. Cycling performance
Symbol
Ncycle
Parameter
Write cycle
endurance
Test condition
Max.
Unit
TA  25 °C, VCC(min) < VCC < VCC(max)
4,000,000
TA = 85°C, VCC(min) < VCC < VCC(max)
1,000,000
Write
cycles
Min.
Unit
Table 10. Memory cell data retention
Parameter
Data retention
Test condition
TA = 55 °C
DocID026468 Rev 2
200
Years
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DC and AC parameters
M24C16-DFCU
Table 11. DC characteristics
Symbol
Parameter
Test condition
Min
Max.
Unit
ILI
Input leakage current 
(SCL, SDA)
VIN = VSS or VCC, 
device in Standby mode
-
±2
µA
ILO
Output leakage current
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
-
±2
µA
fC = 400 kHz, VCC = 5.5 V
-
2
fC = 400 kHz, VCC = 2.5 V
-
2
fC = 400 kHz, VCC = 1.8 V
-
1
fC = 1 MHz, VCC = 5.5 V
-
2
fC = 1 MHz, VCC = 2.5 V
-
2
fC = 1 MHz, VCC = 1.8 V
-
2
During tW
-
2
Device not selected(1), t° = 85 °C,
VIN = VSS or VCC, VCC = 1.8 V
-
1
Device not selected(1), t° = 85 °C
VIN = VSS or VCC, VCC = 2.5 V
-
2
Device not selected(1), t° = 85 °C,
VIN = VSS or VCC, VCC = 5.5 V
-
3
–0.45
0.3 VCC
V
0.7 VCC
6.5
V
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
-
0.4
IOL = 1 mA, VCC = 1.8 V
-
0.3
0.5
1.5
ICC
ICC0
ICC1
Supply current (Read)
Supply current (Write)
Standby supply current
VIL
Input low voltage (SCL,
SDA)
VIH
Input high voltage
(SCL, SDA)
VOL
Output low voltage
VRES (2)
-
Internal reset threshold
voltage
mA
mA
µA
1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
2. Characterized only, not 100% tested.
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V
M24C16-DFCU
DC and AC parameters
Table 12. 400 kHz AC characteristics
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tLOW
tQL1QL2(1)
tF
tXH1XH2
tR
Parameter
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
Clock pulse width low
1300
-
ns
SDA (out) fall time
20
120
ns
Input signal rise time
(2)
(2)
ns
(2)
(2)
ns
100
-
ns
0
-
ns
100
-
ns
-
900
ns
tXL1XL2
tF
Input signal fall time
tDXCH
tSU:DAT
Data in set up time
tCLDX
tHD:DAT
Data in hold time
tCLQX
(3)
tDH
Data out hold time
tCLQV
(4)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tW
tWR
Write time
-
5
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
80
ns
tNS(1)
1. Characterized only, not tested in production.
2. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C
specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
3. The min value for tCLQX (Data out hold time) offers a safe timing to bridge the undefined region of the falling
edge SCL.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is less than 400 ns.
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DC and AC parameters
M24C16-DFCU
Table 13. 1 MHz AC characteristics
Symbol
Alt.
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
MHz
tCHCL
tHIGH
Clock pulse width high
260
-
ns
tCLCH
tLOW
Clock pulse width low
500
-
ns
tXH1XH2
tR
Input signal rise time
(1)
(1)
ns
tF
Input signal fall time
(1)
(1)
ns
tF
SDA (out) fall time
20
120
ns
tDXCH
tSU:DAT
Data in setup time
50
-
ns
tCLDX
tHD:DAT
Data in hold time
0
-
ns
100
-
ns
-
450
ns
tXL1XL2
tQL1QL2
(2)
Parameter
tCLQX
(3)
tDH
Data out hold time
tCLQV
(4)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO
Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
-
ns
tW
tWR
Write time
-
5
ms
tNS (2)
-
Pulse width ignored (input filter on SCL and
SDA)
-
80
ns
1. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC,
assuming that the Rbus × Cbus time constant is within the values specified in Figure 9.
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DC and AC parameters
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an I2C bus at maximum frequency fC = 400 kHz
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DC and AC parameters
M24C16-DFCU
Figure 11. AC waveforms
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30/35
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M24C16-DFCU
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 12. WLCSP 4-bump wafer-level chip-scale package outline
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DocID026468 Rev 2
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34
Package mechanical data
M24C16-DFCU
Table 14. M24C16-DF CU WLCSP 4-bump package related mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
0.270
0.240
0.300
0.0106
0.0094
0.0118
A1
0.095
-
-
0.0037
-
-
A2
0.175
-
-
0.0069
-
-
b
0.185
-
-
0.0073
-
-
D
0.725
-
0.745
0.0285
-
0.0293
E
0.819
-
0.839
0.0322
-
0.0330
e
0.400
-
-
0.0157
-
-
F
0.210
-
-
0.0083
-
-
G
0.163
-
-
0.0064
-
-
N
4
aaa
0.110
-
-
0.0043
-
-
bbb
0.110
-
-
0.0043
-
-
ccc
0.110
-
-
0.0043
-
-
ddd
0.060
-
-
0.0024
-
-
eee
0.060
-
-
0.0024
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
Figure 13. M24C16-DF CU WLCSP 4-bump recommended land pattern
H
H
[
‘E
&/B)3B9
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Part numbering
Part numbering
Table 15. Ordering information scheme
Example:
M24C16-DF CU 6
T
P
/K
Device type
M24 = I2C serial access EEPROM
Device function
C16-D = 16 Kbits (2048 x 8 bits) plus identification page
Operating voltage
F = VCC = 1.6 V to 5.5 V
Package
CU = ultra-thin 4-bump WLCSP(1)
Device grade
6 = device tested with standard test flow over -40 to 85 °C
Option
T = Tape and reel packing
Plating technology
P = ECOPACK2®
Process technology
/K = Manufacturing technology code
1. ECOPACK2®: RoHS-compliant and free of brominated, chlorinated and antimony oxide flame retardants.
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
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Revision history
12
M24C16-DFCU
Revision history
Table 16. Document revision history
Date
Revision
20-Jun-2014
1
Initial release
2
Updated:
– Features on cover page.
– Section 1: Description.
– Figure 12
– Table 6, Table 14 and Table 15.
Added:
– note 1 on Table 15
– sentence about Engineering sample on Table 15.
– Figure 13
04-Dec-2014
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Changes
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