NUMICRO® NANO100 (B) DATASHEET ARM® Cortex® -M 32-bit Microcontroller NuMicro® Family Nano100 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com May 31, 2016 Page 1 of 160 Revision 1.08 NANO100 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NUMICRO® NANO100 (B) DATASHEET Table of Contents LIST OF FIGURES ........................................................................................................................... 6 LIST OF TABLES ............................................................................................................................. 7 1 GENERAL DESCRIPTION ..................................................................................................... 8 2 FEATURES ........................................................................................................................... 10 2.1 Nano100 Features – Base Line ................................................................................. 10 3 2.2 Nano110 Features – LCD Line .................................................................................. 16 2.3 Nano120 Features – USB Connectivity Line.............................................................. 22 2.4 Nano130 Features – Advanced Line .......................................................................... 28 PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 34 ® 3.1 NuMicro Nano100 Series Selection Code ................................................................ 34 3.2 ® NuMicro Nano100 Products Selection Guide ........................................................... 35 3.2.1 3.2.2 3.2.3 3.2.4 3.3 NANO100 SERIES DATASHEET 5 ® NuMicro ® NuMicro ® NuMicro ® NuMicro Nano100 Pin Diagrams .................................................................................. 37 Nano110 Pin Diagrams .................................................................................. 40 Nano120 Pin Diagrams .................................................................................. 42 Nano130 Pin Diagrams .................................................................................. 45 Pin Description ........................................................................................................... 47 3.4.1 3.4.2 3.4.3 3.4.4 4 Nano100 Base Line Selection Guide .............................................................. 35 Nano110 LCD Line Selection Guide ............................................................... 35 Nano120 USB Connectivity Line Selection Guide .......................................... 35 Nano130 Advanced Line Selection Guide ...................................................... 36 Pin Configuration ........................................................................................................ 37 3.3.1 3.3.2 3.3.3 3.3.4 3.4 ® NuMicro ® NuMicro ® NuMicro ® NuMicro ® NuMicro ® NuMicro ® NuMicro ® NuMicro Nano100 Pin Description ................................................................................ 47 Nano110 Pin Description ................................................................................ 58 Nano120 Pin Description ................................................................................ 72 Nano130 Pin Description ................................................................................ 83 BLOCK DIAGRAM ................................................................................................................ 97 4.1 Nano100 Block Diagram ............................................................................................ 97 4.2 Nano110 Block Diagram ............................................................................................ 98 4.3 Nano120 Block Diagram ............................................................................................ 99 4.4 Nano130 Block Diagram .......................................................................................... 100 FUNCTIONAL DESCRIPTION............................................................................................ 101 5.1 Memory Organization ............................................................................................... 101 5.1.1 5.1.2 5.2 Nested Vectored Interrupt Controller (NVIC) ........................................................... 103 5.2.1 5.2.2 5.3 Overview ...................................................................................................................... 104 Features ....................................................................................................................... 104 Clock Controller ........................................................................................................ 105 5.4.1 May 31, 2016 Overview ...................................................................................................................... 103 Features ....................................................................................................................... 103 System Manager ...................................................................................................... 104 5.3.1 5.3.2 5.4 Overview ...................................................................................................................... 101 Memory Map ................................................................................................................ 101 Overview ...................................................................................................................... 105 Page 2 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.4.2 5.5 Analog to Digital Converter (ADC) ........................................................................... 106 5.5.1 5.5.2 5.6 2 2 Overview .................................................................................................................... 122 Features ..................................................................................................................... 122 UART Controller ....................................................................................................... 123 Page 3 of 160 Revision 1.08 NANO100 SERIES DATASHEET May 31, 2016 Overview .................................................................................................................... 121 Features ..................................................................................................................... 121 Timer Controller ........................................................................................................ 122 5.18.1 5.18.2 5.19 Overview .................................................................................................................... 119 Features ..................................................................................................................... 119 SPI ............................................................................................................................ 121 5.17.1 5.17.2 5.18 Overview .................................................................................................................... 119 Features ..................................................................................................................... 119 Smart Card Host Interface (SC) ............................................................................... 119 5.16.1 5.16.2 5.17 Overview .................................................................................................................... 117 Features ..................................................................................................................... 118 RTC .......................................................................................................................... 119 5.15.1 5.15.2 5.16 Overview .................................................................................................................... 116 Features ..................................................................................................................... 116 Pulse Width Modulation (PWM) ............................................................................... 117 5.14.1 5.14.2 5.15 Overview .................................................................................................................... 115 Features ..................................................................................................................... 115 LCD Display Driver ................................................................................................... 116 5.13.1 5.13.2 5.14 Overview .................................................................................................................... 113 Features ..................................................................................................................... 114 I S ............................................................................................................................. 115 5.12.1 5.12.2 5.13 Overview .................................................................................................................... 112 Features ..................................................................................................................... 112 I C ............................................................................................................................. 113 5.11.1 5.11.2 5.12 Overview ...................................................................................................................... 111 Features ....................................................................................................................... 111 General Purpose I/O Controller ................................................................................ 112 5.10.1 5.10.2 5.11 Overview ...................................................................................................................... 110 Features ....................................................................................................................... 110 FLASH Memory Controller (FMC) ............................................................................ 111 5.9.1 5.9.2 5.10 Overview ...................................................................................................................... 108 Features ....................................................................................................................... 108 External Bus Interface .............................................................................................. 110 5.8.1 5.8.2 5.9 Overview ...................................................................................................................... 107 Features ....................................................................................................................... 107 DMA Controller ......................................................................................................... 108 5.7.1 5.7.2 5.8 Overview ...................................................................................................................... 106 Features ....................................................................................................................... 106 Digital to Analog Converter (DAC) ........................................................................... 107 5.6.1 5.6.2 5.7 Features ....................................................................................................................... 105 NUMICRO® NANO100 (B) DATASHEET 5.19.1 Overview .................................................................................................................... 123 5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In LIN mode, one start bit and 8-bit data format with 1-bit stop bit are required in accordance with the LIN standard. Features.............................................................................................................. 124 5.20 USB .......................................................................................................................... 126 5.20.1 5.20.2 5.21 Watchdog Timer Controller ...................................................................................... 127 5.21.1 5.21.2 5.22 ® Features ................................................................................................................... 129 APPLICATION CIRCUIT ..................................................................................................... 131 7.1 LCD Charge Pump ................................................................................................... 131 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 Voltage Reference Source ........................................................................................... 133 DAC Application Circuit ............................................................................................ 135 NANO100 SERIES DATASHEET 7.3.1 7.4 C-type 1/3 Bias ............................................................................................................. 131 C-type 1/2 Bias ............................................................................................................. 131 Internal R-type .............................................................................................................. 131 External R-type ............................................................................................................. 132 ADC Application Circuit ............................................................................................ 133 7.2.1 8 9 Overview .................................................................................................................... 128 Features ..................................................................................................................... 128 ARM CORTEX™-M0 CORE ............................................................................................. 129 6.1 Overview................................................................................................................... 129 6.2 7 Overview .................................................................................................................... 127 Features ..................................................................................................................... 127 Window Watchdog Timer Controller ........................................................................ 128 5.22.1 5.22.2 6 Overview .................................................................................................................... 126 Features ..................................................................................................................... 126 Voltage Reference Source ........................................................................................... 135 Whole Chip Application Circuit ................................................................................. 137 POWER COMSUMPTION .................................................................................................. 138 ELECTRICAL CHARACTERISTIC ..................................................................................... 139 9.1 Absolute Maximum Ratings...................................................................................... 139 9.2 Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics ..................... 139 9.3 AC Electrical Characteristics .................................................................................... 145 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 Analog Characteristics ............................................................................................. 146 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 May 31, 2016 External Input Clock ..................................................................................................... 145 External 4~24 MHz XTAL Oscillator ............................................................................. 145 External 32.768 kHz Crystal ......................................................................................... 146 Internal 12 MHz Oscillator ............................................................................................ 146 Internal 10 kHz Oscillator ............................................................................................. 146 12-bit ADC .................................................................................................................... 146 Brown-out Detector....................................................................................................... 147 Power-on Reset ............................................................................................................ 148 Temperature Sensor..................................................................................................... 148 12-bit DAC .................................................................................................................... 148 LCD .............................................................................................................................. 149 Internal Voltage Reference ........................................................................................... 149 Page 4 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 9.4.8 9.5 10 11 USB PHY Specifications ............................................................................................... 149 Flash DC Electrical Characteristics .......................................................................... 151 PACKAGE DIMENSIONS ................................................................................................... 152 10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm) ............................................................ 152 10.2 LQFP64 (10x10x1.4 mm footprint 2.0 mm) .............................................................. 153 10.3 LQFP64 (7x7x1.4 mm footprint 2.0 mm) .................................................................. 154 10.4 LQFP48 (7x7x1.4 mm footprint 2.0 mm) .................................................................. 156 10.5 QFN48 (7x7x0.85 mm) ............................................................................................. 157 REVISION HISTORY .......................................................................................................... 158 NANO100 SERIES DATASHEET May 31, 2016 Page 5 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET LIST OF FIGURES ® Figure 3‑1 NuMicro Nano100 Series Selection Code .................................................................. 34 ® Figure 3‑2 NuMicro Nano100 LQFP 128-pin Diagram ................................................................ 37 ® Figure 3‑3 NuMicro Nano100 LQFP 64-pin Diagram .................................................................. 38 ® Figure 3‑4 NuMicro Nano100 LQFP 48-pin Diagram ................................................................... 39 ® Figure 3‑5 NuMicro Nano110 LQFP 128-pin Diagram................................................................. 40 ® Figure 3‑6 NuMicro Nano110 LQFP 64-pin Diagram ................................................................... 41 ® Figure 3‑7 NuMicro Nano120 LQFP 128-pin Diagram................................................................. 42 ® Figure 3‑8 NuMicro Nano120 LQFP 64-pin Diagram ................................................................... 43 ® Figure 3‑9 NuMicro Nano120 LQFP 48-pin Diagram ................................................................... 44 ® Figure 3‑10 NuMicro Nano130 LQFP 128-pin Diagram............................................................... 45 ® Figure 3‑11 NuMicro Nano130 LQFP 64-pin Diagram................................................................. 46 ® Figure 4‑1 NuMicro Nano100 Block Diagram .............................................................................. 97 ® Figure 4‑2 NuMicro Nano110 Block Diagram .............................................................................. 98 ® Figure 4‑3 NuMicro Nano120 Block Diagram .............................................................................. 99 ® Figure 4‑4 NuMicro Nano130 Block Diagram ............................................................................ 100 Figure 6‑1 M0 Functional Block ................................................................................................... 129 Figure 9‑1 Typical Crystal Application Circuit .............................................................................. 145 NANO100 SERIES DATASHEET May 31, 2016 Page 6 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET LIST OF TABLES Table 1‑1 Connectivity Support Table ............................................................................................. 9 Table 3‑1 Nano100 Base Line Selection Table ............................................................................. 35 Table 3‑2 Nano110 LCD Line Selection Table .............................................................................. 35 Table 3‑3 Nano120 USB Connectivity Line Selection Table ......................................................... 35 Table 3‑4 Nano130 Advanced Line Selection Table ..................................................................... 36 Table 5‑12 UART Baud Rate Equation ....................................................................................... 123 Table 5‑13 UART Baud Rate Setting .......................................................................................... 124 NANO100 SERIES DATASHEET May 31, 2016 Page 7 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 1 GENERAL DESCRIPTION ® The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM Cortex™-M0 core operated at a wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with 32K/64K/128K bytes embedded Flash and 8K/16K-byte embedded SRAM. Integrating LCD 4x40 or 6x38 (COM/Segment), USB 2.0 full-speed function, RTC, 12-bit SAR ADC, 12-bit DAC and 2 2 provides high performance connectivity peripheral interfaces such as UART, SPI, I C, I S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and ISO-7816-3 for Smart card, the Nano100 series supports Brown-out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. The Nano100 series provides low power voltage, low power consumption, low standby current, high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost 32-bit microcontrollers. The Nano100 series is suitable for a wide range of battery device applications such as: NANO100 SERIES DATASHEET Portable Data Collector Portable Medical Monitor Portable RFID Reader Portable Barcode Scanner Security Alarm System System Supervisors Power Metering USB Accessories Smart Card Reader Wireless Game Control Device IPTV Remote Smart Keyboard Wireless Sensors Node Device (WSN) Wireless RF4CE Remote Control Wireless Audio Wireless Automatic Meter Reader (AMR) Electronic Toll Collection (ETC) ® The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates RTC, 12- channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high 2 2 performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI C, I S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano100 Base line supports Brown-out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. ® The Nano110 LCD line, an ultra-low power 32-bit microcontroller with the embedded ARM Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates LCD 4x40 or 6x38 (COM/Segment). RTC, 12-channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART, 2 2 2xSPI, 2xI C, I S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano110 LCD line supports Brown-out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. May 31, 2016 Page 8 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded ® ARM Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates USB 2.0 full-speed device function, RTC, 12-channels12-bit SAR ADC, 2-channels 12bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano120 USB Connectivity line supports Brownout Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. ® The Nano130 Advanced line, an ultra-low power 32-bit microcontroller with the embedded ARM Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrated LCD 4x40 or 6x38 (COM/Segment), USB 2.0 full-speed device function, RTC, 8channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high performance connectivity 2 2 peripheral interfaces such as 2xUART, 2xSPI, 2xI C, I S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano130 Advanced line supports Brown-out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. I C I S USB LCD ADC DAC RTC EBI 2 2 SC Timer ● ● ● ● ● ● ● Nano120 ● ● ● ● ● Nano130 ● ● ● ● ● Product Line UART SPI Nano100 ● Nano110 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Table 1‑1 Connectivity Support Table NANO100 SERIES DATASHEET May 31, 2016 Page 9 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 Nano100 Features – Base Line Core ARM Cortex™-M0 core running up to 42 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Brown-out NANO100 SERIES DATASHEET Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 42 MHz with zero wait state for discontinuous address read access 64K/32K/123K bytes application program memory (APROM) 4 KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on-chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Supports DMA mode DMA: Supports 8 channels: one VDMA channel, 6 PDMA channels and one CRC channel May 31, 2016 ® VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral memory-to-peripheral, Page 10 of 160 and memory-to-memory Revision 1.08 NUMICRO® NANO100 (B) DATASHEET CRC 12 5 CRC-CCITT: X CRC-8: X + X + X + 1 CRC-16: X CRC-32: X + X 4 2 X +X +X+1 8 +X +X +1 2 16 32 +X 15 +X +1 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 +X +X +X + Flexible selection for different applications Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature range when turning on auto-trim function (system must have external 32.768 kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all temperarure range. Low power 10 kHz OSC for watchdog and low power system operation Supports one PLL, up to 120 MHz, for high performance system operation and USB application (48 MHz). External 4~24 MHz crystal input for precise timing operation External 32.768 kHz crystal input for RTC function and low power system operation GPIO Three I/O modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger I/O pin configured as interrupt source with edge/level setting Supports High Driver and High Sink I/O mode Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~ PC.7 Timer Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit pre-scale counter Independent Clock Source for each timer Provides one-shot,periodic, output toggle and continuous operation modes Internal trigger event to ADC, DAC and PDMA Supports PDMA mode Wake system up from Power-down mode Watchdog Timer May 31, 2016 16 Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock) Page 11 of 160 Revision 1.08 NANO100 SERIES DATASHEET Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 Clock Control Supports address direction: increment, fixed, and wrap around NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source) Interrupt or reset selectable when watchdog time-out Wake system up from Power-down mode Window Watchdog Timer(WWDT) 6-bit down counter and 6-bit compare value to make the window period flexible Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable. RTC Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second Wake system up from Power-down mode Supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers PWM/Capture Supports 2 PWM modules, each has two 16-bit PWM generators Provides eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-zone generator for complementary paired PWM (Shared with PWM timers) with eight 16-bit digital capture timers provides eight rising/ falling/both capture inputs. Supports One-shot and Continuous mode Supports Capture interrupt UART Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS-485 9 bit mode and direction control. Programmable baud rate generator Supports PDMA mode Wake system up from Power-down mode SPI May 31, 2016 Up to three sets of SPI controller Page 12 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET May 31, 2016 Master up to 32 MHz, and Slave up to 16 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when SPI controller is used as the master, and 1 slave/device select line when SPI controller is used as the slave Supports byte suspend mode in 32-bit transmission Supports two channel PDMA requests, one for transmit and another for receive Supports three wire mode, no slave select signal, bi-direction interface Wake system up from Power-down mode 2 IC 2 Up to two sets of I C device Master/Slave up to 1 Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows Programmable clocks allowing for versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) 2 2 2 IS Interface with external audio CODEC Operated as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 2 ADC Page 13 of 160 Revision 1.08 NANO100 SERIES DATASHEET NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 12-bit SAR ADC up to 2Msps conversion rate Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3) Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF), Temperature sensor, AVDD, and AVSS. Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Supports Single Scan, Single Cycle Scan, and Continuous Scan mode Each channel with individual result register Only scan on enabled channels Threshold voltage detection (comparator function) Conversion started by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to enable ADC DAC 12-bit monotonic output with 400K conversion rate Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Synchronized update capability for two DACs (group function) Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3), software or PDMA to trigger DAC to conversion SmartCard (SC) Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Separates receive/transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) A 24-bit and two 8-bit time-out counters for Answer to Reset (ATR) and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop (clock keep) function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detect the card is removal Supports UART mode (Half Duplex) EBI (External bus interface) support Page 14 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode Supports 8bit/16bit data width Supports byte write in 16-bit Data Width mode One built-in temperature sensor with 1℃ resolution 96-bit unique ID 128-bit unique customer ID Operating Temperature: -40℃~85℃ Packages: All Green package (RoHS) LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 48-pin(7x7) NANO100 SERIES DATASHEET May 31, 2016 Page 15 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 2.2 Nano110 Features – LCD Line Core ARM Cortex™-M0 core running up to 42 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Brown-out ® Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 42 MHz with zero wait state for discontinuous address read access. 64K/32K/123K bytes application program memory (APROM) 4 KB In System Programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Supports DMA mode NANO100 SERIES DATASHEET DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC channel VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral Supports address direction: increment, fixed, and wrap around CRC May 31, 2016 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and Page 16 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET CRC-32 May 31, 2016 5 CRC-8: X + X + X + 1 CRC-16: X CRC-32: X + X 4 2 X +X +X+1 8 +X +X +1 2 16 32 +X 15 +X +1 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 +X +X +X + Flexible selection for different applications Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature range when turning on auto-trim function (system must have external 32.768 kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all temperarure range. Low power 10 kHz OSC for watchdog and low power system operation Supports one PLL, up to 120 MHz, for high performance system operation and USB application (48 MHz). External 4~24 MHz crystal input for precise timing operation External 32.768 kHz crystal input for RTC function and low power system operation GPIO Three I/O modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger I/O pin configured as interrupt source with edge/level setting Supports High Driver and High Sink I/O mode Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~ PC.7) Timer Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit prescale counter Independent Clock Source for each timer Provides one-shot,periodic, output toggle and continuous operation modes Internal trigger event to ADC, DAC and PDMA module Supports PDMA mode Wake system up from Power-down mode Watchdog Timer Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock) Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source) Interrupt or reset selectable when watchdog time-out Page 17 of 160 Revision 1.08 NANO100 SERIES DATASHEET 12 CRC-CCITT: X Clock Control 16 NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 Wake system up from Power-down mode Window Watchdog Timer(WWDT) 6-bit down counter and 6-bit compare value to make the window period flexible Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable. RTC Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second Wake system up from Power-down mode Supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers PWM/Capture Supports 2 PWM modules, each has two 16-bit PWM generators Provides eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-zone generator for complementary paired PWM (Shared with PWM timers) with eight 16-bit digital capture timers provides eight rising/ falling/both capture inputs. Supports Capture interrupt UART Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS-485 9 bit mode and direction control (Low Density Only) Programmable baud rate generator Supports PDMA mode Wake system up from Power-down mode SPI Up to three sets of SPI controller Master up to 32 MHz, and Slave up to 16 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Page 18 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET May 31, 2016 Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when SPI controller is as the master, and 1 slave/device select line when SPI controller is as the slave Supports byte suspend mode in 32-bit transmission Supports two channel PDMA requests, one for transmit and another for receive Supports three wire mode, no slave select signal, bi-direction interface Wake system up from Power-down mode 2 IC 2 Up to two sets of I C device Master/Slave up to 1Mbit/s Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requestING the I C interrupt if the I C bus hangs up and timer-out counter overflows Programmable clocks allow versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave address with mask option) 2 2 2 IS Interface with external audio CODEC Operated as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 2 ADC 12-bit SAR ADC up to 2Msps conversion rate Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3) Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF), Page 19 of 160 Revision 1.08 NANO100 SERIES DATASHEET NUMICRO® NANO100 (B) DATASHEET Temperature sensor, AVDD, and AVSS NANO100 SERIES DATASHEET May 31, 2016 Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Single scan/single cycle scan/continuous scan Each channel with individual result register Only scan on enabled channels Threshold voltage detection (comparator function) Conversion start by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TMR0, TMR1, TMR2, and TMR3) to enable ADC DAC 12-bit monotonic output with 400K conversion rate Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Synchronized update capability for two DACs (group function) Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3), software or PDMA to trigger DAC to conversion SmartCard (SC) Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Separates receive / transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop (clock keep) function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detect the card is removal Supports UART mode (Half Duplex) LCD LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG Supports Static,1/2 bias and 1/3 bias voltage Four display modes; Static, 1/2 duty, 1/3 duty,1/4 duty, 1/5 duty and 1/6 duty. Page 20 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Selectable LCD frequency by frequency divider Configurable frame frequency Internal Charge pump, adjustable contrast adjustment Configurable Charge pump frequency Blinking capability Supports R-type/C-type method LCD frame interrupt One built-in temperature sensor with 1℃ resolution 96-bit unique ID 128-bit unique customer ID Operating Temperature: -40℃~85℃ Packages: All Green package (RoHS) LQFP 128-pin(14x14) / 64-pin(10x10) / 64-pin(7x7) NANO100 SERIES DATASHEET May 31, 2016 Page 21 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 2.3 Nano120 Features – USB Connectivity Line Core ARM Cortex™-M0 core running up to 42 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Brown-out ® Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 42 MHz with zero wait state for discontinuous address read access. 64K/32K/123K bytes application program memory (APROM) 4KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Supports PDMA mode NANO100 SERIES DATASHEET DMA: Support 8 channels: one VDMA channel, 6 PDMA channels, and one CRC channel VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral Supports address: increment, fixed, and wrap around and memory-to-memory CRC May 31, 2016 memory-to-peripheral, Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and Page 22 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET CRC-32 May 31, 2016 5 CRC-8: X + X + X + 1 CRC-16: X CRC-32: X + X 4 2 X +X +X+1 8 +X +X +1 2 16 32 +X 15 +X +1 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 +X +X +X + Flexible selection for different applications Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature range when turning on auto-trim function (system must have external 32.768 kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all temperarure range Low power 10 kHz OSC for watchdog and low power system operatin Supports one PLL, up to 120 MHz, for high performance system operation and USB application (48 MHz). External 4~24 MHz crystal input for precise timing operation External 32.768 kHz crystal input for RTC function and low power system operation GPIO Three I/O modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger I/O pin can be configured as interrupt source with edge/level setting High driver and high sink IO mode support Supports input 5V tolerance (except ADC and DAC shared pins) Timer Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit prescale counter Independent Clock Source for each timer Provides one-shot,periodic, output toggle and continuous operation modes Internal trigger event to ADC, DAC and PDMA module Supports PDMA mode Wake system up from Power-down mode Watchdog Timer Clock Source from LIRC. (Internal 10 kHz Low Speed Oscillator Clock) Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source) Interrupt or reset selectable on watchdog time-out Wake system up from Power-down mode Page 23 of 160 Revision 1.08 NANO100 SERIES DATASHEET 12 CRC-CCITT: X Clock Control 16 NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 Window Watchdog Timer(WWDT) 6-bit down counter and 6-bit compare value to make the window period flexible Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable. RTC Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second Wake system up from Power-down or Idle mode Support 80 bytes spare registers and a snoop pin to clear the content of these spare registers PWM/Capture Supports 2 PWM module, each has two 16-bit PWM generators Provide eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-Zone generator for complementary paired PWM (Shared with PWM timers) with eight 16-bit digital capture timers provides eight rising/ falling/both capture inputs. Supports one shot and continuous mode Supports Capture interrupt UART Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS-485 9 bit mode and direction control. (Low Density Only) Programmable baud rate generator Supports PDMA mode Wake system up from Power-down mode SPI Up to three sets of SPI controller Master up to 32 MHz, and Slave up to 16 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Page 24 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET May 31, 2016 Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when SPI controller is as the master, and 1 slave/device select line when SPI controller is as the slave Supports byte suspend mode in 32-bit transmission Supports two channel PDMA requests, one for transmit and another for receive Supports three wire, no slave select signal, bi-direction interface Wake system up from Power-down mode 2 IC 2 Up to two sets of I C device Master/Slave up to 1Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows Programmable clocks allow versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) 2 2 2 IS Interface with external audio CODEC Operated as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 2 ADC 12-bit SAR ADC up to 2Msps conversion rate Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3). Page 25 of 160 Revision 1.08 NANO100 SERIES DATASHEET NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF), Temperature sensor, AVDD, and AVSS. Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD Supports single scan, single cycle scan, and continuous scan modes Each channel with individual result register Only scan on enabled channels Threshold voltage detection (comparator function) Conversion start by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to enable ADC DAC 12-bit monotonic output with 400K conversion rate Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Synchronized update capability for two DACs (group function) Supports up to four timer time-out event (TMR0, TMR1, TMR2 and TMR3), software or PDMA to trigger DAC to conversion SmartCard (SC) Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Separates receive / transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop (clock keep) function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detect the card is removal Supports UART mode (Half Duplex) USB 2.0 Full-Speed Device One set of USB 2.0 FS Device 12 Mbps On-chip USB Transceiver Page 26 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Provides 1 interrupt source with 4 interrupt events Supports Control, Bulk In/Out, Interrupt and Isochronous transfers Auto suspend function when no bus signaling for 3 ms Provides 8 programmable endpoints Includes 512 Bytes internal SRAM as USB buffer Provides remote wake-up capability EBI (External bus interface) support Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode Supports 8bit/16bit data width Supports byte write in 16-bit Data Width mode One built-in temperature sensor with 1℃ resolution 96-bit unique ID 128-bit unique customer ID Operating Temperature: -40℃~85℃ Packages: All Green package (RoHS) LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) NANO100 SERIES DATASHEET May 31, 2016 Page 27 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 2.4 Nano130 Features – Advanced Line Core ARM Cortex™-M0 core running up to 42 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Brown-out ® Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 42 MHz with zero wait state for discontinuous address read access. 64K/32K/123K bytes application program memory (APROM) 4KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Supports DMA mode NANO100 SERIES DATASHEET DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC egiste VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral Supports address direction: increment, fixed, and wrap around and memory-to-memory CRC May 31, 2016 memory-to-peripheral, Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and Page 28 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET CRC-32 May 31, 2016 5 CRC-8: X + X + X + 1 CRC-16: X CRC-32: X + X 4 2 X +X +X+1 8 +X +X +1 2 16 32 +X 15 +X +1 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 +X +X +X + Flexible selection for different applications Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature range when turning on auto-trim function (system must have external 32.768 kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all temperarure range. Low power 10 kHz OSC for watchdog and low power system operation Supports one PLL, up to 120 MHz, for high performance system operation and USB application (48 MHz). External 4~24 MHz crystal input for precise timing operation External 32.768 kHz crystal input for RTC function and low power system operation GPIO Three I/O modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger I/O pin configured as interrupt source with edge/level setting Supports High Driver and High Sink I/O mode Supports input 5V tolerance (except ADC and DAC shared pins) Timer Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter Independent Clock Source for each timer Provides one-shot,periodic, output toggle and continuous operation modes Supports internal trigger event to ADC, DAC and PDMA module Wake system up from Power-down mode Watchdog Timer Clock Source is from LIRC. (Internal 10 kHz Low Speed Oscillator Clock) Selectable time-out period from 1.6ms ~ 26sec (depends on clock source) Interrupt or reset selectable on watchdog time-out WDT can wake system up from Power-down mode Window Watchdog Timer(WWDT) Page 29 of 160 Revision 1.08 NANO100 SERIES DATASHEET 12 CRC-CCITT: X Clock Control 16 NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 6-bit down counter and 6-bit compare value to make the window period flexible Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable. RTC Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second Wake system up from Power-down or Idle mode Supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers PWM/Capture Supports 2 PWM module, each with two 16-bit PWM generators Provides eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-Zone generator for complementary paired PWM (Shared with PWM timers) with eight 16-bit digital capture timers provides eight rising/ falling/both capture inputs. Supports Capture interrupt UART Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS-485 9 bit mode and direction control (Low Density Only) Programmable baud rate generator Supports PDMA mode Wake system up from Power-down or Idle mode SPI Up to 3 sets of SPI controller Master up to 32 MHz, and Slave up to 16 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer Page 30 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET May 31, 2016 RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when used as the master, and 1 slave/device select line when used as the slave Supports byte suspend mode in 32-bit transmission Supports two channel PDMA request, one for transmit and another for receive Supports three wire, no slave select signal, bi-direction interface Wake system up from Power-down or Idle mode 2 IC 2 Up to two sets of I C device Master/Slave up to 1Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter will request the I C interrupt if the I C bus hangs up and timer-out counter overflows Programmable clocks allowing for versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) 2 2 2 IS Interface with external audio CODEC Operate as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 2 ADC 12-bit SAR ADC up to 2Msps conversion rate Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3) Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF), Temperature sensor, AVDD, and AVSS. Supports three reference voltage sources from VREF pin, internal reference Page 31 of 160 Revision 1.08 NANO100 SERIES DATASHEET NUMICRO® NANO100 (B) DATASHEET voltage (Int_VREF), and AVDD NANO100 SERIES DATASHEET May 31, 2016 Single scan/single cycle scan/continuous scan Each channel with individual result register Scan on enabled channels Threshold voltage detection (comparator function) Conversion start by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to enable ADC DAC 12-bit monotonic output with 400K conversion rate Supports three reference voltage sources from VREF pin, internal reference voltage (Int_VREF), and AVDD. Synchronized update capability for two DACs (group function) Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3), software or PDMA to trigger DAC to conversion SmartCard (SC) Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Separates receive/transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop (clock keep) function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detecting the card is removed Support UART mode (Half Duplex) LCD LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG Supports Static,1/2 bias and 1/3 bias voltage Four display modes: Static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty. Selectable LCD frequency by frequency divider Page 32 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Configurable frame frequency Internal Charge pump, adjustable contrast adjustment Configurable Charge pump frequency Blinking capability Supports R-type/C-type method LCD frame interrupt USB 2.0 Full-speed Device One set of USB 2.0 FS Device 12 Mbps On-chip USB Transceiver Provides 1 interrupt source with 4 interrupt events Supports Control, Bulk In/Out, Interrupt and Isochronous transfers Auto suspend function when no bus signaling for 3 ms Provides 8 programmable endpoints Includes 512 Bytes internal SRAM as USB buffer Provides remote wake-up capability EBI (External bus interface) Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode Supports 8bit/16bit data width Supports byte write in 16-bit data width mode One built-in temperature sensor with 1℃ resolution 96-bit unique ID 128-bit unique customer ID Operating Temperature: -40℃~85℃ Packages: May 31, 2016 All Green package (RoHS) LQFP 128-pin(14x14) / 64-pin (7x7) Page 33 of 160 NANO100 SERIES DATASHEET Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 3 3.1 PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro® Nano100 Series Selection Code NANO 1 X X - X X X B N Ultra-Low Power MCU Temperature CPU core N: -40℃ ~ +85℃ E: -40℃ ~ +105℃ C: -40℃ ~ +125℃ 1: Cortex-M0 5/7: ARM7 9: ARM9 Version A : Version B : Version Product Line Function 0: 1: 2: 3: SRAM Size Base Line LCD Line USB Connectivity Line LCD + USB Connectivity Line 0 1 2 3 : 2KB : 4KB : 8KB : 16KB Flash ROM Reserved A: 8KB B: 16KB C: 32KB D: 64KB E: 128KB 0 ~ 9 Sub Product Line Package Type N : QFN48 (7x7 mm) L : LQFP 48 (7x7 mm) R : LQFP 64 (10x10 mm) S : LQFP 64 (7x7 mm) K : LQFP 128 (14x14 mm) NANO100 SERIES DATASHEET ® Figure 3‑1 NuMicro Nano100 Series Selection Code May 31, 2016 Page 34 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET NuMicro® Nano100 Products Selection Guide 3.2 3.2.1 NuMicro® Nano100 Base Line Selection Guide Part No. NANO100NC2BN NANO100ND2BN NANO100ND3BN NANO100NE3BN NANO100LC2BN NANO100LD2BN NANO100LD3BN NANO100LE3BN NANO100SC2BN NANO100SD2BN NANO100SD3BN NANO100SE3BN NANO100KD3BN NANO100KE3BN Flash SRAM (Kbytes) (Kbytes) 32 64 64 128 32 64 64 128 32 64 64 128 64 128 8 8 16 16 8 8 16 16 8 8 16 16 16 16 ISP ROM I/O (Kbytes) Data Flash (Kbytes) Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable 4 4 4 4 4 4 4 4 4 4 4 4 4 4 38 38 38 38 38 38 38 38 52 52 52 52 86 86 Connectivity Timer PWM ADC 2 RTC EBI I S (32-bit) UART* SPI I2C USB (16-bit) (12-bit) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2+2 2+2 2+2 2+2 2+2 2+2 2+2 2+2 2+3 2+3 2+3 2+3 2+3 2+3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 6 6 6 6 6 6 6 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 7 7 12 12 √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ PDMA LCD 8 8 8 8 8 8 8 8 8 8 8 8 8 8 - ICP DAC ISO-7816-3* ISP (12-bit) IAP 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 √ √ √ √ √ √ √ √ √ √ √ √ √ √ IRC 10KHz 12MHz Package Operating Temp. Range (°C ) √ √ √ √ √ √ √ √ √ √ √ √ √ √ QFN48 QFN48 QFN48 QFN48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP64* LQFP64* LQFP64* LQFP64* LQFP128 LQFP128 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 *Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64*:7X7mm *ISO-7816 UART supports half duplex mode. Table 3‑1 Nano100 Base Line Selection Table 3.2.2 NuMicro® Nano110 LCD Line Selection Guide Part No. NANO110SC2BN NANO110SD2BN NANO110SD3BN NANO110SE3BN NANO110RC2BN NANO110RD2BN NANO110RD3BN NANO110RE3BN NANO110KC2BN NANO110KD2BN NANO110KD3BN NANO110KE3BN Flash SRAM (Kbytes) (Kbytes) 32 64 64 128 32 64 64 128 32 64 64 128 8 8 16 16 8 8 16 16 8 8 16 16 Data Flash (Kbytes) Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable ISP ROM I/O (Kbytes) 4 4 4 4 4 4 4 4 4 4 4 4 51 51 51 51 51 51 51 51 86 86 86 86 Connectivity Timer PWM ADC 2 RTC EBI I S (32-bit) UART* SPI I2C USB (16-bit) (12-bit) 4 4 4 4 4 4 4 4 4 4 4 4 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 - 1 1 1 1 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 8 8 8 8 7 7 7 7 7 7 7 7 12 12 12 12 √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ PDMA LCD 8 8 8 8 8 8 8 8 8 8 8 8 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x40, 6x38 4x40, 6x38 4x40, 6x38 4x40, 6x38 ICP DAC ISO-7816-3* ISP (12-bit) IAP 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 √ √ √ √ √ √ √ √ √ √ √ √ IRC 10KHz 12MHz Package Operating Temp. Range (°C ) √ √ √ √ √ √ √ √ √ √ √ √ LQFP64* LQFP64* LQFP64* LQFP64* LQFP64 LQFP64 LQFP64 LQFP64 LQFP128 LQFP128 LQFP128 LQFP128 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 *Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64*:7X7mm *ISO-7816 UART supports half duplex mode. 3.2.3 NuMicro® Nano120 USB Connectivity Line Selection Guide Part No. NANO120LC2BN NANO120LD2BN NANO120LD3BN NANO120LE3BN NANO120SC2BN NANO120SD2BN NANO120SD3BN NANO120SE3BN NANO120KD3BN NANO120KE3BN Flash SRAM (Kbytes) (Kbytes) 32 64 64 128 32 64 64 128 64 128 8 8 16 16 8 8 16 16 16 16 Data Flash (Kbytes) Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable ISP ROM I/O (Kbytes) 4 4 4 4 4 4 4 4 4 4 34 34 34 34 48 48 48 48 86 86 Connectivity Timer PWM ADC RTC EBI I2S (32-bit) UART* SPI I2C USB (16-bit) (12-bit) 4 4 4 4 4 4 4 4 4 4 2+2 2+2 2+2 2+2 2+3 2+3 2+3 2+3 2+3 2+3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 8 8 8 8 8 8 7 7 7 7 7 7 7 7 8 8 √ √ √ √ √ √ √ √ √ √ √ √ PDMA LCD 8 8 8 8 8 8 8 8 8 8 - ICP DAC ISO-7816-3* ISP (12-bit) IAP 2 2 2 2 2 2 2 2 2 2 *Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. 2 2 2 2 3 3 3 3 3 3 √ √ √ √ √ √ √ √ √ √ IRC 10KHz 12MHz Package Operating Temp. Range (°C ) √ √ √ √ √ √ √ √ √ √ LQFP48 LQFP48 LQFP48 LQFP48 LQFP64* LQFP64* LQFP64* LQFP64* LQFP128 LQFP128 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 LQFP64*:7X7mm *ISO-7816 UART supports half duplex mode. Table 3‑3 Nano120 USB Connectivity Line Selection Table May 31, 2016 Page 35 of 160 Revision 1.08 NANO100 SERIES DATASHEET Table 3‑2 Nano110 LCD Line Selection Table NUMICRO® NANO100 (B) DATASHEET 3.2.4 NuMicro® Nano130 Advanced Line Selection Guide Part No. NANO130SC2BN NANO130SD2BN NANO130SD3BN NANO130SE3BN NANO130KC2BN NANO130KD2BN NANO130KD3BN NANO130KE3BN Flash SRAM (Kbytes) (Kbytes) 32 64 64 128 32 64 64 128 8 8 16 16 8 8 16 16 Data Flash (Kbytes) Configurable Configurable Configurable Configurable Configurable Configurable Configurable Configurable ISP ROM I/O (Kbytes) 4 4 4 4 4 4 4 4 47 47 47 47 86 86 86 86 Connectivity Timer PWM ADC 2 RTC EBI I S (32-bit) UART* SPI I2C USB (16-bit) (12-bit) 4 4 4 4 4 4 4 4 2+3 2+3 2+3 2+3 2+3 2+3 2+3 2+3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 7 7 7 8 8 8 8 7 7 7 7 8 8 8 8 √ √ √ √ √ √ √ √ √ √ √ √ PDMA LCD 8 8 8 8 8 8 8 8 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x31, 6x29 4x40, 6x38 4x40, 6x38 4x40, 6x38 4x40, 6x38 ICP DAC ISO-7816-3* ISP (12-bit) IAP 2 2 2 2 2 2 2 2 *Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. 3 3 3 3 3 3 3 3 √ √ √ √ √ √ √ √ IRC 10KHz 12MHz Package Operating Temp. Range (°C ) √ √ √ √ √ √ √ √ LQFP64* LQFP64* LQFP64* LQFP64* LQFP128 LQFP128 LQFP128 LQFP128 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 LQFP64*:7X7mm *ISO-7816 UART supports half duplex mode. Table 3‑4 Nano130 Advanced Line Selection Table NANO100 SERIES DATASHEET May 31, 2016 Page 36 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin Configuration ® ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 80 79 78 77 76 75 74 73 PE.4 ICE_CLK/PF.1 81 PE.3 NC 82 65 VDD 83 PE.2 NC 84 66 VSS 85 PE.1 VSS 86 67 AVSS 87 PE.0 AVSS 88 68 PA.0/AD0 89 PC.13 PA.1/AD1 90 69 PA.2/AD2 91 70 PA.3/AD3 92 PC.11 PA.4/AD4 93 PC.12 PA.5/AD5 94 71 PA.6/AD6 95 72 PA.7/AD7 96 NuMicro Nano100 LQFP 128-pin 97 64 PB.9 NC 98 63 PB.10 AVDD 99 62 PB.11 AD8/PD.0 100 61 PE.5 AD9/PD.1 101 60 NC AD10/PD.2 102 59 NC AD11/PD.3 103 58 PE.6 NC 104 57 PC.0 PD.4 105 56 PC.1 PD.5 106 55 PC.2 PC.7 107 54 PC.3 PC.6 108 53 PC.4 PC.15 109 52 PC.5 PC.14 110 51 PD.15 PB.15 111 50 PD.14 NC 112 49 PD.7 XT1_IN 113 48 PD.6 XT1_OUT 114 47 PB.3 NC 115 46 PB.2 nRESET 116 45 PB.1 VSS 117 44 PB.0 VSS 118 43 NC NC 119 42 NC VDD 120 41 NC NC 121 40 NC PF.4 122 39 NC PF.5 123 38 PE.7 VSS 124 37 PE.8 PVSS 125 36 PE.9 PB.8 126 35 PE.10 PE.15 127 34 PE.11 PE.14 128 33 PE.12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB.13 PB.12 NC X32O X32I NC PA.11 PA.10 PA.9 PA.8 PD.8 PD.9 PD.10 PD.11 PD.12 PD.13 PB.4 PB.5 PB.6 PB.7 NC LDO_CAP NC NC VDD NC VSS VSS VSS VSS 2 NANO100 LQFP 128-pin ® Figure 3‑2 NuMicro Nano100 LQFP 128-pin Diagram May 31, 2016 Page 37 of 160 Revision 1.08 NANO100 SERIES DATASHEET VREF 1 3.3.1.1 NuMicro® Nano100 Pin Diagrams PB.14 3.3.1 PE.13 3.3 NUMICRO® NANO100 (B) DATASHEET ® PA.4/AD4 PA.3/AD3 PA.2/AD2 PA.1/AD1 PA.0/AD0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro Nano100 LQFP 64-pin AD5/PA.5 49 32 PB.9 AD6/PA.6 50 31 PB.10 VREF 51 30 PB.11 AVDD 52 29 PE.5 PC.7 53 28 PC.0 PC.6 54 27 PC.1 PC.15 55 26 PC.2 PC.14 56 25 PC.3 PB.15 57 24 PD.15 XT1_IN 58 23 PD.14 XT1_OUT 59 22 PD.7 nRESET 60 21 PD.6 VSS 61 20 PB.3 NANO100 LQFP 64-pin 15 16 VSS 12 PB.6 VDD 11 PB.5 14 10 PB.4 13 9 PA.8 PB.7 8 LDO_CAP 7 PA.9 6 PA.10 5 X32I NANO100 SERIES DATASHEET PA.11 PB.0 4 17 X32O 64 3 PB.1 PB.8 2 PB.2 18 PB.12 19 63 PB.13 62 1 VDD PVSS PB.14 3.3.1.2 ® Figure 3‑3 NuMicro Nano100 LQFP 64-pin Diagram May 31, 2016 Page 38 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET ® PA.4/AD4 PA.3/AD3 PA.2/AD2 PA.1/AD1 PA.0/AD0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 36 35 34 33 32 31 30 29 28 27 26 25 NuMicro Nano100 LQFP/QFN 48-pin AD5/PA.5 37 24 PB.9 AD6/PA.6 38 23 PB.10 VREF 39 22 PB.11 AVDD 40 21 PE.5 PC.7 41 20 PC.0 PC.6 42 19 PC.1 PB.15 43 18 PC.2 XT1_IN 44 17 PC.3 XT1_OUT 45 16 PB.3 nRESET 46 15 PB.2 PVSS 47 14 PB.1 PB.8 48 13 PB.0 12 VSS 8 PB.4 11 7 PA.8 VDD 6 PA.9 10 5 PA.10 9 4 PA.11 PB.5 3 X32I LDO_CAP 2 X32O NANO100 SERIES DATASHEET 1 NANO100 LQFP/QFN 48-pin PB.12 3.3.1.3 ® Figure 3‑4 NuMicro Nano100 LQFP 48-pin Diagram May 31, 2016 Page 39 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET NuMicro® Nano110 Pin Diagrams ® ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 79 78 77 76 75 74 73 PE.4 ICE_CK/PF.1 80 PE.3 NC 81 65 VDD 82 PE.2 NC 83 66 VSS 84 PE.1 VSS 85 67 AVSS 86 PE.0 AVSS 87 68 PA.0 88 PC.13 PA.1 89 69 PA.2 90 70 PA.3 91 PC.11 PA.4/AD4/LCD_SEG39 92 PC.12 PA.5/AD5/LCD_SEG38 93 71 PA.6/AD6/LCD_SEG37 94 72 PA.7/AD7/LCD_SEG36 NuMicro Nano110 LQFP 128-pin 95 3.3.2.1 96 3.3.2 97 64 PB.9/LCD_V3 NC 98 63 PB.10/LCD_V2 AVDD 99 62 PB.11/LCD_V1 AD8/PD.0 100 61 PE.5 AD9/PD.1 101 60 NC AD10/PD.2 102 59 VLCD AD11/PD.3 103 58 PE.6 NC 104 57 PC.0/LCD_DH1 LCD_SEG35/PD.4 105 56 PC.1/LCD_DH2 LCD_SEG34/PD.5 106 55 PC.2/LCD_COM0 PC.7 107 54 PC.3/LCD_COM1 PC.6 108 53 PC.4/LCD_COM2 LCD_SEG33/PC.15 109 52 PC.5/LCD_COM3 LCD_SEG32/PC.14 110 51 PD.15/LCD_SEG0(COM4) LCD_SEG31/PB.15 111 50 PD.14/LCD_SEG1(COM5) NC 112 49 PD.7/LCD_SEG2 XT1_IN 113 48 PD.6/LCD_SEG3 XT1_OUT 114 47 PB.3/LCD_SEG4 NC 115 46 PB.2/LCD_SEG5 nRESET 116 45 PB.1/LCD_SEG6 VSS 117 44 PB.0/LCD_SEG7 VSS 118 43 NC NC 119 42 NC VDD 120 41 NC NC 121 40 NC PF.4 122 39 NC PF.5 123 38 PE.7/LCD_SEG8 VSS 124 37 PE.8/LCD_SEG9 PVSS 125 36 PE.9 LCD_SEG30/PB.8 126 35 PE.10 LCD_SEG29/PE.15 127 34 PE.11 LCD_SEG28/PE.14 128 33 PE.12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LCD_SEG24/PB.12 NC X32O X32I NC LCD_SEG23/PA.11 LCD_SEG22/PA.10 LCD_SEG21/PA.9 LCD_SEG20/PA.8 LCD_SEG19/PD.8 LCD_SEG18/PD.9 LCD_SEG17/PD.10 LCD_SEG16/PD.11 LCD_SEG15/PD.12 LCD_SEG14/PD.13 LCD_SEG13/PB.4 LCD_SEG12/PB.5 LCD_SEG11/PB.6 LCD_SEG10/PB.7 NC LDO_CAP NC NC VDD NC VSS VSS VSS VSS 2 LCD_SEG25/PB.13 1 LCD_SEG27/PE.13 NANO110 LQFP 128-pin LCD_SEG26//PB.14 NANO100 SERIES DATASHEET VREF ® Figure 3‑5 NuMicro Nano110 LQFP 128-pin Diagram May 31, 2016 Page 40 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET ® PA.4/AD4/LCD_SEG21 PA.3/AD3/LCD_SEG22 PA.2/AD2/LCD_SEG23 PA.1/AD1 PA.0/AD0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12/LCD_SEG24 PA.13/LCD_SEG25 PA.14/LCD_SEG26 PA.15/LCD_SEG27 PC.8/LCD_SEG28 PC.9/LCD_SEG29 PC.10/LCD_SEG30 PC.11/LCD_SEG31 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro Nano110 LQFP 64-pin 48 3.3.2.2 LCD_SEG20/AD5/PA.5 49 32 PB.9/LCD_V3 LCD_SEG19/AD6/PA.6 50 31 PB.10/LCD_V2 VREF 51 30 PB.11/LCD_V1 AVDD 52 29 LCD_VLCD LCD_SEG17/PC.7 53 28 PC.0/LCD_DH1 PC.6 54 27 PC.1/LCD_DH2 LCD_SEG16/PC.15 55 26 PC.2/LCD_COM0 LCD_SEG15/PC.14 56 25 PC.3/LCD_COM1 LCD_SEG14/PB.15 57 24 PD.15 XT1_IN 58 23 PD.14 XT1_OUT 59 22 PD.7 nRESET 60 21 PD.6 VSS 61 20 PB.3/LCD_COM2 VDD 62 19 PB.2/LCD_COM3 PVSS 63 18 PB.1/LCD_SEG0(COM4) LCD_SEG13/PB.8 64 17 PB.0/LCD_SEG1(COM5) 7 8 9 10 11 12 13 14 15 16 LCD_SGE6/PA.8 LCD_SGE5/PB.4 LCD_SGE4/PB.5 LCD_SGE3/PB.6 LCD_SGE2/PB.7 LDO_CAP VDD VSS 5 X32I LCD_SGE7/PA.9 4 X32O LCD_SGE8/PA.10 3 LCD_SGE10/PB.12 6 2 LCD_SGE9/PA.11 1 LCD_SEG11/PB.13 NANO100 SERIES DATASHEET LCD_SEG12/PB.14 Nano110 LQFP 64-pin ® Figure 3‑6 NuMicro Nano110 LQFP 64-pin Diagram May 31, 2016 Page 41 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET ® ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 80 79 78 77 76 75 74 73 PE.4 ICE_CLK/PF.1 81 PE.3 NC 82 65 VDD 83 PE.2 NC 84 66 VSS 85 PE.1 VSS 86 67 AVSS 87 PE.0 AVSS 88 68 PA.0 89 PC.13 PA.1 90 69 PA.2 91 70 PA.3 92 PC.11 PA.4 93 PC.12 PA.5 94 71 PA.6 95 72 PA.7 96 NuMicro Nano120 LQFP 128-pin 97 64 PB.9 NC 98 63 PB.10 AVDD 99 62 PB.11 PD.0 100 61 PE.5 PD.1 101 60 NC PD.2 102 59 NC PD.3 103 58 PE.6 NC 104 57 PC.0 PD.4 105 56 PC.1 PD.5 106 55 PC.2 PC.7 107 54 PC.3 PC.6 108 53 PC.4 PC.15 109 52 PC.5 PC.14 110 51 PD.15 PB.15 111 50 PD.14 NC 112 49 PD.7 XT1_IN 113 48 PD.6 XT1_OUT 114 47 PB.3 NC 115 46 PB.2 nRESET 116 45 PB.1 VSS 117 44 PB.0 VSS 118 43 USB_D+ NC 119 42 USB_D- VDD 120 41 USB_VDD33_CAP NC 121 40 USB_VBUS PF.4 122 39 NC PF.5 123 38 PE.7 VSS 124 37 PE.8 PVSS 125 36 PE.9 PB.8 126 35 PE.10 PE.15 127 34 PE.11 PE.14 128 33 PE.12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB.13 PB.12 NC X32O X32I NC PA.11 PA.10 PA.9 PA.8 PD.8 PD.9 PD.10 PD.11 PD.12 PD.13 PB.4 PB.5 PB.6 PB.7 NC LDO_CAP NC NC VDD NC VSS VSS VSS VSS 2 NANO120 LQFP 128-pin 1 NANO100 SERIES DATASHEET VREF PB.14 3.3.3.1 NuMicro® Nano120 Pin Diagrams PE.13 3.3.3 ® Figure 3‑7 NuMicro Nano120 LQFP 128-pin Diagram May 31, 2016 Page 42 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET ® PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro Nano120 LQFP 64-pin PA.5 49 32 PB.9 PA.6 50 31 PB.10 VREF 51 30 PB.11 AVDD 52 29 PE.5 PC.7 53 28 PC.0 PC.6 54 27 PC.1 PC.15 55 26 PC.2 PC.14 56 25 PC.3 PB.15 57 24 PB.3 XT1_IN 58 23 PB.2 XT1_OUT 59 22 PB.1 nRESET 60 21 PB.0 VSS 61 20 USB_D+ NANO120 LQFP 64-pin 7 8 9 10 11 12 13 14 15 16 PA.9 PA.8 PB.4 PB.5 PB.6 PB.7 LDO VDD VSS 6 PA.10 5 X32I NANO100 SERIES DATASHEET PA.11 USB_VBUS 4 17 X32O 64 3 USB_VDD33_CAP PB.8 2 USB_D- 18 PB.12 19 63 PB.13 62 1 VDD PVSS PB.14 3.3.3.2 ® Figure 3‑8 NuMicro Nano120 LQFP 64-pin Diagram May 31, 2016 Page 43 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET ® PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 36 35 34 33 32 31 30 29 28 27 26 25 NuMicro Nano120 LQFP 48-pin PA.5 37 24 PC.0 PA.6 38 23 PC.1 VREF 39 22 PC.2 AVDD 40 21 PC.3 PC.7 41 20 PB.3 PC.6 42 19 PB.2 PB.15 43 18 PB.1 XT1_IN 44 17 PB.0 XT1_OUT 45 16 USB_D+ nRESET 46 15 USB_D- PVSS 47 14 USB_VDD33_CAP PB.8 48 13 USB_VBUS 12 VSS 8 PB.4 11 7 PA.8 10 6 PA.9 VDD 5 PA.10 9 4 PA.11 PB.5 3 X32I LDO_CAP 2 X32O NANO100 SERIES DATASHEET 1 NANO120 LQFP 48-pin PB.12 3.3.3.3 ® Figure 3‑9 NuMicro Nano120 LQFP 48-pin Diagram May 31, 2016 Page 44 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET NuMicro® Nano130 Pin Diagrams ® ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 79 78 77 76 75 74 73 PE.4 ICE_CLK/PF.1 80 PE.3 NC 81 65 VDD 82 PE.2 NC 83 66 VSS 84 PE.1 VSS 85 67 AVSS 86 PE.0 AVSS 87 68 PA.0/AD0 88 PC.13 PA.1/AD1 89 69 PA.2/AD2 90 70 PA.3/AD3 91 PC.11 PA.4/AD4/LCD_SEG39 92 PC.12 PA.5/AD5/LCD_SEG38 93 71 PA.6/AD6/LCD_SEG37 94 72 PA.7/AD7/LCD_SEG36 NuMicro Nano130 LQFP 128-pin 95 3.3.4.1 96 3.3.4 97 64 PB.9/LCD_V3 NC 98 63 PB.10/LCD_V2 AVDD 99 62 PB.11/LCD_V1 AD8/PD.0 100 61 PE.5 AD9/PD.1 101 60 NC AD10/PD.2 102 59 VLCD AD11/PD.3 103 58 PE.6 NC 104 57 PC.0/LCD_DH1 LCD_SEG35/PD.4 105 56 PC.1/LCD_DH2 LCD_SEG34/PD.5 106 55 PC.2/LCD_COM0 PC.7 107 54 PC.3/LCD_COM1 PC.6 108 53 PC.4/LCD_COM2 LCD_SEG33/PC.15 109 52 PC.5/LCD_COM3 LCD_SEG32/PC.14 110 51 PD.15/LCD_SEG0(COM4) LCD_SEG31/PB.15 111 50 PD.14/LCD_SEG1(COM5) NC 112 49 PD.7/LCD_SEG2 XT1_IN 113 48 PD.6/LCD_SEG3 XT1_OUT 114 47 PB.3/LCD_SEG4 NC 115 46 PB.2/LCD_SEG5 nRESET 116 45 PB.1/LCD_SEG6 VSS 117 44 PB.0/LCD_SEG7 VSS 118 43 USB_D+ NC 119 42 USB_D- VDD 120 41 USB_VDD33_CAP NC 121 40 USB_VBUS PF.4 122 39 NC PF.5 123 38 PE.7/LCD_SEG8 VSS 124 37 PE.8/LCD_SEG9 PVSS 125 36 PE.9 LCD_SEG30/PB.8 126 35 PE.10 LCD_SEG29/PE.15 127 34 PE.11 LCD_SEG28/PE.14 128 33 PE.12 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LCD_SET13/PB.4 LCD_SEG12/PB.5 LCD_SEG11/PB.6 LCD_SEG10/PB.7 NC LDO NC NC VDD NC VSS VSS VSS VSS 12 LCD_SEG20/PA.8 LCD_SEG14/PD.13 11 LCD_SEG21/PA.9 17 10 LCD_SEG22/PA.10 LCD_SEG15/PD.12 9 LCD_SEG23/PA.11 16 8 NC LCD_SEG16/PD.11 7 X32I 15 6 X32O LCD_SEG17/PD.10 5 NC 14 4 LCD_SEG24/PB.12 LCD_SEG18/PD.9 3 LCD_SEG25/PB.13 13 2 LCD_SEG26/PB.14 LCD_SEG19/PD.8 1 LCD_SEG27/PE.13 NANO130 LQFP 128-pin ® Figure 3‑10 NuMicro Nano130 LQFP 128-pin Diagram May 31, 2016 Page 45 of 160 Revision 1.08 NANO100 SERIES DATASHEET VREF NUMICRO® NANO100 (B) DATASHEET ® PA.4/AD4/LCD_SEG21 PA.3/AD3/LCD_SEG22 PA.2/AD2/LCD_SEG23 PA.1/AD1 PA.0/AD0 AVSS ICE_CLK/PF.1 ICE_DAT/PF.0 PA.12/LCD_SEG24 PA.13/LCD_SEG25 PA.14/LCD_SEG26 PA.15/LCD_SEG27 PC.8/LCD_SEG28 PC.9/LCD_SEG29 PC.10/LCD_SEG30 PC.11/LCD_SEG31 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro Nano130 LQFP 64-pin 48 3.3.4.2 LCD_SEG20/AD5/PA.5 49 32 PB.9/LCD_V3 LCD_SEG19/AD6/PA.6 50 31 PB.10/LCD_V2 VREF 51 30 PB.11/LCD_V1 AVDD 52 29 VLCD LCD_SEG17/PC.7 53 28 PC.0/LCD_DH1 PC.6 54 27 PC.1/LCD_DH2 LCD_SEG16/PC.15 55 26 PC.2/LCD_COM0 LCD_SEG15/PC.14 56 25 PC.3/LCD_COM1 LCD_SEG14/PB.15 57 24 PB.3/LCD_COM2 XT1_IN 58 23 PB.2/LCD_COM3 XT1_OUT 59 22 PB.1/LCD_SEG0(COM4) nRESET 60 21 PB.0/LCD_SEG1(COM5) VSS 61 20 USB_D+ VDD 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP LCD_SEG13/PB.8 64 17 USB_VBUS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LCD_SEG11/PB.13 LCD_SGE10/PB.12 X32O X32I LCD_SGE9/PA.11 LCD_SGE8/PA.10 LCD_SGE7/PA.9 LCD_SGE6/PA.8 LCD_SGE5/PB.4 LCD_SGE4/PB.5 LCD_SGE3/PB.6 LCD_SGE2/PB.7 LDO_CAP VDD VSS NANO100 SERIES DATASHEET LCD_SEG12/PB.14 Nano130 LQFP 64-pin ® Figure 3‑11 NuMicro Nano130 LQFP 64-pin Diagram May 31, 2016 Page 46 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 3.4 Pin Description 3.4.1 NuMicro® Nano100 Pin Description Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 1 2 3 4 Pin Type Pin Name Description PE.13 I/O General purpose digital I/O pin PB.14 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin SC2_CD I SmartCard2 card detect pin 1 nd SPI2_SS1 I/O SPI2 2 PB.13 I/O General purpose digital I/O pin EBI_AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital I/O pin EBI_AD0 I/O EBI Address/Data bus bit0 FCLKO O Frequency Divider output pin slave select pin 2 3 1 5 NC 6 4 2 X32O O External 32.768 kHz crystal output pin 7 5 3 X32I I External 32.768 kHz crystal input pin 8 10 11 May 31, 2016 6 7 8 4 5 PA.11 I/O General purpose digital I/O pin I2C1_SCL I/O I C1 clock pin EBI_nRD O EBI read enable output pin SC0_RST O SmartCard0 RST pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin PA.10 I/O General purpose digital I/O pin I2C1_SDA I/O I C1 data I/O pin EBI_nWR O EBI write enable output pin SC0_PWR O SmartCard0 Power pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin PA.9 I/O General purpose digital I/O pin I2C0_SCL I/O I C0 clock pin SC0_DAT I/O SmartCard0 DATA pin(SC0_UART_RXD) SPI2_CLK I/O SPI2 serial clock pin 2 st 2 st 2 6 Page 47 of 160 Revision 1.08 NANO100 SERIES DATASHEET 9 NC NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin Pin Type Pin Name Description PA.8 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin SC0_CLK O SmartCard0 clock pin(SC0_UART_TXD) SPI2_SS0 I/O SPI2 1 slave select pin 13 PD.8 I/O General purpose digital I/O pin 14 PD.9 I/O General purpose digital I/O pin 15 PD.10 I/O General purpose digital I/O pin 16 PD.11 I/O General purpose digital I/O pin 17 PD.12 I/O General purpose digital I/O pin 18 PD.13 I/O General purpose digital I/O pin PB.4 I/O General purpose digital I/O pin UART1_RXD I UART1 Data receiver input pin SC0_CD I SmartCard0 card detect pin 12 19 20 NANO100 SERIES DATASHEET 21 22 9 10 11 st 8 st SPI2_SS0 I/O SPI2 1 slave select pin PB.5 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin SC0_RST O SmartCard0 RST pin SPI2_CLK I/O SPI2 serial clock pin PB.6 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin EBI_ALE O EBI address latch enable output pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin PB.7 I/O General purpose digital I/O pin UART1_CTSn I UART1 Clear to Send input pin EBI_nCS O EBI chip select enable output pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin 9 12 st 13 23 24 2 7 st NC 14 10 LDO_CAP P LDO output pin 25 NC 26 NC May 31, 2016 Page 48 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 27 15 11 Pin Name VDD Pin Type Description P Power supply for I/O ports and LDO source 28 NC VSS P Ground 30 VSS P Ground 31 VSS P Ground 32 VSS P Ground 33 PE.12 I/O General purpose digital I/O pin 34 PE.11 I/O General purpose digital I/O pin 35 PE.10 I/O General purpose digital I/O pin 36 PE.9 I/O General purpose digital I/O pin 37 PE.8 I/O General purpose digital I/O pin 38 PE.7 I/O General purpose digital I/O pin 29 16 12 NC 40 NC 41 NC 42 NC 43 NC I/O General purpose digital I/O pin UART0_RXD I UART0 Data receiver input pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin PB.1 I/O General purpose digital I/O pin UART0_TXD O UART0 Data transmitter output pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin PB.2 I/O General purpose digital I/O pin UART0_RTSn O UART0 Request to Send output pin EBI_nWRL O EBI low byte write enable output pin SPI1_CLK I/O SPI1 serial clock pin PB.3 I/O General purpose digital I/O pin UART0_CTSn I UART0 Clear to Send input pin EBI_nWRH O EBI high byte write enable output pin PB.0 44 45 46 47 May 31, 2016 17 18 19 20 13 14 st st 15 16 Page 49 of 160 Revision 1.08 NANO100 SERIES DATASHEET 39 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin Pin Name Pin Type SPI1_SS0 I/O SPI1 1 slave select pin Description st 48 21 PD.6 I/O General purpose digital I/O pin 49 22 PD.7 I/O General purpose digital I/O pin 50 23 PD.14 I/O General purpose digital I/O pin 51 24 PD.15 I/O General purpose digital I/O pin PC.5 I/O General purpose digital I/O pin SPI0_MOSI1 I/O SPI0 2 PC.4 I/O General purpose digital I/O pin SPI0_MISO1 I/O SPI0 2 PC.3 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin I2S_DO O I S data output SC1_RST O SmartCard1 RST pin PC.2 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin 52 53 54 55 NANO100 SERIES DATASHEET 56 57 25 26 27 28 17 18 58 2 st 2 I I S data input SC1_PWR O SmartCard1 PWR pin PC.1 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin I2S_BCLK I/O I S bit clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) PC.0 / MCLKO I/O General purpose digital I/O pin / Module clock output pin SPI0_SS0 I/O SPI0 1 slave select pin I2S_LRCLK I/O I S left right channel clock SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) PE.6 I/O General purpose digital I/O pin 2 st 2 NC 60 NC May 31, 2016 29 MISO (Master In, Slave Out) pin st 59 61 nd MOSI (Master Out, Slave In) pin I2S_DI 19 20 nd PE.5 I/O General purpose digital I/O pin PWM1_CH1 I/O PWM1 Channel1 output 21 Page 50 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 62 63 64 30 31 32 22 23 24 Pin Type Pin Name Description PB.11 I/O General purpose digital I/O pin PWM1_CH0 I/O PWM1 Channel0 output TM3 O Timer3 external counter input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PB.10 I/O General purpose digital I/O pin SPI0_SS1 I/O SPI0 2 TM2 O Timer2 external counter input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PB.9 I/O General purpose digital I/O pin SPI1_SS1 I/O SPI1 2 TM1 O Timer1 external counter input SC2_RST O SmartCard2 RST pin INT0 I External interrupt0 input pin PE.4 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PE.3 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PE.2 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin PE.1 I/O General purpose digital I/O pin. PWM1_CH3 I/O PWM1 Channel3 output SPI0_SS0 I/O SPI0 1 slave select pin PE.0 I/O General purpose digital I/O pin PWM1_CH2 I/O PWM1 Channel2 output I2S_MCLK O I S master clock output pin PC.13 I/O General purpose digital I/O pin SPI1_MOSI1 I/O SPI1 2 PWM1_CH1 O PWM1 Channel1 output st nd slave select pin st 65 nd slave select pin st st 67 68 69 70 May 31, 2016 Page 51 of 160 st 2 nd MOSI (Master Out, Slave In) pin Revision 1.08 NANO100 SERIES DATASHEET 66 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 71 72 73 74 NANO100 SERIES DATASHEET 75 76 77 May 31, 2016 33 34 35 Pin Name Pin Type SNOOPER I Snooper pin INT1 I External interrupt 1 I2C0_SCL O I C0 clock pin PC.12 I/O General purpose digital I/O pin SPI1_MISO1 I/O SPI1 2 PWM1_CH0 O PWM1 Channel0 output INT0 I External interrupt0 input pin Description 2 nd MISO (Master In, Slave Out) pin 2 I2C0_SDA I/O I C0 data I/O pin PC.11 I/O General purpose digital I/O pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin UART1_TXD O UART1 Data transmitter output pin PC.10 I/O General purpose digital I/O pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin UART1_RXD I UART1 Data receiver input pin PC.9 I/O General purpose digital I/O pin SPI1_CLK I/O SPI1 serial clock pin I2C1_SCL I/O I C1 clock pin PC.8 I/O General purpose digital I/O pin SPI1_SS0 I/O SPI1 1 slave select pin EBI_MCLK O EBI external clock output pin I2C1_SDA I/O I C1 data I/O pin PA.15 I/O General purpose digital I/O pin PWM0_CH3 I/O PWM0 Channel3 output I2S_MCLK O I S master clock output pin TC3 I Timer3 capture input SC0_PWR O SmartCard0 Power pin UART0_TXD O UART0 Data transmitter output pin PA.14 I/O General purpose digital I/O pin PWM0_CH2 I/O PWM0 Channel2 output EBI_AD15 I/O EBI Address/Data bus bit15 st st 2 st 36 37 38 2 2 25 26 Page 52 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 78 39 27 Pin Type Pin Name TC2 I Timer2 capture input UART0_RXD I UART0 Data receiver input pin PA.13 I/O General purpose digital I/O pin PWM0_CH1 I/O PWM0 Channel1 output EBI_AD14 I/O EBI Address/Data bus bit14 I TC1 79 40 28 42 29 2 I/O I C0 clock pin PA.12 I/O General purpose digital I/O pin PWM0_CH0 I/O PWM0 Channel0 output EBI_AD13 I/O EBI Address/Data bus bit13 I Timer0 capture input 2 I2C0_SDA I/O I C0 data I/O pin ICE_DAT I/O Serial Wired Debugger Data pin PF.0 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin ICE_CLK I Serial Wired Debugger Clock pin PF.1 I/O General purpose digital I/O pin FCLKO O Frequency Divider output pin INT1 I External interrupt1 input pin 30 82 NC 83 VDD P 84 Power supply for I/O ports and LDO source for internal PLL and digital circuit NC 85 VSS P Ground 86 VSS P Ground 87 43 31 88 89 44 32 AVSS AP Ground Pin for analog circuit AVSS AP Ground Pin for analog circuit PA.0 I/O General purpose digital I/O pin AD0 AI ADC analog input0 SC2_CD 90 May 31, 2016 45 33 PA.1 I I/O Page 53 of 160 SmartCard2 card detect General purpose digital I/O pin Revision 1.08 NANO100 SERIES DATASHEET 81 41 Timer1 capture input I2C0_SCL TC0 80 Description NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 91 46 Pin Type Pin Name AD1 AI ADC analog input1 EBI_AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin AD2 AI ADC analog input2 EBI_AD11 I/O EBI Address/Data bus bit11 34 I UART1 Data receiver input pin PA.3 I/O General purpose digital I/O pin AD3 AI ADC analog input3 EBI_AD10 I/O EBI Address/Data bus bit10 UART1_TXD O UART1 Data transmitter output pin PA.4 I/O General purpose digital I/O pin AD4 AI ADC analog input4 EBI_AD9 I/O EBI Address/Data bus bit9 SC2_PWR O SmartCard2 Power pin I2C0_SDA I/O I C0 data I/O pin PA.5 I/O General purpose digital I/O pin AD5 AI ADC analog input5 EBI_AD8 I/O EBI Address/Data bus bit8 SC2_RST O SmartCard2 RST pin I2C0_SCL I/O I C0 clock pin PA.6 I/O General purpose digital I/O pin AD6 AI ADC analog input6 EBI_AD7 I/O EBI Address/Data bus bit7 UART1_RXD 92 93 NANO100 SERIES DATASHEET 94 95 47 48 49 50 Description 35 36 37 2 2 38 TC3 I Timer3 capture input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) PWM0_CH3 O PWM0 Channel3 output PA.7 I/O General purpose digital I/O pin AD7 AI ADC analog input7 EBI_AD6 I/O EBI Address/Data bus bit6 96 TC2 May 31, 2016 I Page 54 of 160 Timer2 capture input Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 97 51 39 Pin Name Pin Type SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) PWM0_CH2 O PWM0 Channel2 output AP VREF 98 99 101 Voltage reference input for ADC NC 52 40 AVDD AP Power supply for internal analog circuit PD.0 I/O General purpose digital I/O pin I UART1 Data receiver input pin UART1_RXD 100 Description st I/O SPI2 1 slave select pin SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) AD8 AI ADC analog input8 PD.1 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD). AD9 AI ADC analog input9 PD.2 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin I2S_LRCLK I/O I S left right channel clock SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin SC1_PWR O SmartCard1 Power pin AD10 AI ADC analog input10 PD.3 I/O General purpose digital I/O pin I UART1 Clear to Send input pin 2 102 UART1_CTSn st 2 I2S_BCLK I/O I S bit clock pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin SC1_RST O SmartCard1 RST pin AD11 AI ADC analog input11 103 104 NC PD.4 I/O 105 I2S_DI May 31, 2016 st I Page 55 of 160 General purpose digital I/O pin 2 I S data input Revision 1.08 NANO100 SERIES DATASHEET SPI2_SS0 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin Pin Type Pin Name SPI2_MISO1 I SC1_CD 106 107 108 NANO100 SERIES DATASHEET 109 110 111 53 54 41 I/O May 31, 2016 SPI2 2 nd MISO (Master In, Slave Out) pin SmartCard1 card detect PD.5 I/O General purpose digital I/O pin I2S_DO O I S data output SPI2_MOSI1 I/O SPI2 2 PC.7 I/O General purpose digital I/O pin DA1_OUT AO DAC 1 output EBI_AD5 I/O EBI Address/Data bus bit5 2 nd MOSI (Master Out, Slave In) pin TC1 I Timer1 capture input PWM0_CH1 O PWM1 Channel1 output PC.6 I/O General purpose digital I/O pin DA0_OUT I EBI_AD4 I/O DAC0 output EBI Address/Data bus bit4 42 TC0 I Timer0 capture input SC1_CD I SmartCard1 card detect pin PWM0_CH0 O PWM0 Channel0 output PC.15 I/O General purpose digital I/O pin EBI_AD3 I/O EBI Address/Data bus bit3 55 56 57 TC0 I Timer0 capture input PWM1_CH2 O PWM1 Channel1 output PC.14 I/O General purpose digital I/O pin EBI_AD2 I/O EBI Address/Data bus bit2 PWM1_CH3 I/O PWM1 Channel3 output PB.15 I/O General purpose digital I/O pin INT1 I External interrupt1 input pin SNOOPER I Snooper pin SC1_CD I SmartCard1 card detect 43 112 113 Description NC 58 XT1_IN O External 4~24 MHz crystal output pin PF.3 I/O General purpose digital I/O pin 44 Page 56 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP/QFN 128-pin 64-pin 48-pin 114 59 Pin Name Pin Type XT1_OUT I I/O 115 General purpose digital I/O pin NC 116 60 117 61 46 118 nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. VSS P Ground VSS P Ground 119 NC 62 VDD P 121 Power supply for I/O ports and LDO source for internal PLL and digital circuit NC PF.4 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin PF.5 I/O General purpose digital I/O pin I2C0_SCL I/O I C0 clock pin 122 123 124 125 External 4~24 MHz crystal input pin 45 PF.2 120 Description 63 47 2 2 P Ground PVSS P PLL Ground PB.8 I/O General purpose digital I/O pin STADC I ADC external trigger input. TM0 I Timer0 external counter input INT0 I External interrupt0 input pin SC2_PWR O SmartCard2 Power pin 127 PE.15 I/O General purpose digital I/O pin 128 PE.14 I/O General purpose digital I/O pin 126 64 48 Note: Pin Type: I = Digital Input, O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog Power. May 31, 2016 Page 57 of 160 Revision 1.08 NANO100 SERIES DATASHEET VSS NUMICRO® NANO100 (B) DATASHEET 3.4.2 NuMicro® Nano110 Pin Description Pin No. LQFP 128-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description PE.13 I/O General purpose digital I/O pin LCD_SEG27 O LCD segment output 27 at LQFP128 PB.14 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin SC2_CD I SmartCard2 card detect 1 2 3 4 1 nd NANO100 SERIES DATASHEET SPI2_SS1 I/O SPI2 2 LCD_SEG12 O LCD segment output 12 at LQFP64 LCD_SEG26 O LCD segment output 26 at LQFP128 PB.13 I/O General purpose digital I/O pin EBI_AD1 I/O EBI Address/Data bus bit1 LCD_SEG11 O LCD segment output 11 at LQFP64 LCD_SEG25 O LCD segment output 25 at LQFP128 PB.12 I/O General purpose digital I/O pin EBI_AD0 I/O EBI Address/Data bus bit0 FCLKO O Frequency Divider output pin LCD_SEG10 O LCD segment output 10 at LQFP64 LCD_SEG24 O LCD segment output 24 at LQFP128 slave select pin 2 3 5 NC 6 4 X32O O External 32.768 kHz crystal output pin 7 5 X32I I External 32.768 kHz crystal input pin 8 9 10 May 31, 2016 NC 6 PA.11 I/O General purpose digital I/O pin I2C1_SCL I/O I C1 clock pin EBI_nRD O EBI read enable output pin SC0_RST O SmartCard0 RST pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin LCD_SEG9 O LCD segment output 9 at LQFP64 LCD_SEG23 O LCD segment output 23 at LQFP128 PA.10 I/O General purpose digital I/O pin I2C1_SDA I/O I C1 data I/O pin 7 Page 58 of 160 2 st 2 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 11 12 LQFP 48-pin Pin Name Pin Type Description EBI_nWR O EBI write enable output pin SC0_PWR O SmartCard0 Power pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin LCD_SEG8 O LCD segment output 8 at LQFP64 LCD_SEG22 O LCD segment output 22 at LQFP128 PA.9 I/O General purpose digital I/O pin I2C0_SCL I/O I C0 clock pin SC0_DAT I/O SmartCard0 DATA pin(SC0_UART_RXD) SPI2_CLK I/O SPI2 serial clock pin LCD_SEG7 O LCD segment output 7 at LQFP64 LCD_SEG21 O LCD segment output 21 at LQFP128 PA.8 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin SC0_CLK O SmartCard0 clock pin(SC0_UART_TXD) SPI2_SS0 I/O SPI2 1 slave select pin LCD_SEG6 O LCD segment output 6 at LQFP64 LCD_SEG20 O LCD segment output 20 at LQFP128 PD.8 I/O General purpose digital I/O pin LCD_SEG19 O LCD segment output 19 at LQFP128 PD.9 I/O General purpose digital I/O pin LCD_SEG18 O LCD segment output 18 at LQFP128 PD.10 I/O General purpose digital I/O pin LCD_SEG17 O LCD segment output 17 at LQFP128 PD.11 I/O General purpose digital I/O pin LCD_SEG16 O LCD segment output 16 at LQFP128 PD.12 I/O General purpose digital I/O pin LCD_SEG15 O LCD segment output 15 at LQFP128 PD.13 I/O General purpose digital I/O pin LCD_SEG14 O LCD segment output 14 at LQFP128 PB.4 I/O General purpose digital I/O pin st 2 8 9 2 st 14 15 16 17 18 19 May 31, 2016 10 Page 59 of 160 Revision 1.08 NANO100 SERIES DATASHEET 13 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 20 21 NANO100 SERIES DATASHEET 22 LQFP 48-pin Pin Name Pin Type UART1_RXD I UART1 Data receiver input pin SC0_CD I SmartCard0 card detect pin st SPI2_SS0 I/O SPI2 1 slave select pin LCD_SEG5 O LCD segment output 5 at LQFP64 LCD_SEG13 O LCD segment output 13 at LQFP128 PB.5 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin SC0_RST O SmartCard0 RST pin SPI2_CLK I/O SPI2 serial clock pin LCD_SEG4 O LCD segment output 4 at LQFP64 LCD_SEG12 O LCD segment output 12 at LQFP128 PB.6 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin EBI_ALE O EBI address latch enable output pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin LCD_SEG3 O LCD segment output 3 at LQFP64 LCD_SEG11 O LCD segment output 11 at LQFP128 PB.7 I/O General purpose digital I/O pin UART1_CTSn I UART1 Clear to Send input pin EBI_nCS O EBI chip select enable output pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin LCD_SEG2 O LCD segment output 2 at LQFP64 LCD_SEG10 O LCD segment output 10 at LQFP128 11 12 st 13 23 24 Description st NC 14 LDO_CAP P LDO output pin 25 NC 26 NC 27 15 VDD P 28 29 May 31, 2016 Power supply for I/O ports and LDO source NC 16 VSS P Page 60 of 160 Ground Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description 30 VSS P Ground 31 VSS P Ground 32 VSS P Ground I/O General purpose digital I/O pin I UART1 Clear to Send input pin PE.11 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin PE.10 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin PE.9 I/O General purpose digital I/O pin I UART1 Data receiver input pin PE.8 I/O General purpose digital I/O pin LCD_SEG9 O LCD segment output 9 at LQFP128 PE.7 I/O General purpose digital I/O pin LCD_SEG8 O LCD segment output 8 at LQFP128 PE.12 33 UART1_CTSn 34 35 36 UART1_RXD 37 38 NC 40 NC 41 NC 42 NC 43 NC I/O General purpose digital I/O pin UART0_RXD I UART0 Data receiver input pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin LCD_SEG1 O LCD segment output 1 at LQFP64 (or as LD_COM5) LCD_SEG7 O LCD segment output 7 at LQFP128 PB.1 I/O General purpose digital I/O pin UART0_TXD O UART0 Data transmitter output pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin LCD_SEG0 O LCD segment output 0 at LQFP64 (or as LCD_COM4) PB.0 44 45 May 31, 2016 17 18 Page 61 of 160 st st Revision 1.08 NANO100 SERIES DATASHEET 39 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 46 47 48 49 NANO100 SERIES DATASHEET 50 51 Pin Type Description LCD_SEG6 O LCD segment output 6 at LQFP128 PB.2 I/O General purpose digital I/O pin UART0_RTSn O UART0 Request to Send output pin EBI_nWRL O EBI low byte write enable output pin SPI1_CLK I/O SPI1 serial clock pin LCD_COM3 O LCD common output 3 at LQFP64 LCD_SEG5 O LCD segment output 5 at LQFP128 PB.3 I/O General purpose digital I/O pin UART0_CTSn I UART0 Clear to Send input pin EBI_nWRH O EBI high byte write enable output pin SPI1_SS0 I/O SPI1 1 slave select pin LCD_COM2 O LCD common output 2 at LQFP64 LCD_SEG4 O LCD segment output 4 at LQFP128 PD.6 I/O General purpose digital I/O pin LCD_SEG3 O LCD segment output 3 at LQFP128 PD.7 I/O General purpose digital I/O pin LCD_SEG2 O LCD segment output 2 at LQFP128 PD.14 I/O General purpose digital I/O pin LCD_SEG1 O LCD segment output 1 at LQFP128 (or as LCD_COM5) PD.15 I/O General purpose digital I/O pin LCD_SEG0 O LCD segment output 0 at LQFP128 (or as LCD_COM4) PC.5 I/O General purpose digital I/O pin SPI0_MOSI1 I/O SPI0 2 LCD_COM3 O LCD common output 3 at LQFP128 PC.4 I/O General purpose digital I/O pin SPI0_MISO1 I/O SPI0 2 LCD_COM2 O LCD common output 2 at LQFP128 PC.3 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin 20 st 21 22 23 24 53 May 31, 2016 Pin Name 19 52 54 LQFP 48-pin 25 Page 62 of 160 nd nd MOSI (Master Out, Slave In) pin MISO (Master In, Slave Out) pin st Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 55 56 Pin Type 27 28 29 O I S data output SC1_RST O SmartCard1 RST pin LCD_COM1 O LCD common output 1 at LQFP64 LCD_COM1 O LCD common output 1 at LQFP128 PC.2 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin st 2 I2S_DI I I S data input SC1_PWR O SmartCard1 PWR pin LCD_COM0 O LCD common output 0 at LQFP64 LCD_COM0 O LCD common output 0 at LQFP128 PC.1 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin I2S_BCLK I/O I S bit clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) LCD_DH2 O LCD externl capacitor pin of charge pump circuit at LQFP64 LCD_DH2 O LCD externl capacitor pin of charge pump circuit at LQFP128 PC.0 / MCLKO I/O General purpose digital I/O pin / Module clock output pin SPI0_SS0 I/O SPI0 1 slave select pin I2S_LRCLK I/O I S left right channel clock SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) LCD_DH1 O LCD externl capacitor pin of charge pump circuit at LQFP64 LCD_DH1 O LCD externl capacitor pin of charge pump circuit at LQFP128 PE.6 I/O General purpose digital I/O pin LCD_VLCD AO LCD power supply pin 2 st 2 NC 61 May 31, 2016 2 I2S_DO 60 62 Description 26 58 59 Pin Name PE.5 I/O General purpose digital I/O pin PB.11 I/O General purpose digital I/O pin PWM1_CH0 I/O PWM1 Channel0 output 30 Page 63 of 160 Revision 1.08 NANO100 SERIES DATASHEET 57 LQFP 48-pin NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 63 NANO100 SERIES DATASHEET 64 31 32 LQFP 48-pin Pin Name Pin Type Description TM3 O Timer3 external counter input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin LCD_V1 O Unit voltage for LCD charge pump circuit at LQFP64 LCD_V1 O LCD Unit voltage for LCD charge pump circuit at LQFP128 PB.10 I/O General purpose digital I/O pin SPI0_SS1 I/O SPI0 2 TM2 O Timer2 external counter input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin LCD_V2 O LCD driver biasing voltage at LQFP64 LCD_V2 O LCD driver biasing voltage at LQFP128 PB.9 I/O General purpose digital I/O pin SPI1_SS1 I/O SPI1 2 TM1 O Timer1 external counter input SC2_RST O SmartCard2 RST pin INT0 I External interrupt0 input pin LCD_V3 O LCD driver biasing voltage at LQFP64 LCD_V3 O LCD driver biasing voltage at LQFP128 PE.4 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PE.3 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PE.2 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin PE.1 I/O General purpose digital I/O pin PWM1_CH3 I/O PWM1 Channel3 output SPI0_SS0 I/O SPI0 1 slave select pin PE.0 I/O General purpose digital I/O pin 65 66 st nd slave select pin st nd slave select pin st st 67 68 69 May 31, 2016 Page 64 of 160 st Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description PWM1_CH2 I/O PWM1 Channel2 output I2S_MCLK O I S master clock output pin PC.13 I/O General purpose digital I/O pin SPI1_MOSI1 I/O SPI1 2 PWM1_CH1 O PWM1 Channel1 output SNOOPER I Snooper pin INT1 I External interrupt 1 I2C0_SCL O I C0 clock pin PC.12 I/O General purpose digital I/O pin SPI1_MISO1 I/O SPI1 2 PWM1_CH0 O PWM1 Channel0 output INT0 I External interrupt0 input pin 2 nd MOSI (Master Out, Slave In) pin 70 71 72 74 75 May 31, 2016 nd MISO (Master In, Slave Out) pin 2 I2C0_SDA I/O I C0 data I/O pin PC.11 I/O General purpose digital I/O pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin UART1_TXD O UART1 Data transmitter output pin LCD_SEG31 O LCD segment output 31 at LQFP64 PC.10 I/O General purpose digital I/O pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin UART1_RXD I UART1 Data receiver input pin LCD_SEG30 O LCD segment output 30 at LQFP64 PC.9 I/O General purpose digital I/O pin SPI1_CLK I/O SPI1 serial clock pin I2C1_SCL I/O I C1 clock pin LCD_SEG29 O LCD segment output 29 at LQFP64 PC.8 I/O General purpose digital I/O pin SPI1_SS0 I/O SPI1 1 slave select pin EBI_MCLK O EBI external clock output pin I2C1_SDA I/O I C1 data I/O pin LCD_SEG28 O LCD segment output 28 at LQFP64 st 33 st 34 35 36 Page 65 of 160 2 st 2 Revision 1.08 NANO100 SERIES DATASHEET 73 2 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 76 77 78 37 LQFP 48-pin Pin Name Pin Type PA.15 I/O General purpose digital I/O pin PWM0_CH3 I/O PWM0 Channel3 output I2S_MCLK O I S master clock output pin TC3 I Timer3 capture input SC0_PWR O SmartCard0 Power pin UART0_TXD O UART0 Data transmitter output pin LCD_SEG27 O LCD segment output 27 at LQFP64 PA.14 I/O General purpose digital I/O pin PWM0_CH2 I/O PWM0 Channel2 output EBI_AD15 I/O EBI Address/Data bus bit15 TC2 I Timer2 capture input UART0_RXD I UART0 Data receiver input pin LCD_SEG26 O LCD segment output 26 at LQFP64 PA.13 I/O General purpose digital I/O pin PWM0_CH1 I/O PWM0 Channel1 output EBI_AD14 I/O EBI Address/Data bus bit14 39 NANO100 SERIES DATASHEET I 81 2 I/O I C0 clock pin LCD_SEG25 O LCD segment output 25 at LQFP64 PA.12 I/O General purpose digital I/O pin PWM0_CH0 I/O PWM0 Channel0 output EBI_AD13 I/O EBI Address/Data bus bit13 40 I 41 Timer0 capture input 2 I2C0_SDA I/O I C0 data I/O pin LCD_SEG24 O LCD segment output 24 at LQFP64 ICE_DAT I/O Serial Wired Debugger Data pin PF.0 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin ICE_CLK I Serial Wired Debugger Clock pin 42 PF.1 May 31, 2016 Timer1 capture input I2C0_SCL TC0 80 2 38 TC1 79 Description I/O Page 66 of 160 General purpose digital I/O pin Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description FCLKO O Frequency Divider output pin INT1 I External interrupt1 input pin 82 NC 83 P VDD 84 Power supply for I/O ports and LDO source for internal PLL and digital circuit NC 85 VSS P Ground 86 VSS P Ground 87 43 88 89 44 AVSS AP Ground Pin for analog circuit AVSS AP Ground Pin for analog circuit PA.0 I/O General purpose digital I/O pin AD0 AI ADC analog input0 I SC2_CD 90 92 93 May 31, 2016 46 47 48 PA.1 I/O General purpose digital I/O pin AD1 AI ADC analog input1 EBI_AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin AD2 AI ADC analog input2 EBI_AD11 I/O EBI Address/Data bus bit11 UART1_RXD I LCD_SEG23* AO LCD segment output 23 at LQFP64 PA.3 I/O General purpose digital I/O pin AD3 AI ADC analog input3 EBI_AD10 I/O EBI Address/Data bus bit10 UART1_TXD O UART1 Data transmitter output pin LCD_SEG22* AO LCD segment output 22 at LQFP64 PA.4 I/O General purpose digital I/O pin AD4 AI ADC analog input4 EBI_AD9 I/O EBI Address/Data bus bit9 SC2_PWR O SmartCard2 Power pin I2C0_SDA I/O I C0 data I/O pin Page 67 of 160 UART1 Data receiver input pin 2 Revision 1.08 NANO100 SERIES DATASHEET 91 45 SmartCard2 card detect NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 94 95 49 Pin Name Pin Type LCD_SEG21* AO LCD segment output 21 at LQFP64 LCD_SEG39* AO LCD segment output 39 at LQFP128 PA.5 I/O General purpose digital I/O pin AD5 AI ADC analog input5 EBI_AD8 I/O EBI Address/Data bus bit8 SC2_RST O SmartCard2 RST pin I2C0_SCL I/O I C0 clock pin LCD_SEG20* AO LCD segment output 19 at LQFP64 LCD_SEG38* AO LCD segment output 37 at LQFP128 PA.6 I/O General purpose digital I/O pin AD6 AI ADC analog input6 EBI_AD7 I/O EBI Address/Data bus bit7 NANO100 SERIES DATASHEET 100 I Timer3 capture input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) PWM0_CH3 O PWM0 Channel3 output LCD_SEG19* AO LCD segment output 19 at LQFP64 LCD_SEG37* AO LCD segment output 37 at LQFP128 PA.7 I/O General purpose digital I/O pin AD7 AI ADC analog input7 EBI_AD6 I/O EBI Address/Data bus bit6 I TC2 51 Timer2 capture input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) PWM0_CH2 O PWM0 Channel2 output LCD_SEG36* AO LCD segment output 36 output at LQFP128 VREF AP Voltage reference input for ADC NC 52 AVDD AP Power supply for internal analog circuit PD.0 I/O General purpose digital I/O pin I UART1 Data receiver input pin UART1_RXD SPI2_SS0 May 31, 2016 2 TC3 98 99 Description 50 96 97 LQFP 48-pin I/O Page 68 of 160 st SPI2 1 slave select pin Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 101 LQFP 48-pin Pin Name Pin Type SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) AD8 AI ADC analog input8 PD.1 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) AD9 AI ADC analog input9 PD.2 I/O General purpose digital I/O pin UART1_RTSn Description UART1 Request to Send output pin 2 I2S_LRCLK I/O I S left right channel clock SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin SC1_PWR O SmartCard1 Power pin AD10 AI ADC analog input10 PD.3 I/O General purpose digital I/O pin 102 UART1_CTSn st UART1 Clear to Send input pin 2 I2S_BCLK I/O I S bit clock pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin SC1_RST O SmartCard1 RST pin AD11 AI ADC analog input11 103 NC I/O PD.4 I I2S_DI 105 SPI2_MISO1 I/O I SC1_CD General purpose digital I/O pin 2 I S data input SPI2 2 May 31, 2016 53 MISO (Master In, Slave Out) pin SmartCard1 card detect LCD_SEG35 AO LCD segment output 35 at LQFP10 PD.5 I/O General purpose digital I/O pin I2S_DO O I S data output SPI2_MOSI1 I/O SPI2 2 LCD_SEG34 AO LCD segment output 34 at LQFP128 PC.7 I/O General purpose digital I/O pin 2 106 107 nd Page 69 of 160 nd MOSI (Master Out, Slave In) pin Revision 1.08 NANO100 SERIES DATASHEET 104 st NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 108 109 NANO100 SERIES DATASHEET 110 111 LQFP 48-pin Pin Name Pin Type DA1_OUT AO DAC 1 output EBI_AD5 I/O EBI Address/Data bus bit5 TC1 I Timer1 capture input PWM0_CH1 O PWM1 Channel1 output LCD_SEG17* AO LCD segment output 17 at LQFP64 PC.6 I/O General purpose digital I/O pin DA0_OUT I EBI_AD4 I/O May 31, 2016 DAC0 output EBI Address/Data bus bit4 54 TC0 I Timer0 capture input SC1_CD I SmartCard1 card detect pin PWM0_CH0 O PWM0 Channel0 output PC.15 I/O General purpose digital I/O pin EBI_AD3 I/O EBI Address/Data bus bit3 TC0 I Timer0 capture input PWM1_CH2 O PWM1 Channel1 output LCD_SEG16 AO LCD segment output 16 at LQFP64 LCD_SEG33 AO LCD segment output 33 at LQFP128 PC.14 I/O General purpose digital I/O pin EBI_AD2 I/O EBI Address/Data bus bit2 PWM1_CH3 I/O PWM1 Channel3 output LCD_SEG15 AO LCD segment output 15 at LQFP64 LCD_SEG32 AO LCD segment output 32 at LQFP128 PB.15 I/O General purpose digital I/O pin INT1 I External interrupt1 input pin SNOOPER I Snooper pin 55 56 57 LCD_SEG14 AO LCD segment output 14 at LQFP64 LCD_SEG31 AO LCD segment output 31 at LQFP128 112 113 Description NC XT1_IN O External 4~24 MHz crystal output pin PF.3 I/O General purpose digital I/O pin 58 Page 70 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128-pin LQFP 64-pin 114 59 LQFP 48-pin Pin Name Pin Type XT1_OUT I I/O PF.2 115 Description External 4~24 MHz crystal input pin General purpose digital I/O pin NC 116 60 nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. 117 61 VSS P Ground VSS P Ground 118 119 120 NC 62 P VDD 121 NC PF.4 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin PF.5 I/O General purpose digital I/O pin I2C0_SCL I/O I C0 clock pin 122 123 124 125 63 64 2 2 VSS P Ground PVSS P PLL Ground PB.8 I/O General purpose digital I/O pin STADC I ADC external trigger input. TM0 I Timer0 external counter input INT0 I External interrupt0 input pin SC2_PWR O SmartCard2 Power pin LCD_SEG13 AO LCD segment output 13 at LQFP64 LCD_SEG30 AO LCD segment output 30 at LQFP128 PE.15 I/O General purpose digital I/O pin LCD_SEG29 O LCD segment output 29 at LQFP128 PE.14 I/O General purpose digital I/O pin LCD_SEG28 O LCD segment output 28 at LQFP128 127 128 Note: 1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power; 2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance. May 31, 2016 Page 71 of 160 Revision 1.08 NANO100 SERIES DATASHEET 126 Power supply for I/O ports and LDO source for internal PLL and digital circuit NUMICRO® NANO100 (B) DATASHEET 3.4.3 NuMicro® Nano120 Pin Description Pin No. LQFP 128 LQFP 64 LQFP 48 1 2 3 4 Pin Name Pin Type Description PE.13 I/O General purpose digital IO pin PB.14 I/O General purpose digital IO pin INT0 I External interrupt0 input pin SC2_CD I SmartCard2 card detect 1 nd SPI2_SS1 I/O SPI2 2 PB.13 I/O General purpose digital IO pin EBI_AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital IO pin EBI_AD0 I/O EBI Address/Data bus bit0 FCLKO O Frequency Divider output pin slave select pin 2 3 1 5 NC 6 4 2 X32O O External 32.768 kHz crystal output pin 7 5 3 X32I I External 32.768 kHz crystal input pin 8 NANO100 SERIES DATASHEET 9 10 11 12 NC 6 7 8 9 May 31, 2016 4 5 PA.11 I/O General purpose digital IO pin I2C1_SCL I/O I C 1 clock pin EBI_nRD O EBI read enable output pin SC0_RST O SmartCard0 RST pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin PA.10 I/O General purpose digital IO pin I2C1_SDA I/O I C 1 data I/O pin EBI_nWR O EBI write enable output pin SC0_PWR O SmartCard0 Power pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin PA.9 I/O General purpose digital IO pin I2C0_SCL I/O I C 0 clock pin SC0_DAT I/O SmartCard0 DATA pin(SC0_UART_RXD) SPI2_CLK I/O SPI2 serial clock pin PA.8 I/O General purpose digital IO pin 2 st 2 st 2 6 7 Page 72 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name Pin Type Description 2 I2C0_SDA I/O I C 0 data I/O pin SC0_CLK O SmartCard0 clock pin(SC0_UART_TXD) SPI2_SS0 I/O SPI2 1 slave select pin 13 PD.8 I/O General purpose digital IO pin 14 PD.9 I/O General purpose digital IO pin 15 PD.10 I/O General purpose digital IO pin 16 PD.11 I/O General purpose digital IO pin 17 PD.12 I/O General purpose digital IO pin 18 PD.13 I/O General purpose digital IO pin PB.4 I/O General purpose digital IO pin UART1_RXD I UART1 Data receiver input pin SC0_CD I SmartCard0 card detect pin 19 20 22 11 8 I/O SPI2 1 slave select pin PB.5 I/O General purpose digital IO pin UART1_TXD O UART1 Data transmitter output pin SC0_RST O SmartCard0 RST pin SPI2_CLK I/O SPI2 serial clock pin PB.6 I/O General purpose digital IO pin UART1_nRTS O UART1 Request to Send output pin EBI_ALE O EBI address latch enable output pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin PB.7 I/O General purpose digital IO pin UART1_nCTS I UART1 Clear to Send input pin EBI_nCS O EBI chip select enable output pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin 9 12 st 13 23 24 st SPI2_SS0 st NC 14 10 LDO_CAP P LDO output pin 25 NC 26 NC 27 NANO100 SERIES DATASHEET 21 10 st 15 May 31, 2016 11 VDD P Power supply for I/O ports and LDO source Page 73 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name Pin Type 28 Description NC VSS P Ground 30 VSS P Ground 31 VSS P Ground 32 VSS P Ground 33 PE.12 I/O General purpose digital IO pin 34 PE.11 I/O General purpose digital IO pin 35 PE.10 I/O General purpose digital IO pin 36 PE.9 I/O General purpose digital IO pin 37 PE.8 I/O General purpose digital IO pin 38 PE.7 I/O General purpose digital IO pin 29 16 12 39 NC USB POWER SUPPLY: From USB Host or HUB. NANO100 SERIES DATASHEET 40 17 13 USB_VBUS 41 18 14 USB_VDD33_C Internal Power Regulator Output 3.3V Decoupling USB AP Pin 42 19 15 USB_D- USB USB Differential Signal D- 43 20 16 USB_D+ USB USB Differential Signal D+ I/O General purpose digital IO pin UART0_RXD I UART0 Data receiver input pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin PB.1 I/O General purpose digital IO pin UART0_TXD O UART0 Data transmitter output pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin PB.2 I/O General purpose digital IO pin UART0_nRTS O UART0 Request to Send output pin EBI_nWRL O EBI low byte write enable output pin SPI1_CLK I/O SPI1 serial clock pin PB.3 I/O General purpose digital IO pin UART0_nCTS I UART0 Clear to Send input pin EBI_nWRH O EBI high byte write enable output pin SPI1_SS0 I/O SPI1 1 slave select pin PB.0 44 45 46 47 21 22 23 24 May 31, 2016 17 18 st st 19 20 st Page 74 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name Pin Type Description 48 PD.6 I/O General purpose digital IO pin 49 PD.7 I/O General purpose digital IO pin 50 PD.14 I/O General purpose digital IO pin 51 PD.15 I/O General purpose digital IO pin PC.5 I/O General purpose digital IO pin SPI0_MOSI1 I/O SPI0 2 PC.4 I/O General purpose digital IO pin SPI0_MISO1 I/O SPI0 2 PC.3 I/O General purpose digital IO pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin I2S_DO O I S data output SC1_RST O SmartCard1 RST pin PC.2 I/O General purpose digital IO pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin 52 53 54 55 57 26 27 28 58 21 22 st 2 st 2 I I S data input SC1_PWR O SmartCard1 PWR pin PC.1 I/O General purpose digital IO pin SPI0_CLK I/O SPI0 serial clock pin I2S_BCLK I/O I S bit clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) PC.0 / MCLKO I/O General purpose digital IO pin / Module clock output pin SPI0_SS0 I/O SPI0 1 slave select pin I2S_LRCLK I/O I S left right channel clock SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) PE.6 I/O General purpose digital IO pin 2 st 2 59 NC 60 NC 61 62 MISO (Master In, Slave Out) pin I2S_DI 23 24 nd MOSI (Master Out, Slave In) pin PE.5 I/O General purpose digital IO pin PWM1_CH1 I/O PWM1 Channel1 output PB.11 I/O General purpose digital IO pin 29 30 May 31, 2016 Page 75 of 160 Revision 1.08 NANO100 SERIES DATASHEET 56 25 nd NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 63 64 LQFP 64 31 32 LQFP 48 Pin Name Pin Type Description PWM1_CH0 I/O PWM1 Channel0 output TM3 O Timer3 external counter input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PB.10 I/O General purpose digital IO pin SPI0_SS1 I/O SPI0 2 TM2 O Timer2 external counter input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PB.9 I/O General purpose digital IO pin SPI1_SS1 I/O SPI1 2 TM1 O Timer1 external counter input SC2_RST O SmartCard2 RST pin INT0 I External interrupt0 input pin PE.4 I/O General purpose digital IO pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PE.3 I/O General purpose digital IO pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PE.2 I/O General purpose digital IO pin SPI0_CLK I/O SPI0 serial clock pin PE.1 I/O General purpose digital IO pin PWM1_CH3 I/O PWM1 Channel3 output SPI0_SS0 I/O SPI0 1 slave select pin PE.0 I/O General purpose digital IO pin PWM1_CH2 I/O PWM1 Channel2 output I2S_MCLK O I S master clock output pin PC.13 I/O General purpose digital IO pin SPI1_MOSI1 I/O SPI1 2 PWM1_CH1 O PWM1 Channel1 output SNOOPER I Snooper pin st nd slave select pin st 65 nd slave select pin st NANO100 SERIES DATASHEET 66 st 67 68 69 st 2 nd MOSI (Master Out, Slave In) pin 70 May 31, 2016 Page 76 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 71 72 73 74 76 77 34 35 Pin Type Description INT1 I External interrupt 1 input pin I2C0_SCL O I C 0 clock pin PC.12 I/O General purpose digital IO pin SPI1_MISO1 I/O SPI1 2 PWM1_CH0 O PWM1 Channel 0 output INT0 I External interrupt 0 input pin 2 nd MISO (Master In, Slave Out) pin 2 I2C0_SDA I/O I C 0 data I/O pin PC.11 I/O General purpose digital IO pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin UART1_TXD O UART1 Data transmitter output pin PC.10 I/O General purpose digital IO pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin UART1_RXD I UART1 Data receiver input pin PC.9 I/O General purpose digital IO pin SPI1_CLK I/O SPI1 serial clock pin I2C1_SCL I/O I C 1 clock pin PC.8 I/O General purpose digital IO pin SPI1_SS0 I/O SPI1 1 slave select pin EBI_MCLK O EBI external clock output pin I2C1_SDA I/O I C 1 data I/O pin PA.15 I/O General purpose digital IO pin PWM0_CH3 I/O PWM0 Channel3 output I2S_MCLK O I S master clock output pin TC3 I Timer3 capture input SC0_PWR O SmartCard0 Power pin UART0_TXD O UART0 Data transmitter output pin PA.14 I/O General purpose digital IO pin PWM0_CH2 I/O PWM0 Channel2 output EBI_AD15 I/O EBI Address/Data bus bit15 st st 2 NANO100 SERIES DATASHEET 75 33 Pin Name st 36 37 38 2 25 26 TC2 May 31, 2016 2 I Timer 2 capture input Page 77 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name 39 27 UART0 Data receiver input pin PA.13 I/O General purpose digital IO pin PWM0_CH1 I/O PWM0 Channel1 output EBI_AD14 I/O EBI Address/Data bus bit14 TC1 79 40 28 81 41 42 29 I Timer1 capture input 2 I2C0_SCL I/O I C 0 clock pin PA.12 I/O General purpose digital IO pin PWM0_CH0 I/O PWM0 Channel0 output EBI_AD13 I/O EBI Address/Data bus bit13 TC0 80 Description I UART0_RXD 78 Pin Type I Timer 0 capture input 2 I2C0_SDA I/O I C 0 data I/O pin ICE_DAT I/O Serial Wired Debugger Data pin PF.0 I/O General purpose digital IO pin INT0 I External interrupt0 input pin ICE_CLK I Serial Wired Debugger Clock pin NANO100 SERIES DATASHEET PF.1 I/O General purpose digital IO pin FCLKO O Frequency Divider output pin INT1 I External interrupt1 input pin 30 82 NC 83 VDD P 84 Power supply for I/O ports and LDO source for internal PLL and digital circuit NC 85 VSS P Ground 86 VSS P Ground 87 43 31 88 89 44 32 AVSS AP Ground Pin for analog circuit AVSS AP Ground Pin for analog circuit PA.0 I/O General purpose digital IO pin AD0 AI ADC analog input0 SC2_CD 90 45 May 31, 2016 I SmartCard2 card detect PA.1 I/O General purpose digital IO pin AD1 AI ADC analog input1 33 Page 78 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 91 LQFP 64 46 LQFP 48 Pin Name 93 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital IO pin AD2 AI ADC analog input2 EBI_AD11 I/O EBI Address/Data bus bit11 34 I UART1 Data receiver input pin PA.3 I/O General purpose digital IO pin AD3 AI ADC analog input3 EBI_AD10 I/O EBI Address/Data bus bit10 UART1_TXD O UART1 Data transmitter output pin PA.4 I/O Digital GPIO pin AD4 AI ADC analog input4 95 48 EBI_AD9 I/O EBI Address/Data bus bit9 SC2_PWR O SmartCard2 Power pin I2C0_SDA I/O I C 0 data I/O pin PA.5 I/O General purpose digital IO pin AD5 AI ADC analog input5 49 EBI_AD8 I/O EBI Address/Data bus bit8 SC2_RST O SmartCard2 RST pin I2C0_SCL I/O I C 0 clock pin PA.6 I/O General purpose digital IO pin AD6 AI ADC analog input6 50 EBI_AD7 I/O EBI Address/Data bus bit7 96 35 36 37 2 38 TC3 I Timer3 capture input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) PWM0_CH3 O PWM0 Channel3 output PA.7 I/O General purpose digital IO pin AD7 AI ADC analog input7 EBI_AD6 I/O EBI Address/Data bus bit6 TC2 SC2_DAT May 31, 2016 2 NANO100 SERIES DATASHEET 94 47 Description EBI_AD12 UART1_RXD 92 Pin Type I I/O Timer2 capture input SmartCard2 DATA pin(SC2_UART_RXD) Page 79 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name PWM0_CH2 97 51 39 VREF Pin Type O AP 98 99 Description PWM0 Channel2 output Voltage reference input for ADC NC 52 40 AVDD AP Power supply for internal analog circuit PD.0 I/O General purpose digital IO pin I UART1 Data receiver input pin UART1_RXD 100 101 st NANO100 SERIES DATASHEET SPI2_SS0 I/O SPI2 1 slave select pin SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) AD8 AI ADC analog input8 PD.1 I/O General purpose digital IO pin UART1_TXD O UART1 Data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) AD9 AI ADC analog input9 PD.2 I/O General purpose digital IO pin UART1_nRTS O UART1 Request to Send output pin I2S_LRCLK I/O I S left right channel clock SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin SC1_PWR O SmartCard1 Power pin AD10 AI ADC analog input10 PD.3 I/O General purpose digital IO pin I UART1 Clear to Send input pin 2 102 UART1_nCTS st 2 I2S_BCLK I/O I S bit clock pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin SC1_RST O SmartCard1 RST pin AD11 AI ADC analog input11 103 104 NC PD.4 105 I2S_DI SPI2_MISO1 May 31, 2016 st I/O I I/O General purpose digital IO pin 2 I S data input SPI2 2 nd MISO (Master In, Slave Out) pin Page 80 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name SC1_CD 106 107 108 53 54 41 Pin Type I I/O General purpose digital IO pin I2S_DO O I S data output SPI2_MOSI1 I/O SPI2 2 PC.7 I/O General purpose digital IO pin DA1+OUT AO DAC 1 output EBI_AD5 I/O EBI Address/Data bus bit5 114 MOSI (Master Out, Slave In) pin I Timer1 capture input PWM0_CH1 O PWM1 Channel1 output PC.6 I/O General purpose digital IO pin DA0_OUT I EBI_AD4 I/O DAC0 output EBI Address/Data bus bit4 42 I Timer 0 capture input SmartCard1 card detect pin PWM0_CH0 O PWM0 Channel0 output PC.15 I/O General purpose digital IO pin EBI_AD3 I/O EBI Address/Data bus bit3 55 56 57 TC0 I Timer0 capture input PWM1_CH2 O PWM1 Channel1 output PC.14 I/O General purpose digital IO pin EBI_AD2 I/O EBI Address/Data bus bit2 PWM1_CH3 I/O PWM1 Channel3 output PB.15 I/O General purpose digital IO pin INT1 I External interrupt1 input pin SNOOPER I Snooper pin SC1_CD I SmartCard1 card detect 43 112 113 nd NANO100 SERIES DATASHEET 111 2 TC1 SC1_CD 110 SmartCard1 card detect PD.5 TC0 109 Description NC 58 59 May 31, 2016 XT1_IN O External 4~24 MHz crystal output pin PF.3 I/O General purpose digital I/O pin 44 45 XT1_OUT I External 4~24 MHz crystal input pin Page 81 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP 128 LQFP 64 LQFP 48 Pin Name PF.2 Pin Type I/O 115 60 117 61 46 118 nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. VSS P Ground VSS P Ground 119 NC 62 VDD P 121 Power supply for I/O ports and LDO source for internal PLL and digital circuit NC PF.4 I/O General purpose digital IO pin I2C0_SDA I/O I C 0 data I/O pin PF.5 I/O General purpose digital IO pin I2C0_SCL I/O I C 0 clock pin 122 123 124 125 General purpose digital I/O pin NC 116 120 Description 63 47 2 2 VSS P Ground PVSS P PLL Ground PB.8 I/O General purpose digital IO pin NANO100 SERIES DATASHEET STADC I ADC external trigger input. TM0 I Timer0 external counter input INT0 I External interrupt0 input pin SC2_PWR O SmartCard2 Power pin 127 PE.15 I/O General purpose digital IO pin 128 PE.14 I/O General purpose digital IO pin 126 64 48 Note: 1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power; May 31, 2016 Page 82 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 3.4.4 NuMicro® Nano130 Pin Description Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin Pin Type Description PE.13 I/O General purpose digital I/O pin LCD_SEG27 O LCD segment output 27 at LQFP128 PB.14 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin SC2_CD I SmartCard2 card detect 1 2 3 4 1 nd SPI2_SS1 I/O SPI2 2 LCD_SEG12 O LCD segment output 12 at LQFP64 LCD_SEG26 O LCD segment output 26 at LQFP128 PB.13 I/O General purpose digital I/O pin EBI_AD1 I/O EBI Address/Data bus bit1 LCD_SEG11 O LCD segment output 11 at LQFP64 LCD_SEG25 O LCD segment output 25 at LQFP128 PB.12 I/O General purpose digital I/O pin EBI_AD0 I/O EBI Address/Data bus bit0 FCLKO O Frequency Divider output pin LCD_SEG10 O LCD segment output 10 at LQFP64 LCD_SEG24 O LCD segment output 24 at LQFP128 slave select pin 2 3 NC 6 4 X32O O External 32.768 kHz crystal output pin 7 5 X32I I External 32.768 kHz crystal input pin 8 9 10 May 31, 2016 NC 6 PA.11 I/O General purpose digital I/O pin I2C1_SCL I/O I C1 clock pin EBI_nRD O EBI read enable output pin SC0_RST O SmartCard0 RST pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin LCD_SEG9 O LCD segment output 9 at LQFP64 LCD_SEG23 O LCD segment output 23 at LQFP128 PA.10 I/O General purpose digital I/O pin I2C1_SDA I/O I C1 data I/O pin 7 2 st 2 Page 83 of 160 Revision 1.08 NANO100 SERIES DATASHEET 5 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP 128-pin 64-pin 48-pin 11 Pin Name Pin Type Description O EBI write enable output pin SC0_PWR O SmartCard0 Power pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin LCD_SEG8 O LCD segment output 8 at LQFP64 LCD_SEG22 O LCD segment output 22 at LQFP128 PA.9 I/O General purpose digital I/O pin I2C0_SCL I/O I C0 clock pin SC0_DAT I/O SmartCard0 DATA pin(SC0_UART_RXD) SPI2_CLK I/O SPI2 serial clock pin LCD_SEG7 O LCD segment output 7 at LQFP64 LCD_SEG21 O LCD segment output 21 at LQFP128 PA.8 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin SC0_CLK O SmartCard0 clock pin(SC0_UART_TXD) SPI2_SS0 I/O SPI2 1 slave select pin LCD_SEG6 O LCD segment output 6 at LQFP64 LCD_SEG20 O LCD segment output 20 at LQFP128 PD.8 I/O General purpose digital I/O pin LCD_SEG19 O LCD segment output 19 at LQFP128 PD.9 I/O General purpose digital I/O pin LCD_SEG18 O LCD segment output 18 at LQFP128 PD.10 I/O General purpose digital I/O pin LCD_SEG17 O LCD segment output 17 at LQFP128 PD.11 I/O General purpose digital I/O pin LCD_SEG16 O LCD segment output 16 at LQFP128 PD.12 I/O General purpose digital I/O pin LCD_SEG15 O LCD segment output 15 at LQFP128 PD.13 I/O General purpose digital I/O pin LCD_SEG14 O LCD segment output 14 at LQFP128 PB.4 I/O General purpose digital I/O pin st 2 8 12 NANO100 SERIES DATASHEET EBI_nWR 2 9 st 13 14 15 16 17 18 19 10 May 31, 2016 Page 84 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 20 21 UART1_RXD I UART1 Data receiver input pin SC0_CD I SmartCard0 card detect pin st SPI2_SS0 I/O SPI2 1 slave select pin LCD_SEG5 O LCD segment output 5 at LQFP64 LCD_SEG13 O LCD segment output 13 at LQFP128 PB.5 I/O General purpose digital I/O pin UART1_TXD O UART1 Data transmitter output pin SC0_RST O SmartCard0 RST pin SPI2_CLK I/O SPI2 serial clock pin LCD_SEG4 O LCD segment output 4 at LQFP64 LCD_SEG12 O LCD segment output 12 at LQFP128 PB.6 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin EBI_ALE O EBI address latch enable output pin SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin LCD_SEG3 O LCD segment output 3 at LQFP64 LCD_SEG11 O LCD segment output 11 at LQFP128 PB.7 I/O General purpose digital I/O pin UART1_CTSn I UART1 Clear to Send input pin EBI_nCS O EBI chip select enable output pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin LCD_SEG2 O LCD segment output 2 at LQFP64 LCD_SEG10 O LCD segment output 10 at LQFP128 11 12 st 13 23 24 Description st NC 14 LDO_CAP P LDO output pin 25 NC 26 NC 27 15 VDD P 28 29 Power supply for I/O ports and LDO source NC 16 May 31, 2016 VSS P Ground Page 85 of 160 Revision 1.08 NANO100 SERIES DATASHEET 22 Pin Type NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Type Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin Description 30 VSS P Ground 31 VSS P Ground 32 VSS P Ground 33 PE.12 I/O General purpose digital I/O pin 34 PE.11 I/O General purpose digital I/O pin 35 PE.10 I/O General purpose digital I/O pin 36 PE.9 I/O General purpose digital I/O pin PE.8 I/O General purpose digital I/O pin LCD_SEG9 O LCD segment output 9 at LQFP128 PE.7 I/O General purpose digital I/O pin LCD_SEG8 O LCD segment output 8 at LQFP128 37 38 39 NC 40 17 USB_VBUS USB POWER SUPPLY: From USB Host or HUB. 41 18 USB_VDD33_CAP USB Internal Power Regulator Output 3.3V Decoupling Pin 42 19 USB_D- USB USB Differential Signal D- 43 20 USB_D+ USB USB Differential Signal D+ NANO100 SERIES DATASHEET I/O General purpose digital I/O pin UART0_RXD I UART0 Data receiver input pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin LCD_SEG1 O LCD segment LCD_COM5) LCD_SEG7 O LCD segment output 7 at LQFP128 PB.1 I/O General purpose digital I/O pin UART0_TXD O UART0 Data transmitter output pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin LCD_SEG0 O LCD segment LCD_COM4) LCD_SEG6 O LCD segment output 6 at LQFP128 PB.2 I/O General purpose digital I/O pin UART0_RTSn O UART0 Request to Send output pin EBI_nWRL O EBI low byte write enable output pin PB.0 44 45 46 21 22 23 May 31, 2016 st output 1 at LQFP64 (or as (or as st Page 86 of 160 output 0 at LQFP64 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP 128-pin 64-pin 48-pin 47 Pin Name Pin Type Description SPI1_CLK I/O SPI1 serial clock pin LCD_COM3 O LCD common output 3 at LQFP64 LCD_SEG5 O LCD segment output 5 at LQFP128 PB.3 I/O General purpose digital I/O pin UART0_CTSn I UART0 Clear to Send input pin EBI_nWRH O EBI high byte write enable output pin SPI1_SS0 I/O SPI1 1 slave select pin LCD_COM2 O LCD common output 2 at LQFP64 LCD_SEG4 O LCD segment output 4 at LQFP128 PD.6 I/O General purpose digital I/O pin LCD_SEG3 O LCD segment output 3 at LQFP128 PD.7 I/O General purpose digital I/O pin LCD_SEG2 O LCD segment output 2 at LQFP128 PD.14 I/O General purpose digital I/O pin LCD_SEG1 O LCD segment LCD_COM5) PD.15 I/O General purpose digital I/O pin LCD_SEG0 O LCD segment LCD_COM4) PC.5 I/O General purpose digital I/O pin SPI0_MOSI1 I/O SPI0 2 LCD_COM3 O LCD common output 3 at LQFP128 PC.4 I/O General purpose digital I/O pin SPI0_MISO1 I/O SPI0 2 LCD_COM2 O LCD common output 2 at LQFP128 PC.3 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin I2S_DO O I S data output SC1_RST O SmartCard1 RST pin LCD_COM1 O LCD common output 1 at LQFP64 LCD_COM1 O LCD common output 1 at LQFP128 24 st 48 49 50 52 53 54 nd nd output 1 0 at at LQFP128 (or as LQFP128 (or as MOSI (Master Out, Slave In) pin MISO (Master In, Slave Out) pin st 2 25 May 31, 2016 Page 87 of 160 Revision 1.08 NANO100 SERIES DATASHEET 51 output NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 55 56 NANO100 SERIES DATASHEET 57 PC.2 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin st 2 I2S_DI I I S data input SC1_PWR O SmartCard1 PWR pin LCD_COM0 O LCD common output 0 at LQFP64 LCD_COM0 O LCD common output 0 at LQFP128 PC.1 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin I2S_BCLK I/O I S bit clock pin 27 SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) LCD_DH2 O LCD externl capacitor pin of charge pump circuit at LQFP64 LCD_DH2 O LCD externl capacitor pin of charge pump circuit at LQFP128 PC.0 / MCLKO I/O General purpose digital I/O pin / Module clock output pin SPI0_SS0 I/O SPI0 1 slave select pin I2S_LRCLK I/O I S left right channel clock 28 SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) LCD_DH1 O LCD externl capacitor pin of charge pump circuit at LQFP64 LCD_DH1 O LCD externl capacitor pin of charge pump circuit at LQFP128 PE.6 I/O General purpose digital I/O pin 29 LCD_VLCD AO LCD power supply pin 60 2 st 2 NC 61 62 Description 26 58 59 Pin Type PE.5 30 May 31, 2016 General purpose digital I/O pin PB.11 I/O General purpose digital I/O pin PWM1_CH0 I/O PWM1 Channel0 output TM3 O Timer3 external counter input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin Page 88 of 160 st Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Type Description LCD_V1 O LCD Unit voltage for LCD charge pump circuit at LQFP64 LCD_V1 O LCD Unit voltage for LCD charge pump circuit at LQFP128 PB.10 I/O General purpose digital I/O pin SPI0_SS1 I/O SPI0 2 TM2 O Timer2 external counter input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin LCD_V2 O LCD driver biasing voltage at LQFP64 LCD_V2 O LCD driver biasing voltage at LQFP128 PB.9 I/O General purpose digital I/O pin SPI1_SS1 I/O SPI1 2 TM1 O Timer1 external counter input SC2_RST O SmartCard2 RST pin INT0 I External interrupt0 input pin LCD_V3 O LCD driver biasing voltage at LQFP64 LCD_V3 O LCD driver biasing voltage at LQFP128 PE.4 I/O General purpose digital I/O pin SPI0_MOSI0 I/O SPI0 1 MOSI (Master Out, Slave In) pin PE.3 I/O General purpose digital I/O pin SPI0_MISO0 I/O SPI0 1 MISO (Master In, Slave Out) pin PE.2 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin PE.1 I/O General purpose digital I/O pin PWM1_CH3 I/O PWM1 Channel3 output SPI0_SS0 I/O SPI0 1 slave select pin PE.0 I/O General purpose digital I/O pin PWM1_CH2 I/O PWM1 Channel2 output I2S_MCLK O I S master clock output pin PC.13 I/O General purpose digital I/O pin Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 63 64 31 32 nd slave select pin st slave select pin st 66 st 67 68 69 70 May 31, 2016 st 2 Page 89 of 160 Revision 1.08 NANO100 SERIES DATASHEET 65 nd NUMICRO® NANO100 (B) DATASHEET Pin No. LQFP LQFP LQFP 128-pin 64-pin 48-pin 71 72 73 NANO100 SERIES DATASHEET 74 75 76 Pin Name Pin Type Description nd SPI1_MOSI1 I/O SPI1 2 PWM1_CH1 O PWM1 Channel1 output SNOOPER I Snooper pin INT1 I External interrupt 1 input pin I2C0_SCL O I C0 clock pin PC.12 I/O General purpose digital I/O pin SPI1_MISO1 I/O SPI1 2 PWM1_CH0 O PWM1 Channel0 output INT0 I External interrupt0 input pin MOSI (Master Out, Slave In) pin 2 nd MISO (Master In, Slave Out) pin 2 I2C0_SDA I/O I C0 data I/O pin PC.11 I/O General purpose digital I/O pin SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin UART1_TXD O UART1 Data transmitter output pin LCD_SEG31 O LCD segment output 31 at LQFP64 PC.10 I/O General purpose digital I/O pin SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin UART1_RXD I UART1 Data receiver input pin LCD_SEG30 O LCD segment output 30 at LQFP64 PC.9 I/O General purpose digital I/O pin SPI1_CLK I/O SPI1 serial clock pin I2C1_SCL I/O I C1 clock pin LCD_SEG29 O LCD segment output 29 at LQFP64 PC.8 I/O General purpose digital I/O pin SPI1_SS0 I/O SPI1 1 slave select pin EBI_MCLK O EBI external clock output pin I2C1_SDA I/O I C1 data I/O pin LCD_SEG28 O LCD segment output 28 at LQFP64 PA.15 I/O General purpose digital I/O pin PWM0_CH3 I/O PWM0 Channel3 output I2S_MCLK O I S master clock output pin st 33 st 34 35 36 37 May 31, 2016 2 st 2 2 Page 90 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 77 78 I Timer3 capture input SC0_PWR O SmartCard0 Power pin UART0_TXD O UART0 Data transmitter output pin LCD_SEG27 O LCD segment output 27 at LQFP64 PA.14 I/O General purpose digital I/O pin PWM0_CH2 I/O PWM0 Channel2 output EBI_AD15 I/O EBI Address/Data bus bit15 38 TC2 I Timer2 capture input UART0_RXD I UART0 Data receiver input pin LCD_SEG26 O LCD segment output 26 at LQFP64 PA.13 I/O General purpose digital I/O pin PWM0_CH1 I/O PWM0 Channel1 output EBI_AD14 I/O EBI Address/Data bus bit14 39 Timer1 capture input 2 I/O I C0 clock pin LCD_SEG25 O LCD segment output 25 at LQFP64 PA.12 I/O General purpose digital I/O pin PWM0_CH0 I/O PWM0 Channel0 output EBI_AD13 I/O EBI Address/Data bus bit13 NANO100 SERIES DATASHEET 81 I I2C0_SCL 40 TC0 80 Description TC3 TC1 79 Pin Type 41 I Timer0 capture input 2 I2C0_SDA I/O I C0 data I/O pin LCD_SEG24 O LCD segment output 24 at LQFP64 ICE_DAT I/O Serial Wired Debugger Data pin PF.0 I/O General purpose digital I/O pin INT0 I External interrupt0 input pin ICE_CLK I Serial Wired Debugger Clock pin PF.1 I/O General purpose digital I/O pin FCLKO O Frequency Divider output pin INT1 I External interrupt1 input pin 42 82 May 31, 2016 NC Page 91 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 83 VDD Pin Type Description P Power supply for I/O ports and LDO source for internal PLL and digital circuit 84 NC 85 VSS P Ground 86 VSS P Ground 87 43 88 89 44 AVSS AP Ground Pin for analog circuit AVSS AP Ground Pin for analog circuit PA.0 I/O General purpose digital I/O pin AD0 AI ADC analog input0 SC2_CD 90 91 NANO100 SERIES DATASHEET 92 93 94 45 46 47 48 49 May 31, 2016 I SmartCard2 card detect PA.1 I/O General purpose digital I/O pin AD1 AI ADC analog input1 EBI_AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin AD2 AI ADC analog input2 EBI_AD11 I/O EBI Address/Data bus bit11 UART1_RXD I LCD_SEG23* AO LCD segment output 23 at LQFP64 PA.3 I/O General purpose digital I/O pin AD3 AI ADC analog input3 EBI_AD10 I/O EBI Address/Data bus bit10 UART1_TXD O UART1 Data transmitter output pin LCD_SEG22* AO LCD segment output 22 at LQFP64 PA.4 I/O General purpose digital I/O pin AD4 AI ADC analog input4 EBI_AD9 I/O EBI Address/Data bus bit9 SC2_PWR O SmartCard2 Power pin I2C0_SDA I/O I C0 data I/O pin LCD_SEG21* AO LCD segment output 21 at LQFP64 LCD_SEG39* AO LCD segment output 39 at LQFP128 PA.5 I/O General purpose digital I/O pin UART1 Data receiver input pin 2 Page 92 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin 95 AD5 AI ADC analog input5 EBI_AD8 I/O EBI Address/Data bus bit8 SC2_RST O SmartCard2 RST pin I2C0_SCL I/O I C0 clock pin LCD_SEG20* AO LCD segment output 20 at LQFP64 LCD_SEG38* AO LCD segment output 38 at LQFP128 PA.6 I/O General purpose digital I/O pin AD6 AI ADC analog input6 EBI_AD7 I/O EBI Address/Data bus bit7 2 TC3 I Timer3 capture input SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD) PWM0_CH3 O PWM0 Channel3 output AO LCD segment output 19 at LQFP64 LCD_SEG37* AO LCD segment output 37 at LQFP128 PA.7 I/O General purpose digital I/O pin AD7 AI ADC analog input7 EBI_AD6 I/O EBI Address/Data bus bit6 TC2 51 I Timer2 capture input SC2_DAT I/O SmartCard2 DATA pin(SC2_UART_RXD) PWM0_CH2 O PWM0 Channel2 output LCD_SEG36* AO LCD segment output 36 output at LQFP128 VREF AP Voltage reference input for ADC NC 52 AVDD AP Power supply for internal analog circuit PD.0 I/O General purpose digital I/O pin I UART1 Data receiver input pin UART1_RXD 100 101 May 31, 2016 st SPI2_SS0 I/O SPI2 1 slave select pin SC1_CLK O SmartCard1 clock pin(SC1_UART_TXD) AD8 AI ADC analog input8 PD.1 I/O General purpose digital I/O pin Page 93 of 160 Revision 1.08 NANO100 SERIES DATASHEET LCD_SEG19* 98 99 Description 50 96 97 Pin Type NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin Pin Type Description TX1 O UART1 Data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD) AD9 AI ADC analog input9 PD.2 I/O General purpose digital I/O pin UART1_RTSn O UART1 Request to Send output pin I2S_LRCLK I/O I S left right channel clock SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin SC1_PWR O SmartCard1 Power pin AD10 AI ADC analog input10 PD.3 I/O General purpose digital I/O pin I UART1 Clear to Send input pin 2 102 UART1_CTSn st 2 I2S_BCLK I/O I S bit clock pin SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin SC1_RST O SmartCard1 RST pin AD11 AI ADC analog input11 103 NANO100 SERIES DATASHEET 104 st NC PD.4 I2S_DI 105 SPI2_MISO1 SC1_CD I/O I I/O I General purpose digital I/O pin 2 I S data input SPI2 2 MISO (Master In, Slave Out) pin SmartCard1 card detect LCD_SEG35 AO LCD segment output 35 at LQFP128 PD.5 I/O General purpose digital I/O pin I2S_DO O I S data output SPI2_MOSI1 I/O SPI2 2 LCD_SEG34 AO LCD segment output 34 at LQFP128 PC.7 I/O General purpose digital I/O pin DA1_OUT AO DAC 1 output EBI_AD5 I/O EBI Address/Data bus bit5 2 106 107 nd nd MOSI (Master Out, Slave In) pin 53 TC1 May 31, 2016 I Timer1 capture input Page 94 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin PWM0_CH1 108 Pin Type O AO LCD segment output 17 at LQFP64 PC.6 I/O General purpose digital I/O pin DA0_OUT I EBI_AD4 I/O I PWM0_CH0 O PWM0 Channel0 output PC.15 I/O General purpose digital I/O pin EBI_AD3 I/O EBI Address/Data bus bit3 TC0 I Timer0 capture input PWM1_CH2 O PWM1 Channel1 output LCD_SEG16 AO LCD segment output 16 at LQFP64 LCD_SEG33 AO LCD segment output 33 at LQFP128 PC.14 I/O General purpose digital I/O pin EBI_AD2 I/O EBI Address/Data bus bit2 PWM1_CH3 I/O PWM1 Channel3 output LCD_SEG15 AO LCD segment output 15 at LQFP64 LCD_SEG32 AO LCD segment output 32 at LQFP128 PB.15 I/O General purpose digital I/O pin INT1 I External interrupt1 input pin SNOOPER I Snooper pin SC1_CD I SmartCard1 card detect 55 56 57 LCD_SEG14 AO LCD segment output 14 at LQFP64 LCD_SEG31 AO LCD segment output 31 at LQFP128 NC XT1_IN O External 4~24 MHz crystal output pin PF.3 I/O General purpose digital I/O pin 58 XT1_OUT 114 Timer0 capture input SmartCard1 card detect pin 112 113 EBI Address/Data bus bit4 NANO100 SERIES DATASHEET 111 DAC0 output 54 SC1_CD 110 PWM1 Channel1 output LCD_SEG17* TC0 109 Description I External 4~24 MHz crystal input pin 59 PF.2 May 31, 2016 I/O General purpose digital I/O pin Page 95 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Pin No. Pin Name LQFP LQFP LQFP 128-pin 64-pin 48-pin Pin Type 115 Description NC 116 60 nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. 117 61 VSS P Ground VSS P Ground 118 119 120 NC 62 VDD P 121 NC PF.4 I/O General purpose digital I/O pin I2C0_SDA I/O I C0 data I/O pin PF.5 I/O Digital GPI/O pin I2C0_SCL I/O I C0 clock pin 122 123 124 125 NANO100 SERIES DATASHEET 126 Power supply for I/O ports and LDO source for internal PLL and digital circuit VSS 63 64 P 2 2 Ground PVSS I/O PLL Ground PB.8 I/O General purpose digital I/O pin STADC I ADC external trigger input. TM0 I Timer0 external counter input INT0 I External interrupt0 input pin SC2_PWR O SmartCard2 Power pin LCD_SEG13 AO LCD segment output 13 at LQFP64 LCD_SEG30 AO LCD segment output 30 at LQFP128 PE.15 I/O General purpose digital I/O pin LCD_SEG29 O LCD segment output 29 at LQFP128 PE.14 I/O General purpose digital I/O pin LCD_SEG28 O LCD segment output 28 at LQFP128 127 128 Note: 1. Pin Type: I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power 2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance. May 31, 2016 Page 96 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 4 4.1 BLOCK DIAGRAM Nano100 Block Diagram LXT EBI FLASH 123/64/ 32 KB Cortex-M0 42 MHz DMA CLK_CTL P L L LIRC HXT HIRC 1.8V LDO (input: 1.8 ~ 3.6V) POR (1.8V) ISP 4KB SRAM 16/8 KB I2C 1 I2C 0 PWM 1 PWM 0 Timer 2/3 Timer 0/1 UART 1 UART 0 SPI 1 SPI 0 I2S SPI 2 SC 0/UART3 RTC SC 1/UART4 WDT BOD (1.7/2.0/2.5 V) GPIO A,B,C,D,E,F 12-b ADC 12-b DAC 1.8/2.5V REF TEMP Sensor Peripherals with wake-up ® Figure 4‑1 NuMicro Nano100 Block Diagram May 31, 2016 Page 97 of 160 Revision 1.08 NANO100 SERIES DATASHEET Peripherals with PDMA SC 2/UART5 NOTE: BOD can wake up system. External interrupts, included in GPIO, can wake up system, too. NUMICRO® NANO100 (B) DATASHEET 4.2 Nano110 Block Diagram LXT EBI FLASH 123/64/ 32 KB Cortex-M0 42 MHz DMA CLK_CTL P L L LIRC HXT HIRC 1.8V LDO (input: 1.8 ~ 3.6V) POR (1.8V) BOD (1.7/2.0/2.5 V) ISP 4KB SRAM 16/8 KB I2C 1 I2C 0 PWM 1 PWM 0 Timer 2/3 Timer 0/1 UART 1 UART 0 SPI 1 SPI 0 I2S SPI 2 SC 0/UART3 RTC SC 1/UART4 WDT GPIO A,B,C,D,E,F 12-b ADC 12-b DAC 1.8/2.5V REF TEMP Sensor LCD Booster LCD LCD COM/SEG Up to 4x40/6x38 Peripherals with PDMA SC 2/UART5 NOTE: BOD can wake up system. External interrupts, included in GPIO, can wake up system, too. Peripherals with wake-up NANO100 SERIES DATASHEET ® Figure 4‑2 NuMicro Nano110 Block Diagram May 31, 2016 Page 98 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 4.3 Nano120 Block Diagram LXT EBI FLASH 123/64/ 32 KB Cortex-M0 42 MHz DMA CLK_CTL P L L LIRC HXT HIRC 1.8V LDO (input: 1.8 ~ 3.6V) POR (1.8V) BOD (1.7/2.0/2.5 V) ISP 4KB SRAM 16/8 KB I2C 1 I2C 0 PWM 1 PWM 0 Timer 2/3 Timer 0/1 UART 1 UART 0 SPI 1 SPI 0 I2S SPI 2 SC 0/UART3 RTC SC 1/UART4 WDT GPIO A,B,C,D,E,F 12-b ADC 12-b DAC 1.8/2.5V REF TEMP Sensor USB -512B USB PHY Peripherals with PDMA SC 2/UART5 NOTE: BOD can wake up system. External interrupts, included in GPIO, can wake up system, too. Peripherals with wake-up NANO100 SERIES DATASHEET ® Figure 4‑3 NuMicro Nano120 Block Diagram May 31, 2016 Page 99 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 4.4 Nano130 Block Diagram LXT EBI FLASH 123/64/ 32 KB Cortex-M0 42 MHz DMA CLK_CTL P L L LIRC HXT HIRC 1.8V LDO (input: 1.8 ~ 3.6V) POR (1.8V) BOD (1.7/2.0/2.5 V) GPIO A,B,C,D,E,F ISP 4KB SRAM 16/8 KB I2C 1 I2C 0 PWM 1 PWM 0 Timer 2/3 Timer 0/1 UART 1 UART 0 SPI 1 SPI 0 I2S SPI 2 LCD SC 0/UART3 RTC USB -512B SC 1/UART4 WDT 12-b ADC 12-b DAC 1.8/2.5V REF TEMP Sensor LCD Booster LCD COM/SEG Up to 4x40/6x38 USB PHY Peripherals with PDMA SC 2/UART5 NANO100 SERIES DATASHEET NOTE: BOD can wake up system. External interrupts, included in GPIO, can wake up system, too. Peripherals with wake up ® Figure 4‑4 NuMicro Nano130 Block Diagram May 31, 2016 Page 100 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5 FUNCTIONAL DESCRIPTION 5.1 Memory Organization 5.1.1 Overview The Nano100 provides 4G-byte addressing space. The memory locations assigned to each onchip modules are shown in following. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip module. The Nano100 series only supports little-endian data format. 5.1.2 Memory Map The memory locations assigned to each on-chip controllers are shown in the following table. Address Space Token Modules 0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128KB) 0x2000_0000 – 0x2000_3FFF SRAM_BA SRAM Memory Space (16KB) 0x6000_0000 --- 0x6001_FFFF EXTMEM_BA External Memory Space(128KB) Flash & SRAM Memory Space AHB Modules Space (0x5000_0000 – 0x501F_FFFF) GCR_BA System Management Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 – 0x5000_BFFF DMA_BA DMA Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 – 0x5001_03FF EBI_BA External Bus Interface Control Registers APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF) 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4000_8000 – 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0 and Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with Master/Slave function Control Registers 0x4004_0000 – 0x4004_3FFF PWM0_BA PWM0 Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x4006_0000 – 0x4006_3FFF USBD_BA USB FS device Controller Registers 0x400A_0000 – 0x400A_3FFF DAC_BA Digital-Analog-Converter (DAC) Control Registers 0x400B_0000 – 0x400B_3FFF LCD_BA LCD Control Registers 0x400D_0000 – 0x400D_3FFF SPI2_BA SPI2 with Master/Slave function Control Registers May 31, 2016 2 Page 101 of 160 Revision 1.08 NANO100 SERIES DATASHEET 0x5000_0000 – 0x5000_01FF NUMICRO® NANO100 (B) DATASHEET 0x400E_0000 – 0x400E_3FFF ADC12_BA 12-bit Analog-Digital-Converter Registers (ADC12) Control APB2 Modules Space (0x4010_0000 ~ 0x401F_FFFF) 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2 and Timer3 Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I C1 Interface Control Registers 0x4013_0000 – 0x4013_3FFF SPI1_BA SPI1 with Master/Slave function Control Registers 0x4014_0000 – 0x4014_3FFF PWM1_BA PWM1 Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers 0x4019_0000 – 0x4019_3FFF SC0_BA SmartCard0 Control Registers 0x401A_0000 – 0x401A_3FFF I2S_BA I S Control Registers 0x401B_0000 – 0x401B_3FFF SC1_BA SmartCard1 Control Registers 0x401C_0000 – 0x401C_3FFF SC2_BA SmartCard2 Control Registers 2 2 System Control Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers NANO100 SERIES DATASHEET May 31, 2016 Page 102 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.2 Nested Vectored Interrupt Controller (NVIC) 5.2.1 Overview The Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides following features: 5.2.2 Features Nested and Vectored interrupt support Automatic processor state saving and restoration Dynamic priority changing Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. For more detailed information, please refer to the “ARM ® Manual” and “ARM v6-M Architecture Reference Manual”. May 31, 2016 Page 103 of 160 ® Cortex™-M0 Technical Reference Revision 1.08 NANO100 SERIES DATASHEET The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. NUMICRO® NANO100 (B) DATASHEET 5.3 5.3.1 System Manager Overview System manager mainly controls the power modes, wake-up source, system resets and system memory map. It also provides information about product ID, chip reset, IP reset, and multi-function pin control. 5.3.2 Features Power modes and wake-up sources System resets System Memory Map System manager registers for : Product ID Chip and IP reset Multi-functional pin control NANO100 SERIES DATASHEET May 31, 2016 Page 104 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.4 Clock Controller 5.4.1 Overview The clock controller generates clocks for the whole chip, Iincluding system clocks (CPU clock, HCLKx, and PCLKx) and all peripheral engine clocks. HCLKx means AHB bus clock for peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until CPU sets the power down enable bit (PD_EN) and CPU executes the WFI instruction. In the Power-down mode, clock controller turns off the external high frequency crystal, internal high frequency oscillator, and system clocks (CPU clock, HCLKx, and PCLKx) to reduce the power consumption to minimum. 5.4.2 Features Generates clocks for system clocks and all peripheral engine clocks. Each peripheral engine clock can be turned on/off. High frequency crystal, internal high frequency oscillator, and system clocks will be turned off when chip is in Power-down mode. NANO100 SERIES DATASHEET May 31, 2016 Page 105 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.5 Analog to Digital Converter (ADC) 5.5.1 Overview This chip contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with 12 external input channels and 6 internal channels. The A/D converter supports three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started by software and external STADC/PB.8 pin and timer event start. Note that the I/O pins used as ADC analog input pins must be configured as input type and off digital function (GPIOA_OFFD) should be turned on before ADC function is enabled. 5.5.2 Features Analog input voltage range: 0~Vref (Max to 3.6V) Selectable 12-bits, 10-bits, 8-bits and 6-bits resolution Supports sampling time settings (in ADC_CLK unit) for channel 0~11 individually and channel 12~17 share the same one sampling time setting Supports two power-down modes: Power-down mode Standby mode Up to 12 external analog input channels (channel0 ~ channel11), and 6 internal channels (channel12~channel17) converting six voltage sources, including DAC0, DAC1, internal band-gap voltage, internal temperature sensor output, AVDD, and AVSS. Maximum ADC clock frequency is 42 MHz and each conversion is 19 clocks+ sampling time depending on the input resistance. Three operating modes NANO100 SERIES DATASHEET Single mode: A/D conversion is performed one time on a specified channel. Single-cycle Scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel. Continuous Scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion. An A/D conversion can be started by: Software write 1 to ADST bit External pin STADC Selects one from four timer events (TMR0, TMR1, TMR2 and TMR3) that enable ADC and transfer AD results by PDMA Conversion results held in data registers for each channel Conversion result can be compared with a specified value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting. Supports Calibration and load Calibration words capability. May 31, 2016 Page 106 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.6 Digital to Analog Converter (DAC) 5.6.1 Overview DAC is a 12-bit voltage-output digital-to-analog converter. Two DACs are implemented in this chip. 5.6.2 Features DAC is a 12-bit voltage-output DAC. DAC can use in conjunction with the PDMA controller. When two DACs are present, they may be grouped together for synchronous update operation. Features: Int_VREF or VREF or AVDD reference voltage selection Synchronized update capability for two DACs DAC maximum conversion rate is 500 KSPS NANO100 SERIES DATASHEET May 31, 2016 Page 107 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.7 DMA Controller 5.7.1 Overview The DMA controller contains six channel peripheral direct memory access (PDMA) controllers, a video direct memory access (VDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA controller can transfer data to and from memory or transfer data to and from APB devices. The DMA has eight channels of DMA including one channel VDMA (Memory-to-Memory) and six channels PDMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory) and a CRC controller. For channel0 VDMA, it supports block transfer from memory to memory. For PDMA channel (DMA CH1~CH6), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory. And for channel 0 VDMA, there is a two-word buffer. Software can stop the DMA operation by disable PDMA [PDMACEN]/VDMA [VDMACEN]. Software can recognize the completion of a DMA operation by software polling or when it receives an internal DMA interrupt. The DMA controller can increase source or destination address, fixed or wrap around them as well. The DMA controller also contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine support CPU PIO mode and DMA transfer mode. 5.7.2 Features Seven DMA channels and a CRC generator: 1 VDMA channel and 6 PDMA channels. Each channel can support a unidirectional transfer. AMBA AHB master/slave interface compatible, for data transfer and register read/write. Hardware round robin priority scheme. NANO100 SERIES DATASHEET VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-to-memory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral Supports address direction: increment, fixed, and wrap around Cyclic Redundancy Check (CRC) May 31, 2016 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 16 12 5 CRC-CCITT: X CRC-8: X + X + X + 1 CRC-16: X CRC-32: X 2 X +X+1 8 +X +X +1 2 16 +X 15 +X +1 32 +X 2 26 +X 23 +X 22 +X Page 108 of 160 16 +X 12 +X 11 +X 10 8 7 5 4 +X +X +X +X + Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Programmable seed value Supports programmable order reverse setting for input data and CRC checksum Supports programmable 1’s complement setting for input data and CRC checksum Supports CPU PIO mode or DMA transfer mode Supports 8/16/32-bit of data width in CPU PIO mode 8-bit write mode: 1-AHB clock cycle operation 16-bit write mode: 2-AHB clock cycle operation 32-bit write mode: 4-AHB clock cycle operation Supports byte alignment transfer length in CRC DMA mode NANO100 SERIES DATASHEET May 31, 2016 Page 109 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.8 External Bus Interface 5.8.1 Overview This chip is equipped with an external bus interface (EBI) to access external device. To save the connections between external device and this chip, EBI support address bus and data bus multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the address and data cycle. 5.8.2 Features External devices with max. 64 Kbytes size (8-bit data width)/128 Kbytes (16-bit data width) supported Supports variable external bus base clock (MCLK) Supports 8-bit or 16-bit data width Supports variable data access time (tACC), address latch enable time (tALE) and address hold time (tAHD) Address bus and data bus multiplex mode supported to save the address pins Configurable idle cycle supported for different access condition: Write command finish (W2X), Read-to-Read (R2R), Read-to-Write (R2W) Supports PDMA and VDMA transfer NANO100 SERIES DATASHEET May 31, 2016 Page 110 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.9 FLASH Memory Controller (FMC) 5.9.1 Overview This chip is equipped with 32K/64K/123K bytes on-chip embedded Flash EPROM for application program memory (APROM) that can be updated through ISP/IAP procedure. In System Programming (ISP) function enables user to update program memory when chip is soldered on PCB. After chip powered on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in Config0. By the way, this chip also provides DATA Flash Region, the data flash is shared with original program memory and its start address is configurable and defined by user in Config1. The data flash size is defined by user application request. 5.9.2 Features AHB interface compatible Run up to 42 MHz with zero wait state for discontinuous address read access 32/64/123KB application program memory (APROM) 4KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM NANO100 SERIES DATASHEET May 31, 2016 Page 111 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.10 General Purpose I/O Controller 5.10.1 Overview Up to 86 General Purpose I/O pins can be shared with other function pins; it depends on the chip configuration. These 86 pins are arranged in 6 ports named with GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. Ports A ~ E have the maximum of 16 pins while port F have 6 pins. Each one of the 86 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be independently software configured as input, output, and open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110 K~300 K for VDD from 1.8 V to 3.6 V. 5.10.2 Features Up to 86 general purpose I/O pins Supports Input, Output, Open-drain Operation mode Programmable de-bounce timing Each I/O pin can be programmed as either edge-trigger or level-sensitive Each I/O pin can be programmed as either low-level active or high-level active Each I/O pin can be programmed as either falling-edge trigger or rising-edge trigger NANO100 SERIES DATASHEET May 31, 2016 Page 112 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.11 I2C 5.11.1 Overview 2 I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data 2 exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1.0 Mbps. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. 2 2 The controller’s on-chip I C logic provides the serial interface that meets the I C bus standard 2 mode specification. The I C controller handles byte transfers autonomously. Pull up resistor is 2 needed for I C operation as these are open drain pins. 2 The I C controller is equipped with two slave address registers. The contents of the registers are 2 irrelevant when I C is in Master mode. In the Slave mode, the seven most significant bits must be 2 loaded with the user’s own slave address. The I C hardware will react if the contents of I2CADDR are matched with the received slave address. This controller supports the “General Call (GC)” function. If the GC bit is set this controller will respond to General Call address (00H). Clear GC bit to disable general call function. When GC bit 2 is set and the I C is in Slave mode, it can receive the general call address which is equal to 00H 2 after master sends general call address to the I C bus, then it will follow status of GC mode. If it is 2 in Master mode, the ACK bit must be cleared when it sends general call address of 00H to the I C bus. 2 May 31, 2016 Page 113 of 160 Revision 1.08 NANO100 SERIES DATASHEET The I C-bus controller supports multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don’t-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. NUMICRO® NANO100 (B) DATASHEET 5.11.2 Features Acts as Master or Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer One built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows. Programmable clock divider allows versatile rate control Supports 7-bit addressing mode Supports multiple address recognition ( Two slave addresses with mask option) Supports Power-down wake-up function 2 2 NANO100 SERIES DATASHEET May 31, 2016 Page 114 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.12 I2S 5.12.1 Overview 2 The audio controller consists of I S protocol to interface with external audio CODEC. Two 8 word deep FIFO for receiving path and transmitting path respectively and is capable of handling 8 ~ 32 bit word sizes. PDMA controller handles the data movement between FIFO and memory. 5.12.2 Features I S can operate as either master or Slave mode. Capable of handling 8, 16, 24 and 32 bits word sizes. Mono and stereo of audio data are supported. I S and MSB justified data format are supported. Two FIFO data buffers (each 32 bits) are provided, one is for transmitting and the other is for receiving. Generate interrupt when buffer levels cross a programmable boundary. Two PDMA channels request, one is for transmitting and the other is for receiving. 2 2 NANO100 SERIES DATASHEET May 31, 2016 Page 115 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.13 LCD Display Driver 5.13.1 Overview The LCD driver can directly drive a LCD glass by creating the ac segment and common voltage signals automatically. It can support static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty LCD glass with up to 38 segments with 6 COM (segment 0 is used as LCD_COM4 and segment 1 is used as LCD_COM5) or 40 segments with 4 COM (LCD_COM0 ~ LCD_COM3). A built-in charge pump function can be enabled to provide the LCD glass with higher voltage than the system voltage. The LCD driver would generate voltage higher than the threshold voltage in older to darken a segment and a voltage lower than threshold to make a segment clear. However, the LCD display segment will degrade if the applied voltage has a DC-component. To avoid this, the generated waveform by LCD driver are arranged such that average voltage of each segment is zero and the RMS(root-mean-square) voltage applied on a LCD segment lower than the segment threshold making LCD clear and RMS voltage higher than the segment threshold making LCD dark. Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance. (LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23) (LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39) 5.13.2 Features NANO100 SERIES DATASHEET Supports up to 174 dots (6x29) or 124 dots (4x31) in LQFP64 package and 228 dots (6x38) or 160 dots (4x40) in LQFP100/LQFP128 package Segment/Com pins: Common 0-5 multiplexing functions with GPI/O pins Segment 0-39 multiplexing function with GPI/O pins Supports Static,1/2 bias and 1/3 bias voltage Six display modes: Static,1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty or 1/6 duty Selectable LCD frequency by frequency divider Configurable frame frequency Internal Charge pump, adjustable contrast adjustment Embedded LCD bias reference ladder (R-Type, 200kΩ resisters) Configurable Charge pump frequency Blinking capability Supports R/C-type method LCD frame interrupt May 31, 2016 Page 116 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.14 Pulse Width Modulation (PWM) 5.14.1 Overview This chip has two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3, or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators. Each two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent 16-bit PWM down-count counter for PWM period control, and 16-bit comparators for PWM duty control. Each dead-zone generator has two outputs. The first dead-zone generator output is CH0 and CH1, and for the second dead-zone generator, the output is CH2 and CH3. The 2 sets of PWM controller total provide eight independent PWM interrupt flags which are set by hardware when the corresponding PWM period down counter reaches zero. PWM interrupt will be asserted when both PWM interrupt source and its corresponding enable bit are active. Each PWM output can be configured as one-shot mode to produce only one PWM cycle signal or continuous mode to output PWM waveform continuously. When DZEN01 of PWMx_CTL is set, CH0 and CH1 perform complementary PWM paired function; the paired PWM timing, period, duty and dead-time are determined by PWM channel 0 timer and Dead-zone generator 0. Similarly, When DZEN23 of PWMx_CTL is set the complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/ comparator at the time down counter reaching zero. The double buffering feature avoids glitch at PWM outputs. The value of PWM counter comparator is used for pulse width modulation. The counter control logic changes the output level when down-counter value matches the value of compare register. The alternate feature of the PWM is digital input capture function. If capture function is enabled the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user must setup the PWM timer before enabling capture feature. After capture feature is enabled, the capture always latches PWM timer to Capture Rising Latch Register (PWMx_CRLy) where y=0~3, when input channel has a rising transition and latches PWM timer to Capture Falling Latch Register (PWMx_CFLy) where y=0~3, when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting PWMx_CAPINTEN. Whenever Capture event latched for channel 0/1/2/3, the PWM timer 0/1/2/3 will be reload at this moment if the corresponding reload enable bit specified in CAPCTL are set. The maximum captured frequency that PWM can capture is dominated by the capture interrupt latency. When capture interrupt occurs, software will do at least three steps, they are: Read PWMINTSTS to tell it from interrupt source and Read PWMx_CRLy/PWMx_CFLy(y=0~3) to get capture value and finally write 1 to clear PWMx_INTSTS. If interrupt latency will take time T0 to finish, the capture signal mustn’t transient during this interval. In this case, the maximum capture frequency will be 1/T0. May 31, 2016 Page 117 of 160 Revision 1.08 NANO100 SERIES DATASHEET When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM output is set as continuous mode, when the down counter reaches zero, it is reloaded with CN of PWMx_DUTYy(y=0~3) Register automatically then start decreases, repeatedly. If the PWM output is set as one-shot mode, the down counter will stop and generate one interrupt request when it reaches zero. NUMICRO® NANO100 (B) DATASHEET 5.14.2 Features 5.14.2.1 PWM Function: Two PWM controllers, each controller having 4 independent PWM outputs, CH0~CH3, or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators Up to 8 PWM channels or 4 PWM paired channels Up to 16 bits PWM counter width PWM Interrupt request synchronous with PWM period Single-shot or Continuous mode Four Dead-Zone generators 5.14.2.2 Capture Function: Timing control logic shared with PWM timer. 8 Capture input channels shared with 8 PWM output channels. Each channel supports one rising latch register (PWMx_CRLy), one falling latch register (PWMx_CFLy) and Capture interrupt flag (CAPIFy) where x=0~1,y=0~3. Eight 16-bit counters for eight capture channels or four 32-bit counter for four capture channels when cascade is enabled: when CH01CASKEN is set, the original 16-bit counter of channel 1 will combine with channel 0’s 16 bit counter for channel 0 input capture counting and so does CH23CASKEN for channel 2, 3 Supports PDMA transfer function for PWMx channel 0, 2 NANO100 SERIES DATASHEET May 31, 2016 Page 118 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.15 RTC 5.15.1 Overview Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference to pin Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is expressed in BCD format. This unit offers alarm function that user can preset the alarm time in Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR). The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR (TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and CAR, the alarm interrupt status (RIIR.AIS) is set and the alarm interrupt is requested if the alarm interrupt is enabled (RIER.AIER=1). The RTC Time Tick (if wake-up CPU function is enabled, RTC_TTR[TWKE] high) and Alarm Match can cause CPU wake-up from idle or Power-down mode. 5.15.2 Features One time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time Alarm register (second, minute, hour, day, month, year) 12-hour or 24-hour mode is selectable Leap year compensation automatically Day of week counter Frequency compensate register (FCR) All time and calendar message is expressed in BCD code Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second Supports RTC Time Tick and Alarm Match interrupt Supports wake-up CPU from Power-down mode Supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers 5.16 Smart Card Host Interface (SC) 5.16.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 5.16.2 Features ISO-7816-3 T = 0, T = 1 compliant EMV2000 compliant Supports up to three ISO-7816-3 ports Separates receive / transmit 4 byte entry buffer for data payloads Programmable transmission clock frequency May 31, 2016 Page 119 of 160 Revision 1.08 NANO100 SERIES DATASHEET NUMICRO® NANO100 (B) DATASHEET Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) A 24-bit and two 8-bit counters for Answer to Reset (ATR) and waiting times processing Supports auto inverse convention function Supports stop clock level and clock stop (clock keep) function Supports transmitter and receiver error retry and error number limitation function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detected the card removal. Support UART mode Half duplex, asynchronous communications Separate receiving / transmitting 4 bytes entry FIFO for data payloads Support programmable baud rate generator for each channel Support programmable receiver buffer trigger level Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register Programmable even, odd or no parity bit generation and detection Programmable stop bit, 1 or 2 stop bit generation NANO100 SERIES DATASHEET May 31, 2016 Page 120 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.17 SPI 5.17.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol. Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to perform a serial-to-parallel conversion on data received from a peripheral device, and a parallelto-serial conversion on data transmitted to a peripheral device. The SPI controller can be configured as a master or a slave devicee. The SPI controller supports wake-up function. When this chip stays in power-down mode, it can be waked up chip by off-chip device. This controller supports variable serial clock function for special application and 2-bit transfer mode to connect 2 off-chip slave devices at the same time. The SPI controller also supports PDMA function to access the data buffer. 5.17.2 Features Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation Supports 1 bit and 2 bit transfer mode Support Dual IO transfer mode Configurable bit length of a transaction from 8 to 32-bit Supports MSB first or LSB first transfer sequence Two slave select lines supported in Master mode Configurable byte or word suspend mode Supports byte re-ordering function Supports variable serial clock in Master mode Provide separate 8-level depth transmit and receive FIFO buffer Supports wake-up function Supports PDMA transfer Supports three wires, no slave select signal, bi-direction interface May 31, 2016 Page 121 of 160 NANO100 SERIES DATASHEET Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.18 Timer Controller 5.18.1 Overview This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3 (TIMER0/1 is at APB1 and TIMER2/3 is at APB2), which allow user to easily implement a counting scheme or timing control for applications. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer can generate an interrupt signal upon timeout, or provide the current value of count during operation. 5.18.2 Features Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3) Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit TCMP) Counting cycle time = (1 / TMRx_CLK) * (2^8) * (2^24) Internal 8-bit pre-scale counter Internal 24-bit up counter is readable through TDR (Timer Data Register) Supports One-shot, Periodic,Output Toggle and Countinuous Counting Operation mode Supports external pin capture for interval measurement Supports external pin capture for timer counter reset Supports Inter-Timer trigger Supports Internal trigger event to ADC, DAC and PDMA NANO100 SERIES DATASHEET May 31, 2016 Page 122 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.19 UART Controller 5.19.1 Overview The UART controllers provides up to two channels of Universal Asynchronous Receiver/Transmitter (UART) modules that are UART0 and UART1. (UART0 is at APB1 and UART1 is at APB2). The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA (SIR) function mode, LIN Master/Slave function mode and RS-485 function mode. Each UART channel supports nine types of interrupts including receiver threshold level reaching interrupt (INT_RDA), transmitter FIFO empty interrupt (INT_THRE), line status interrupt (break error, parity error, framing error or RS485 interrupt) (INT_RLS), time-out interrupt (INT_TOUT), MODEM status interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR), wake-up interrupt (INT_WAKE), autobaud rate detect or auto-baud rate counter overflow flag (INT_ABAUD) and LIN function interrupt (INT_LIN). The UART0 and UART1 are built-in with a 16-byte transmitter FIFO (TX_FIFO) and a 16-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 3 error conditions (parity error, framing error or break interrupt) occur while receiving data. The UART controller supports auto-baud rate detection. The auto-baud rate detection controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user discretion. The UART controller also support incoming data or CTSn wake-up function. When the system is in power-down mode, an incoming data or CTSn signal will wake-up CPU from power-down mode. The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver need. The baud rate equation is Baud Rate = UART_CLK / [BRD + 1], where BRD are defined in UART Baud Rate Divider Register (UARTx_BAUD). Below table lists the equations in the various conditions and the UART baud rate setting table. BRD Baud Rate Equation Disable (Mode 0) A UART_CLK / (A+1), A must >8 Enable (Mode 1) A UART_CLK / [16 * (A+1)] NANO100 SERIES DATASHEET DIV_16_EN Table 5‑1 UART Baud Rate Equation System clock =12 MHz Baud rate Mode 0 Mode 1 921600 A=12 Not Supported 460800 A=25 Not Supported 230400 A=51 A=2 115200 A=103 A=6 57600 A=207 A=12 38400 A=311 A=19 May 31, 2016 Page 123 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 19200 A=624 A=38 9600 A=1249 A=77 4800 A=2499 A=155 Table 5‑2 UART Baud Rate Setting 5.19.1.1 Auto-Flow Control The UART0 and UART1 controllers support auto-flow control function that uses two low-level signals, CTSn (clear-to-send) and RTSn (request-to-send) to control the flow of data transfer between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts RTSn (RTSn high) to external device. When the number of bytes in the RX-FIFO equals the value of UART_TLCTL [RTS_TRI_LEV], the RTSn is de-asserted. The UART sends data out when UART controller detects CTSn is asserted (CTSn high) from external device. If a valid asserted CTSn is not detected the UART controller will not send data out. 5.19.1.2 Auto-Baud Rate Detection The UART0 and UART1 controllers support auto-baud rate detection. The auto-baud rate function can be used to measure the receiver incoming data baud rate. If enabled the auto-baud feature, UART controller will measure the bit time of the received data stream and set the divisor latch registers UART_BARD. Auto-baud rate detection is started by setting the UART_CTL [ABAUD_EN]. 5.19.1.3 UART Wake-Up Function The UART0 and UART1 controllers support wake-up system function. The wake-up function includes CTSn wake-up function (UART_CTL [WAKE_CTS_EN]) and data wake-up function (UART_CTL [WAKE_DATA_EN]). When the system is operation in power-down mode, the UART can wake-up system by CTSn pin or by incoming data. NANO100 SERIES DATASHEET 5.19.1.4 IrDA Function Mode The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set UART_FUN_SEL to select IrDA function). The SIR specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum 10 ms transfer delay between transmission and reception, and in IrDA Operation mode the UART_BAUD setting must be mode1 (UART_BAUD [DIV_16_EN] = “1”). 5.19.1.5 RS-485 Function Mode Another alternate function of UART controllers is RS-485 9 bit mode function whose direction control can be controlled by RTSn pin or GPIO. The RS-485 function mode is selected by setting the UART_FUN_SEL register to select RS-485 function. The RS-485 driver control is implemented by using the RTSn control signal from an asynchronous serial port to enable the RS485 driver. In RS-485 mode, many characteristics of the RX and TX are same as UART. 5.19.1.6 LIN Function Mode 5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In LIN mode, one start bit and 8-bit data format with 1-bit stop bit are required in accordance with the LIN standard. Features May 31, 2016 Full duplex, asynchronous communications. Page 124 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Separate receiving / transmitting 16 bytes entry FIFO for data payloads. Supports hardware auto-flow control/flow control function (CTSn, RTSn) and programmable (CTSn, RTSn) flow control trigger level. Supports programmable baud rate generator for each channel. Supports auto-baud rate detect function. Supports programmable receiver buffer trigger level. Supports incoming data or CTSn to wake-up function. Supports 9 bit receiver buffer time-out detection function. All UART channels can be served by the PDMA controller. Programmable transmitting data delay time between the last stop bit leaving the TXFIFO and the de-assertion by setting UART_TMCTL [DLY] register. Supports break error, frame error, parity error and receiving / transmitting buffer overflow detect function. Fully programmable serial-interface characteristics: Programmable number of data bit, 5, 6, 7, 8 character. Programmable parity bit, even, odd, no parity or stick parity bit generation and detection. Programmable stop bit, 1, 1.5, or 2 stop bit generation. Supports IrDA SIR function mode May 31, 2016 Supports LIN function mode. Supports LIN Master/Slave mode Supports programmable break generation function for transmitter. Supports break detect function for receiver. Supports RS-485 function mode. Supports RS-485 9bit mode. Supports hardware or software controls RTSn or software control GPIO to control transfer direction. Page 125 of 160 Revision 1.08 NANO100 SERIES DATASHEET Supports 3/16 bit period modulation. NUMICRO® NANO100 (B) DATASHEET 5.20 USB 5.20.1 Overview The USB controller is a USB 2.0 full-speed device controller. It is compliant with USB 2.0 full speed device specification and supports control/bulk/interrupt/isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There is an internal 512-byte SRAM as data buffer in this controller. For IN token or OUT token transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface. Users need to allocate the effective starting address of SRAM for each endpoint buffer through “buffer segmentation register (BUFSEG)”. This device controller contains 8 configurable endpoints. Each endpoint can be configured as IN or OUT endpoint. The function address of the device and endpoint number in each endpoint shall be configured properly in advance for receiving or transmitting a data packet correctly. The transmitting/receiving length in each endpoint is defined in maximum payload register (MXPLD) and the handshakes between Host and Device are also handled by it. There are four different interrupt events in this controller. They are the wake-up function, device plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of events occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint. A software-disable function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables the DRVSE0 bit (USB_CTL[4]), the USB controller will force USB_DP and USB_DM to level low and USB device function is disabled (disconnected). After disable the DRVSE0 bit, USB_DP will be pulled high by internal pull-high circuit then host will enumerate the USB device connection again. Reference: Universal Serial Bus Specification Revision 2.0 NANO100 SERIES DATASHEET 5.20.2 Features This Universal Serial Bus (USB) performs a serial interface with a single connector type for attaching all USB peripherals to the host system. Following is the feature listing of this USB. Compliant with USB 2.0 Full-Speed specification. Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB and BUS). Supports Control/Bulk/Interrupt/Isochronous transfer type. Supports suspend function when no bus activity existing for 3 ms. Provide 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types 512-byte SRAM buffer inside Provide remote wake-up capability. May 31, 2016 Page 126 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.21 Watchdog Timer Controller 5.21.1 Overview The purpose of Watchdog Timer is to perform a system reset after the software running into a problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up CPU from power-down mode. The watchdog timer includes an 18-bit free running counter with programmable time-out intervals. 5.21.2 Features 18-bit free running WDT counter for Watchdog timer time-out interval. Selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.316 s (if WDT_CLK = 10 kHz). Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz. NANO100 SERIES DATASHEET May 31, 2016 Page 127 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 5.22 Window Watchdog Timer Controller 5.22.1 Overview The purpose of Window Watchdog Timer is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 5.22.2 Features 6-bit down counter and 6-bit compare value to make the window period flexible Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable NANO100 SERIES DATASHEET May 31, 2016 Page 128 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 6 6.1 ARM® CORTEX™-M0 CORE Overview The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor. The profile supports two modes – Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. The following figure shows the functional controller of processor. Cortex-M 0 components Cortex-M 0 processor Nested Vectored Interrupt Controller ( NVIC) Interrupts Wakeup Interrupt Controller ( WIC) Debug Cortex-M0 Processor Core Bus Matrix Breakpoint and Watchpoint Unit Debugger interface AHB- Lite interface Debug Access Port ( DAP) Serial Wire or JTAG debug port Figure 6‑1 M0 Functional Block NANO100 SERIES DATASHEET 6.2 Features A low gate count processor: ARMv6-M Thumb instruction set Thumb-2 technology ARMv6-M compliant 24-bit SysTick timer A 32-bit hardware multiplier Supports little-endian data accesses Capable of deterministic, fixed-latency, interrupt handling Load/store-multiples and multi-cycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature NVIC: May 31, 2016 ® 32 external interrupt inputs, each with four levels of priority Page 129 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Dedicated Non-Maskable Interrupt (NMI) input Supports for both level-sensitive and pulse-sensitive interrupt lines Wake-up Interrupt Controller (WIC), providing Ultra-low Power Sleep mode support Debug support: Four hardware breakpoints Two watch points Program Counter Sampling Register (PCSR) for non-intrusive code profiling Single step and vector catch capabilities Bus interfaces: Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to all system peripherals and memory Single 32-bit slave port that supports the DAP (Debug Access Port) NANO100 SERIES DATASHEET May 31, 2016 Page 130 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 7 APPLICATION CIRCUIT 7.1 LCD Charge Pump 7.1.1 C-type 1/3 Bias 0.1uF DH 1 VLC D DH 2 V3 NANO130 V2 V1 7.1.2 0.1uF 0.1uF 0.1uF 0.1uF C-type 1/2 Bias DH 2 NANO130 VLC D 0.1uF V3 0.1uF V2 0.1uF V1 0.1uF NANO100 SERIES DATASHEET 0.1uF DH 1 7.1.3 Internal R-type Nano110/130 series MCUs also support external R-type mode (bypass internal R) to reduce current consumption. For external R-type application, VLCD is normally connected to system VDD, or it can be connected to VDD through an external variable resistor (VR) which is used for adjusting LCD contrast. May 31, 2016 Page 131 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET VDD VLCD DH1 DH2 NANO110 NANO130 VR 200k V3 200k V2 200k V1 7.1.4 External R-type To reduce the current, the resistor ladder value can be increased. At some point, when the resistor ladder value is increased, the contrast will become affected and the waveform shape will be altered. Therefore, capacitors around 0.1uF should be chosen and place closed to resistor ladder based on the contrast and size of the pixels on the glass. VDD VR NANO100 SERIES DATASHEET VLCD DH1 DH2 NANO110 NANO130 R1 V3 R2 V2 R3 V1 May 31, 2016 Page 132 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET VDD VR VLCD DH1 R1 NANO110 NANO130 DH2 0.1uF V3 R2 0.1uF V2 R3 0.1uF V1 7.2 ADC Application Circuit 7.2.1 7.2.1.1 Voltage Reference Source AVDD NANO100 1uF // 0.1F VREF VREF REFSEL[1:0] EXT_MODE=0 Int Vref 1uF // 0.1uF AVSS M ADC Vref U X In Case VREF = AVDD AVSS REFSEL[1:0] of ADCR 00 AVDD as Voltage reference 01 Int. Vref as Voltage reference 10 Ext. VREF pin as Voltage reference 11 Reserve May 31, 2016 Page 133 of 160 Revision 1.08 NANO100 SERIES DATASHEET AVDD AVDD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 NUMICRO® NANO100 (B) DATASHEET 7.2.1.2 Vref Pin NANO100 AVDD AVDD 1uF // 0.1uF M ADC Vref U X In Case VREF = AVDD VREF VREF REFSEL[1:0] EXT_MODE=0 Int Vref 1uF // 0.1uF AVSS AVSS REFSEL[1:0] of ADCR 00 AVDD as Voltage reference 01 Int. Vref as Voltage reference AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 10 Ext. VREF pin as Voltage reference 11 Reserve 7.2.1.3 Int Vref NANO100 AVDD AVDD 1uF // 0.1uF NANO100 SERIES DATASHEET VREF VREF REFSEL[1:0] EXT_MODE=1 Int Vref 1uF // 0.1uF AVSS M ADC Vref U X In Case VREF = AVDD AVSS REFSEL[1:0] of ADCR 00 AVDD as Voltage reference 01 Int. Vref as Voltage reference AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 10 Ext. VREF pin as Voltage reference 11 Reserve May 31, 2016 Page 134 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 7.3 DAC Application Circuit 7.3.1 7.3.1.1 Voltage Reference Source AVDD NANO100 AVDD AVDD 1uF // 0.1uF M DAC Vref U X In Case VREF = AVDD VREF VREF EXT_MODE=0 REFSEL[1:0] DAC2_out Int Vref 1uF // 0.1uF REFSEL[1:0] of DAC AVSS AVSS DAC1_out 00 Int. Vref as Voltage reference 01 Ext. VREF pin as Voltage reference 10 AVDD as Voltage reference 11 AVDD as Voltage reference 7.3.1.2 Vref Pin NANO100 1uF // 0.1uF M DAC Vref U X In Case VREF = AVDD VREF VREF EXT_MODE=0 REFSEL[1:0] DAC2_out Int Vref 1uF // 0.1uF AVSS DAC1_out AVSS REFSEL[1:0] of DAC 00 Int. Vref as Voltage reference 01 Ext. VREF pin as Voltage reference 10 AVDD as Voltage reference 11 AVDD as Voltage reference May 31, 2016 Page 135 of 160 Revision 1.08 NANO100 SERIES DATASHEET AVDD AVDD NUMICRO® NANO100 (B) DATASHEET 7.3.1.3 Int Vref NANO100 AVDD AVDD 1uF // 0.1uF M DAC Vref U X In Case VREF = AVDD VREF VREF EXT_MODE=1 REFSEL[1:0] DAC2_out Int Vref 1uF // 0.1uF AVSS DAC1_out AVSS REFSEL[1:0] of DAC 00 Int. Vref as Voltage reference 01 Ext. VREF pin as Voltage reference 10 AVDD as Voltage reference 11 AVDD as Voltage reference NANO100 SERIES DATASHEET May 31, 2016 Page 136 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 7.4 Whole Chip Application Circuit DVDD R1 10K 0603R SW1 TICE_RST DVDD DVDD CB3 0.1uF C0603 C15 1uF C0603 CB4 0.1uF C0603 From ICE Bridge's USB Power DVDD JP4 TICE_DAT TICE_CLK TICE_RST HEADER 5PX2 HEADER 5PX2 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 X32KO X32KI ICE Interface DVDD C2 C3 R2 XTAL2 20pF 0603C X2 12MHz XTAL3-1 10uF/10V TANT-A 33 R4 0603R 1M/DNE 0603R C5 XTAL1 20pF 0603C DVDD C7 6pF 0603C CB2 0.1uF C0603 PE.13 PB.14 PB.13 PB.12 NC X32O X32I NC PA.11 PA.10 PA.9 PA.8 PD.8 PD.9 PD.10 PD.11 PD.12 PD.13 PB.4 PB.5 PB.6 PB.7 NC LDO NC NC VDD NC VSS VSS VSS VSS PA.7 PA.6 PA.5 PA.4 PA.3 PA.2 PA.1 PA.0 AVSS AVSS VSS VSS NC VDD NC ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 PC.12 PC.13 PE.0 PE.1 PE.2 PE.3 PE.4 NANO130_LQFP128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PIN96 PIN95 PIN94 PIN93 PIN92 PIN91 PIN90 PIN89 PIN88 PIN87 PIN86 PIN85 PIN84 PIN83 PIN82 PIN81 PIN80 PIN79 PIN78 PIN77 PIN76 PIN75 PIN74 PIN73 PIN72 PIN71 PIN70 PIN69 PIN68 PIN67 PIN66 PIN65 DVDD TICE_CLK TICE_DAT DVDD CB5 0.1uF C0603 PIN33 PIN34 PIN35 PIN36 PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52 PIN53 PIN54 PIN55 PIN56 PIN57 PIN58 PIN59 PIN60 PIN61 PIN62 PIN63 PIN64 X32KO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PE.12 PE.11 PE.10 PE.9 PE.8 PE.7 NC VBUS VDD33 USB_DM USB_DP PB.0 PB.1 PB.2 PB.3 PD.6 PD.7 PD.14 PD.15 PC.5 PC.4 PC.3 PC.2 PC.1 PC.0 PE.6 VLCD NC PE.5 PB.11 PB.10 PB.9 2 4 6 8 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 3 5 7 9 C14 1uF C0603 PE.14 PE.15 PB.8 PVSS VSS PF.5 PF.4 NC VDD NC VSS VSS RESET NC XT1_Out XT1_In NC PB.15 PC.14 PC.15 PC.6 PC.7 PD.5 PD.4 NC PD.3 PD.2 PD.1 PD.0 AVDD NC VREF U1 C13 0.1uF C0603 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PIN128 PIN127 PIN126 PIN125 PIN124 PIN123 PIN122 PIN121 PIN120 PIN119 PIN118 PIN117 PIN116 PIN115 PIN114 PIN113 PIN112 PIN111 PIN110 PIN109 PIN108 PIN107 PIN106 PIN105 PIN104 PIN103 PIN102 PIN101 PIN100 PIN99 PIN98 PIN97 Reset Circuit XTAL2 XTAL1 C1 10uF/10V TANT-A TICE_RST SW PUSH BUTTON X1 32.768KHz XTAL3-1 C8 X32KI C12 1uF C0603 6pF 0603C C9 0.1uF C0603 C10 1uF C0603 Crystal NANO100 SERIES DATASHEET May 31, 2016 Page 137 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 8 POWER COMSUMPTION Part No Nano100 (B) series 128 KB Flash 16 KB RAM Test Condition VDD CPU Clock Current Operating Mode: CPU run while(1) in FLASH ROM Clock = 12 MHz Crystal Oscillator Disable all peripherial 3.3V 12 MHz 2.41mA 200uA/MHz 1.8V 12 MHz N/A Idle Mode: CPU stop Clock = 12 MHz Crystal Oscillator Disable all peripherial 3.3V 12 MHz 900uA 75uA/MHz 1.8V 12 MHz N/A RTC + LCD Mode: (RAM retention) (Power down with 32K and LCD enabled) CPU stop Clock = 32.768 kHz Crystal Oscillator Disable all peripherial except RTC and LCD circuit Without panel loading C-type Internal R-type ( With 200kΩ Resistor ladder ) External R-type ( With 1MΩ Resistor ladder ) C-type/R-type NANO100 SERIES DATASHEET RTC Mode: (RAM retention) (Power down with 32K enabled) CPU stop Clock = 32.768 kHz Crystal Oscillator Disable all peripherial except RTC circuit 10uA 3.3V - 8.5uA 4.5uA 1.8V - N/A 3.3V - 2.5uA 1.8V - 2.0uA 3.3V - 1uA 1.8V - 0.8uA 3.3V 7us N/A Power-down Mode: (RAM retention) CPU and all clocks stop Wake-Up from Power-down Mode Note: Wake-up time: 7us from wake-up event to first CPU core valid clock; 10us from interrupt event to interrupt service routine first instruction. May 31, 2016 Page 138 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 9 9.1 ELECTRICAL CHARACTERISTIC Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT VDDVSS -0.3 +4.0 V Input Voltage on 5V Tolerance Pin VIN VSS -0.3 VDD +3.7 V Input Voltage on Any Other Pin without 5V Tolerance Pin VIN VSS -0.3 VDD +0.3 V 1/tCLCL 4 24 MHz Operating Temperature TA -40 +85 C Storage Temperature TST -55 +150 C Maximum Current into VDD - 150 mA Maximum Current out of VSS - 150 mA Maximum Current sunk by a I/O Pin - 25 mA Maximum Current Sourced by a I/O Pin - 25 mA Maximum Current Sunk by Total I/O Pins - 100 mA Maximum Current Sourced by Total I/O Pins - 100 mA DC Power Supply Oscillator Frequency (LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23) (LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39) 9.2 Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics (VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.) SPECIFICATIONS PARAMETER Operation voltage Power Ground SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 1.8 - 3.6 V -0.3 - VLDO1 1.62 1.8 1.98 V MCU operating in Run or Idle mode VLDO2 1.49 1.66 1.83 V MCU operating in Power-down mode VDD VSS AVSS VDD =1.8V up to 42 MHz V LDO Output Voltage May 31, 2016 Page 139 of 160 Revision 1.08 NANO100 SERIES DATASHEET Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance. NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. Analog Operating Voltage AVDD Reference Voltage Vref TYP. MAX. UNIT VDD 1.8 V AVDD V Run Mode CPU run while(1) in FLASH ROM at IRC = 12 MHz Clock = 12 MHz Crystal Oscillator Crystal Oscillator Disable all peripherial Disable all peripherial Operating Current IDD1 20.5 mA IDD2 10.6 mA IDD3 19.1 mA IDD4 10.3 mA IDD5 16.2 mA IDD6 8.3 mA IDD7 15.3 mA IDD8 8.0 mA IDD9 6.4 mA IDD10 2.8 mA IDD11 6.3 mA IDD12 2.8 mA IDD13 6.7 mA Run Mode at XTAL 12 MHz, HCLK = 42 MHz NANO100 SERIES DATASHEET Operating Current Run Mode at XTAL 12 MHz, HCLK = 32 MHz Operating Current Run Mode at XTAL 12 MHz, HCLK = 12 MHz Operating Current Run Mode May 31, 2016 Page 140 of 160 VDD = 3.6V at 42 MHz, all IP and PLL enabled [*5] VDD = 3.6V at 42 MHz all IP disabled and PLL enabled VDD = 1.8V at 42 MHz all IP and PLL enabled [*5] VDD = 1.8V at 42 MHz all IP disabled and PLL enabled VDD = 3.6V at 32 MHz, all IP and PLL enabled [*5] VDD = 3.6V at 32 MHz all IP disabled and PLL enabled VDD = 1.8V at 32 MHz all IP and PLL enabled [*5] VDD = 1.8V at 32 MHz all IP disabled and PLL enabled VDD = 3.6V at 12 MHz, all IP enabled and PLL disabled VDD = 3.6V at 12 MHz, all IP and PLL disabled VDD = 1.8V at 12 MHz, all IP enabled and PLL disabled VDD = 1.8V at 12 MHz, all IP and PLL disabled VDD = 3.6V at 12 MHz, all IP enabled and PLL disabled Revision 1.08 NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT at IRC 12 MHz, HCLK = 12 MHz Operating Current 3.0 mA IDD15 6.6 mA IDD16 3.0 mA IDD17 3.3 mA IDD18 1.3 mA IDD19 3.2 mA IDD20 1.3 mA IDD21 82 uA IDD22 74 uA IDD23 77 uA IDD24 68 uA IDD25 70 uA IDD26 68 uA IDD27 65 uA IDD28 62 uA IIDLE1 14.5 mA IIDLE2 4.6 mA Run Mode at XTAL 4 MHz, HCLK = 4 MHz Operating Current Run Mode at XTAL 32.768 kHz, HCLK = 32.768 kHz Operating Current Run Mode at IRC 10 kHz, HCLK = 10 kHz Operating Current Idle Mode at XTAL 12 MHz, HCLK = 42 MHz May 31, 2016 Page 141 of 160 VDD = 3.6V at 12 MHz, all IP and PLL disabled VDD = 1.8V at 12 MHz, all IP enabled and PLL disabled VDD = 1.8V at 12 MHz, all IP and PLL disabled VDD = 3.6V at 4 MHz, all IP enabled and PLL disabled VDD = 3.6V at 4 MHz, all IP and PLL disabled VDD = 1.8V at 4 MHz, all IP enabled and PLL disabled VDD = 1.8V at 4 MHz, all IP and PLL disabled VDD = 3.6V at 32.768 kHz all IP enabled and PLL disabled, VDD = 3.6V at 32.768 kHz all IP and PLL disabled VDD = 1.8V at 32.768 kHz all IP enabled and PLL disabled VDD = 1.8V at 32.768 kHz all IP and PLL disabled VDD = 3.6V at 10 kHz all IP enabled and PLL disabled VDD = 3.6V at 10 kHz all IP and PLL disabled VDD = 1.8V at 10 kHz all IP enabled and PLL disabled VDD = 1.8V at 10 kHz all IP and PLL disabled VDD= 3.6V at 42 MHz all IP and PLL enabled [*5] VDD=3.6V at 42 MHz all IP disabled and PLL enabled Revision 1.08 NANO100 SERIES DATASHEET IDD14 NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. Operating Current TYP. MAX. UNIT IIDLE3 13.8 mA IIDLE4 4.5 mA IIDLE5 11.6 mA IIDLE6 3.6 mA IIDLE7 11.1 mA IIDLE8 3.6 mA IIDLE9 4.7 mA IIDLE10 0.99 mA IIDLE11 4.6 mA IIDLE12 0.94 mA IIDLE13 5.9 mA IIDLE14 1.3 mA IIDLE15 4.9 mA IIDLE16 1.3 mA IIDLE17 2.7 mA IIDLE18 0.66 mA IIDLE19 2.7 mA Idle Mode at XTAL 12 MHz, HCLK = 32 MHz Operating Current Idle Mode at XTAL 12 MHz, HCLK = 12 MHz NANO100 SERIES DATASHEET Operating Current Idle Mode at IRC 12 MHz, HCLK = 12 MHz Operating Current Idle Mode at XTAL 4 MHz, HCLK = 4 MHz May 31, 2016 Page 142 of 160 VDD = 1.8V at 42MHz all IP and PLL enabled [*5] VDD = 1.8V at 42 MHz all IP disabled and PLL enabled VDD= 3.6V at 32 MHz all IP and PLL enabled [*5] VDD=3.6V at 32 MHz all IP disabled and PLL enabled VDD = 1.8V at 32MHz all IP and PLL enabled [*5] VDD = 1.8V at 32 MHz all IP disabled and PLL enabled VDD = 3.6V at 12 MHz, all IP enabled and PLL disabled VDD = 3.6V at 12 MHz, all IP and PLL disabled VDD = 1.8V at 12 MHz, all IP enabled and PLL disabled VDD = 1.8V at 12 MHz, all IP and PLL disabled VDD = 3.6V at 12 MHz, all IP enabled and PLL disabled VDD = 3.6V at 12 MHz, all IP and PLL disabled VDD = 1.8V at 12 MHz, all IP enabled and PLL disabled VDD = 1.8V at 12 MHz, all IP and PLL disabled VDD = 3.6V at 4 MHz, all IP enabled and PLL disabled VDD = 3.6V at 4 MHz, all IP and PLL disabled VDD = 1.8V at 4 MHz, all IP enabled and PLL disabled Revision 1.08 NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. Operating Current TYP. MAX. UNIT 0.64 mA IIDLE21 78 uA IIDLE22 69 uA IIDLE23 72 uA IIDLE24 63 uA IIDLE25 69 uA IIDLE26 66 uA IIDLE27 63 uA IIDLE28 61 uA IPWD1 1.2 A IPWD2 0.8 A IPWD3 2.8 Idle Mode at XTAL 32.768 kHz, HCLK = 32.768 kHz Operating Current Idle Mode at IRC 10 kHz, HCLK = 10 kHz Standby Current Power-down Mode A VDD = 1.8V at 4 MHz, all IP and PLL disabled VDD = 3.6V at 32.768 kHz all IP enabled and PLL disabled VDD = 3.6V at 32.768 kHz all IP and PLL disabled VDD = 1.8V at 32.768 kHz all IP enabled and PLL disabled VDD = 1.8V at 32.768 kHz all IP and PLL disabled VDD = 3.6V at 10 kHz all IP enabled and PLL disabled VDD = 3.6V at 10 kHz all IP and PLL disabled VDD = 1.8V at 10 kHz all IP enabled and PLL disabled VDD = 1.8V at 10 kHz all IP and PLL disabled VDD = 3.6V, RTC OFF, all clock stop With RAM Retenstion, IO no loading VDD = 1.8V, RTC OFF, all clock stop With RAM Retenstion, IO no loading VDD = 3.6V, RTC ON, all clock stop except 32.768 kHz With RAM Retenstion, IO no loading IPWD4 A 2.0 VDD = 1.8V, RTC ON, all clock stop except 32.768 kHz With RAM Retenstion, IO no loading Input Pull Up Resistor PA, PB, PC, PD, PE, PF RIN Input Leakage Current PA, PB, PC, PD, PE, PF ILK May 31, 2016 -0.1 40 KΩ VDD = 3.3V 98 KΩ VDD = 1.8V A VDD = 3.3V, 0<VIN<VDD - +0.1 Page 143 of 160 Revision 1.08 NANO100 SERIES DATASHEET IIDLE20 NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. Input Low Voltage PA, PB, PC, PD, PE, PF VIL1 TYP. MAX. UNIT - 0.4VDD V 5.5 V (Schmitt input) Input High Voltage PA, PB, PC, PD, PE, PF VIH1 0.6VDD (Schmitt input) ADC and DAC shared pins without Input 5V tolerance. Hysteresis voltage of PA~PF (Schmitt input) VHY Input Low Voltage XT1_IN / XT1_OUT [*2] VIL2 0 - 0.4 Input High Voltage [*2] XT1_IN / XT1_OUT VIH2 1.5 - VDD +0.2 V Input Low Voltage [*2] X32I / X32O VIL4 0 - 0.3 V Input High Voltage [*2] X32I / X32O VIH4 1.5 - 1.98 V VILS 1.28 1.33 1.37 V VDD = 3.3V VIHS 1.75 1.98 2.25 V VDD = 3.3V ISR21 -10 -14 - mA ISR22 -3 -5 - mA Sink Current PA, PB, PC, PD, PE, PF ISK21 10 15 - mA (Push-pull Mode) ISK22 3 6 - mA Negative going threshold (Schmitt input), /RESET Positive going threshold 0.2VDD V VDD = 1.8V VDD = 1.8V NANO100 SERIES DATASHEET (SchmittIput), /RESET Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode) VDD = 3.3V, VS = Vdd-0.7V VDD = 1.8V, VS = Vdd-0.45V VDD = 3.3V, VS = 0.7V VDD = 1.8V, VS = 0.45V Note: 1. /RESET pin is a Schmitt trigger input. 2. Crystal Input is a CMOS input. 3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and the closest VSS pin of the device. 4. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin and the closest VSS pin of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise. 5. All peripherals’ clock source is from HXT (12 MHz), except SPI from HCLK. May 31, 2016 Page 144 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 9.3 AC Electrical Characteristics 9.3.1 External Input Clock SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT Clock High Time tCHCX 10 - nS Clock Low Time tCLCX 10 - nS Clock Rise Time tCLCH 2 - 15 nS Clock Fall Time tCHCL 2 - 15 nS tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. 9.3.2 External 4~24 MHz XTAL Oscillator SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT fHXT 4 12 24 Temperature THXT -40 - +85 Operating current IHXT 9.3.2.1 0.3 MHz o VDD = 1.8V ~ 3.6V C VDD = 3.0V mA Typical Crystal Application Circuits CRYSTAL 4MHz ~ 24 MHz C1 C2 Optional(Depend on crystal specification) R without C1 XTAL IN R XTAL OUT C2 Figure 9‑1 Typical Crystal Application Circuit May 31, 2016 Page 145 of 160 Revision 1.08 NANO100 SERIES DATASHEET Oscillator frequency NUMICRO® NANO100 (B) DATASHEET 9.3.3 External 32.768 kHz Crystal SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. Oscillator frequency fLXT Temperature TLXT Operating current ILXT 9.3.4 TYP. MAX. UNIT 32.768 -40 - kHz o +85 VDD = 1.8V ~ 3.6V C A 1.2 VDD = 3.0V Internal 12 MHz Oscillator SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. Supply voltage [1] Calibrated Internal Oscillator Frequency VHRC MAX. UNIT 1.8 V o 11.88 12 12.12 MHz 25 C, VDD = 3V 11.76 12 12.24 MHz -40 C~+85 C, VDD = 1.8V~3.6V FHRC 11.97 Operating current TYP. IHRC 12 o o o o -40 C~+85 C, VDD = 1.8V~3.6V MHz Enable 32.768K crystal oscillator and set TRIM_SEL[1:0]=”10” 12.03 A 450 Note: Internal oscillator operation voltage comes from LDO. 9.3.5 Internal 10 kHz Oscillator NANO100 SERIES DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. Supply voltage [1] Center Frequency Operating current VLRC FLRC TYP. MAX. UNIT 1.8 V o 7 10 13 kHz 5 10 15 kHz -40 C~+85 C, VDD = 1.8V~3.6V ILRC o A 0.7 25 C, VDD = 3V o VDD = 3V Note: Internal oscillator operation voltage comes from LDO. 9.4 9.4.1 Analog Characteristics 12-bit ADC SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. Operating voltage May 31, 2016 AVDD 1.8 TYP. MAX. UNIT 3.6 Page 146 of 160 V AVDD = VDD Revision 1.08 NUMICRO® NANO100 (B) DATASHEET SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT IADC42 147 A AVDD = VDD = 3.0V ADC_VREF = AVDD ADC Clock Rate = 42 MHz IADC12 50 A AVDD = VDD = 3.0V ADC_VREF = AVDD ADC Clock Rate = 12 MHz Operating current Resolution RADC Reference voltage VREF Reference input current (Avg.) IREF ADC input voltage VIN 0 Conversion time TCONV 0.5 Sampling Rate FSPS Integral Non-Linearity Error INL ±1 Differential Non-Linearity DNL ±0.8 Gain error EG - ±2 LSB VREF is external Vref pin Offset error EOFFSET - ±3 LSB VREF is external Vref pin Absolute error EABS - ±6 LSB VREF is external Vref pin ADC Clock frequency FADC 0.25 42 MHz ADCYC 20 CIN - Clock cycle Monotonic 9.4.2 Bit AVDD V 10 A VREF V S 2M Hz ±2 VDD = 3V LSB VREF is external Vref pin -1~+1.5 LSB VREF is external Vref pin Cycle 5 - - pF Guaranteed - Brown-out Detector SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT 3.6 V Operating voltage VBOD BOD17 Quiescent current IBOD17 1 A AVDD = 3.0V, BOD17 enabled BOD20 Quiescent current IBOD20 1 A AVDD = 3.0V, BOD20 enabled BOD25 Quiescent current IBOD25 1 A AVDD = 3.0V, BOD25 enabled BOD17 detection level VB17dt 1.6 1.7 1.8 V 25C BOD20 detection level VB20dt 1.9 2.0 2.1 V 25 C BOD25 detection level VB25dt 2.4 2.5 2.6 V 25 C May 31, 2016 1.8 Page 147 of 160 o o Revision 1.08 NANO100 SERIES DATASHEET Internal Capacitance 1.8 12 NUMICRO® NANO100 (B) DATASHEET 9.4.3 Power-on Reset SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT Reset voltage VPOR - 1.6 - V Quiescent current IPOR - 1 - nA 9.4.4 LDO output > Reset voltage Temperature Sensor SPECIFICATIONS PARAMETER TEST CONDITION (SUPPLY VOLTAGE = 3.36V) SYM. MIN. TYP. MAX. UNIT o Detection Temperature TDET -40 Operating current ITEMP - 5 - A Gain VTG -1.80 -1.73 -1.65 mV/ C Offset VTO 730 740 750 mV +110 C o o Tempeature at 0 C Note: Internal operation voltage comes form LDO. 9.4.5 12-bit DAC SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. NANO100 SERIES DATASHEET Operating voltage AVDD Operating current IDAC Resolution RADC Reference voltage VREF Reference input current (Avg.) IREF DAC output swin range VOUT Conversion Rate (code to adjacent code) FSPS Integral Non-Linearity Error INL Differential Non-Linearity TYP. 2.0 MAX. UNIT 3.6 V 2.20 1.8 mA 12 Bit AVDD V 0.85 AVDD = VDD = 3.0V, DAC_VREF = AVDD DAC conversion rate 500kHz AVDD = VDD = 3.0V DAC_VREF=Ext_Vref DAC conversion rate 500kHz 0.9 x VREF V 500 kHz VDD = 3V ±4 ±5 LSB VREF is external Vref pin Not include offset and gain error DNL ±1 ±2 LSB VREF is external Vref pin Not include offset and gain error Gain error EG 290 LSB Offset error EOFFSET 150 LSB May 31, 2016 0.1 x VREF mA AVDD = VDD - Page 148 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 9.4.6 LCD SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT VDD 1.8 - 3.6 V VLCD voltage VLCD34 - 3.4 - V CPUMP_VOL_SET=111, no loading VLCD voltage VLCD33 - 3.3 - V CPUMP_VOL_SET=110, no loading VLCD voltage VLCD32 - 3.2 - V CPUMP_VOL_SET=101, no loading VLCD voltage VLCD31 - 3.1 - V CPUMP_VOL_SET=100, no loading VLCD voltage VLCD30 - 3.0 - V CPUMP_VOL_SET=011, no loading VLCD voltage VLCD29 - 2.9 - V CPUMP_VOL_SET=010, no loading VLCD voltage VLCD28 - 2.8 - V CPUMP_VOL_SET=001, no loading VLCD voltage VLCD27 - 2.7 - V CPUMP_VOL_SET=000, no loading ILCD - 10 - A VDD = 3V, frame rate = 32Hz Without loading Operating voltage Operating current 9.4.7 Internal Voltage Reference SPECIFICATIONS PARAMETER SYM. TEST CONDITION MIN. TYP. MAX. UNIT AVDD 1.8 - 3.6 V 1.8V voltage reference VREF1 1.69 1.8 1.87 V AVDD ≥ 2.0V (-40C ~85C) 2.5V voltage reference VREF2 2.35 2.5 2.60 V AVDD ≥ 2.8V (-40C ~85C) TREFTAB - 1 - ms IVREF - 30 - A Stable Time Operating current 9.4.8 NANO100 SERIES DATASHEET Operating voltage AVDD = 3V USB PHY Specifications 9.4.8.1 USB PHY DC Electrical Characteristics SYMBOL PARAMETER VIH Input high (driven) VIL Input low VDI Differential input sensitivity May 31, 2016 CONDITION MIN. TYP. 2.0 - |PADP-PADM| Page 149 of 160 0.2 - MAX. UNIT V 0.8 V V Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Differential VCM common-mode range VSE Includes VDI range Single-ended receiver threshold 0.8 - 2.5 V 0.8 - 2.0 V Receiver hysteresis 200 mV VOL Output low (driven) 0 - 0.3 V VOH Output high (driven) 2.8 - 3.6 V VCRS Output signal cross voltage 1.3 - 2.0 V RPU Pull-up resistor 1.425 - 1.575 kΩ RPD Pull-down resistor 14.25 - 15.75 kΩ VTRM Termination Voltage for upstream port pull up (RPU) 3.0 - 3.6 V ZDRV Driver output resistance Steady state drive* 10 CIN Transceiver capacitance Pin to GND - 20 pF Ω *Driver output resistance doesn’t include series resistor resistance. 9.4.8.2 USB PHY Full-Speed Driver Elevtrical Characteristics NANO100 SERIES DATASHEET SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT TFR Rise Time CL=50p 4 - 20 ns TFF Fall Time CL=50p 4 - 20 ns TFRFF Rise and fall time matching TFRFF=TFR/TFF 90 - 111.11 % PARAMETER CONDITION MIN. TYP. MAX. UNIT VDDD and VDDREG Supply Current (Steady State) Standby 9.4.8.3 USB PHY Power Dissipation SYMBOL IVDDREG (Full Speed) 9.4.8.4 50 uA USB LDO DC Electrical Characteristics SYMBOL PARAMETER CONDITION MIN. VBUS MAX. 5 V33 Output voltage Iop Operation Current May 31, 2016 TYP. VBUS = 5V, 25C 2.97 3.3 100 Page 150 of 160 UNIT V 3.63 V uA Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 9.5 Flash DC Electrical Characteristics Symbol Parameter Min Typ Max Unit [2] VFLA Supply Voltage 1.62 1.8 1.98 V NENDUR Endurance 20000 TRET Data Retention 100 TERASE Page Erase Time - 20 - ms TPROG Program Time - 40 - us IDD1 Read Current 0.150 mA/MHz IDD2 Program Current 7 mA IDD3 Erase Current 7 mA cycles Test Condition [1] year TA = 25℃ Notes: 1. Number of program/erase cycles. 2. VFLA is source from chip LDO output voltage. 3. Guaranteed by design, not test in production. NANO100 SERIES DATASHEET May 31, 2016 Page 151 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 10 PACKAGE DIMENSIONS 10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm) NANO100 SERIES DATASHEET May 31, 2016 Page 152 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 10.2 LQFP64 (10x10x1.4 mm footprint 2.0 mm) NANO100 SERIES DATASHEET May 31, 2016 Page 153 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 10.3 LQFP64 (7x7x1.4 mm footprint 2.0 mm) NANO100 SERIES DATASHEET May 31, 2016 Page 154 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET NANO100 SERIES DATASHEET May 31, 2016 Page 155 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 10.4 LQFP48 (7x7x1.4 mm footprint 2.0 mm) NANO100 SERIES DATASHEET May 31, 2016 Page 156 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 10.5 QFN48 (7x7x0.85 mm) NANO100 SERIES DATASHEET May 31, 2016 Page 157 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 11 REVISION HISTORY Date Revision Description 2012.10.11 1.00 Initial release 1. Added SmartCard UART mode description in Pin Description. 2. Unified the abbreviation (TMR) in the Timer Controller section. 3. Modified the specifications of external input clock. 2012.12.11 1.01 4. Added LCD COM4 and COM5 description for each pin description and diagram. 5. Updated the ADC enabled by timer event description in the ADC section. 6. Changed Timer0/1 Ch0/1 to Timer x (x=0, 1, 2, 3) in the Timer Controller section. 2012.12.17 1.02 1. Added description of reading UCID in ISP mode. 1. Added R-type related description in LCD section. 2012.12.28 1.03 2. Updated the operating current data of Run mode and Idle mode at each frequency and added related data at 42 MHz in section 9.2. 2013.01.02 1.04 1. Updated the table in Power Consumption section. 1. Updated the display modes from four to six in section 5.13.2. 2. Corrected the pin descriptions in section 3.4. 2013.03.05 1.05 NANO100 SERIES DATASHEET 3. Updated temperature sensor of analog characteristic in section 9.4.4. 4. Corrected Smart Card’s feature to be half duplex in UART mode in section 5.16.2. 1. Updated the Nano110 LQFP128-pin diagram in section 3.3.2. 2013.05.28 1.06 2. Updated “12 MHz OSC has 2 % deviation within all temperarure range” in sections 2.1 to 2.4. 3. Updated DAC analog characteristics in section 9.4.5. 4. Added Nano110RC2BN to the Nano110 LCD Line Selection Guide. 1. Updated Nano100 series selection code in section 3.1. 2. Added the Nano100 QFN48 package in section 3.2 and QFN48 package dimensions in chapter 10. 2013.12.04 1.07 3. Fixed the typo of LCD characteristic in section 9.4.7. 4. Added a note that “Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance.” for pin description in section 3.4, LCD overview in section 5.13.1 and Absolute Maximum Ratings in section 9.1. 5. Modified the schematic for ADC and DAC application circuit in section May 31, 2016 Page 158 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET 7.2 and 7.3. 1. Added Flash DC Electrical Characteristics in section 9.5. 2. Fixed the typo of LCD Feature in section 5.13.2. 2016.05.31 1.08 3. Fixed the typo of Products Selection Guide in section 3.2 4. Modified the schematic for ADC, DAC and Whole Chip Application Circuit in section 7.2, 7.3 and 7.4. NANO100 SERIES DATASHEET May 31, 2016 Page 159 of 160 Revision 1.08 NUMICRO® NANO100 (B) DATASHEET Important Notice NANO100 SERIES DATASHEET Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. May 31, 2016 Page 160 of 160 Revision 1.08