Renesas H8S2472 16-bit single-chip microcomputer h8s family / h8s/2400 sery Datasheet

REJ09B0403-0200
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2472, H8S/2463, H8S/2462 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2472
H8S/2463
H8S/2462
Rev.2.00
Revision Date: Aug. 20, 2008
R4F2472
R4F2463
R4F2462
Rev. 2.00 Aug. 20, 2008 Page ii of xlviii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Aug. 20, 2008 Page iii of xlviii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 2.00 Aug. 20, 2008 Page iv of xlviii
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00 Aug. 20, 2008 Page v of xlviii
Preface
The H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group products are single-chip
microcomputers made up of the high-speed H8S/2600 CPU employing Renesas Technology
original architecture as its core, and the peripheral functions required to configure a system. The
H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs.
Target Users: This manual was written for users who will be using the H8S/2472 Group,
H8S/2463 Group, and H8S/2462 Group in the design of application systems. Target
users are expected to understand the fundamentals of electrical circuits, logical
circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group to
the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a
detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 29,
List of Registers.
Examples:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Rev. 2.00 Aug. 20, 2008 Page vi of xlviii
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group manuals:
Document Title
Document No.
H8S/2472 Group, H8S/2463 Group, and H8S/2462 Group Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Software Manual
REJ09B0139
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0058
User's Manual
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial
REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's
Manual
REJ10B0026
All trademarks and registered trademarks are the property of their respective owners.
Rev. 2.00 Aug. 20, 2008 Page vii of xlviii
Rev. 2.00 Aug. 20, 2008 Page viii of xlviii
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
Overview................................................................................................................................ 1
Block Diagram ....................................................................................................................... 3
Pin Description....................................................................................................................... 4
1.3.1 Pin Assignments ....................................................................................................... 4
1.3.2 Pin Assignment in Each Operating Mode................................................................. 7
1.3.3 Pin Functions .......................................................................................................... 14
Section 2 CPU......................................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features................................................................................................................................ 25
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 26
2.1.2 Differences from H8/300 CPU ............................................................................... 27
2.1.3 Differences from H8/300H CPU............................................................................. 27
CPU Operating Modes ......................................................................................................... 28
2.2.1 Normal Mode.......................................................................................................... 28
2.2.2 Advanced Mode...................................................................................................... 30
Address Space...................................................................................................................... 32
Registers............................................................................................................................... 33
2.4.1 General Registers .................................................................................................... 34
2.4.2 Program Counter (PC) ............................................................................................ 35
2.4.3 Extended Control Register (EXR) .......................................................................... 35
2.4.4 Condition-Code Register (CCR) ............................................................................. 36
2.4.5 Multiply-Accumulate Register (MAC) ................................................................... 37
2.4.6 Initial Values of CPU Registers .............................................................................. 37
Data Formats........................................................................................................................ 38
2.5.1 General Register Data Formats ............................................................................... 38
2.5.2 Memory Data Formats ............................................................................................ 40
Instruction Set ...................................................................................................................... 41
2.6.1 Table of Instructions Classified by Function .......................................................... 42
2.6.2 Basic Instruction Formats ....................................................................................... 52
Addressing Modes and Effective Address Calculation ........................................................ 53
2.7.1 Register DirectRn................................................................................................ 53
2.7.2 Register Indirect@ERn ....................................................................................... 53
2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 54
2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn ..... 54
2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 54
Rev. 2.00 Aug. 20, 2008 Page ix of xlviii
2.8
2.9
2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 55
2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)....................................... 55
2.7.8 Memory Indirect@@aa:8 ................................................................................... 56
2.7.9 Effective Address Calculation ................................................................................ 57
Processing States.................................................................................................................. 59
Usage Note........................................................................................................................... 61
2.9.1 Notes on Using the Bit Operation Instruction......................................................... 61
Section 3 MCU Operating Modes .......................................................................63
3.1
3.2
3.3
3.4
Operating Mode Selection ................................................................................................... 63
Register Descriptions ........................................................................................................... 64
3.2.1 Mode Control Register (MDCR) ............................................................................ 64
3.2.2 System Control Register (SYSCR) ......................................................................... 65
3.2.3 Serial Timer Control Register (STCR) ................................................................... 66
Operating Mode Descriptions .............................................................................................. 68
3.3.1 Mode 2.................................................................................................................... 68
Address Map ........................................................................................................................ 69
Section 4 Exception Handling .............................................................................71
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Exception Handling Types and Priority............................................................................... 71
Exception Sources and Exception Vector Table.................................................................. 72
Reset .................................................................................................................................... 74
4.3.1 Reset Exception Handling ...................................................................................... 74
4.3.2 Interrupts after Reset............................................................................................... 75
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled............................................ 75
Interrupt Exception Handling............................................................................................... 76
Trap Instruction Exception Handling................................................................................... 76
Stack Status after Exception Handling................................................................................. 77
Usage Note........................................................................................................................... 78
Section 5 Interrupt Controller..............................................................................79
5.1
5.2
5.3
Features................................................................................................................................ 79
Input/Output Pins................................................................................................................. 80
Register Descriptions ........................................................................................................... 81
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .............................................. 81
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 82
5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 83
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 84
5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 86
5.3.6 IRQ Status Registers (ISR16, ISR) ......................................................................... 87
Rev. 2.00 Aug. 20, 2008 Page x of xlviii
5.4
5.5
5.6
5.7
Interrupt Sources.................................................................................................................. 88
5.4.1 External Interrupts .................................................................................................. 88
5.4.2 Internal Interrupts ................................................................................................... 89
Interrupt Exception Handling Vector Table......................................................................... 90
Interrupt Control Modes and Interrupt Operation ................................................................ 93
5.6.1 Interrupt Control Mode 0 ........................................................................................ 95
5.6.2 Interrupt Control Mode 1 ........................................................................................ 97
5.6.3 Interrupt Exception Handling Sequence ............................................................... 100
5.6.4 Interrupt Response Times ..................................................................................... 101
5.6.5 DTC Activation by Interrupt................................................................................. 102
Usage Notes ....................................................................................................................... 104
5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 104
5.7.2 Instructions that Disable Interrupts ....................................................................... 105
5.7.3 Interrupts during Execution of EEPMOV Instruction........................................... 105
5.7.4 IRQ Status Registers (ISR16, ISR) ....................................................................... 105
Section 6 Bus Controller (BSC).........................................................................107
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Features.............................................................................................................................. 107
Input/Output Pins ............................................................................................................... 110
Register Descriptions ......................................................................................................... 111
6.3.1 Bus Control Register (BCR) ................................................................................. 111
6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 113
6.3.3 Wait State Control Register (WSCR) ................................................................... 114
6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 116
6.3.5 System Control Register 2 (SYSCR2) .................................................................. 117
Bus Control ........................................................................................................................ 118
6.4.1 Bus Specifications................................................................................................. 118
6.4.2 Advanced Mode.................................................................................................... 125
6.4.3 I/O Select Signals.................................................................................................. 126
Bus Interface ...................................................................................................................... 127
6.5.1 Data Size and Data Alignment.............................................................................. 127
6.5.2 Valid Strobes......................................................................................................... 129
6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 130
6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 131
6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode .................. 142
6.5.6 Wait Control ......................................................................................................... 150
Burst ROM Interface.......................................................................................................... 154
6.6.1 Basic Operation Timing........................................................................................ 154
6.6.2 Wait Control ......................................................................................................... 155
Idle Cycle........................................................................................................................... 156
Rev. 2.00 Aug. 20, 2008 Page xi of xlviii
6.8
Bus Arbitration .................................................................................................................. 157
6.8.1 Overview .............................................................................................................. 157
6.8.2 Operation .............................................................................................................. 157
6.8.3 Bus Mastership Transfer Timing .......................................................................... 158
Section 7 Data Transfer Controller (DTC)........................................................161
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Features.............................................................................................................................. 161
Register Descriptions ......................................................................................................... 163
7.2.1 DTC Mode Register A (MRA) ............................................................................. 164
7.2.2 DTC Mode Register B (MRB).............................................................................. 165
7.2.3 DTC Source Address Register (SAR)................................................................... 165
7.2.4 DTC Destination Address Register (DAR)........................................................... 165
7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 166
7.2.6 DTC Transfer Count Register B (CRB)................................................................ 166
7.2.7 DTC Enable Registers (DTCER).......................................................................... 166
7.2.8 DTC Vector Register (DTVECR)......................................................................... 167
7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 168
7.2.10 Event Counter Control Register (ECCR).............................................................. 169
7.2.11 Event Counter Status Register (ECS) ................................................................... 170
DTC Event Counter ........................................................................................................... 171
7.3.1 Event Counter Handling Priority .......................................................................... 173
7.3.2 Usage Notes .......................................................................................................... 173
Activation Sources............................................................................................................. 174
Location of Register Information and DTC Vector Table ................................................. 175
Operation ........................................................................................................................... 177
7.6.1 Normal Mode........................................................................................................ 178
7.6.2 Repeat Mode......................................................................................................... 179
7.6.3 Block Transfer Mode ............................................................................................ 180
7.6.4 Chain Transfer ...................................................................................................... 181
7.6.5 Interrupt Sources................................................................................................... 182
7.6.6 Operation Timing.................................................................................................. 182
7.6.7 Number of DTC Execution States ........................................................................ 184
Procedures for Using DTC................................................................................................. 185
7.7.1 Activation by Interrupt.......................................................................................... 185
7.7.2 Activation by Software ......................................................................................... 185
Examples of Use of the DTC ............................................................................................. 186
7.8.1 Normal Mode........................................................................................................ 186
7.8.2 Software Activation .............................................................................................. 187
Usage Notes ....................................................................................................................... 188
7.9.1 Module Stop Mode Setting ................................................................................... 188
Rev. 2.00 Aug. 20, 2008 Page xii of xlviii
7.9.2
7.9.3
7.9.4
On-Chip RAM ...................................................................................................... 188
DTCE Bit Setting.................................................................................................. 188
DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .................. 188
Section 8 I/O Ports .............................................................................................189
8.1
8.2
8.3
I/O Ports for the H8S/2472 Group ..................................................................................... 189
8.1.1 Port 1..................................................................................................................... 194
8.1.2 Port 2..................................................................................................................... 197
8.1.3 Port 3..................................................................................................................... 202
8.1.4 Port 4..................................................................................................................... 208
8.1.5 Port 5..................................................................................................................... 216
8.1.6 Port 6..................................................................................................................... 221
8.1.7 Port 7..................................................................................................................... 227
8.1.8 Port 8..................................................................................................................... 231
8.1.9 Port 9..................................................................................................................... 236
8.1.10 Port A.................................................................................................................... 240
8.1.11 Port B .................................................................................................................... 248
8.1.12 Port C .................................................................................................................... 254
8.1.13 Port D.................................................................................................................... 259
8.1.14 Port E .................................................................................................................... 264
8.1.15 Port F .................................................................................................................... 268
I/O Ports for the H8S/2463 Group and the H8S/2462 Group ............................................ 272
8.2.1 Port 1..................................................................................................................... 277
8.2.2 Port 2..................................................................................................................... 280
8.2.3 Port 3..................................................................................................................... 285
8.2.4 Port 4..................................................................................................................... 291
8.2.5 Port 5..................................................................................................................... 299
8.2.6 Port 6..................................................................................................................... 304
8.2.7 Port 7..................................................................................................................... 311
8.2.8 Port 8..................................................................................................................... 315
8.2.9 Port 9..................................................................................................................... 320
8.2.10 Port A.................................................................................................................... 324
8.2.11 Port B .................................................................................................................... 332
8.2.12 Port C .................................................................................................................... 338
8.2.13 Port D.................................................................................................................... 343
8.2.14 Port E .................................................................................................................... 348
8.2.15 Port F .................................................................................................................... 353
Change of Peripheral Function Pins................................................................................... 356
8.3.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port
Select Register (ISSR) .......................................................................................... 356
Rev. 2.00 Aug. 20, 2008 Page xiii of xlviii
8.3.2
Port Control Register 0 (PTCNT0) ....................................................................... 358
Section 9 14-Bit PWM Timer (PWMX) ...........................................................359
9.1
9.2
9.3
9.4
9.5
Features.............................................................................................................................. 359
Input/Output Pins............................................................................................................... 360
Register Descriptions ......................................................................................................... 360
9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 361
9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).......................... 362
9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 364
9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 365
Bus Master Interface .......................................................................................................... 366
Operation ........................................................................................................................... 367
Section 10 16-Bit Free-Running Timer (FRT)..................................................375
10.1 Features.............................................................................................................................. 375
10.2 Register Descriptions ......................................................................................................... 377
10.2.1 Free-Running Counter (FRC) ............................................................................... 377
10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 377
10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 378
10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 379
10.2.5 Timer Control/Status Register (TCSR)................................................................. 380
10.2.6 Timer Control Register (TCR).............................................................................. 381
10.2.7 Timer Output Compare Control Register (TOCR) ............................................... 382
10.3 Operation Timing............................................................................................................... 383
10.3.1 FRC Increment Timing......................................................................................... 383
10.3.2 Output Compare Output Timing........................................................................... 383
10.3.3 FRC Clear Timing ................................................................................................ 384
10.3.4 Timing of Output Compare Flag (OCF) Setting ................................................... 384
10.3.5 Timing of FRC Overflow Flag (OVF) Setting...................................................... 385
10.3.6 Automatic Addition Timing.................................................................................. 386
10.4 Interrupt Sources................................................................................................................ 386
10.5 Usage Notes ....................................................................................................................... 387
10.5.1 Conflict between FRC Write and Clear ................................................................ 387
10.5.2 Conflict between FRC Write and Increment......................................................... 388
10.5.3 Conflict between OCR Write and Compare-Match .............................................. 389
10.5.4 Switching of Internal Clock and FRC Operation.................................................. 390
Section 11 8-Bit Timer (TMR)..........................................................................393
11.1 Features.............................................................................................................................. 393
11.2 Register Descriptions ......................................................................................................... 396
Rev. 2.00 Aug. 20, 2008 Page xiv of xlviii
11.3
11.4
11.5
11.6
11.2.1 Timer Counter (TCNT)......................................................................................... 396
11.2.2 Time Constant Register A (TCORA).................................................................... 397
11.2.3 Time Constant Register B (TCORB) .................................................................... 397
11.2.4 Timer Control Register (TCR).............................................................................. 398
11.2.5 Timer Control/Status Register (TCSR)................................................................. 401
11.2.6 Timer Connection Register S (TCONRS)............................................................. 405
Operation Timing............................................................................................................... 406
11.3.1 TCNT Count Timing............................................................................................. 406
11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 406
11.3.3 Timing of Counter Clear at Compare-Match ........................................................ 407
11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 407
TMR_0 and TMR_1 Cascaded Connection ....................................................................... 408
11.4.1 16-Bit Count Mode ............................................................................................... 408
11.4.2 Compare-Match Count Mode ............................................................................... 408
Interrupt Sources................................................................................................................ 409
Usage Notes ....................................................................................................................... 410
11.6.1 Conflict between TCNT Write and Counter Clear................................................ 410
11.6.2 Conflict between TCNT Write and Increment...................................................... 411
11.6.3 Conflict between TCOR Write and Compare-Match............................................ 412
11.6.4 Switching of Internal Clocks and TCNT Operation.............................................. 413
11.6.5 Mode Setting with Cascaded Connection ............................................................. 414
Section 12 Watchdog Timer (WDT)..................................................................415
12.1 Features.............................................................................................................................. 415
12.2 Input/Output Pins ............................................................................................................... 417
12.3 Register Descriptions ......................................................................................................... 417
12.3.1 Timer Counter (TCNT)......................................................................................... 417
12.3.2 Timer Control/Status Register (TCSR)................................................................. 418
12.4 Operation ........................................................................................................................... 422
12.4.1 Watchdog Timer Mode ......................................................................................... 422
12.4.2 Interval Timer Mode............................................................................................. 424
12.4.3 RESO Signal Output Timing ................................................................................ 425
12.5 Interrupt Sources................................................................................................................ 426
12.6 Usage Notes ....................................................................................................................... 427
12.6.1 Notes on Register Access...................................................................................... 427
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 428
12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 428
12.6.4 Changing Value of PSS Bit................................................................................... 428
12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 429
12.6.6 System Reset by RESO Signal.............................................................................. 429
Rev. 2.00 Aug. 20, 2008 Page xv of xlviii
Section 13 Serial Communication Interface (SCI)............................................431
13.1 Features.............................................................................................................................. 431
13.2 Input/Output Pins............................................................................................................... 434
13.3 Register Descriptions ......................................................................................................... 434
13.3.1 Receive Shift Register (RSR) ............................................................................... 435
13.3.2 Receive Data Register (RDR) ............................................................................... 435
13.3.3 Transmit Data Register (TDR).............................................................................. 435
13.3.4 Transmit Shift Register (TSR) .............................................................................. 435
13.3.5 Serial Mode Register (SMR) ................................................................................ 436
13.3.6 Serial Control Register (SCR) .............................................................................. 439
13.3.7 Serial Status Register (SSR) ................................................................................. 442
13.3.8 Smart Card Mode Register (SCMR)..................................................................... 446
13.3.9 Bit Rate Register (BRR) ....................................................................................... 447
13.4 Operation in Asynchronous Mode ..................................................................................... 451
13.4.1 Data Transfer Format............................................................................................ 452
13.4.2 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode............................................................................................. 453
13.4.3 Clock..................................................................................................................... 454
13.4.4 SCI Initialization (Asynchronous Mode).............................................................. 455
13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 456
13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 458
13.5 Multiprocessor Communication Function.......................................................................... 462
13.5.1 Multiprocessor Serial Data Transmission ............................................................. 464
13.5.2 Multiprocessor Serial Data Reception .................................................................. 465
13.6 Operation in Clock Synchronous Mode............................................................................. 468
13.6.1 Clock..................................................................................................................... 468
13.6.2 SCI Initialization (Clock Synchronous Mode)...................................................... 469
13.6.3 Serial Data Transmission (Clock Synchronous Mode)......................................... 470
13.6.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 473
13.6.5 Simultaneous Serial Data Transmission and Reception
(Clock Synchronous Mode) .................................................................................. 475
13.7 Smart Card Interface Description ...................................................................................... 477
13.7.1 Sample Connection ............................................................................................... 477
13.7.2 Data Format (Except in Block Transfer Mode) .................................................... 477
13.7.3 Block Transfer Mode ............................................................................................ 479
13.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 480
13.7.5 Initialization.......................................................................................................... 481
13.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 482
13.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 485
13.7.8 Clock Output Control............................................................................................ 487
Rev. 2.00 Aug. 20, 2008 Page xvi of xlviii
13.8 Interrupt Sources................................................................................................................ 489
13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 489
13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 490
13.9 Usage Notes ....................................................................................................................... 491
13.9.1 Module Stop Mode Setting ................................................................................... 491
13.9.2 Break Detection and Processing ........................................................................... 491
13.9.3 Mark State and Break Sending.............................................................................. 491
13.9.4 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 491
13.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 491
13.9.6 Restrictions on Using DTC ................................................................................... 492
13.9.7 SCI Operations during Mode Transitions ............................................................. 493
13.9.8 Notes on Switching from SCK Pins to Port Pins .................................................. 497
Section 14 CRC Operation Circuit (CRC).........................................................499
14.1 Features.............................................................................................................................. 499
14.2 Register Descriptions ......................................................................................................... 500
14.2.1 CRC Control Register (CRCCR) .......................................................................... 500
14.2.2 CRC Data Input Register (CRCDIR).................................................................... 501
14.2.3 CRC Data Output Register (CRCDOR)................................................................ 501
14.3 CRC Operation Circuit Operation...................................................................................... 501
14.4 Note on CRC Operation Circuit......................................................................................... 505
Section 15 Serial Communication Interface with FIFO (SCIF) ........................507
15.1 Features.............................................................................................................................. 507
15.2 Input/Output Pins ............................................................................................................... 509
15.3 Register Descriptions ......................................................................................................... 510
15.3.1 Receive Shift Register (FRSR) ............................................................................. 511
15.3.2 Receive Buffer Register (FRBR) .......................................................................... 511
15.3.3 Transmitter Shift Register (FTSR)........................................................................ 511
15.3.4 Transmitter Holding Register (FTHR).................................................................. 512
15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 512
15.3.6 Interrupt Enable Register (FIER) .......................................................................... 513
15.3.7 Interrupt Identification Register (FIIR)................................................................. 514
15.3.8 FIFO Control Register (FFCR) ............................................................................. 516
15.3.9 Line Control Register (FLCR) .............................................................................. 517
15.3.10 Modem Control Register (FMCR) ........................................................................ 518
15.3.11 Line Status Register (FLSR) ................................................................................. 520
15.3.12 Modem Status Register (FMSR)........................................................................... 524
15.3.13 Scratch Pad Register (FSCR)................................................................................ 525
Rev. 2.00 Aug. 20, 2008 Page xvii of xlviii
15.3.14 SCIF Control Register (SCIFCR) ......................................................................... 526
15.4 Operation ........................................................................................................................... 528
15.4.1 Baud Rate ............................................................................................................. 528
15.4.2 Operation in Asynchronous Communication........................................................ 529
15.4.3 Initialization of the SCIF ...................................................................................... 530
15.4.4 Data Transmission/Reception with Flow Control................................................. 533
15.4.5 Data Transmission/Reception Through the LPC Interface ................................... 539
15.5 Interrupt Sources................................................................................................................ 541
15.6 Usage Note......................................................................................................................... 541
15.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 541
Section 16 Serial Pin Multiplexed Modes .........................................................543
16.1 Features.............................................................................................................................. 543
16.2 Input/Output Pins............................................................................................................... 544
16.3 Register Descriptions ......................................................................................................... 545
16.3.1 Serial Multiplexed Mode Register 0 (SMR0) ....................................................... 545
16.3.2 Serial Multiplexed Mode Register 1 (SMR1) ....................................................... 546
16.4 Operation of Serial Pin Multiplexed Modes ...................................................................... 547
16.4.1 Serial Pin Multiplexed Mode 0
(Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])................................. 547
16.4.2 Serial Pin Multiplexed Mode 1
(SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])............................................... 548
16.4.3 Serial Pin Multiplexed Mode 2
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])............................................... 549
16.4.4 Serial Pin Multiplexed Mode 3
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])............................................... 550
16.4.5 Serial Pin Multiplexed Mode 4
(SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])............................................... 551
16.5 Serial Port Pin Configuration............................................................................................. 552
Section 17 Synchronous Serial Communication Unit (SSU) ............................ 553
17.1 Features.............................................................................................................................. 553
17.2 Input/Output Pins............................................................................................................... 555
17.3 Register Descriptions ......................................................................................................... 555
17.3.1 SS Control Register H (SSCRH) .......................................................................... 556
17.3.2 SS Control Register L (SSCRL) ........................................................................... 558
17.3.3 SS Mode Register (SSMR) ................................................................................... 559
17.3.4 SS Enable Register (SSER) .................................................................................. 560
17.3.5 SS Status Register (SSSR) .................................................................................... 561
17.3.6 SS Control Register 2 (SSCR2) ............................................................................ 563
Rev. 2.00 Aug. 20, 2008 Page xviii of xlviii
17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 564
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) .................................... 565
17.3.9 SS Shift Register (SSTRSR) ................................................................................. 565
17.4 Operation ........................................................................................................................... 566
17.4.1 Transfer Clock ...................................................................................................... 566
17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 566
17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 567
17.4.4 Communication Modes and Pin Functions ........................................................... 568
17.4.5 SSU Mode............................................................................................................. 570
17.4.6 SCS Pin Control and Conflict Error...................................................................... 578
17.4.7 Clock Synchronous Communication Mode .......................................................... 579
17.5 Interrupt Requests .............................................................................................................. 585
17.6 Usage Note......................................................................................................................... 585
17.6.1 Setting of Module Stop Mode............................................................................... 585
Section 18 I2C Bus Interface (IIC) .....................................................................587
18.1 Features.............................................................................................................................. 587
18.2 Input/Output Pins ............................................................................................................... 590
18.3 Register Descriptions ......................................................................................................... 591
2
18.3.1 I C Bus Data Register (ICDR) .............................................................................. 591
18.3.2 Slave Address Register (SAR) .............................................................................. 592
18.3.3 Second Slave Address Register (SARX) .............................................................. 593
2
18.3.4 I C Bus Mode Register (ICMR)............................................................................ 595
2
18.3.5 I C Bus Transfer Rate Select Register (IICX3)..................................................... 597
2
18.3.6 I C Bus Control Register (ICCR) .......................................................................... 600
2
18.3.7 I C Bus Status Register (ICSR)............................................................................. 609
2
18.3.8 I C Bus Extended Control Register (ICXR).......................................................... 613
2
18.3.9 I C SMBus Control Register (ICSMBCR)............................................................ 617
18.4 Operation ........................................................................................................................... 619
2
18.4.1 I C Bus Data Format ............................................................................................. 619
18.4.2 Initialization .......................................................................................................... 621
18.4.3 Master Transmit Operation ................................................................................... 621
18.4.4 Master Receive Operation..................................................................................... 625
18.4.5 Slave Receive Operation....................................................................................... 634
18.4.6 Slave Transmit Operation ..................................................................................... 642
18.4.7 IRIC Setting Timing and SCL Control ................................................................. 645
18.4.8 Operation Using the DTC ..................................................................................... 648
18.4.9 Noise Canceler ...................................................................................................... 650
18.4.10 Initialization of Internal State ............................................................................... 650
18.5 Interrupt Source ................................................................................................................. 652
Rev. 2.00 Aug. 20, 2008 Page xix of xlviii
18.6 Usage Notes ....................................................................................................................... 653
Section 19 LPC Interface (LPC)........................................................................665
19.1 Features.............................................................................................................................. 665
19.2 Input/Output Pins............................................................................................................... 668
19.3 Register Descriptions ......................................................................................................... 669
19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 671
19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 679
19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 682
19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 683
19.3.5 Pin Function Control Register (PINFNCR) .......................................................... 684
19.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)..................... 684
19.3.7 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................. 686
19.3.8 Input Data Registers 1 to 3 (IDR1 to IDR3) ......................................................... 689
19.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3) ................................................... 689
19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 690
19.3.11 Status Registers 1 to 3 (STR1 to STR3) ............................................................... 691
19.3.12 SERIRQ Control Register 0 (SIRQCR0).............................................................. 699
19.3.13 SERIRQ Control Register 1 (SIRQCR1).............................................................. 703
19.3.14 SERIRQ Control Register 2 (SIRQCR2).............................................................. 707
19.3.15 SERIRQ Control Register 3 (SIRQCR3).............................................................. 708
19.3.16 SERIRQ Control Register 4 (SIRQCR4).............................................................. 709
19.3.17 SERIRQ Control Register 5 (SIRQCR5).............................................................. 710
19.3.18 Host Interface Select Register (HISEL)................................................................ 711
19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 712
19.3.20 SMIC Flag Register (SMICFLG) ......................................................................... 713
19.3.21 SMIC Control Status Register (SMICCSR).......................................................... 714
19.3.22 SMIC Data Register (SMICDTR) ........................................................................ 714
19.3.23 SMIC Interrupt Register 0 (SMICIR0) ................................................................. 715
19.3.24 SMIC Interrupt Register 1 (SMICIR1) ................................................................. 717
19.3.25 BT Status Register 0 (BTSR0).............................................................................. 718
19.3.26 BT Status Register 1 (BTSR1).............................................................................. 721
19.3.27 BT Control Status Register 0 (BTCSR0) .............................................................. 724
19.3.28 BT Control Status Register 1 (BTCSR1) .............................................................. 725
19.3.29 BT Control Register (BTCR)................................................................................ 727
19.3.30 BT Data Buffer (BTDTR)..................................................................................... 730
19.3.31 BT Interrupt Mask Register (BTIMSR)................................................................ 730
19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0) ........................................................ 732
19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1) ........................................................ 732
Rev. 2.00 Aug. 20, 2008 Page xx of xlviii
19.4 Operation ........................................................................................................................... 733
19.4.1 LPC interface Activation ...................................................................................... 733
19.4.2 LPC I/O Cycles ..................................................................................................... 733
19.4.3 SMIC Mode Transfer Flow................................................................................... 735
19.4.4 BT Mode Transfer Flow ....................................................................................... 738
19.4.5 Gate A20 ............................................................................................................... 740
19.4.6 LPC Interface Shutdown Function (LPCPD)........................................................ 743
19.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ)...................................... 747
19.4.8 LPC Interface Clock Start Request ....................................................................... 749
19.4.9 SCIF Control from LPC Interface......................................................................... 749
19.5 Interrupt Sources................................................................................................................ 750
19.5.1 IBFI1, IBFI2, IBFI3, and ERRI ............................................................................ 750
19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 751
19.6 Usage Note......................................................................................................................... 754
19.6.1 Data Conflict......................................................................................................... 754
Section 20 Ethernet Controller (EtherC)............................................................757
20.1 Features.............................................................................................................................. 757
20.2 Input/Output Pins ............................................................................................................... 759
20.3 Register Description........................................................................................................... 760
20.3.1 EtherC Mode Register (ECMR)............................................................................ 761
20.3.2 EtherC Status Register (ECSR)............................................................................. 764
20.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 766
20.3.4 PHY Interface Register (PIR) ............................................................................... 767
20.3.5 MAC Address High Register (MAHR)................................................................. 768
20.3.6 MAC Address Low Register (MALR).................................................................. 768
20.3.7 Receive Frame Length Register (RFLR) .............................................................. 769
20.3.8 PHY Status Register (PSR)................................................................................... 770
20.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 770
20.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 771
20.3.11 Lost Carrier Counter Register (LCCR) ................................................................. 771
20.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 771
20.3.13 CRC Error Frame Counter Register (CEFCR)...................................................... 772
20.3.14 Frame Receive Error Counter Register (FRECR)................................................. 772
20.3.15 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 772
20.3.16 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 773
20.3.17 Residual-Bit Frame Counter Register (RFCR) ..................................................... 773
20.3.18 Multicast Address Frame Counter Register (MAFCR)......................................... 773
20.3.19 IPG Register (IPGR) ............................................................................................. 774
Rev. 2.00 Aug. 20, 2008 Page xxi of xlviii
20.3.20 Automatic PAUSE Frame Set Register (APR) ..................................................... 774
20.3.21 Manual PAUSE Frame Set Register (MPR) ......................................................... 775
20.3.22 Automatic PAUSE Frame Retransmission Count Set Register (TPAUSER) ....... 775
20.4 Operation ........................................................................................................................... 776
20.4.1 Transmission......................................................................................................... 776
20.4.2 Reception .............................................................................................................. 779
20.4.3 RMII Frame Timing.............................................................................................. 780
20.4.4 Accessing MII Registers ....................................................................................... 782
20.4.5 Magic Packet Detection ........................................................................................ 785
20.4.6 Operation by IPG Setting...................................................................................... 786
20.4.7 Flow Control......................................................................................................... 786
20.5 Usage Notes ....................................................................................................................... 788
20.5.1 Conditions for Setting LCHNG Bit ...................................................................... 788
20.5.2 Flow Control Defect 1 .......................................................................................... 788
20.5.3 Flow Control Defect 2 .......................................................................................... 788
20.5.4 Operation Seed...................................................................................................... 789
Section 21 Ethernet Controller Direct Memory Access Controller
(E-DMAC).......................................................................................791
21.1 Features.............................................................................................................................. 791
21.2 Register Descriptions ......................................................................................................... 792
21.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 794
21.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 795
21.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 796
21.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 797
21.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 797
21.2.6 EtherC/E-DMAC Status Register (EESR) ............................................................ 798
21.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ....................... 803
21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 806
21.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 806
21.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 807
21.2.11 FIFO Depth Register (FDR) ................................................................................. 809
21.2.12 Receiving method Control Register (RMCR)....................................................... 810
21.2.13 Receiving-Buffer Write Address Register (RBWAR) .......................................... 810
21.2.14 Receiving-Descriptor Fetch Address Register (RDFAR) ..................................... 811
21.2.15 Transmission-Buffer Read Address Register (TBRAR) ....................................... 811
21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR) ................................ 811
21.2.17 Flow Control FIFO Threshold Register (FCFTR) ................................................ 812
21.2.18 Bit Rate Setting Register (ECBRR) ...................................................................... 813
21.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 814
Rev. 2.00 Aug. 20, 2008 Page xxii of xlviii
21.3 Operation ........................................................................................................................... 815
21.3.1 Descriptor List and Data Buffers .......................................................................... 815
21.3.2 Transmission......................................................................................................... 825
21.3.3 Reception .............................................................................................................. 827
21.3.4 Multi-Buffer Frame Transmit/Receive Processing ............................................... 829
Section 22 USB Function Module (USB)..........................................................831
22.1 Features.............................................................................................................................. 831
22.2 Input/Output Pins ............................................................................................................... 832
22.3 Register Descriptions ......................................................................................................... 833
22.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 834
22.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 836
22.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 837
22.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 838
22.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 839
22.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 839
22.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 840
22.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 840
22.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 841
22.3.10 EP0i Data Register (EPDR0i) ............................................................................... 841
22.3.11 EP0o Data Register (EPDR0o) ............................................................................. 842
22.3.12 EP0s Data Register (EPDR0s) .............................................................................. 842
22.3.13 EP1 Data Register (EPDR1) ................................................................................. 843
22.3.14 EP2 Data Register (EPDR2) ................................................................................. 843
22.3.15 EP3 Data Register (EPDR3) ................................................................................. 843
22.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 844
22.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 844
22.3.18 Trigger Register (TRG)......................................................................................... 844
22.3.19 Data Status Register (DASTS).............................................................................. 846
22.3.20 FIFO Clear Register (FCLR) ................................................................................ 847
22.3.21 DTC Transfer Setting Register (DMA) ................................................................ 848
22.3.22 Endpoint Stall Register (EPSTL).......................................................................... 851
22.3.23 Configuration Value Register (CVR) ................................................................... 852
22.3.24 Control Register (CTLR) ...................................................................................... 852
22.3.25 Endpoint Information Register (EPIR) ................................................................. 854
22.3.26 Transceiver Test Register 0 (TRNTREG0)........................................................... 858
22.3.27 Transceiver Test Register 1 (TRNTREG1)........................................................... 859
22.4 Interrupt Sources................................................................................................................ 861
22.5 Operation ........................................................................................................................... 863
22.5.1 Operation at Cable Connection ............................................................................. 863
Rev. 2.00 Aug. 20, 2008 Page xxiii of xlviii
22.6
22.7
22.8
22.9
22.10
22.5.2 Operation at Cable Disconnection ........................................................................ 864
22.5.3 Suspend and Resume Operations.......................................................................... 865
22.5.4 Control Transfer.................................................................................................... 870
22.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 876
22.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 877
22.5.7 EP3 Interrupt-In Transfer...................................................................................... 879
Processing of USB Standard Commands and Class/Vendor Commands .......................... 880
22.6.1 Processing of Commands Transmitted by Control Transfer................................. 880
Stall Operations.................................................................................................................. 881
22.7.1 Overview .............................................................................................................. 881
22.7.2 Forcible Stall by Application ................................................................................ 881
22.7.3 Automatic Stall by USB Function Module ........................................................... 883
DTC Transfer..................................................................................................................... 884
22.8.1 Overview .............................................................................................................. 884
22.8.2 DTC Transfer for Endpoint 1................................................................................ 885
22.8.3 DTC Transfer for Endpoint 2................................................................................ 886
22.8.4 DTC Transfer End Interrupt.................................................................................. 887
Example of USB External Circuitry .................................................................................. 888
Usage Notes ....................................................................................................................... 890
22.10.1 Receiving Setup Data............................................................................................ 890
22.10.2 Clearing the FIFO ................................................................................................. 890
22.10.3 Overreading and Overwriting the Data Registers ................................................. 890
22.10.4 Assigning Interrupt Sources to EP0 ...................................................................... 891
22.10.5 Clearing the FIFO When DTC Transfer is Enabled.............................................. 891
22.10.6 Notes on TR Interrupt ........................................................................................... 891
22.10.7 Restrictions on Peripheral Module Clock (φ) Operating Frequency..................... 892
Section 23 A/D Converter .................................................................................893
23.1 Features.............................................................................................................................. 893
23.2 Input/Output Pins............................................................................................................... 895
23.3 Register Descriptions ......................................................................................................... 896
23.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 896
23.3.2 A/D Control/Status Register (ADCSR) ................................................................ 897
23.3.3 A/D Control Register (ADCR) ............................................................................. 899
23.4 Operation ........................................................................................................................... 900
23.4.1 Single Mode.......................................................................................................... 900
23.4.2 Scan Mode ............................................................................................................ 901
23.4.3 Input Sampling and A/D Conversion Time .......................................................... 903
23.4.4 Timing of External Trigger Input ......................................................................... 906
23.5 Interrupt Source ................................................................................................................. 907
Rev. 2.00 Aug. 20, 2008 Page xxiv of xlviii
23.6 A/D Conversion Accuracy Definitions .............................................................................. 907
23.7 Usage Notes ....................................................................................................................... 909
23.7.1 Setting of Module Stop Mode............................................................................... 909
23.7.2 Permissible Signal Source Impedance .................................................................. 909
23.7.3 Influences on Absolute Accuracy ......................................................................... 910
23.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 910
23.7.5 Notes on Board Design ......................................................................................... 910
23.7.6 Notes on Noise Countermeasures ......................................................................... 911
23.7.7 Note on the Usage in Software Standby Mode ..................................................... 912
Section 24 RAM ................................................................................................913
Section 25 Flash Memory ..................................................................................915
25.1 Features.............................................................................................................................. 915
25.1.1 Operating Mode .................................................................................................... 917
25.1.2 Mode Comparison................................................................................................. 918
25.1.3 Flash Memory MAT Configuration ...................................................................... 919
25.1.4 Block Division ...................................................................................................... 919
25.1.5 Programming/Erasing Interface ............................................................................ 921
25.2 Input/Output Pins ............................................................................................................... 923
25.3 Register Descriptions ......................................................................................................... 924
25.3.1 Programming/Erasing Interface Register .............................................................. 926
25.3.2 Programming/Erasing Interface Parameter ........................................................... 934
25.4 On-Board Programming Mode .......................................................................................... 945
25.4.1 Boot Mode ............................................................................................................ 946
25.4.2 USB Boot Mode.................................................................................................... 950
25.4.3 User Program Mode.............................................................................................. 954
25.4.4 User Boot Mode.................................................................................................... 965
25.4.5 Procedure Program and Storable Area for Programming Data............................. 970
25.5 Protection ........................................................................................................................... 980
25.5.1 Hardware Protection ............................................................................................. 980
25.5.2 Software Protection............................................................................................... 982
25.5.3 Error Protection..................................................................................................... 982
25.6 Switching between User MAT and User Boot MAT ......................................................... 984
25.7 Programmer Mode ............................................................................................................. 985
25.8 Serial Communication Interface Specification for Boot Mode.......................................... 986
25.9 Usage Notes ..................................................................................................................... 1014
Section 26 Boundary Scan (JTAG)..................................................................1017
26.1 Features............................................................................................................................ 1017
Rev. 2.00 Aug. 20, 2008 Page xxv of xlviii
26.2 Input/Output Pins............................................................................................................. 1019
26.3 Register Descriptions ....................................................................................................... 1020
26.3.1 Instruction Register (SDIR) ................................................................................ 1021
26.3.2 Bypass Register (SDBPR) .................................................................................. 1022
26.3.3 Boundary Scan Register (SDBSR) ..................................................................... 1022
26.3.4 ID Code Register (SDIDR)................................................................................. 1040
26.4 Operation ......................................................................................................................... 1041
26.4.1 TAP Controller State Transitions........................................................................ 1041
26.4.2 JTAG Reset......................................................................................................... 1042
26.5 Boundary Scan................................................................................................................. 1042
26.5.1 Supported Instructions ........................................................................................ 1042
26.6 Usage Notes ..................................................................................................................... 1045
Section 27 Clock Pulse Generator...................................................................1049
27.1 Oscillator.......................................................................................................................... 1050
27.1.1 Connecting Crystal Resonator ............................................................................ 1050
27.1.2 External Clock Input Method.............................................................................. 1051
27.2 PLL Multiplier Circuit ..................................................................................................... 1052
27.3 Medium-Speed Clock Divider ......................................................................................... 1052
27.4 Bus Master Clock Select Circuit...................................................................................... 1052
27.5 Subclock Input Circuit ..................................................................................................... 1052
27.6 Subclock Waveform Shaping Circuit .............................................................................. 1052
27.7 Clock Select Circuit ......................................................................................................... 1053
27.8 Usage Notes ..................................................................................................................... 1054
27.8.1 Note on Resonator .............................................................................................. 1054
27.8.2 Notes on Board Design ....................................................................................... 1054
27.8.3 Note on Operation Check ................................................................................... 1054
Section 28 Power-Down Modes ......................................................................1055
28.1 Register Descriptions ....................................................................................................... 1056
28.1.1 Standby Control Register (SBYCR) ................................................................... 1056
28.1.2 Low-Power Control Register (LPWRCR) .......................................................... 1059
28.1.3 Module Stop Control Registers H, L, and A
(MSTPCRH, MSTPCRL, MSTPCRA) .............................................................. 1060
28.1.4 Sub-Chip Module Stop Control Registers BH, BL
(SUBMSTPBH, SUBMSTPBL)......................................................................... 1062
28.2 Mode Transitions and LSI States ..................................................................................... 1063
28.3 Medium-Speed Mode....................................................................................................... 1065
28.4 Sleep Mode ...................................................................................................................... 1066
28.5 Software Standby Mode................................................................................................... 1067
Rev. 2.00 Aug. 20, 2008 Page xxvi of xlviii
28.6 Hardware Standby Mode ................................................................................................. 1069
28.7 Module Stop Mode .......................................................................................................... 1070
28.8 Usage Notes ..................................................................................................................... 1070
28.8.1 I/O Port Status..................................................................................................... 1070
28.8.2 Current Consumption when Waiting for Oscillation Settling ............................. 1070
28.8.3 DTC Module Stop Mode .................................................................................... 1070
28.8.4 Notes on Subclock Usage ................................................................................... 1070
Section 29 List of Registers .............................................................................1071
29.1 Register Addresses (Address Order)................................................................................ 1072
29.2 Register Bits..................................................................................................................... 1086
29.3 Register States in Each Operating Mode.......................................................................... 1104
Section 30 Platform Environment Control Interface (PECI)...........................1117
Section 31 Electrical Characteristics ...............................................................1119
31.1 Absolute Maximum Ratings ............................................................................................ 1119
31.2 DC Characteristics ........................................................................................................... 1120
31.3 AC Characteristics ........................................................................................................... 1125
31.3.1 Clock Timing ...................................................................................................... 1125
31.3.2 Control Signal Timing ........................................................................................ 1130
31.3.3 Bus Timing ......................................................................................................... 1132
31.3.4 Multiplex Bus Timing......................................................................................... 1141
31.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1144
31.4 A/D Conversion Characteristics....................................................................................... 1161
31.5 Flash Memory Characteristics ......................................................................................... 1162
31.6 Usage Notes ..................................................................................................................... 1163
Appendix
A.
B.
C.
........................................................................................................1165
I/O Port States in Each Processing State.......................................................................... 1165
Product Lineup................................................................................................................. 1168
Package Dimensions ........................................................................................................ 1169
Main Revisions and Additions in this Edition ...................................................1173
Index
........................................................................................................1191
Rev. 2.00 Aug. 20, 2008 Page xxvii of xlviii
Rev. 2.00 Aug. 20, 2008 Page xxviii of xlviii
Figures
Section 1
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Overview
Internal Block Diagram ................................................................................................ 3
Pin Assignments (H8S/2472 Group) ............................................................................ 4
Pin Assignments (H8S/2463 Group) ............................................................................ 5
Pin Assignments (H8S/2462 Group) ............................................................................ 6
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode).................................................................... 29
Figure 2.2 Stack Structure in Normal Mode................................................................................ 29
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................ 30
Figure 2.4 Stack Structure in Advanced Mode............................................................................ 31
Figure 2.5 Memory Map.............................................................................................................. 32
Figure 2.6 CPU Registers ............................................................................................................ 33
Figure 2.7 Usage of General Registers ........................................................................................ 34
Figure 2.8 Stack........................................................................................................................... 35
Figure 2.9 General Register Data Formats (1)............................................................................. 38
Figure 2.9 General Register Data Formats (2)............................................................................. 39
Figure 2.10 Memory Data Formats ............................................................................................. 40
Figure 2.11 Instruction Formats (Examples) ............................................................................... 52
Figure 2.12 Branch Address Specification in Memory Indirect Mode........................................ 56
Figure 2.13 State Transitions....................................................................................................... 60
Section 3 MCU Operating Modes
Figure 3.1 Address Map .............................................................................................................. 69
Section 4
Figure 4.1
Figure 4.2
Figure 4.3
Exception Handling
Reset Sequence........................................................................................................... 75
Stack Status after Exception Handling ....................................................................... 77
Operation When SP Value is Odd .............................................................................. 78
Section 5
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Interrupt Controller
Block Diagram of Interrupt Controller....................................................................... 80
Block Diagram of Interrupts IRQ15 to IRQ0............................................................. 89
Block Diagram of Interrupt Control Operation .......................................................... 93
Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 ..... 96
State Transition in Interrupt Control Mode 1 ............................................................. 97
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.... 99
Interrupt Exception Handling................................................................................... 100
Interrupt Control for DTC ........................................................................................ 102
Rev. 2.00 Aug. 20, 2008 Page xxix of xlviii
Figure 5.9 Conflict between Interrupt Generation and Disabling.............................................. 104
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller............................................................................. 109
Figure 6.2 IOS Signal Output Timing ....................................................................................... 126
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space) ............................. 127
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ........................... 128
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................ 131
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................ 132
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access).......................... 133
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ........................... 134
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ................................. 135
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)........................ 136
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ......................... 137
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ............................... 138
Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)........................................... 139
Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0) ............................................ 140
Figure 6.15 Glueless Extension Word Access (ADMXE = 0) .................................................. 141
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space .......................................................... 142
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space .......................................................... 143
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space .......................................................... 143
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) .................. 144
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) .................. 145
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) ................... 145
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) ................... 146
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access).......................... 147
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access).......................... 147
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) .................. 148
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) ................... 149
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access).......................... 149
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode) .................................... 151
Figure 6.29 Example of Wait State Insertion Timing................................................................ 153
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)................... 154
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)................... 155
Figure 6.32 Examples of Idle Cycle Operation ......................................................................... 156
Section 7
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Data Transfer Controller (DTC)
Block Diagram of DTC ............................................................................................ 162
Block Diagram of DTC Activation Source Control ................................................. 174
DTC Register Information Location in Address Space ............................................ 175
DTC Operation Flowchart........................................................................................ 177
Rev. 2.00 Aug. 20, 2008 Page xxx of xlviii
Figure 7.5 Memory Mapping in Normal Mode ......................................................................... 178
Figure 7.6 Memory Mapping in Repeat Mode .......................................................................... 179
Figure 7.7 Memory Mapping in Block Transfer Mode ............................................................. 180
Figure 7.8 Chain Transfer Operation......................................................................................... 181
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) .................... 182
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2).............................................................................................. 183
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ........................................... 183
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit ............................................................................................. 205
Figure 8.2 Noise Canceler Operation ........................................................................................ 206
Figure 8.3 Noise Canceler Circuit ............................................................................................. 212
Figure 8.4 Noise Canceler Operation ........................................................................................ 212
Figure 8.5 Noise Canceler Circuit ............................................................................................. 251
Figure 8.6 Noise Canceler Operation ........................................................................................ 252
Figure 8.7 Noise Canceler Circuit ............................................................................................. 288
Figure 8.8 Noise Canceler Operation ........................................................................................ 289
Figure 8.9 Noise Canceler Circuit ............................................................................................. 295
Figure 8.10 Noise Canceler Operation ...................................................................................... 295
Figure 8.11 Noise Canceler Circuit ........................................................................................... 335
Figure 8.12 Noise Canceler Operation ...................................................................................... 336
Section 9
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
14-Bit PWM Timer (PWMX)
PWMX (D/A) Block Diagram ................................................................................. 359
PWMX (D/A) Operation .......................................................................................... 367
Output Waveform (OS = 0, DADR corresponds to TL) ........................................... 370
Output Waveform (OS = 1, DADR corresponds to TH) ........................................... 371
D/A Data Register Configuration when CFS = 1 ..................................................... 371
Output Waveform when DADR = H'0207 (OS = 1) ................................................ 372
Section 10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
16-Bit Free-Running Timer (FRT)
Block Diagram of 16-Bit Free-Running Timer ...................................................... 376
Increment Timing with Internal Clock Source ....................................................... 383
Timing of Output Compare A Output .................................................................... 383
Clearing of FRC by Compare-Match A Signal ...................................................... 384
Timing of Output Compare Flag (OCFA or OCFB) Setting .................................. 384
Timing of Overflow Flag (OVF) Setting................................................................ 385
OCRA Automatic Addition Timing ....................................................................... 386
Conflict between FRC Write and Clear.................................................................. 387
Conflict between FRC Write and Increment .......................................................... 388
Rev. 2.00 Aug. 20, 2008 Page xxxi of xlviii
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used).............................................. 389
Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)..................................................... 390
Section 11
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
8-Bit Timer (TMR)
Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)........................................... 394
Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ......................................... 395
Count Timing for Internal Clock Input................................................................... 406
Timing of CMF Setting at Compare-Match ........................................................... 406
Timing of Counter Clear by Compare-Match ........................................................ 407
Timing of OVF Flag Setting .................................................................................. 407
Conflict between TCNT Write and Counter Clear ................................................. 410
Conflict between TCNT Write and Increment ....................................................... 411
Conflict between TCOR Write and Compare-Match ............................................. 412
Section 12
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Watchdog Timer (WDT)
Block Diagram of WDT ......................................................................................... 416
Watchdog Timer Mode (RST/NMI = 1) Operation................................................ 423
Interval Timer Mode Operation.............................................................................. 424
OVF Flag Set Timing ............................................................................................. 424
Output Timing of RESO signal .............................................................................. 425
Writing to TCNT and TCSR (WDT_0).................................................................. 427
Conflict between TCNT Write and Increment ....................................................... 428
Sample Circuit for Resetting the System by the RESO Signal............................... 429
Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI_1 and SCI_3 ...................................................................... 433
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 451
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 453
Figure 13.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)............................................................................................ 454
Figure 13.5 Sample SCI Initialization Flowchart ...................................................................... 455
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 456
Figure 13.7 Sample Serial Transmission Flowchart .................................................................. 457
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 458
Figure 13.9 Sample Serial Reception Flowchart (1).................................................................. 460
Figure 13.9 Sample Serial Reception Flowchart (2).................................................................. 461
Rev. 2.00 Aug. 20, 2008 Page xxxii of xlviii
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ......................................... 463
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ....................................... 464
Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)........................................................................ 465
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)....................................... 466
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)....................................... 467
Figure 13.14 Data Format in Synchronous Communication (LSB-First).................................. 468
Figure 13.15 Sample SCI Initialization Flowchart .................................................................... 469
Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode..................... 471
Figure 13.17 Sample Serial Transmission Flowchart ................................................................ 472
Figure 13.18 Example of SCI Receive Operation in Clock Synchronous Mode ....................... 473
Figure 13.19 Sample Serial Reception Flowchart ..................................................................... 474
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ............. 476
Figure 13.21 Pin Connection for Smart Card Interface ............................................................. 477
Figure 13.22 Data Formats in Normal Smart Card Interface Mode .......................................... 478
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ..................................................... 478
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1) ................................................... 478
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate) ............................................ 481
Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode....................................... 483
Figure 13.27 TEND Flag Set Timings during Transmission ..................................................... 483
Figure 13.28 Sample Transmission Flowchart .......................................................................... 484
Figure 13.29 Data Re-transfer Operation in SCI Reception Mode............................................ 485
Figure 13.30 Sample Reception Flowchart................................................................................ 486
Figure 13.31 Clock Output Fixing Timing ................................................................................ 487
Figure 13.32 Clock Stop and Restart Procedure........................................................................ 488
Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode .......................... 492
Figure 13.34 Sample Flowchart for Mode Transition during Transmission.............................. 494
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ........... 494
Figure 13.36 Pin States during Transmission in Clock Synchronous Mode
(Internal Clock) .................................................................................................... 495
Figure 13.37 Sample Flowchart for Mode Transition during Reception ................................... 496
Figure 13.38 Switching from SCK Pins to Port Pins................................................................. 497
Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins......... 498
Section 14
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
CRC Operation Circuit (CRC)
Block Diagram of CRC Operation Circuit ............................................................. 499
LSB-First Data Transmission ................................................................................. 501
MSB-First Data Transmission................................................................................ 502
LSB-First Data Reception ...................................................................................... 503
Rev. 2.00 Aug. 20, 2008 Page xxxiii of xlviii
Figure 14.5 MSB-First Data Reception ..................................................................................... 504
Figure 14.6 LSB-First and MSB-First Transmit Data ............................................................... 505
Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.1 Block Diagram of SCIF.......................................................................................... 508
Figure 15.2 Data Format in Serial Transmission/Reception
(Example with 8-Bit Data, Parity and 2 Stop Bits) ................................................ 529
Figure 15.3 Example of Initialization Flowchart ....................................................................... 530
Figure 15.4 Example of Data Transmission Flowchart ............................................................. 531
Figure 15.5 Example of Data Reception Flowchart................................................................... 532
Figure 15.6 Example of Initialization Flowchart ....................................................................... 533
Figure 15.7 Example of Data Transmission/Reception Standby Flowchart .............................. 534
Figure 15.8 Example of Data Transmission Flowchart ............................................................. 535
Figure 15.9 Example of Data Transmission Suspension Flowchart .......................................... 536
Figure 15.10 Example of Data Reception Flowchart................................................................. 537
Figure 15.11 Example of Data Reception Suspension Flowchart.............................................. 538
Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Serial Pin Multiplexed Modes
Serial Pin Multiplexed Mode 0............................................................................... 547
Serial Pin Multiplexed Mode 1............................................................................... 548
Serial Pin Multiplexed Mode 2............................................................................... 549
Serial Pin Multiplexed Mode 3............................................................................... 550
Serial Pin Multiplexed Mode 4............................................................................... 551
Section 17 Synchronous Serial Communication Unit (SSU)
Figure 17.1 Block Diagram of SSU........................................................................................... 554
Figure 17.2 Relationship of Clock Phase, Polarity, and Data.................................................... 566
Figure 17.3 Relationship between Data Input/Output Pins and the Shift Register .................... 567
Figure 17.4 Example of Initial Settings in SSU Mode .............................................................. 570
Figure 17.5 Example of Transmission Operation (SSU Mode)................................................. 572
Figure 17.6 Flowchart Example of Data Transmission (SSU Mode) ........................................ 573
Figure 17.7 Example of Reception Operation (SSU Mode) ...................................................... 575
Figure 17.8 Flowchart Example of Data Reception (SSU Mode) ............................................. 576
Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)......... 577
Figure 17.10 Conflict Error Detection Timing (Before Transfer) ............................................. 578
Figure 17.11 Conflict Error Detection Timing (After Transfer End) ........................................ 578
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode .......... 579
Figure 17.13 Example of Transmission Operation (Clock Synchronous
Communication Mode)......................................................................................... 580
Figure 17.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)....................................................... 581
Rev. 2.00 Aug. 20, 2008 Page xxxiv of xlviii
Figure 17.15 Example of Reception Operation (Clock Synchronous
Communication Mode)......................................................................................... 582
Figure 17.16 Flowchart Example of Data Reception (Clock Synchronous
Communication Mode) ........................................................................................ 583
Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)....................................................... 584
I2C Bus Interface (IIC)
Block Diagram of I2C Bus Interface ...................................................................... 588
I2C Bus Interface Connections (Example: This LSI as Master) ............................. 589
I2C Bus Data Formats (I2C Bus Formats)............................................................... 619
I2C Bus Data Formats (Serial Formats) .................................................................. 619
I2C Bus Timing....................................................................................................... 620
Sample Flowchart for IIC Initialization ................................................................. 621
Sample Flowchart for Operations in Master Transmit Mode ................................. 622
Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0).......... 624
Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)................................................................................................ 625
Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............ 626
Figure 18.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1) ........................................................................... 628
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) ........................................................................... 628
Figure 18.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1) ................................................................ 629
Figure 18.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1)................................................................... 630
Figure 18.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)........................................................................... 633
Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)........................................................................... 633
Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) .............. 635
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)....... 637
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 637
Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) .............. 638
Figure 18.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0).......................................................................... 640
Figure 18.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0) .......................................................................... 641
Figure 18.23 Sample Flowchart for Slave Transmit Mode........................................................ 642
Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0)............................. 644
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Figure 18.6
Figure 18.7
Figure 18.8
Figure 18.9
Rev. 2.00 Aug. 20, 2008 Page xxxv of xlviii
Figure 18.25
Figure 18.26
Figure 18.27
Figure 18.28
Figure 18.29
Figure 18.30
Figure 18.31
Figure 18.32
Figure 18.33
Figure 18.34
Figure 18.35
IRIC Setting Timing and SCL Control (1) ........................................................... 645
IRIC Setting Timing and SCL Control (2) ........................................................... 646
IRIC Setting Timing and SCL Control (3) ........................................................... 647
Block Diagram of Noise Canceler........................................................................ 650
Notes on Reading Master Receive Data ............................................................... 658
Flowchart for Start Condition Issuance Instruction
for Retransmission and Timing ............................................................................ 659
Stop Condition Issuance Timing .......................................................................... 660
IRIC Flag Clearing Timing When WAIT = 1 ...................................................... 661
ICDR Register Read and ICCR Register Access Timing in
Slave Transmit Mode ........................................................................................... 662
TRS Bit Set Timing in Slave Mode...................................................................... 663
Diagram of Erroneous Operation when Arbitration Lost ..................................... 665
Section 19 LPC Interface (LPC)
Figure 19.1 Block Diagram of LPC........................................................................................... 669
Figure 19.2 Typical LFRAME Timing...................................................................................... 737
Figure 19.3 Abort Mechanism ................................................................................................... 737
Figure 19.4 SMIC Write Transfer Flow .................................................................................... 738
Figure 19.5 SMIC Read Transfer Flow ..................................................................................... 739
Figure 19.6 BT Write Transfer Flow ......................................................................................... 740
Figure 19.7 BT Read Transfer Flow.......................................................................................... 741
Figure 19.8 GA20 Output .......................................................................................................... 743
Figure 19.9 Power-Down State Termination Timing ................................................................ 748
Figure 19.10 SERIRQ Timing ................................................................................................... 749
Figure 19.11 Clock Start Request Timing ................................................................................. 751
Figure 19.12 HIRQ Flowchart (Example of Channel 1)............................................................ 755
Section 20 LPC Interface (LPC)
Figure 20.1 Configuration of EtherC......................................................................................... 760
Figure 20.2 EtherC Transmitter State Transitions ..................................................................... 779
Figure 20.3 EtherC Receiver State Transmissions .................................................................... 781
Figure 20.4 RMII Frame Transmit Timing (Normal Transmission).......................................... 782
Figure 20.5 RMII Frame Receive Timing (Normal Reception) ................................................ 782
Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier) ................................ 783
Figure 20.7 MII Management Frame Format ............................................................................ 784
Figure 20.8 1-Bit Data Write Flowchart .................................................................................... 785
Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7).............................................. 785
Figure 20.10 1-Bit Data Read Flowchart................................................................................... 786
Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7) .................. 786
Figure 20.12 Changing IPG and Transmission Efficiency ........................................................ 788
Rev. 2.00 Aug. 20, 2008 Page xxxvi of xlviii
Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Ethernet Controller Direct Memory Access Controller (E-DMAC)
Configuration of E-DMAC, and Descriptors and Buffers...................................... 794
Relationship between Transmit Descriptor and Transmit Buffer ........................... 818
Relationship between Receive Descriptor and Receive Buffer .............................. 822
Sample Transmission Flowchart ............................................................................ 828
Sample Reception Flowchart.................................................................................. 830
E-DMAC Operation after Transmit Error .............................................................. 831
E-DMAC Operation after Receive Error................................................................ 832
Section 22 USB Function Module (USB)
Figure 22.1 Block Diagram of USB .......................................................................................... 834
Figure 22.2 Operation at Cable Connection .............................................................................. 865
Figure 22.3 Operation at Cable Disconnection.......................................................................... 866
Figure 22.4 Suspend Operation ................................................................................................. 867
Figure 22.5 Resume Operation from Up-Stream....................................................................... 868
Figure 22.6 Flow of Transition to and Canceling Software Standby Mode .............................. 869
Figure 22.7 Timing of Transition to and Canceling Software Standby Mode........................... 870
Figure 22.8 Remote-Wakeup..................................................................................................... 871
Figure 22.9 Transfer Stages in Control Transfer ....................................................................... 872
Figure 22.10 Setup Stage Operation .......................................................................................... 873
Figure 22.11 Data Stage (Control-In) Operation ....................................................................... 874
Figure 22.12 Data Stage (Control-Out) Operation .................................................................... 875
Figure 22.13 Status Stage (Control-In) Operation ..................................................................... 876
Figure 22.14 Status Stage (Control-Out) Operation .................................................................. 877
Figure 22.15 EP1 Bulk-Out Transfer Operation........................................................................ 878
Figure 22.16 EP2 Bulk-In Transfer Operation .......................................................................... 879
Figure 22.17 Operation of EP3 Interrupt-In Transfer ................................................................ 881
Figure 22.18 Forcible Stall by Application ............................................................................... 884
Figure 22.19 Automatic Stall by USB Function Module........................................................... 885
Figure 22.20 RDFN Bit Operation for EP1 ............................................................................... 887
Figure 22.21 PKTE Bit Operation for EP2................................................................................ 888
Figure 22.22 Example of Circuitry in Self-Powered Mode ....................................................... 891
Figure 22.23 TR Interrupt Flag Set Timing ............................................................................... 893
Section 23 A/D Converter
Figure 23.1 Block Diagram of the A/D Converter .................................................................... 896
Figure 23.2 Example of A/D Converter Operation (When Channel 1 is
Selected in Single Mode) ....................................................................................... 903
Figure 23.3 Example of A/D Converter Operation (When Channels AN0 to AN3 are
Selected in Scan Mode).......................................................................................... 904
Figure 23.4 A/D Conversion Timing......................................................................................... 906
Rev. 2.00 Aug. 20, 2008 Page xxxvii of xlviii
Figure 23.5 Timing of External Trigger Input ........................................................................... 908
Figure 23.6 A/D Conversion Accuracy Definitions................................................................... 910
Figure 23.7 A/D Conversion Accuracy Definitions................................................................... 910
Figure 23.8 Example of Analog Input Circuit ........................................................................... 911
Figure 23.9 Example of Analog Input Protection Circuit .......................................................... 913
Figure 23.10 Analog Input Pin Equivalent Circuit .................................................................... 914
Section 25 Flash Memory
Figure 25.1 Block Diagram of Flash Memory........................................................................... 918
Figure 25.2 Mode Transition of Flash Memory......................................................................... 919
Figure 25.3 Flash Memory Configuration ................................................................................. 921
Figure 25.4 Block Division of User MAT ................................................................................. 922
Figure 25.5 Overview of User Procedure Program.................................................................... 923
Figure 25.6 System Configuration in Boot Mode...................................................................... 948
Figure 25.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................ 949
Figure 25.8 Overview of Boot Mode State Transition Diagram................................................ 951
Figure 25.9 System Configuration in USB Boot Mode ............................................................. 952
Figure 25.10 USB Boot Mode State Transition Diagram.......................................................... 954
Figure 25.11 Programming/Erasing Overview Flow................................................................. 956
Figure 25.12 RAM Map When Programming/Erasing is Executed .......................................... 957
Figure 25.13 Programming Procedure....................................................................................... 958
Figure 25.14 Erasing Procedure................................................................................................. 963
Figure 25.15 Repeating Procedure of Erasing and Programming.............................................. 965
Figure 25.16 Procedure for Programming User MAT in User Boot Mode ............................... 968
Figure 25.17 Procedure for Erasing User MAT in User Boot Mode ......................................... 970
Figure 25.18 Transitions to Error-Protection State.................................................................... 985
Figure 25.19 Switching between the User MAT and User Boot MAT...................................... 986
Figure 25.20 Boot Program States.............................................................................................989
Figure 25.21 Bit-Rate-Adjustment Sequence ............................................................................ 990
Figure 25.22 Communication Protocol Format ......................................................................... 991
Figure 25.23 New Bit-Rate Selection Sequence...................................................................... 1002
Figure 25.24 Programming Sequence...................................................................................... 1006
Figure 25.25 Erasure Sequence ............................................................................................... 1009
Section 26
Figure 26.1
Figure 26.2
Figure 26.3
Figure 26.4
Figure 26.5
Boundary Scan (JTAG)
JTAG Block Diagram........................................................................................... 1020
TAP Controller State Transitions ......................................................................... 1043
Reset Signal Circuit Without Reset Signal Interference....................................... 1047
Serial Data Input/Output (1)................................................................................. 1048
Serial Data Input/Output (2)................................................................................. 1049
Rev. 2.00 Aug. 20, 2008 Page xxxviii of xlviii
Section 27
Figure 27.1
Figure 27.2
Figure 27.3
Figure 27.4
Figure 27.5
Clock Pulse Generator
Block Diagram of Clock Pulse Generator ............................................................ 1051
Typical Connection to Crystal Resonator............................................................. 1052
Equivalent Circuit of Crystal Resonator............................................................... 1052
Example of External Clock Input ......................................................................... 1053
Note on Board Design of Oscillation Circuit Section .......................................... 1056
Section 28
Figure 28.1
Figure 28.2
Figure 28.3
Figure 28.4
Power-Down Modes
Mode Transition Diagram .................................................................................... 1065
Medium-Speed Mode Timing .............................................................................. 1068
Software Standby Mode Application Example .................................................... 1070
Hardware Standby Mode Timing ......................................................................... 1071
Section 31 Electrical Characteristics
Figure 31.1 Darlington Transistor Drive Circuit (Example).................................................... 1125
Figure 31.2 LED Drive Circuit (Example) .............................................................................. 1126
Figure 31.3 Output Load Circuit ............................................................................................. 1127
Figure 31.4 System Clock Timing........................................................................................... 1129
Figure 31.5 Oscillation Stabilization Timing .......................................................................... 1129
Figure 31.6 Oscillation Stabilization Timing (Exiting Software Standby Mode).................... 1129
Figure 31.7 External Clock Input Timing................................................................................ 1130
Figure 31.8 Timing of External Clock Output Stabilization Delay Time................................ 1130
Figure 31.9 Subclock Input Timing......................................................................................... 1131
Figure 31.10 Reset Input Timing............................................................................................. 1132
Figure 31.11 Interrupt Input Timing........................................................................................ 1133
Figure 31.12 Basic Bus Timing/2-State Access ...................................................................... 1135
Figure 31.13 Basic Bus Timing/3-State Access ...................................................................... 1136
Figure 31.14 Basic Bus Timing/3-State Access with One Wait State ..................................... 1137
Figure 31.15 Even Byte Access (ADMXE = 0) ...................................................................... 1138
Figure 31.16 Odd Byte Access (ADMXE = 0)........................................................................ 1139
Figure 31.17 Word Access (ADMXE = 0) .............................................................................. 1140
Figure 31.18 Burst ROM Access Timing/2-State Access........................................................ 1141
Figure 31.19 Burst ROM Access Timing/1-State Access........................................................ 1142
Figure 31.20 Multiplex Bus Timing/Data 2-State Access ....................................................... 1144
Figure 31.21 Multiplex Bus Timing/Data 3-State Access ....................................................... 1145
Figure 31.22 I/O Port Input/Output Timing............................................................................. 1149
Figure 31.23 PWMX Output Timing....................................................................................... 1149
Figure 31.24 SCK Clock Input Timing ................................................................................... 1149
Figure 31.25 SCI Input/Output Timing (Clock Synchronous Mode) ...................................... 1149
Figure 31.26 A/D Converter External Trigger Input Timing................................................... 1150
Figure 31.27 WDT Output Timing (RESO) ............................................................................ 1150
Rev. 2.00 Aug. 20, 2008 Page xxxix of xlviii
Figure 31.28
Figure 31.29
Figure 31.30
Figure 31.31
Figure 31.32
Figure 31.33
Figure 31.34
Figure 31.35
Figure 31.36
Figure 31.37
Figure 31.38
Figure 31.39
Figure 31.40
Figure 31.41
Figure 31.42
Figure 31.43
Figure 31.44
Figure 31.45
Figure 31.46
SSU Timing (Master, CPHS = 1) ....................................................................... 1150
SSU Timing (Master, CPHS = 0) ....................................................................... 1151
SSU Timing (Slave, CPHS = 1) ......................................................................... 1151
SSU Timing (Slave, CPHS = 0) ......................................................................... 1152
I2C Bus Interface Input/Output Timing .............................................................. 1154
LPC Interface (LPC) Timing.............................................................................. 1155
Timing of RM_REF-CLK and RMII Signals..................................................... 1156
RMII Transmit Timing ....................................................................................... 1157
RMII Receive Timing (Normal Operation)........................................................ 1157
RMII Receive Timing (When an Error is Detected) .......................................... 1157
MDIO Input Timing ........................................................................................... 1158
MDIO Output Timing ........................................................................................ 1158
WOL Output Timing .......................................................................................... 1158
Data Signal Timing ............................................................................................ 1160
Load Condition................................................................................................... 1160
JTAG ETCK Timing .......................................................................................... 1161
Reset Hold Timing ............................................................................................. 1162
JTAG Input/Output Timing................................................................................ 1162
Connecting Capacitors to VCC and VCL Pins................................................... 1165
Appendix
Figure C.1 Package Dimensions (PLBGA0176GA-A) ........................................................... 1171
Figure C.2 Package Dimensions (PLQP0144KA-A)............................................................... 1172
Figure C.3 Package Dimensions (PTQP0144LC-A) ............................................................... 1173
Rev. 2.00 Aug. 20, 2008 Page xl of xlviii
Tables
Section 1 Overview
Table 1.1 Pin Assignments in Each Operating Mode..................................................................... 7
Table 1.2 Pin Functions................................................................................................................ 14
Section 2
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.13
CPU
Instruction Classification ............................................................................................. 41
Operation Notation....................................................................................................... 42
Data Transfer Instructions............................................................................................ 43
Arithmetic Operations Instructions (1)......................................................................... 44
Arithmetic Operations Instructions (2)......................................................................... 45
Logic Operations Instructions ...................................................................................... 46
Shift Instructions .......................................................................................................... 46
Bit Manipulation Instructions (1) ................................................................................. 47
Bit Manipulation Instructions (2) ................................................................................. 48
Branch Instructions ...................................................................................................... 49
System Control Instructions ......................................................................................... 50
Block Data Transfer Instructions ............................................................................... 51
Addressing Modes...................................................................................................... 53
Absolute Address Access Ranges .............................................................................. 55
Effective Address Calculation (1) .............................................................................. 57
Effective Address Calculation (2) .............................................................................. 58
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection.................................................................................. 63
Section 4
Table 4.1
Table 4.2
Table 4.3
Exception Handling
Exception Types and Priority....................................................................................... 71
Exception Handling Vector Table................................................................................ 72
Status of CCR after Trap Instruction Exception Handling........................................... 76
Section 5
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Interrupt Controller
Pin Configuration ......................................................................................................... 80
Correspondence between Interrupt Source and ICR .................................................... 82
Interrupt Sources, Vector Addresses, and Interrupt Priorities...................................... 90
Interrupt Control Modes............................................................................................... 93
Interrupts Selected in Each Interrupt Control Mode .................................................... 94
Operations and Control Signal Functions in Each Interrupt Control Mode ................. 95
Interrupt Response Times .......................................................................................... 101
Number of States in Interrupt Handling Routine Execution Status............................ 101
Rev. 2.00 Aug. 20, 2008 Page xli of xlviii
Table 5.9 Interrupt Source Selection and Clearing Control ....................................................... 103
Section 6
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.12
Table 6.13
Table 6.14
Table 6.15
Bus Controller (BSC)
Pin Configuration....................................................................................................... 110
Address Ranges and External Address Spaces........................................................... 119
Bit Settings and Bus Specifications of Basic Bus Interface ....................................... 120
Bus Specifications for Basic Extended Area/Basic Bus Interface ............................. 120
Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface ..................... 121
Address-Data Multiplex Address Spaces ................................................................... 123
Bit Settings and Bus Specifications of Basic Bus Interface ....................................... 124
Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Address Cycle) ......................................................................................................... 124
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle).... 124
Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Address Cycle) ....................................................................................................... 125
Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Data Cycle)............................................................................................................. 125
Address Range for IOS Signal Output ..................................................................... 126
Data Buses Used and Valid Strobes......................................................................... 129
Data Buses Used and Valid Strobes (Gluless Extension) ........................................ 130
Pin States in Idle Cycle ............................................................................................ 157
Section 7
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Data Transfer Controller (DTC)
Correspondence between Interrupt Sources and DTCER .......................................... 167
DTC Event Counter Conditions ................................................................................. 171
Flag Status/Address Code .......................................................................................... 172
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs.................... 176
Register Functions in Normal Mode .......................................................................... 178
Register Functions in Repeat Mode ........................................................................... 179
Register Functions in Block Transfer Mode .............................................................. 180
DTC Execution Status................................................................................................ 184
Number of States Required for Each Execution Status.............................................. 184
Section 8
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
I/O Ports
Port Functions ............................................................................................................ 190
Port 1 Input Pull-Up MOS States............................................................................... 196
Port 2 Input Pull-Up MOS States............................................................................... 201
Port 3 Input Pull-Up MOS States............................................................................... 207
Port 4 Input Pull-Up MOS States............................................................................... 215
Port 6 Input Pull-Up MOS States............................................................................... 226
Input Pull-Up MOS States ......................................................................................... 247
Port D Input Pull-Up MOS States .............................................................................. 263
Table 6.9
Table 6.10
Table 6.11
Rev. 2.00 Aug. 20, 2008 Page xlii of xlviii
Table 8.9
Table 8.10
Table 8.11
Table 8.12
Table 8.13
Table 8.14
Table 8.15
Table 8.16
Port Functions ............................................................................................................ 273
Port 1 Input Pull-Up MOS States ............................................................................. 279
Port 2 Input Pull-Up MOS States ............................................................................. 284
Port 3 Input Pull-Up MOS States ............................................................................. 290
Port 4 Input Pull-Up MOS States ............................................................................. 298
Port 6 Input Pull-Up MOS States ............................................................................. 310
Input Pull-Up MOS States........................................................................................ 331
Port D Input Pull-Up MOS States ............................................................................ 347
Section 9
Table 9.1
Table 9.2
Table 9.3
Table 9.4
14-Bit PWM Timer (PWMX)
Pin Configuration ....................................................................................................... 360
Clock Select of PWMX_1 and PWMX_0.................................................................. 365
Settings and Operation (Examples when φ = 34 MHz).............................................. 368
Locations of Additional Pulses Added to Base Pulse (When CFS = 1) ..................... 373
Section 10 16-Bit Free-Running Timer (FRT)
FRT Interrupt Sources........................................................................................... 386
Table 10.1
Table 10.2
Switching of Internal Clock and FRC Operation .................................................. 391
Section 11 8-Bit Timer (TMR)
Table 11.1 (1) Clock Input to TCNT and Count Condition (TMR_0) ....................................... 399
Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1) ....................................... 400
Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)....................... 400
Table 11.2 Registers Accessible by TMR_X/TMR_Y............................................................... 405
Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X........... 409
Table 11.4 Switching of Internal Clocks and TCNT Operation................................................. 413
Section 12 Watchdog Timer (WDT)
Table 12.1 Pin Configuration ..................................................................................................... 417
Table 12.2 WDT Interrupt Source.............................................................................................. 426
Section 13
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7
Table 13.8
Serial Communication Interface (SCI)
Pin Configuration ..................................................................................................... 434
Relationships between N Setting in BRR and Bit Rate B ........................................ 447
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) ............... 448
Maximum Bit Rate for Each Frequency (Asynchronous Mode).............................. 448
Maximum Bit Rate with External Clock Input (Asynchronous Mode).................... 448
BRR Settings for Various Bit Rates (Clock Synchronous Mode)............................ 449
Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........... 450
BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0,
s = 372) .................................................................................................................... 450
Table 13.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) ..... 450
Table 13.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 452
Rev. 2.00 Aug. 20, 2008 Page xliii of xlviii
Table 13.11 SSR Status Flags and Receive Data Handling ....................................................... 459
Table 13.12 SCI Interrupt Sources............................................................................................. 489
Table 13.13 SCI Interrupt Sources............................................................................................. 490
Section 15
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Serial Communication Interface with FIFO (SCIF)
Pin Configuration..................................................................................................... 509
Register Access ........................................................................................................ 510
Interrupt Control Function ....................................................................................... 515
SCIF Output Setting................................................................................................. 527
Example of Baud Rate Settings................................................................................ 528
Correspondence Between LPC Interface I/O Address and the SCIF Registers ....... 539
Register States.......................................................................................................... 540
Interrupt Sources ...................................................................................................... 541
Interrupt Source, Vector Address, and Interrupt Priority ......................................... 541
Section 16 Serial Pin Multiplexed Modes
Table 16.1 Pin Configuration..................................................................................................... 544
Section 17
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Synchronous Serial Communication Unit (SSU)
Pin Configuration..................................................................................................... 555
Communication Modes and Pin States of SSI and SSO Pins................................... 568
Communication Modes and Pin States of SSCK Pin ............................................... 569
Communication Modes and Pin States of SCS Pin .................................................. 569
Interrupt Sources ...................................................................................................... 585
Section 18
Table 18.1
Table 18.2
Table 18.3
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Table 18.10
Table 18.11
Table 18.12
Table 18.13
I2C Bus Interface (IIC)
Pin Configuration..................................................................................................... 590
Transfer Format........................................................................................................ 594
I2C bus Transfer Rate (1) ......................................................................................... 598
I2C bus Transfer Rate (2) ......................................................................................... 599
Flags and Transfer States (Master Mode) ................................................................ 606
Flags and Transfer States (Slave Mode)................................................................... 607
Output Data Hold Time............................................................................................ 618
ISCMBCR Setting.................................................................................................... 618
I2C Bus Data Format Symbols ................................................................................. 620
Examples of Operation Using the DTC ................................................................... 649
IIC Interrupt Source ............................................................................................... 652
I2C Bus Timing (SCL and SDA Outputs) .............................................................. 653
Permissible SCL Rise Time (tsr) Values................................................................. 654
I2C Bus Timing (with Maximum Influence of tSr/tSf) ............................................. 656
Section 19 LPC Interface (LPC)
Table 19.1 Pin Configuration..................................................................................................... 670
Rev. 2.00 Aug. 20, 2008 Page xliv of xlviii
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Table 19.6
Table 19.7
Table 19.8
Table 19.9
Table 19.10
Table 19.11
Table 19.12
Table 19.13
Table 19.14
LADR1, LADR2 Initial Values ............................................................................... 686
Host Register Selection ............................................................................................ 687
Slave Selection Internal Registers............................................................................ 687
LPC I/O Cycle.......................................................................................................... 736
GA20 Setting/Clearing Timing ................................................................................ 742
Fast Gate A20 Output Signals.................................................................................. 744
Scope of LPC Interface Pin Shutdown..................................................................... 746
Scope of Initialization in Each LPC interface Mode................................................ 747
Serialized Interrupt Transfer Cycle Frame Configuration...................................... 750
Receive Complete Interrupts and Error Interrupt ................................................... 752
HIRQ Setting and Clearing Conditions when LPC Channels are Used ................. 754
HIRQ Setting and Clearing Conditions when SCIF Channels are Used ................ 755
Host Address Example ........................................................................................... 757
Section 20 Ethernet Controller (EtherC)
Table 20.1 Pin Configuration ..................................................................................................... 761
Section 22
Table 22.1
Table 22.2
Table 22.3
Table 22.4
Table 22.5
Table 22.6
Table 22.7
Table 22.8
USB Function Module (USB)
Pin Configuration ..................................................................................................... 834
Example of Limitations for Setting Values .............................................................. 858
Example of Setting ................................................................................................... 859
Relationship between TRNTREG0 Setting and Pin Output..................................... 861
Relationship between Pin Input and TRNTREG1 Monitoring Value ...................... 862
Interrupt Sources ...................................................................................................... 863
Command Decoding on Application Side................................................................ 882
Selection of Peripheral Module Clock (φ) when USB Connection is Made ............ 894
Section 23
Table 23.1
Table 23.2
Table 23.3
Table 23.4
Table 23.5
Table 23.6
A/D Converter
Pin Configuration ..................................................................................................... 897
Analog Input Channels and Corresponding ADDR Registers ................................. 899
A/D Conversion Characteristics (Single Mode)....................................................... 907
A/D Conversion Characteristics (Scan Mode) ......................................................... 907
A/D Converter Interrupt Source ............................................................................... 909
Standard of Analog Pins........................................................................................... 913
Section 25
Table 25.1
Table 25.2
Table 25.3
Table 25.4
Table 25.5
Table 25.6
Flash Memory
Comparison of Programming Modes ....................................................................... 920
Pin Configuration ..................................................................................................... 925
Register/Parameter and Target Mode....................................................................... 927
Parameters and Target Modes .................................................................................. 937
Setting On-Board Programming Mode .................................................................... 947
System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI ............ 949
Rev. 2.00 Aug. 20, 2008 Page xlv of xlviii
Table 25.7 Enumeration Information ......................................................................................... 953
Table 25.8 Executable MAT ...................................................................................................... 973
Table 25.9 (1) Useable Area for Programming in User Program Mode .................................... 974
Table 25.9 (2) Useable Area for Erasure in User Program Mode .............................................. 976
Table 25.9 (3) Useable Area for Programming in User Boot Mode .......................................... 978
Table 25.9 (4) Useable Area for Erasure in User Boot Mode .................................................... 980
Table 25.10 Hardware Protection .............................................................................................. 983
Table 25.11 Software Protection................................................................................................ 984
Table 25.12 Inquiry and Selection Commands .......................................................................... 992
Table 25.13 Programming/Erasing Command ......................................................................... 1005
Table 25.14 Status Code .......................................................................................................... 1014
Table 25.15 Error Code............................................................................................................ 1015
Section 26
Table 26.1
Table 26.2
Table 26.3
Boundary Scan (JTAG)
Pin Configuration................................................................................................... 1021
JTAG Register Serial Transfer............................................................................... 1022
Correspondence between Pins and Boundary Scan Register
(H8S/2472 Group) ................................................................................................. 1025
Table 26.4 Correspondence between Pins and Boundary Scan Register
(H8S/2462 Group and H8S/2463 Group) .............................................................. 1034
Section 27
Table 27.1
Table 27.2
Table 27.3
Clock Pulse Generator
Damping Resistance Values................................................................................... 1052
Crystal Resonator Parameters ................................................................................ 1053
Ranges of Multiplied Clock Frequency ................................................................. 1054
Section 28 Power-Down Modes
Table 28.1 Operating Frequency and Wait Time ..................................................................... 1060
Table 28.2 LSI Internal States in Each Mode .......................................................................... 1066
Section 31
Table 31.1
Table 31.2
Table 31.2
Table 31.3
Table 31.4
Table 31.5
Table 31.6
Table 31.7
Table 31.8
Table 31.9
Table 31.10
Electrical Characteristics
Absolute Maximum Ratings .................................................................................. 1121
DC Characteristics (1)............................................................................................ 1122
DC Characteristics (2)............................................................................................ 1124
Permissible Output Currents .................................................................................. 1125
Clock Timing ......................................................................................................... 1127
External Clock Input Conditions............................................................................ 1128
Subclock Input Conditions..................................................................................... 1128
Control Signal Timing ........................................................................................... 1132
Bus Timing............................................................................................................. 1134
Multiplex Bus Timing ............................................................................................ 1143
Timing of On-Chip Peripheral Modules .............................................................. 1147
Rev. 2.00 Aug. 20, 2008 Page xlvi of xlviii
Table 31.11
Table 31.12
Table 31.13
Table 31.14
Table 31.15
Timing of On-Chip Peripheral Modules (2)......................................................... 1148
I2C Bus Timing .................................................................................................... 1153
LPC Module Timing ............................................................................................ 1154
Ethernet Controller Signal Timing ....................................................................... 1156
USB Characteristics when On-Chip USB Transceiver is Used
(USD+, USD− pin characteristics)....................................................................... 1159
Table 31.16 JTAG Timing ....................................................................................................... 1161
Table 31.17 A/D Conversion Characteristics
(AN7 to AN0 Input: 80/160-State Conversion) ................................................... 1163
Table 31.18 Flash Memory Characteristics.............................................................................. 1164
Appendix
Table A.1 I/O Port States in Each Processing State ................................................................. 1167
Rev. 2.00 Aug. 20, 2008 Page xlvii of xlviii
Rev. 2.00 Aug. 20, 2008 Page xlviii of xlviii
Section 1 Overview
Section 1 Overview
1.1
Overview
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
Multiplication and accumulation instructions
• Various peripheral functions
Data transfer controller (DTC)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or synchronous serial communication interface (SCI)
CRC operation circuit (CRC)
Serial communication interface with FIFO (SCIF)
Synchronous serial communication unit (SSU)
2
I C bus interface (IIC)
LPC interface (LPC)
Ethernet controller (EtherC)
Direct memory access controller for Ethernet controller (E-DMAC)
USB function module (USB)*
1
10-bit A/D converter
2
Platform Environment Control Interface (PECI)*
Boundary scan (JTAG)
Clock pulse generator
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
Rev. 2.00 Aug. 20, 2008 Page 1 of 1198
REJ09B0403-0200
Section 1 Overview
• On-chip memory
ROM Type
Model
ROM
RAM
Remarks
Flash memory
Version
R4F2472
512 Kbytes
40 Kbytes
176 pins,
USB incorporated
R4F2463
512 Kbytes
40 Kbytes
144 pins,
USB and PECI not
incorporated
R4F2462
512 Kbytes
40 Kbytes
144 pins,
USB not incorporated
• Reprogramming count: 1000 times (Tpy.)
• General I/O ports
I/O pins: 110 (for 176-pin), 106 (for 144-pin)
Input-only pins: 9
• Supports various power-down states
• Compact package
Package (code)
Body Size
Pin Pitch
PLBG0176GA-A
13 × 13 mm
0.8 mm
PTQP0144LC-A
16 × 16 mm
0.4 mm
PLQP0144KA-A
20 × 20 mm
0.5 mm
Rev. 2.00 Aug. 20, 2008 Page 2 of 1198
REJ09B0403-0200
Section 1 Overview
Block Diagram
DTC
H8S/2600
CPU
RAM
40K
ROM
(Flash)
512K
(+16K UB)
Port E
Port 2
Port F
Port 1
Clock pulse
generator
LPC
EtherC
E-DMAC
JTAG
8-bit timer × 4
SSU
CRC calculator
FRT
USB* 1
IIC_0 to IIC_5
PECI* 2
Port 5
SCIF
Port 7
Port 8
Port C
A/D converter
Port B
Port 4
SCI_1, SCI_3
Bus controller
14-bit PWM × 4
Interrupt controller
Port D
EVC
Port A
Port 3
WDT × 2
Port 6
1.2
Port 9
[Legend]
CPU:
DTC:
EVC:
SCI:
SCIF:
IIC:
EtherC:
E-DMAC:
SSU:
USB:
FRT:
PWM:
LPC:
WDT:
JTAG:
PECI:
Central processing unit
Data transfer controller
Event counter
Serial communication interface
Serial communication interface with FIFO
I2C bus interface
Ethernet controller
Direct memory access controller for Ethernet controller
Synchronous serial communication unit
USB function module
16-bit free running timer
14-bit PWM timer
LPC interface
Watchdog timer
Boundary scan
PECI interface
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
Figure 1.1 Internal Block Diagram
Rev. 2.00 Aug. 20, 2008 Page 3 of 1198
REJ09B0403-0200
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Assignments
A
B
C
D
E
F
G
H
J
15
P11
P13
P16
P21
P24
P27
PF1
ETDI
PUPDPLS
14
P10
P12
P14
P20
P23
P26
PF0
ETCK
13
PB5
PB7
VSS
P17
P25
VSS
PF2
12
PB2
PB4
PB6
P15
P22
NC
ETRST
11
VCC
PB0
PB1
10
P32
P33
9
P36
P37
K
L
M
N
USD-
P67
P64
P61
AVCC
P76
15
VBUS
USD+
P66
P62
AVref
P75
P74
14
ETD0
DrVSS
DrVCC
P65
P60
P77
P73
P71
13
ETMS
NC
VCC
P63
P72
P70
AVSS
NC
12
PB3
PD0
PD3
PD1
PD2
11
P31
P30
PD7
PD6
PD4
PD5
10
P35
P34
PE2
PE1
VCC
PE0
9
PE6
PE5
PE3
PE4
8
H8S/2472 Group
PLBG0176GA-A
BP-176V
(Top view)
P
R
8
P42
P43
P41
P40
7
P52
P53
PECI
PEVref
P80
NC
NC
PE7
7
6
P55
P44
P54
FWE
P84
P83
P81
P82
6
VCC
UXSEL
UXSEL
F
PEVref
5
UXTAL UEXTAL
P34
P30
PB3
VSS
P87
P86
P85
5
4
PF5
PF4
NC
PF3
RES
NC
P50
P94
P91
PC6
PC1
PA5
NC
NC
NC
4
3
VSS
RESO
P45
P56
PF6
VCL
P97
P93
P90
PC5
NC
PA7
PA2
PA1
PA0
3
2
XTAL
EXTAL
P47
VSS
NMI
P51
P95
P92
PC7
PC3
NC
PC0
VCC
PA3
NC
2
1
VCC
P46
P57
MD1
STBY
MD2
P96
NC
NC
PC4
PC2
NC
PA6
PA4
NC
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
: NC pin
Figure 1.2 Pin Assignments (H8S/2472 Group)
Rev. 2.00 Aug. 20, 2008 Page 4 of 1198
REJ09B0403-0200
P75/AN5
P76/AN6
P77/AN7
AVCC
P60/IRQ14/PWX0/D0
P61/IRQ15/PWX1/D1
P62/PWX2/D2
P63/PWX3/D3
P64/ExIRQ11/CTS
P65/ExIRQ10/RTS
P66/ExIRQ9/SCS
P67/ExIRQ8/SSCK
VCC
ETMS
ETDO
ETDI
ETCK
ETRST
NC
PF1/RS9/MDC
PF0/RS8/MDIO
VSS
P27/DTR
P26/DSR
P25/RI
P24/DCD
P23/A11/AD11
P22/A10/AD10
P21/A9/AD9
P20/A8/AD8
P17/A7/AD7
P16/A6/AD6
P15/A5/AD5
P14/A4/AD4
P13/A3/AD3
P12/A2/AD2
Section 1 Overview
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P11/A1/AD1 109
72 P74/AN4
VSS 110
71 P73/AN3
P10/A0/AD0 111
70 P72/AN2
PB7/EVENT15/RM_RX-ER 112
69 P71/AN1
PB6/EVENT14/RM_CRS-DV 113
68 P70/AN0
67 AVSS
PB5/EVENT13/RM_REF-CLK 114
PB4/EVENT12/RM_TX-EN 115
66 PD0/LSCI
PB3/EVENT11/DB3/RM_RXD1 116
65 PD1/LSMI
PB2/EVENT10/DB2/RM_RXD0 117
64 PD2/PME
PB1/EVENT9/DB1/RM_TXD1 118
63 PD3/GA20
PB0/EVENT8/DB0/RM_TXD0 119
62 PD4/CLKRUN
61 PD5/LPCPD
VCC 120
P30/ExDB0/D8 121
60 PD6/SCL5
P31/ExDB1/D9 122
59 PD7/SDA5
P32/ExDB2/D10 123
58 PE0/LAD0
57 PE1/LAD1
P33/ExDB3/D11 124
P34/ExDB4/D12 125
56 PE2/LAD2
H8S/2463 Group
PTQP0144LC-A
TFP-144V
(Top view)
P35/ExDB5/D13 126
P36/ExDB6/D14 127
P37/ExDB7/D15 128
P40/IRQ0/RS0/HC0/D4 129
55 PE3/LAD3
54 PE4/LFRAME
53 PE5/LRESET
52 PE6/LCLK
P41/IRQ1/RS1/HC1/D5 130
51 PE7/SERIRQ
P42/IRQ2/RS2/HC2/D6 131
50 P80/SCL0
P43/IRQ3/RS3/HC3/D7 132
49 P81/SDA0
P52/IRQ10/TxD1 133
48 P82/SCL1
P53/IRQ11/RxD1 134
47 P83/SDA1
FWE 135
46 P84/ExIRQ12/SCK3
P54/IRQ12/SSO 136
45 P85/ExIRQ13/SCK1
P55/IRQ13/SSI 137
44 P86/ExIRQ14/RxD3
43 P87/ExIRQ15/TxD3/ADTRG
P44/IRQ4/RS4/DB4/HC4/A12/AD12 138
NC 139
42 VSS
NC 140
41 PA0/ExIRQ0/EVENT0/A16
VSS 141
40 PA1/ExIRQ1/EVENT1/A17
RESO 142
39 PA2/ExIRQ2/EVENT2/A18
XTAL 143
38 PA3/ExIRQ3/EVENT3/A19
37 PA4/ExIRQ4/EVENT4/A20
VCC
PA5/ExIRQ5/EVENT5/WOL/A21
PA6/ExIRQ6/EVENT6/LNKSTA/A22
PC0/SCL2
PA7/ExIRQ7/EVENT7/EXOUT/A23
PC1/SDA2
PC2/SCL3
PC3/SDA3
PC4/SCL4
PC5/SDA4
PC7/RD
PC6/LWR
P90/LBE
P91/AH
P92/HBE
P93/ExPWX0
P94/ExPWX1
P96
P95/AS/IOS
P97/CS256/WAIT
P50/IRQ8/TxDF
P51/IRQ9/RxDF
MD2
VCL
NMI
STBY
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PF6/ExPWX2/RS14
RES
P56/EXCL/φ
8
MD1
5 6 7
VSS
4
P57/WR/HWR
3
P47/IRQ7/RS7/DB7/HC7/A15/AD15
VCC
P45/IRQ5/RS5/DB5/HC5/A13/AD13
1 2
P46/IRQ6/RS6/DB6/HC6/A14/AD14
EXTAL 144
Figure 1.3 Pin Assignments (H8S/2463 Group)
Rev. 2.00 Aug. 20, 2008 Page 5 of 1198
REJ09B0403-0200
P75/AN5
P76/AN6
P77/AN7
AVCC
AVref
P60/IRQ14/PWX0/D0
P61/IRQ15/PWX1/D1
P62/PWX2/D2
P63/PWX3/D3
P64/ExIRQ11/CTS
P65/ExIRQ10/RTS
P66/ExIRQ9/SCS
P67/ExIRQ8/SSCK
VCC
ETMS
ETDO
ETDI
ETCK
ETRST
PF1/RS9/MDC
PF0/RS8/MDIO
VSS
P27/DTR
P26/DSR
P25/RI
P24/DCD
P23/A11/AD11
P22/A10/AD10
P21/A9/AD9
P20/A8/AD8
P17/A7/AD7
P16/A6/AD6
P15/A5/AD5
P14/A4/AD4
P13/A3/AD3
P12/A2/AD2
Section 1 Overview
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P11/A1/AD1 109
72 P74/AN4
VSS 110
71 P73/AN3
P10/A0/AD0 111
70 P72/AN2
PB7/EVENT15/RM_RX-ER 112
69 P71/AN1
PB6/EVENT14/RM_CRS-DV 113
68 P70/AN0
67 AVSS
PB5/EVENT13/RM_REF-CLK 114
PB4/EVENT12/RM_TX-EN 115
66 PD0/LSCI
PB3/EVENT11/DB3/RM_RXD1 116
65 PD1/LSMI
PB2/EVENT10/DB2/RM_RXD0 117
64 PD2/PME
PB1/EVENT9/DB1/RM_TXD1 118
63 PD3/GA20
PB0/EVENT8/DB0/RM_TXD0 119
62 PD4/CLKRUN
61 PD5/LPCPD
VCC 120
P30/ExDB0/D8 121
60 PD6/SCL5
P31/ExDB1/D9 122
59 PD7/SDA5
58 PE0/LAD0
P32/ExDB2/D10 123
P33/ExDB3/D11 124
57 PE1/LAD1
H8S/2462 Group
PLQP0144KA-A
FP-144LV
(Top view)
P34/ExDB4/D12 125
P35/ExDB5/D13 126
P36/ExDB6/D14 127
P37/ExDB7/D15 128
56 PE2/LAD2
55 PE3/LAD3
54 PE4/LFRAME
53 PE5/LRESET
P40/IRQ0/RS0/HC0/D4 129
52 PE6/LCLK
P41/IRQ1/RS1/HC1/D5 130
51 PE7/SERIRQ
P42/IRQ2/RS2/HC2/D6 131
50 P80/SCL0
P43/IRQ3/RS3/HC3/D7 132
49 P81/SDA0
PEVref 133
48 P82/SCL1
PECI 134
47 P83/SDA1
P52/IRQ10/TxD1 135
46 P84/ExIRQ12/SCK3
P53/IRQ11/RxD1 136
45 P85/ExIRQ13/SCK1
FWE 137
44 P86/ExIRQ14/RxD3
43 P87/ExIRQ15/TxD3/ADTRG
P54/IRQ12/SSO 138
42 VSS
P55/IRQ13/SSI 139
P44/IRQ4/RS4/DB4/HC4/A12/AD12 140
41 PA0/ExIRQ0/EVENT0/A16
VSS 141
40 PA1/ExIRQ1/EVENT1/A17
RESO 142
39 PA2/ExIRQ2/EVENT2/A18
XTAL 143
38 PA3/ExIRQ3/EVENT3/A19
37 PA4/ExIRQ4/EVENT4/A20
Figure 1.4 Pin Assignments (H8S/2462 Group)
Rev. 2.00 Aug. 20, 2008 Page 6 of 1198
REJ09B0403-0200
VCC
PA5/ExIRQ5/EVENT5/WOL/A21
PA6/ExIRQ6/EVENT6/LNKSTA/A22
PA7/ExIRQ7/EVENT7/EXOUT/A23
PC0/SCL2
PC2/SCL3
PC1/SDA2
PC3/SDA3
PC4/SCL4
PC6/LWR
PC5/SDA4
PC7/RD
P90/LBE
P91/AH
P92/HBE
P93/ExPWX0
P94/ExPWX1
P96
P95/AS/IOS
P97/CS256/WAIT
P50/IRQ8/TxDF
MD2
P51/IRQ9/RxDF
VCL
STBY
NMI
MD1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PF6/ExPWX2/RS14
8
RES
P47/IRQ7/RS7/DB7/HC7/A15/AD15
VSS
P46/IRQ6/RS6/DB6/HC6/A14/AD14
5 6 7
P56/EXCL/φ
4
P57/WR/HWR
3
VCC
1 2
P45/IRQ5/RS5/DB5/HC5/A13/AD13
EXTAL 144
Section 1 Overview
1.3.2
Table 1.1
Pin Assignment in Each Operating Mode
Pin Assignments in Each Operating Mode
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode
1
1
A1
VCC
VCC
VCC
2
2
C3
P45/IRQ5/RS5/DB5/ P45/IRQ5/RS5/DB5/ FA13
HC5/A13/AD13
HC5
3
3
B1
P46/IRQ6/RS6/DB6/ P46/IRQ6/RS6/DB6/ FA14
HC6/A14/AD14
HC6
4
4
C2
P47/IRQ7/RS7/DB7/ P47/IRQ7/RS7/DB7/ FA15
HC7/A15/AD15
HC7
5
5
D3
P56/EXCL/phi
P56/EXCL/phi
NC
6
6
C1
WR/HWR
P57
NC
7
7
D2
VSS
VSS
VSS
8
8
E4
RES
RES
RES
9
9
D1
MD1
MD1
VSS
10
10
E3
PF6/ExPWX2/RS14
PF6/ExPWX2/RS14
VSS
11
11
E2
NMI
NMI
FA9
12
12
E1
STBY
STBY
VCC


F4
NC
NC
NC
13
13
F3
VCL
VCL
VCL
14
14
F1
MD2
MD2
VCC
15
15
F2
P51/IRQ9/RxDF
P51/IRQ9/RxDF
NC
16
16
G4
P50/IRQ8/TxDF
P50/IRQ8/TxDF
NC
17
17
G3
P97/CS256/WAIT
P97
NC
18
18
G1
P96
P96
NC
19
19
G2
AS/IOS
P95
NC
20
20
H4
P94/ExPWX1
P94/ExPWX1
NC
21
21
H3
P93/ExPWX0
P93/ExPWX0
NC


H1
NC
NC
NC
22
22
H2
P92/HBE
P92
NC
Rev. 2.00 Aug. 20, 2008 Page 7 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode
23
23
J4
P91/AH
P91
NC
24
24
J3
P90/LBE
P90
NC


J1
NC
NC
NC
25
25
J2
RD
PC7
WE
26
26
K4
PC6/LWR
PC6
NC
27
27
K3
PC5/SDA4
PC5/SDA4
NC
28
28
K1
PC4/SCL4
PC4/SCL4
NC
29
29
K2
PC3/SDA3
PC3/SDA3
NC


L3
NC
NC
NC
30
30
L1
PC2/SCL3
PC2/SCL3
NC


L2
NC
NC
NC
31
31
L4
PC1/SDA2
PC1/SDA2
NC


M1
NC
NC
NC
32
32
M2
PC0/SCL2
PC0/SCL2
NC
33
33
M3
PA7/ExIRQ7/
PA7/ExIRQ7/
EVENT7/EXOUT/A23 EVENT7/EXOUT
VCC
34
34
N1
PA6/ExIRQ6/
EVENT6/LNKSTA/A22
PA6/ExIRQ6/
EVENT6/LNKSTA
VCC
35
35
M4
PA5/ExIRQ5/
EVENT5/WOL/A21
PA5/ExIRQ5/
EVENT5/WOL
VSS
36
36
N2
VCC
VCC
VCC
37
37
P1
PA4/ExIRQ4/EVENT4/
A20
PA4/ExIRQ4/EVENT4
CE
38
38
P2
PA3/ExIRQ3/EVENT3/
A19
PA3/ExIRQ3/EVENT3
FA19


R1
NC
NC
NC
39
39
N3
PA2/ExIRQ2/EVENT2/
A18
PA2/ExIRQ2/EVENT2
FA18


R2
NC
NC
NC
40
40
P3
PA1/ExIRQ1/EVENT1/
A17
PA1/ExIRQ1/EVENT1
FA17
Rev. 2.00 Aug. 20, 2008 Page 8 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode


N4
NC
NC
NC
41
41
R3
PA0/ExIRQ0/EVENT0/
A16
PA0/ExIRQ0/EVENT0
FA16


P4
NC
NC
NC
42
42
M5
VSS
VSS
VSS


R4
NC
NC
NC
43
43
N5
P87/ExIRQ15/TxD3/ P87/ExIRQ15/TxD3/ NC
ADTRG
ADTRG
44
44
P5
P86/ExIRQ14/RxD3
45
45
R5
P85/ExIRQ13/SCK1 P85/ExIRQ13/SCK1 NC
46
46
M6
P84/ExIRQ12/SCK3 P84/ExIRQ12/SCK3 NC
47
47
N6
P83/SDA1
P83/SDA1
NC
48
48
R6
P82/SCL1
P82/SCL1
NC
49
49
P6
P81/SDA0
P81/SDA0
NC
50
50
M7
P80/SCL0
P80/SCL0
NC


N7
NC
NC
NC
51
51
R7
PE7/SERIRQ
PE7/SERIRQ
NC


P7
NC
NC
NC
52
52
M8
PE6/LCLK
PE6/LCLK
NC
53
53
N8
PE5/LRESET
PE5/LRESET
NC
54
54
R8
PE4/LFRAME
PE4/LFRAME
NC
55
55
P8
PE3/LAD3
PE3/LAD3
NC
56
56
M9
PE2/LAD2
PE2/LAD2
NC
57
57
N9
PE1/LAD1
PE1/LAD1
NC
58
58
R9
PE0/LAD0
PE0/LAD0
NC


P9
VCC
VCC
NC
59
59
M10
PD7/SDA5
PD7/SDA5
NC
60
60
N10
PD6/SCL5
PD6/SCL5
NC
61
61
R10
PD5/LPCPD
PD5/LPCPD
NC
62
62
P10
PD4/CLKRUN
PD4/CLKRUN
NC
P86/ExIRQ14/RxD3
NC
Rev. 2.00 Aug. 20, 2008 Page 9 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode
63
63
N11
PD3/GA20
PD3/GA20
NC
64
64
R11
PD2/PME
PD2/PME
NC
65
65
P11
PD1/LCMI
PD1/LCMI
NC
66
66
M11
PD0/LSCI
PD0/LSCI
NC


R12
NC
NC
NC
67
67
P12
AVSS
AVSS
VSS
68
68
N12
P70/AN0
P70/AN0
NC
69
69
R13
P71/AN1
P71/AN1
NC
70
70
M12
P72/AN2
P72/AN2
NC
71
71
P13
P73/AN3
P73/AN3
NC
72
72
R14
P74/AN4
P74/AN4
NC
73
73
P14
P75/AN5
P75/AN5
NC
74
74
R15
P76/AN6
P76/AN6
NC
75
75
N13
P77/AN7
P77/AN7
NC
76
76
P15
AVCC
AVCC
VCC
77

N14
AVref
AVref
VCC
78
77
M13
P60/IRQ14/PWX0/D0 P60/IRQ14/PWX0
NC
79
78
N15
P61/IRQ15/PWX1/D1 P61/IRQ15/PWX1
NC
80
79
M14
P62/PWX2/D2
P62/PWX2
NC
81
80
L12
P63/PWX3/D3
P63/PWX3
NC
82
81
M15
P64/ExIRQ11/CTS
P64/ExIRQ11/CTS
NC
83
82
L13
P65/ExIRQ10/RTS
P65/ExIRQ10/RTS
NC
84
83
L14
P66/ExIRQ9/SCS
P66/ExIRQ9/SCS
NC
85
84
L15
P67/ExIRQ8/SSCK
P67/ExIRQ8/SSCK
NC
86
85
K12
VCC
VCC
VCC


K13
DrVCC
DrVCC
VCC


K15
USD−
USD−
NC


K14
USD+
USD+
NC
Rev. 2.00 Aug. 20, 2008 Page 10 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode


J12
NC
NC
NC


J13
DrVSS
DrVSS
VSS


J15
PUPDPLS
PUPDPLS
NC


J14
VBUS
VBUS
NC
87
86
H12
ETMS
ETMS
NC
88
87
H13
ETDO
ETDO
NC
89
88
H15
ETDI
ETDI
NC
90
89
H14
ETCK
ETCK
NC
91
90
G12
ETRST
ETRST
RES


G13
PF2/RS10
PF2/RS10
NC

91

NC
NC
NC
92
92
G15
PF1/RS9/MDC
PF1/RS9/MDC
NC
93
93
G14
PF0/RS8/MDIO
PF0/RS8/MDIO
NC


F12
NC
NC
NC
94
94
F13
VSS
VSS
VSS
95
95
F15
P27/DTR
P27/DTR
NC
96
96
F14
P26/DSR
P26/DSR
NC
97
97
E13
P25/RI
P25/RI
NC
98
98
E15
P24/DCD
P24/DCD
NC
99
99
E14
P23/A11/AD11
P23
FA11
100
100
E12
P22/A10/AD10
P22
FA10
101
101
D15
P21/A9/AD9
P21
OE
102
102
D14
P20/A8/AD8
P20
FA8
103
103
D13
P17/A7/AD7
P17
FA7
104
104
C15
P16/A6/AD6
P16
FA6
105
105
D12
P15/A5/AD5
P15
FA5
106
106
C14
P14/A4/AD4
P14
FA4
107
107
B15
P13/A3/AD3
P13
FA3
108
108
B14
P12/A2/AD2
P12
FA2
Rev. 2.00 Aug. 20, 2008 Page 11 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode
109
109
A15
P11/A1/AD1
P11
FA1
110
110
C13
VSS
VSS
VSS
111
111
A14
P10/A0/AD0
P10
FA0
112
112
B13
PB7/EVENT15/
RM_RX-ER
PB7/EVENT15/
RM_RX-ER
NC
113
113
C12
PB6/EVENT14/
RM_CRS-DV
PB6/EVENT14/
RM_CRS-DV
NC
114
114
A13
PB5/EVENT13/
RM_REF-CLK
PB5/EVENT13/
RM_REF-CLK
NC
115
115
B12
PB4/EVENT12/
RM_TX-EN
PB4/EVENT12/
RM_TX-EN
NC
116
116
D11
PB3/EVENT11/DB3/ PB3/EVENT11/DB3/ NC
RM_RXD1
RM_RXD1
117
117
A12
PB2/EVENT10/DB2/ PB2/EVENT10/DB2/ NC
RM_RXD0
RM_RXD0
118
118
C11
PB1/EVENT9/DB1/
RM_TXD1
PB1/EVENT9/DB1/
RM_TXD1
NC
119
119
B11
PB0/EVENT8/DB0/
RM_TXD0
PB0/EVENT8/DB0/
RM_TXD0
NC
120
120
A11
VCC
VCC
VCC
121
121
D10
D8
P30/ExDB0
FO0
122
122
C10
D9
P31/ExDB1
FO1
123
123
A10
D10
P32/ExDB2
FO2
124
124
B10
D11
P33/ExDB3
FO3
125
125
D9
D12
P34/ExDB4
FO4
126
126
C9
D13
P35/ExDB5
FO5
127
127
A9
D14
P36/ExDB6
FO6
128
128
B9
D15
P37/ExDB7
FO7
129
129
D8
P40/IRQ0/RS0/HC0/ P40/IRQ0/RS0/HC0
D4
NC
130
130
C8
P41/IRQ1/RS1/HC1/ P41/IRQ1/RS1/HC1
D5
NC
Rev. 2.00 Aug. 20, 2008 Page 12 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
Pin Name
H8S/2462
H8S/2463 H8S/2472 Extended Mode
(FP-144LV) (TFP-144V) (BP-176V) (EXPE = 1)
Single-Chip Mode
(EXPE = 0)
Flash Memory
Programmer
Mode
131
131
A8
P42/IRQ2/RS2/HC2/ P42/IRQ2/RS2/HC2
D6
NC
132
132
B8
P43/IRQ3/RS3/HC3/ P43/IRQ3/RS3/HC3
D7
NC
133

D7
PEVref
PEVref
VSS
134

C7
PECI
PECI
NC
135
133
A7
P52/IRQ10/TxD1
P52/IRQ10/TxD1
VCC
136
134
B7
P53/IRQ11/RxD1
P53/IRQ11/RxD1
VSS
137
135
D6
FWE
FWE
FWE
138
136
C6
P54/IRQ12/SSO
P54/IRQ12/SSO
NC
139
137
A6
P55/IRQ13/SSI
P55/IRQ13/SSI
NC
140
138
B6
P44/IRQ4/RS4/DB4/ P44/IRQ4/RS4/DB4/ FA12
HC4/A12/AD12
HC4


C5
VCC
VCC
VCC


A5
UXTAL
UXTAL
NC


B5
UEXTAL
UEXTAL
NC


D5
UXSEL
UXSEL
NC


A4
PF5/RS13
PF5/RS13
NC


B4
PF4/RS12
PF4/RS12
NC

139
C4
NC
NC
NC

140

NC
NC
NC
141
141
A3
VSS
VSS
VSS


D4
PF3/ExPWX3/RS11
PF3/ExPWX3/RS11
NC
142
142
B3
RESO
RESO
NC
143
143
A2
XTAL
XTAL
XTAL
144
144
B2
EXTAL
EXTAL
EXTAL
Rev. 2.00 Aug. 20, 2008 Page 13 of 1198
REJ09B0403-0200
Section 1 Overview
1.3.3
Table 1.2
Pin Functions
Pin Functions
Pin No.
H8S/2462 H8S/2463 H8S/2472
I/O
Name and Function
Type
Symbol
144-Pin
Power
supply
VCC
1, 36,
1, 36,
A1, N2, Input
86, 120 86, 120 P9,
K12,
A11, C5
Power supply pins. Connect all
these pins to the system power
supply. Connect the bypass
capacitor between VCC and VSS
(near VCC).
VCL
13
External capacitance pin for
internal step-down power. Connect
this pin to Vss through an external
capacitor (that is located near this
pin) to stabilize internal step-down
power.
VSS
7, 42,
7, 42,
D2, M5, Input
94, 110, 94, 110, F13,
141
141
C13, A3
Ground pins. Connect all these
pins to the system power supply
(0V).
XTAL
143
143
A2
Input
EXTAL
144
144
B2
Input
For connection to a crystal
resonator. An external clock can be
supplied from the EXTAL pin. For
an example of crystal resonator
connection, see section 27, Clock
Pulse Generator.
UXTAL


A5
Input
UEXTAL


B5
Input
UXSEL


D5
Input
USB clock source select pin
φ
5
5
D3
Output
Supplies the system clock to
external devices.
EXCL
5
5
D3
Input
32.768-kHz external clock for sub
clock should be supplied.
14
9
14
9
F1
D1
Input
These pins set the operating mode.
Inputs at these pins should not be
changed during operation.
8
8
E4
Input
Reset pin. When this pin is low, the
chip is reset.
Clock
Operating
MD2
mode control MD1
System
control
RES
144-Pin
13
Rev. 2.00 Aug. 20, 2008 Page 14 of 1198
REJ09B0403-0200
176-Pin
F3
Input
For connection to a crystal
resonator for USB
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
I/O
Name and Function
System
control
RESO
142
142
B3
142
Outputs a reset signal to an
external device.
STBY
12
12
E1
12
When this pin is low, a transition is
made to hardware standby mode.
FWE
137
135
D6
Input
Pin for use by flash memory.
33 to
35, 37
to 41
33 to
35, 37
to 41
M3, N1, Output
M4, P1,
P2, N3,
P3, R3
A15 to A0 4 to 2,
140,
99 to
109,
111
4 to 2,
138,
99 to
109,
111
C2, B1,
C3, B6,
E14,
E12,
D15,
D14,
D13,
C15,
D12,
C14,
B15,
B14,
A15,
A14
D15 to D8 128 to
121
128 to
121
B9, A9, Input/
C9, D9, Output
B10,
A10,
C10,
D10
Address bus A23 to
A16
Data bus
D7 to D0
132 to 132 to B8, A8,
129,
129,
C8, D8,
81 to 78 80 to 77 L12,
M14,
N15,
M13
Address output pins
Upper 8 bits of bidirectional bus
Lower 8 bits of bidirectional bus
Rev. 2.00 Aug. 20, 2008 Page 15 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
AddressAD15 to
data
AD8
multiplex bus
4 to 2,
140,
99 to
102
4 to 2,
138,
99 to
102
C2, B1, Input/
C3, B6, Output
E14,
E12,
D15,
D14
8 bit bus or upper 8 bits of 16-bit
bus
AD7 to
AD0
103 to
109,
111
103 to
109,
111
D13,
C15,
D12,
C14,
B15,
B14,
A15,
A14
Lower 8 bits of 16-bit bus
NMI
11
11
E2
Input
Nonmaskable interrupt request
input pin
IRQ15 to
IRQ0
79, 78,
139,
138,
136,
135, 15,
16,
4 to 2,
140,
132 to
129
78, 77,
137,
136,
134,
133, 15,
16,
4 to 2,
138,
132 to
129
N15,
Input
M13,
A6, C6,
B7, D6,
F2, G4,
C2, B1,
C3, B6,
B8, A8,
C8, D8
These pins are used to request
maskable interrupts.
ExIRQ15 43 to
to ExIRQ0 46, 82
to 85,
33 to
35,
37 to 41
43 to
46, 81
to 84,
33 to
35,
37 to 41
N5, P5, Input
R5, M6,
M15,
L13,
L14,
L15,
M3, N1,
M4, P1,
P2, N3,
P3, R3
These pins are used to request
maskable interrupts.
WAIT
17
G3
Interrupts
Bus control
17
Rev. 2.00 Aug. 20, 2008 Page 16 of 1198
REJ09B0403-0200
I/O
Input
Name and Function
Either IRQn or ExIRQn can be
selected as the IRQn interrupt
signal input pin.
Either IRQn or ExIRQn can be
selected as the IRQn interrupt
signal input pin.
Requests wait state insertion to
bus cycles when an external tristate address space is accessed.
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
I/O
Name and Function
Bus control
RD
25
25
J2
Output
Low level on this pin indicates that
the MCU is reading from an
external address space.
HWR
6
6
C1
Output
Low level on this pin indicates that
the MCU is writing to an external
address space.
The upper byte of the data bus is
valid.
LWR
26
26
K4
Output
Low level on this pin indicates that
the MCU is writing to an external
address space.
The lower byte of the data bus is
valid.
AS/IOS
19
19
G2
Output
Low level on this pin indicates that
the address output on the address
bus is valid.
CS256
17
17
G3
Output
Indicates access to the 256-Kbyte
area of H'F80000 to H'FBFFFF.
WR
6
6
C1
Output
Low level on this pin indicates that
the MCU is writing to an external
address space.
HBE
22
22
H2
Output
Low level on this pin indicates that
the MCU is accessing an external
address space.
The upper byte of the data bus is
valid.
LBE
24
24
J3
Output
Low level on this pin indicates that
the MCU is accessing an external
address space.
The lower byte of the data bus is
valid.
AH
23
23
J4
Output
Address latch signal for the
address-data multiplex bus
ETRST
91
90
G12
Input
Boundary scan interface pins
ETMS
87
86
H12
Input
ETDO
88
87
H13
Output
ETDI
89
88
H15
Input
ETCK
90
89
H14
Input
Bus control
Boundary
scan
Rev. 2.00 Aug. 20, 2008 Page 17 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
14-bit PWM
timer
(PWMX)
PWX0 to
PWX3
ExPWX0
to
ExPWX2
78 to
81, 21,
20, 10
77 to
80, 21,
20, 10
Output
M13,
N15,
M14,
L12,
H3, H4,
E3
ExPWX3


D4
TxD1,
TxD3
135, 43 133, 43 A7, N5
Output
Transmit data output pins
RxD1,
RxD3
136, 44 134, 44 B7, P5
Input
Receive data input pins
SCK1,
SCK3
45, 46
45, 46
R5, M6 Input/
Output
Clock input/output pins.
TxDF
16
16
G4
Output
Transmit data output pin
RxDF
15
15
F2
Input
Receive data input pin
CTS
82
81
M15
Input
Transmit grant input pin
RTS
83
82
L13
Output
Transmit request output pin
DTR
95
95
F15
Output
Data terminal ready output pin
DSR
96
96
F14
Input
Data set ready input pin
RI
97
97
E13
Input
Ring indicator input pin
DCD
98
98
E15
Input
Data carrier detection input pin
85
84
L15
Input/
Output
SSU clock I/O pin
139
137
A6
Input/
Output
SSU data I/O pin
138
136
C6
Input/
Output
SSU data I/O pin
SCS
84
83
L14
Input/
Output
SSU chip select I/O pin
SCL0 to
SCL5
50, 48,
32, 30,
28, 60
50, 48,
32, 30,
28, 60
M7, R6, Input/
M2, L1, Output
K1, N10
Serial
communication
interface
(SCI_1 and
SCI_3)
Serial
communication
interface
with FIFO
(SCIF)
Synchronous SSCK
serial
communiSSI
cation unit
(SSU)
SSO
2
I C bus
interface
(IIC)
Rev. 2.00 Aug. 20, 2008 Page 18 of 1198
REJ09B0403-0200
I/O
Name and Function
PWM D/A pulse output pins
Pin ExPWX3 is supported only by
the H8S/2472 Group.

IIC clock input/output pins. These
pins can drive a bus directly with
the NMOS open drain output.
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
I C bus
interface
(IIC)
SDA0 to
SDA5
49, 47,
31, 29,
27, 59
49, 47,
31, 29,
27, 59
P6, N6, Input/
L4, K2, Output
K3, M10
A/D
converter
AN7 to
AN0
75 to 68 75 to 68 N13,
R15,
P14,
R14,
P13,
M12,
R13,
N12
Input
Analog input pins
AVCC
76
76
P15
Input
Analog power supply pins. When
the A/D converter is not used,
these pins should be connected to
the system power supply (+3.3 V).
AVref
77

N14
Input
Analog reference voltage input pin.
When the A/D converter is not
used, this pin should be connected
to the system power supply (+3.3
V).
AVSS
67
67
P12
Input
Analog ground pins. These pins
should be connected to the system
power supply (0 V).
ADTRG
43
43
N5
Input
External trigger input pin to start
A/D conversion
LAD3 to
LAD0
55 to 58 55 to 58 P8, M9, Input/
N9, R9 Output
Transfer cycle type/address/data
I/O pins
LFRAME
54
54
R8
Input
Input pin indicating transfer cycle
start and forced termination
LRESET
53
53
N8
Input
LPC reset pin. When this pin is low,
a reset state is entered.
LCLK
52
52
M8
Input
PCI clock input pin
SERIRQ
51
51
R7
Input/
Output
LPC serialized host interrupt
request signal
LSCI,
LSMI,
PME
66
65
64
66
65
64
M11
P11
R11
Input/
Output
LPC auxiliary output. Their
functions are general I/O port.
2
LPC
Interface
(LPC)
I/O
Name and Function
IIC data input/output pins. These
pins can drive a bus directly with
the NMOS open drain output.
Rev. 2.00 Aug. 20, 2008 Page 19 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
I/O
Name and Function
LPC
Interface
(LPC)
GA20
63
63
N11
Input/
Output
GATE A20 control signal output
pin; also used as the input pin for
monitoring the output state.
CLKRUN
62
62
P10
Input/
Output
Input/output pin used to request
starting the LCLK operation while
LCLK is stopped.
LPCPD
61
61
R10
Input
Input pin used to control shutdown
of the LCP module
RM_REF- 114
CLK
114
A13
Input
Transmit/receive Clock
115
115
B12
Output
Transmit enable
RM_TXD1 118
RM_TXD0 119
118
119
C11
B11
Output
Output
Transmit data
RM_CRS- 113
DV
113
C12
Input
Carrier detection/receive data valid
RM_RXD1 116
RM_RXD0 117
116
117
D11
A12
Input
Input
Receive data
RM_RXER
112
112
B13
Input
Receive error
MDC
92
92
G15
Input
Management data clock
MDIO
93
93
G14
Input/
Output
Management data I/O
LNKSTA
34
34
N1
Input
Link status
EXOUT
33
33
M3
Output
General-purpose external output
WOL
35
35
M4
Output
Wake-on-LAN
USB function VBUS
module
USD+
(USB)


J14
Input
USB cable connection monitor pin


K14
Input/
Output
USB data I/O pin
USD−


K15
Input/
Output
USB data I/O pin
DrVcc


K13
Input
Power supply pin for USB built-in
transceiver
DrVss


J13
Input
Ground pin for USB built-in
transceiver
PUPDPLS 

J15
Output
USB+ pull-up control pin
Ethernet
controller
(EtherC)
RM_TXEN
Rev. 2.00 Aug. 20, 2008 Page 20 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
Event
Counter
EVENT15 112 to
to
119,
EVENT0 33 to
35, 37
to 41
112 to
119,
33 to
35, 37
to 41
Input
B13,
C12,
A13,
B12,
D11,
A12,
C11,
B11,
M3, N1,
M4, P1,
P2, N3,
P3, R3
Event counter input pins
10
10
E3


A4, B4,
D4, G13
RS9 to
RS0
92, 93,
4 to 2,
140,
132 to
129
92,93,4
to 2,
138,
132 to
129
G15,
G14,
C2, B1,
C3, B6,
B8, A8,
C8, D8
Retain state output pins.
The outputs on these pins are only
initialized by a system reset.
Pins RS13 to RS10 are supported
only by the H8S/2472 Group.
DB7 to
DB0
4 to 2,
140,
116 to
119
4 to 2,
138,
116 to
119
C2, B1, Input
C3, B6,
D11,
A12,
C11,
B11
ExDB7 to 128 to
ExDB0
121
128 to
121
B9, A9,
C9, D9,
B10,
A10,
C10,
D10
Retain state RS14
output pins
RS13 to
RS10
Debounced
input pins
I/O
Output
Name and Function
Pins with noise eliminating
functions.
Rev. 2.00 Aug. 20, 2008 Page 21 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
144-Pin
176-Pin
Large
current
output pins
HC7 to
HC0
4 to 2,
140,
132 to
129
4 to 2,
138,
132 to
129
C2, B1, Output
C3, B6,
B8, A8,
C8, D8
These pins can be used to drive
LEDs or for other purposes where
large currents are required.
I/O ports
P17 to
P10
103 to
109,
111
103 to
109,
111
D13,
C15,
D12,
C14,
B15,
B14,
A15
Input/
Output
8-bit input/output pins
P27 to
P20
95 to
102
95 to
102
F15,
F14,
E13,
E15,
E14,
E12,
D15,
D14
Input/
Output
8-bit input/output pins
P37 to
P30
128 to
121
128 to
121
B9, A9, Input/
C9, D9, Output
B10,
A10,
C10,
D10
8-bit input/output pins
P47 to
P40
4 to 2,
140,
132 to
129
4 to 2,
138,
132 to
129
C2, B1, Input/
C3, B6, Output
B8, A8,
C8, D8
8-bit input/output pins
P57 to
P50
6, 5,
139,
138,
136,
135, 15,
16
6, 5,
137,
136,
134,
133, 15,
16
C1, D3, Input/
A6, C6, Output
B7, A7,
F2, G4
8-bit input/output pins
Rev. 2.00 Aug. 20, 2008 Page 22 of 1198
REJ09B0403-0200
I/O
Name and Function
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
I/O ports
P67 to
P60
I/O
Name and Function
85 to 78 84 to 77 L15,
L14,
L13,
M15,
L12,
M14,
N15,
M13
Input/
Output
8-bit input/output pins
P77 to
P70
75 to 68 75 to 68 N13,
R15,
P14,
R14,
P13,
M12,
R13,
N12
Input
8-bit input pins
P87 to
P80
43 to 50 43 to 50 N5, P5, Input/
R5, M6, Output
N6, R6,
P6, M7
8-bit input/output pins
P97 to
P90
17 to 24 17 to 24 G3, G1, Input/
G2, H4, Output
H3, H2,
J4, J3
8-bit input/output pins
PA7 to
PA0
33 to
35, 37
to 41
33 to
35, 37
to 41
M3, N1, Input/
M4, P1, Output
P2, N3,
P3, R3
8-bit input/output pins
PB7 to
PB0
112 to
119
112 to
119
B13,
C12,
A13,
B12,
D11,
A12,
C11,
B11
Input/
Output
8-bit input/output pins
PC7 to
PC0
25 to 32 25 to 32 J2, K4, Input/
K3, K1, Output
K2, L1,
L4, M2
8-bit input/output pins
144-Pin
176-Pin
Rev. 2.00 Aug. 20, 2008 Page 23 of 1198
REJ09B0403-0200
Section 1 Overview
Pin No.
H8S/2462 H8S/2463 H8S/2472
Type
Symbol
144-Pin
I/O ports
PD7 to
PD0
59 to 66 59 to 66 M10,
N10,
R10,
P10,
N11,
R11,
P11,
M11
I/O
Name and Function
Input/
Output
8-bit input/output pins
PE7 to
PE0
51 to 58 51 to 58 R7, M8, Input/
N8, R8, Output
P8, M9,
N9, R9
8-bit input/output pins
PF6
10
10
E3
PF5 to
PF2


A4, B4,
D4, G13
7-bit input/output pins.
Pins PF5 to PF2 are supported
only by the H8S/2472 Group.
92, 93
G15,
G14
PF1, PF0 92, 93
144-Pin
Rev. 2.00 Aug. 20, 2008 Page 24 of 1198
REJ09B0403-0200
176-Pin
Input/
Output
Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
• Upward-compatible with H8/300 and H8/300H CPUs
 Can execute H8/300 and H8/300H CPUs object programs
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-nine basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
 Multiply-and-accumulate instruction
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte address space
 Program: 16 Mbytes
 Data:
16 Mbytes
• High-speed operation
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 2 states
Rev. 2.00 Aug. 20, 2008 Page 25 of 1198
REJ09B0403-0200
Section 2 CPU
 16 ÷ 8-bit register-register divide: 12 states
 16 × 16-bit register-register multiply: 3 states
 32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
 Normal mode*
 Advanced mode
• Power-down state
 Transition to power-down state by the SLEEP instruction
 CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
2*
12
MULXU.W Rs, ERd
2*
20
MULXS.B Rs, Rd
3*
13
MULXS.W Rs, ERd
3*
21
CLRMAC
CLRMAC
1*
Not supported
LDMAC
LDMAC ERs,MACH
1*
LDMAC ERs,MACL
1*
STMAC
STMAC MACH,ERd
1*
STMAC MACl,ERd
1*
MULXS
Note:
*
This becomes one state greater immediately after a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,
and power-down modes, etc., depending on the model.
Rev. 2.00 Aug. 20, 2008 Page 26 of 1198
REJ09B0403-0200
Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements:
• More general registers and control registers
 Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
 Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements:
• More control registers
 One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
Rev. 2.00 Aug. 20, 2008 Page 27 of 1198
REJ09B0403-0200
Section 2 CPU
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
Linear access to a 64-kbyte maximum address space is provided.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or
post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table structure in normal mode is
shown in figure 2.1. For details of the exception vector table, see section 4, Exception
Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to
H'00FF. Note that the first part of this range is also used for the exception vector table.
• Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mode is not available in this LSI.
Rev. 2.00 Aug. 20, 2008 Page 28 of 1198
REJ09B0403-0200
Section 2 CPU
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Exception vector 1
Exception vector 2
Exception vector 3
Exception
vector table
Exception vector 4
Exception vector 5
Exception vector 6
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
(SP *
2
Reserved*1,*3
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
Rev. 2.00 Aug. 20, 2008 Page 29 of 1198
REJ09B0403-0200
Section 2 CPU
2.2.2
Advanced Mode
• Address Space
Linear access to a 16-Mbyte maximum address space is provided.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is
stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
Reserved
Exception vector 1
H'00000003
Reserved
H'00000004
Exception vector 2
H'00000007
H'00000008
Reserved
Exception vector table
Exception vector 3
H'0000000B
Reserved
H'0000000C
Exception vector 4
H'00000010
Reserved
Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 2.00 Aug. 20, 2008 Page 30 of 1198
REJ09B0403-0200
Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also used for the exception vector table.
• Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When
EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4,
Exception Handling.
EXR*1
SP
SP
Reserved
PC
(24 bits)
(SP
*2
Reserved*1, *3
)
(a) Subroutine Branch
CCR
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
Rev. 2.00 Aug. 20, 2008 Page 31 of 1198
REJ09B0403-0200
Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'00000000
64-kbyte
16-Mbyte
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be
used in this LSI
H'FFFFFFFF
(a) Normal Mode
(b) Advanced Mode
Figure 2.5 Memory Map
Rev. 2.00 Aug. 20, 2008 Page 32 of 1198
REJ09B0403-0200
Section 2 CPU
2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), an
8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit
multiply-accumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
63
41
MAC
32
MACH
Sign extension
MACL
31
0
[Legend]
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
H:
U:
N:
Z:
V:
C:
MAC:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
Figure 2.6 CPU Registers
Rev. 2.00 Aug. 20, 2008 Page 33 of 1198
REJ09B0403-0200
Section 2 CPU
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
Rev. 2.00 Aug. 20, 2008 Page 34 of 1198
REJ09B0403-0200
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0).
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions, except for the STC instruction, are executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit
Bit Name
Initial
Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
6 to 3

All 1

Reserved
These bits are always read as 1.
2
I2
1
R/W
1
I1
1
R/W
0
I0
1
R/W
These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.
Rev. 2.00 Aug. 20, 2008 Page 35 of 1198
REJ09B0403-0200
Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.
6
UI
Undefined R/W
User Bit or Interrupt Mask Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions. This bit cannot be
used as an interrupt mask bit in this LSI.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Rev. 2.00 Aug. 20, 2008 Page 36 of 1198
REJ09B0403-0200
Section 2 CPU
Bit
Bit Name
Initial
Value
1
V
Undefined R/W
R/W
Description
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.6
Initial Values of CPU Registers
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
Rev. 2.00 Aug. 20, 2008 Page 37 of 1198
REJ09B0403-0200
Section 2 CPU
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
7 6 5 4 3 2 1 0
4 3
Upper
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
Figure 2.9 General Register Data Formats (1)
REJ09B0403-0200
0
Don't care
MSB
Rev. 2.00 Aug. 20, 2008 Page 38 of 1198
0
Lower
LSB
Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
[Legend]
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
RnL:
General register RL
MSB:
Most significant bit
LSB:
Least significant bit
Figure 2.9 General Register Data Formats (2)
Rev. 2.00 Aug. 20, 2008 Page 39 of 1198
REJ09B0403-0200
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 is used as an address register to access the stack, the operand size should be word or
longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.10 Memory Data Formats
Rev. 2.00 Aug. 20, 2008 Page 40 of 1198
REJ09B0403-0200
LSB
Section 2 CPU
2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Data transfer
MOV
Size
B/W/L 5
1
POP* , PUSH*
1
W/L
LDM, STM
3
MOVFPE* , MOVTPE*
Arithmetic
operation
Types
L
3
B
ADD, SUB, CMP, NEG
B/W/L 23
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS*
4
B
MAC, LDMAC, STMAC, CLRMAC

Logic operations
AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc* , JMP, BSR, JSR, RTS
System control
B
14

5
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 
9

1
2
Block data transfer EEPMOV
Total: 69
Notes: B-byte; W-word; L-longword.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and
MOV.L ERn,@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.00 Aug. 20, 2008 Page 41 of 1198
REJ09B0403-0200
Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
MAC
Multiply-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 2.00 Aug. 20, 2008 Page 42 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 2.00 Aug. 20, 2008 Page 43 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 2.00 Aug. 20, 2008 Page 44 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (2)
1
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC

(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC

0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L
Rs → MAC, MAC → Rd
Transfers data between a general register and a multiply-accumulate
register.
TAS*
Note:
2
1. Refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.00 Aug. 20, 2008 Page 45 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼(Rd) → (Rd)
Takes the one’s complement (logical complement) of general register
contents.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 2.00 Aug. 20, 2008 Page 46 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼(<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
*
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ [∼(<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ [∼(<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Refers to the operand size.
B: Byte
Rev. 2.00 Aug. 20, 2008 Page 47 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.7
Bit Manipulation Instructions (2)
1
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
BLD
B
BILD
B
C ⊕ [∼(<bit-No.> of <EAd>)] → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
∼(<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
BIST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
∼C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
Rev. 2.00 Aug. 20, 2008 Page 48 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP

Branches unconditionally to a specified address.
BSR

Branches to a subroutine at a specified address.
JSR

Branches to a subroutine at a specified address.
RTS

Returns from a subroutine
Rev. 2.00 Aug. 20, 2008 Page 49 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA

Starts trap-instruction exception handling.
RTE

Returns from an exception-handling routine.
SLEEP

Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves general register or memory contents or immediate data to CCR
or EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically XORs the CCR or EXR contents with immediate data.
NOP

PC + 2 → PC
Only increments the program counter.
Note:
*
Refers to the operand size.
B: Byte
W: Word
Rev. 2.00 Aug. 20, 2008 Page 50 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 2.00 Aug. 20, 2008 Page 51 of 1198
REJ09B0403-0200
Section 2 CPU
2.6.2
Basic Instruction Formats
The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.11 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
Rev. 2.00 Aug. 20, 2008 Page 52 of 1198
REJ09B0403-0200
Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
Rev. 2.00 Aug. 20, 2008 Page 53 of 1198
REJ09B0403-0200
Section 2 CPU
2.7.3
Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
Register indirect with post-increment@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For the word or longword transfer instructions, the register value
should be even.
Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result is the
address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For the word or longword transfer instructions, the register value should be even.
2.7.5
Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Rev. 2.00 Aug. 20, 2008 Page 54 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode*
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
H'000000 to H'FFFFFF
24 bits (@aa:24)
Note: Normal mode is not available in this LSI.
2.7.6
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7
Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H′00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
Rev. 2.00 Aug. 20, 2008 Page 55 of 1198
REJ09B0403-0200
Section 2 CPU
2.7.8
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode,
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode,
the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
Rev. 2.00 Aug. 20, 2008 Page 56 of 1198
REJ09B0403-0200
Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not available in this LSI.
Table 2.13 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
disp
31
0
31
24 23
0
Don't care
General register contents
r
•Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
1, 2, or 4
31
0
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
Rev. 2.00 Aug. 20, 2008 Page 57 of 1198
REJ09B0403-0200
Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
23
Program-counter relative
0
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
8 7
31
op
abs
H'000000
31
0
Memory contents
Note: * Normal mode is not available in this LSI.
Rev. 2.00 Aug. 20, 2008 Page 58 of 1198
REJ09B0403-0200
0
abs
31
24 23
Don't care
0
Section 2 CPU
2.8
Processing States
The H8S/2600 CPU has four main processing states: the reset state, exception handling state,
program execution state and power-down state. Figure 2.13 indicates the state transitions.
• Reset State
In this state, the CPU and all on-chip peripheral modules are initialized and not operating.
When the RES input goes low, all current processing stops and the CPU enters the reset state.
All interrupts are masked in the reset state. Reset exception handling starts when the RES
signal changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program Execution State
In this state, the CPU executes program instructions in sequence.
• Program Stop State
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters software standby mode. For further
details, refer to section 28, Power-Down Modes.
Rev. 2.00 Aug. 20, 2008 Page 59 of 1198
REJ09B0403-0200
Section 2 CPU
End of bus request
Bus request
Program execution
state
End of bus
request
SLEEP
instruction
with
PSS = 0 and
SSBY = 1
Bus
request
SLEEP
instruction
with
SSBY = 0
Bus-released state
Request for
exception
handling
End of
exception
handling
Sleep mode
Interrupt
request
Exception-handling state
External interrupt
request
Software standby mode
RES = high
Reset state*1
STBY = High, RES = Low
Hardware standby mode*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
Rev. 2.00 Aug. 20, 2008 Page 60 of 1198
REJ09B0403-0200
Section 2 CPU
2.9
Usage Note
2.9.1
Notes on Using the Bit Operation Instruction
Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte
units after bit operation. Therefore, attention must be paid when these instructions are used for
ports or registers including write-only bits.
Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that
the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag
beforehand.
Rev. 2.00 Aug. 20, 2008 Page 61 of 1198
REJ09B0403-0200
Section 2 CPU
Rev. 2.00 Aug. 20, 2008 Page 62 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
This LSI supports one operating mode (mode 2). The operating mode is determined by the setting
of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection.
Table 3.1
MCU Operating Mode Selection
MCU Operating
Mode
MD2
CPU Operating
Description
MD1 Mode
2
1
1
Advanced
Extended mode with on-chip ROM
Single-chip mode
Mode 2 is single-chip mode after a reset. The CPU can switch to extended mode by setting bit
EXPE in MDCR to 1.
Modes 0, 1, 3, 5, and 7 are not available in this LSI. Modes 4 and 6 are operating mode for a
special purpose. Thus, mode pins should be set to enable mode 2 in normal program execution
state. Mode pins should not be changed during operation.
Rev. 2.00 Aug. 20, 2008 Page 63 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode. For details on the bus control register
(BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2
(BCR2), see section 6.3.2, Bus Control Register 2 (BCR2).
• Mode control register (MDCR)
• System control register (SYSCR)
• Serial timer control register (STCR)
3.2.1
Mode Control Register (MDCR)
MDCR is used to set an operating mode and to monitor the current operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
EXPE
0
R/W
Extended Mode Enable
Specifies extended mode.
0: Single-chip mode
1: Extended mode
6 to 3

All 0
R
Reserved
2
MDS2
*
R
Mode Select 2 and 1
1
MDS1
*
R
These bits indicate the input levels at mode pins (MD2
and MD1) (the current operating mode). Bits MDS2 and
MDS1 correspond to MD2 and MD1, respectively. MDS2
and MDS1 are read-only bits and they cannot be written
to. The mode pin (MD2 and MD1) input levels are latched
into these bits when MDCR is read. These latches are
canceled by a reset.
0


R
Reserved
Note:
*
The initial values are determined by the settings of the MD2 and MD1 pins.
Rev. 2.00 Aug. 20, 2008 Page 64 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, enables or disables register access to the on-chip peripheral
modules, and enables or disables on-chip RAM address space.
Bit
Bit Name
Initial
Value
R/W
Description
7
CS256E
0
R/W
Chip Select 256 Enable
Enables or disables P97/WAIT/CS256 pin function in
extended mode.
0: P97/WAIT pin
WAIT pin function is selected by the settings of
WSCR and WSCR2.
1: CS256 pin
Outputs low when a 256-kbyte expansion area of
addresses H'F80000 to H'FBFFFF is accessed.
6
IOSE
0
R/W
IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
Outputs low when an external area is accessed.
1: IOS pin
Outputs low when an IOS expansion area of
addresses H'FFF000 to H'FFF7FF is accessed.
5
INTM1
0
R
4
INTM0
0
R/W
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
Rev. 2.00 Aug. 20, 2008 Page 65 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
Bit
Bit Name
Initial
Value
R/W
Description
3
XRST
1
R
External Reset
This bit indicates the reset source. A reset is caused by an
external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
2
NMIEG
0
R/W
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
1

0
R/W
Reserved
The initial value should not be changed.
0
RAME
1
R/W
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
3.2.3
Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit
Bit Name
Initial
Value
R/W
Description
7
IICX2
0
R/W
IIC Transfer Rate Select 2, 1, and 0
6
IICX1
0
R/W
5
IICX0
0
R/W
These bits control the IIC operation. These bits select a
transfer rate in master mode together with bits CKS2 to
2
CKS0 in the I C bus mode register (ICMR). For details on
the transfer rate, see table 18.3.
Rev. 2.00 Aug. 20, 2008 Page 66 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
Bit
Bit Name
Initial
Value
R/W
Description
4

0
R/W
Reserved
The initial value should not be changed.
3
FLSHE
0
R/W
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR),
control registers of power-down states (SBYCR,
LPWRCR, MSTPCRH, MSTPCRL), and control registers
of on-chip peripheral modules (BCR2, WSCR2, PCSR,
SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is reserved.
Area from H'FFFEA0 to H'FFFEBF is allocated to
registers of AD, serial multiplexed functions, and I/O
ports.
Area from H'FFFF80 to H'FFFF87 is allocated to control
registers of power-down states and on-chip peripheral
modules.
1: Area from H'FFFE88 to H'FFFE8F is allocated to
control registers of flash memory.
Area from H'FFFEA0 to H'FFFEBF is reserved.
Area from H'FFFF80 to H'FFFF87 is reserved.
2

1
R/(W)
1
ICKS1
0
R/W
Internal Clock Source Select 1, 0
0
ICKS0
0
R/W
These bits select a clock to be input to the timer counter
(TCNT) and a count condition together with bits CKS2 to
CKS0 in the timer control register (TCR). For details, see
section 11.2.4, Timer Control Register (TCR).
Reserved
The initial value should not be changed.
Rev. 2.00 Aug. 20, 2008 Page 67 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 2
The CPU can access a 16 Mbytes address space in advanced mode. The on-chip ROM is enabled.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
• Normal extended mode
In extended mode, ports 1, 2 (P23 to P20), and 4 (P47 to P44) function as input ports after a
reset.
Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction
register (DDR). Port 3 functions as a data bus port, and parts of port 9 and port C carry bus
control signals. Ports 4 (P43 to P40) and 6 (P63 to P60) function as a data bus port when the
ABW bit in WSCR is cleared to 0.
• Multiplex extended mode
When 8-bit bus is specified, port 1 functions as the port for address output and data
input/output regardless of the setting of the data direction register (DDR). Ports 2 (P23 to P20)
and 4 (P47 to P44) can be used as a general port.
When 16-bit bus is specified, ports 1, 2 (P23 to P20), and 4 (P47 to P44) function as the port
for address output and data input/output regardless of the setting of the data direction register
(DDR).
Rev. 2.00 Aug. 20, 2008 Page 68 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
3.4
Address Map
Figure 3.1 shows the memory map in operating modes.
ROM: 512 Kbytes, RAM: 40 Kbytes
Mode 2 (EXPE = 1)
Advanced mode
Extended mode with
on-chip ROM
H'000000
ROM: 512 Kbytes, RAM: 40 Kbytes
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
H'000000
On-chip ROM
H'07FFFF
H'080000
H'F7FFFF
H'F80000
H'FBFFFF
H'FC0000
H'FEFFFF
H'FF0000
H'FF07FF
H'FF0800
On-chip ROM
H'07FFFF
External address
space
256 Kbytes
extended area
External address
space
Reserved area
H'FF0000
H'FF07FF
H'FF0800
On-chip RAM*
(36 Kbytes)
Reserved area
On-chip RAM
(36 Kbytes)
H'FF97FF
H'FF9800
H'FF97FF
H'FF9800
Reserved area
Reserved area *
H'FFDFFF
H'FFE000
H'FFE07F
H'FFE080
H'FFEFFF
H'FFF000
H'FFF7FF
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
External address
space
On-chip RAM*
(3,968 bytes)
External address
space
(IOS extended area)
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM*
(128 bytes)
Internal I/O
registers 1
H'FFBFFF
H'FFE080
H'FFEFFF
On-chip RAM
(3,968 bytes)
H'FFF800
H'FFFE3F
H'FFFE40
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O
registers 3
Internal I/O
registers 2
On-chip RAM
(128 bytes)
Internal I/O
registers 1
Notes: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.1 Address Map
Rev. 2.00 Aug. 20, 2008 Page 69 of 1198
REJ09B0403-0200
Section 3 MCU Operating Modes
Rev. 2.00 Aug. 20, 2008 Page 70 of 1198
REJ09B0403-0200
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, illegal instruction,
or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Illegal instruction
Started by execution of an undefined code.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Trap instruction
Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Low
Rev. 2.00 Aug. 20, 2008 Page 71 of 1198
REJ09B0403-0200
Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.
Table 4.2
Exception Handling Vector Table
Vector Address
Exception Source
Vector Number
Advanced Mode
Reset
0
H'000000 to H'000003
Reserved for system use
1

3
H'000004 to H'000007
|
H'00000C to H'00000F
Illegal instruction
4
H'000010 to H'000013
Reserved for system use
5
H'000014 to H'000017
6
H'000018 to H'00001B
External interrupt (NMI)
7
H'00001C to H'00001F
Trap instruction (four sources)
8
H'000020 to H'000023
9
H'000024 to H'000027
10
H'000028 to H'00002B
11
H'00002C to H'00002F
Reserved for system use
12

15
H'000030 to H'000033
|
H'00003C to H'00003F
External interrupt IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
16
17
18
19
20
21
22
23
H'000040 to H'000043
H'000044 to H'000047
H'000048 to H'00004B
H'00004C to H'00004F
H'000050 to H'000053
H'000054 to H'000057
H'000058 to H'00005B
H'00005C to H'00005F
Internal interrupt*
24

29
H'000060 to H'000063

H'000074 to H'000077
Rev. 2.00 Aug. 20, 2008 Page 72 of 1198
REJ09B0403-0200
Section 4 Exception Handling
Vector Address
Exception Source
Vector Number
Advanced Mode
Reserved for system use
30
H'000078 to H'00007B


33
H'000084 to H'000087
Internal interrupt*
34

55
H'000088 to H'00008B

H'0000DC to H'0000DF
External interrupt IRQ8
56
H'0000E0 to H'0000E3
IRQ9
57
H'0000E4 to H'0000E7
IRQ10
58
H'0000E8 to H'0000EB
IRQ11
59
H'0000EC to H'0000EF
IRQ12
60
H'0000F0 to H'0000F3
IRQ13
61
H'0000F4 to H'0000F7
IRQ14
62
H'0000F8 to H'0000FB
IRQ15
63
H'0000FC to H'0000FF
64

119
H'000100 to H'000103

H'0001DC to H'0001DF
Internal interrupt*
Note:
*
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Table.
Rev. 2.00 Aug. 20, 2008 Page 73 of 1198
REJ09B0403-0200
Section 4 Exception Handling
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip
can also be reset by overflow of the watchdog timer. For details, see section 12, Watchdog Timer
(WDT).
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit in CCR is set to 1.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
Rev. 2.00 Aug. 20, 2008 Page 74 of 1198
REJ09B0403-0200
Section 4 Exception Handling
Vector
fetch
Internal
processing
Prefetch of first
program instruction
φ
RES
Internal address bus
(1) U
(1) L
(3)
Internal read signal
High
Internal write signal
Internal data bus
(2) U
(2) L
(4)
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2)U + (2)L)
(4) First program instruction
Figure 4.1 Reset Sequence
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR, MSTPCRA, and
SUBMSTPB) are initialized, and all modules except the DTC operate in module stop mode.
Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read
from and write to these registers, clear module stop mode.
Rev. 2.00 Aug. 20, 2008 Page 75 of 1198
REJ09B0403-0200
Section 4 Exception Handling
4.4
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI and IRQ15 to IRQ0) and internal interrupt sources
from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see
section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
4.5
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3
Status of CCR after Trap Instruction Exception Handling
CCR
Interrupt Control Mode
I
UI
0
Set to 1
Retains value prior to
execution
1
Set to 1
Set to 1
Rev. 2.00 Aug. 20, 2008 Page 76 of 1198
REJ09B0403-0200
Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Advanced mode
SP
CCR
PC
(24 bits)
Figure 4.2 Stack Status after Exception Handling
Rev. 2.00 Aug. 20, 2008 Page 77 of 1198
REJ09B0403-0200
Section 4 Exception Handling
4.7
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed in words or longwords, and the value of the stack pointer (SP:
ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what
happens when the SP value is odd.
Address
SP
CCR
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
SP
H'FFFEFF
TRAPA instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7 executed
Data saved above SP
Contents of CCR lost
[Legend]
CCR:
PC:
R1L:
SP:
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0.
Figure 4.3 Operation When SP Value is Odd
Rev. 2.00 Aug. 20, 2008 Page 78 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels
can be set for each module for all interrupts except NMI.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR, and ICR, 3-level interrupt mask
control is performed.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Thirty-three external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQn (n = 15 to 0) and ExIRQn (n = 15 to 0).
• DTC control
The DTC can be activated by an interrupt request.
Rev. 2.00 Aug. 20, 2008 Page 79 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
CPU
INTM1, INTM0
SYSCR
NMIEG
NMI input
NMI input
IRQ input
IRQ input
ISR
ISCR
IER
Interrupt
request
Vector number
Priority level
determination
I, UI
CCR
Internal interrupt sources
SWDTEND to EINT
ICR
Interrupt controller
[Legend]
ICR:
ISCR:
IER:
ISR:
SYSCR:
Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Symbol
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ15 to IRQ0
ExIRQ15 to
ExIRQ0
Input
Maskable external interrupts
Rising edge, falling edge, or both edges, or level sensing can be
selected individually for each pin. Pin of IRQn or ExIRQn to input
IRQn (n = 15 to 0) interrupt can be selected.
Rev. 2.00 Aug. 20, 2008 Page 80 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense
port select registers (ISSR16 and ISSR), see section 8.3.1, IRQ Sense Port Select Register 16
(ISSR16), IRQ Sense Port Select Register (ISSR).
• Interrupt control registers A to D (ICRA to ICRD)
• Address break control register (ABRKCR)
• Break address registers A to C (BARA to BARC)
• IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, and ISCRL)
• IRQ enable registers (IER16 and IER)
• IRQ status registers (ISR16 and ISR)
5.3.1
Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI.
The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2.
Bit
Bit Name
7 to 0
ICRn7 to
IRCn0
Initial
Value
R/W
Description
All 0
R/W
Interrupt Control Level
0: Corresponding interrupt source is interrupt control level
0 (no priority)
1: Corresponding interrupt source is interrupt control level
1 (priority)
[Legend]
n:
A to D
Rev. 2.00 Aug. 20, 2008 Page 81 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Table 5.2
Correspondence between Interrupt Source and ICR
Register
Bit
Bit Name
ICRA
ICRB
ICRC
ICRD
7
ICRn7
IRQ0
A/D converter
SCI_3
IRQ8 to IRQ11
6
ICRn6
IRQ1
FRT
SCI_1
IRQ12 to IRQ15
5
4
ICRn5
ICRn4
IRQ2, IRQ3
IRQ4, IRQ5

TMR_X
SSU
IIC_0
EtherC

3
2
ICRn3
ICRn2
IRQ6, IRQ7
DTC
TMR_0
TMR_1
IIC_1
IIC_2, IIC_3

2
PECI*
1
0
ICRn1
ICRn0
WDT_0
WDT_1
TMR_Y
IIC_4, IIC_5
LPC
1
USB*
SCIF

[Legend]
n:
A to D
:
Reserved. The write value should always be 0.
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
5.3.2
Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit
Bit Name
Initial
Value
7
CMF
Undefined R
6 to 1

All 0
R
0
BIE
0
R/W
R/W
Rev. 2.00 Aug. 20, 2008 Page 82 of 1198
REJ09B0403-0200
Description
Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an address
break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
Reserved
These bits are always read as 0 and cannot be modified.
Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Section 5 Interrupt Controller
5.3.3
Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first
byte of an instruction exists should be set as a break address.
• BARA
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
A23 to A16
All 0
R/W
Addresses 23 to 16
The A23 to A16 bits are compared with A23 to A16 in the
internal address bus.
• BARB
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
A15 to A8
All 0
R/W
Addresses 15 to 8
The A15 to A8 bits are compared with A15 to A8 in the
internal address bus.
• BARC
Bit
Bit Name
Initial
Value
R/W
7 to 1
A7 to A1
All 0
R/W
Description
Addresses 7 to 1
The A7 to A1 bits are compared with A7 to A1 in the
internal address bus.
0

0
R
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 2.00 Aug. 20, 2008 Page 83 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or
pins ExIRQ15 to ExIRQ0.
• ISCR16H
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ15SCB
0
R/W
6
IRQ15SCA
0
R/W
IRQn Sense Control B
IRQn Sense Control A
5
IRQ14SCB
0
R/W
4
IRQ14SCA
0
R/W
3
IRQ13SCB
0
R/W
2
IRQ13SCA
0
R/W
1
IRQ12SCB
0
R/W
0
IRQ12SCA
0
R/W
00: Interrupt request generated at low level of IRQn* or
ExIRQn input
01: Interrupt request generated at falling edge of IRQn* or
ExIRQn input
10: Interrupt request generated at rising edge of IRQn* or
ExIRQn input
11: Interrupt request generated at both falling and rising
edges of IRQn* or ExIRQn input
(n = 15 to 12)
Note:
*
IRQn stands for IRQ15 to IRQ12.
• ISCR16L
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ11SCB
0
R/W
6
IRQ11SCA
0
R/W
IRQn Sense Control B
IRQn Sense Control A
5
IRQ10SCB
0
R/W
4
IRQ10SCA
0
R/W
3
IRQ9SCB
0
R/W
2
IRQ9SCA
0
R/W
1
IRQ8SCB
0
R/W
0
IRQ8SCA
0
R/W
00: Interrupt request generated at low level of IRQn* or
ExIRQn input
01: Interrupt request generated at falling edge of IRQn* or
ExIRQn input
10: Interrupt request generated at rising edge of IRQn* or
ExIRQn input
11: Interrupt request generated at both falling and rising
edges of IRQn* or ExIRQn input
(n = 11 to 8)
Note: *
IRQn stands for IRQ11 to IRQ8.
Rev. 2.00 Aug. 20, 2008 Page 84 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
• ISCRH
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ7SCB
0
R/W
6
IRQ7SCA
0
R/W
IRQn Sense Control B
IRQn Sense Control A
5
IRQ6SCB
0
R/W
4
IRQ6SCA
0
R/W
3
IRQ5SCB
0
R/W
2
IRQ5SCA
0
R/W
1
IRQ4SCB
0
R/W
0
IRQ4SCA
0
R/W
00: Interrupt request generated at low level of IRQn or
ExIRQn input
01: Interrupt request generated at falling edge of IRQn or
ExIRQn input
10: Interrupt request generated at rising edge of IRQn or
ExIRQn input
11: Interrupt request generated at both falling and rising
edges of IRQn or ExIRQn input
(n = 7 to 4)
IRQn stands for IRQ7 to IRQ4.
Note: *
• ISCRL
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
IRQn Sense Control B
IRQn Sense Control A
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
0
IRQ0SCA
0
R/W
00: Interrupt request generated at low level of IRQn or
ExIRQn input
01: Interrupt request generated at falling edge of IRQn or
ExIRQn input
10: Interrupt request generated at rising edge of IRQn or
ExIRQn input
11: Interrupt request generated at both falling and rising
edges of IRQn or ExIRQn input
(n = 3 to 0)
Note:
*
IRQn stands for IRQ3 to IRQ0.
Rev. 2.00 Aug. 20, 2008 Page 85 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.3.5
IRQ Enable Registers (IER16, IER)
The IER registers control the enabling and disabling of interrupt requests IRQ15 to IRQ0.
• IER16
Bit
Bit Name
7 to 0
IRQ15E to
IRQ8E
Initial
Value
R/W
Description
All 0
R/W
IRQn Enable (n = 15 to 8)
The IRQn interrupt request is enabled when this bit is 1.
• IER
Bit
Bit Name
7 to 0
IRQ7E to
IRQ0E
Initial
Value
R/W
Description
All 0
R/W
IRQn Enable (n = 7 to 0)
Rev. 2.00 Aug. 20, 2008 Page 86 of 1198
REJ09B0403-0200
The IRQn interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller
5.3.6
IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
• ISR16
Bit
Bit Name
7 to 0
IRQ15F to
IRQ8F
Initial
Value
R/W
Description
All 0
R/W
[Setting condition]
•
When the interrupt source selected by the ISCR16
registers occurs
[Clearing conditions]
•
When reading 1, then writing 0
•
When interrupt exception handling is executed when
low-level detection is set and IRQn* or ExIRQn input is
high
•
When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
(n = 15 to 8)
Note: *
IRQn stands for IRQ15 to IRQ8.
• ISR
Bit
Bit Name
7 to 0
IRQ7F to
IRQ0F
Initial
Value
R/W
Description
All 0
R/W
[Setting condition]
•
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
•
•
•
When reading 1, then writing 0
When interrupt exception handling is executed when
low-level detection is set and IRQn* or ExIRQn input is
high
When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
(n = 7 to 0)
Note: *
IRQn stands for IRQ7 to IRQ0.
Rev. 2.00 Aug. 20, 2008 Page 87 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.4
Interrupt Sources
5.4.1
External Interrupts
There are four external interrupts: NMI, IRQ15 to IRQ0. These interrupts can be used to restore
this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. Interrupts IRQ15 to IRQ0 have the following
features:
• The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an
independent vector address.
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, clear the
corresponding port DDR to 0 so that it is not used as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
Rev. 2.00 Aug. 20, 2008 Page 88 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
S
Q
IRQn interrupt
request
R
IRQn input or
ExIRQn* input
Clear signal
n = 15 to 0
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
5.4.2
Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
• The control level for each interrupt can be set by ICR.
• The DTC can be activated by an interrupt request from an on-chip peripheral module.
• An interrupt request that activates the DTC is not affected by the interrupt control mode or the
status of the CPU interrupt mask bits.
Rev. 2.00 Aug. 20, 2008 Page 89 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.5
Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are
given priority and processed before interrupt requests from modules that are set to interrupt
control level 0 (no priority).
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Name
Vector Address
Vector
Number Advanced Mode
ICR
Priority
External pin
NMI
7
H'00001C

High
IRQ0
16
H'000040
ICRA7
IRQ1
17
H'000044
ICRA6
IRQ2
IRQ3
18
19
H'000048
H'00004C
ICRA5
IRQ4
IRQ5
20
21
H'000050
H'000054
ICRA4
IRQ6
IRQ7
22
23
H'000058
H'00005C
ICRA3
DTC
SWDTEND (Software activation
data transfer end)
24
H'000060
ICRA2
WDT_0
WOVI0 (Interval timer)
25
H'000064
ICRA1
WDT_1
WOVI1 (Interval timer)
26
H'000068
ICRA0

Address break
27
H'00006C

A/D converter ADI (A/D conversion end)
28
H'000070
ICRB7
EVC
EVENTI
29
H'000074

TMR_X
CMIAX (Compare match A)
CMIBX (Compare match B)
OVIX (Overflow)
44
45
46
H'0000B0
H'0000B4
H'0000B8
ICRB4
FRT
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
52
53
54
H'0000D0
H'0000D4
H'0000D8
ICRB6
Rev. 2.00 Aug. 20, 2008 Page 90 of 1198
REJ09B0403-0200
Low
Section 5 Interrupt Controller
Origin of
Interrupt
Source
Name
Vector Address
Vector
Number Advanced Mode
IRQ8
IRQ9
IRQ10
IRQ11
56
57
58
59
IRQ12
IRQ13
IRQ14
IRQ15
TMR_0
ICR
Priority
H'0000E0
H'0000E4
H'0000E8
H'0000EC
ICRD7
High
60
61
62
63
H'0000F0
H'0000F4
H'0000F8
H'0000FC
ICRD6
CMIA0 (Compare match A)
CMIB0 (Compare match B)
OVI0 (Overflow)
64
65
66
H'000100
H'000104
H'000108
ICRB3
TMR_1
CMIA1 (Compare match A)
CMIB1 (Compare match B)
OVI1 (Overflow)
68
69
70
H'000110
H'000114
H'000118
ICRB2
TMR_Y
CMIAY (Compare match A)
CMIBY (Compare match B)
OVIY (Overflow)
72
73
74
H'000120
H'000124
H'000128
ICRB1
IIC_2
IICI2
76
H'000130
ICRC2
IIC_3
IICI3
78
H'000138
SCI_3
ERI3 (Reception error 3)
RXI3 (Reception completion 3)
TXI3 (Transmission data empty 3)
TEI3 (Transmission end 3)
80
81
82
83
H'000140
H'000144
H'000148
H'00014C
ICRC7
SCI_1
ERI1 (Reception error 1)
RXI1 (Reception completion 1)
TXI1 (Transmission data empty 1)
TEI1 (Transmission end 1)
84
85
86
87
H'000150
H'000154
H'000158
H'00015C
ICRC6
SSU
ERIS (Reception error S)
88
RXIS (Reception completion S)
89
TXIS (Transmission data empty S)
90
H'000160
H'000164
H'000168
ICRC5
SCIF
SCIFI
92
H'000170
ICRD1
IIC_0
IICI0
94
H'000178
ICRC4
IIC_1
IICI1
98
H'000188
ICRC3
IIC_4
IICI4
100
H'000190
ICRB0
IIC_5
IICI5
102
H'000198
ICRB0
LPC
ERR1(transfer error, etc.)
IBFI1 (IDR1 reception completion)
IBFI2 (IDR2 reception completion)
IBFI3 (IDR3 reception completion)
104
105
106
107
H'0001A0
H'0001A4
H'0001A8
H′0001AC
ICRC1
External pin
Low
Rev. 2.00 Aug. 20, 2008 Page 91 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Origin of
Interrupt
Source
Name
Vector Address
Vector
Number Advanced Mode
PEWFCSEI
PERFCSEI
PETEI
108
109
110
USB*1 (only in RESUME
the H8S/2472) USBINT0
USBINT2
USBINT3
USBINT1
EtherC
PECI*
2
EINT
ICR
Priority
H'0001B0
H'0001B4
H'0001B8
ICRD2
High
114
115
116
117
118
H'0001C8
H'0001CC
H'0001D0
H'0001D4
H'0001D8
ICRC0
119
H'0001DC
ICRD5
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the H8S/2462 Group.
Rev. 2.00 Aug. 20, 2008 Page 92 of 1198
REJ09B0403-0200
Low
Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1.
Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address
break interrupts are always accepted except for in reset state or in hardware standby mode. The
interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes.
Table 5.4
Interrupt Control Modes
SYSCR
Interrupt
Control
Mode
INTM1
INTM0
Priority
Setting
Registers
Interrupt
Mask Bits
0
0
ICR
I
Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
1
ICR
I, UI
3-level interrupt mask control is
performed by the I and UI bits. Priority
levels can be set with ICR.
0
1
Description
Figure 5.3 shows a block diagram of the priority decision circuit.
I
UI
ICR
Interrupt
source
Interrupt
acceptance control
and 3-level mask
control
Default priority
determination
Vector
number
Interrupt control modes
0 and 1
Figure 5.3 Block Diagram of Interrupt Control Operation
Rev. 2.00 Aug. 20, 2008 Page 93 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR and ICR (control level).
Table 5.5 shows the interrupts selected in each interrupt control mode.
Table 5.5
Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode I
UI
Selected Interrupts
0
0
*
All interrupts (interrupt control level 1 has
priority)
1
*
NMI and address break interrupts
0
*
All interrupts (interrupt control level 1 has
priority)
1
0
NMI, address break, and interrupt control level 1
interrupts
1
NMI and address break interrupts
1
[Legend]
*
Don't care
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
Rev. 2.00 Aug. 20, 2008 Page 94 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control Mode
INTM1
INTM0
0
0
0
1
1
Interrupt Acceptance Control
3-Level Control
Setting
I
UI
ICR
Default Priority
Determination
T (Trace)
O
IM

PR
O

O
IM
IM
PR
O

[Legend]
O:
Interrupt operation control performed
IM:
Used as an interrupt mask bit
PR:
Sets priority
:
Not used
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupts other than NMI are masked by ICR and the I bit of the CCR
in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller accepts an
interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request
with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt
request with the highest priority is accepted according to the priority order, an interrupt
handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, only NMI and address break interrupt requests are accepted by
the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted. KIN, WUE, and EVENTI interrupts are enabled or disabled
by the I bit.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
Rev. 2.00 Aug. 20, 2008 Page 95 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution state
Interrupt generated?
No
Yes
Yes
NMI
No
No
An interrupt with interrupt
control level 1?
Pending
Yes
No
No
IRQ0
Yes
IRQ0
No
Yes
IRQ1
No
IRQ1
Yes
Yes
EINT
EINT
Yes
Yes
I=0
No
Yes
Save PC and CCR
I
1
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 2.00 Aug. 20, 2008 Page 96 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
• An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
to 0. When the I bit is set to 1, the interrupt request is held pending.
EVENTI, KIN, and WUE interrupts are enabled or disabled by the I bit.
• An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
For instance, the state when the interrupt enable bit corresponding to each interrupt is set to 1, and
ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are
set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown
below. Figure 5.6 shows a state transition diagram.
• All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 >
IRQ1 > address break …)
• Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
0.
• Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
I
All interrupt requests
are accepted
I
I
0
0
1, UI
Only NMI, address break, and
interrupt control level 1 interrupt
requests are accepted
0
UI
0
Exception handling
execution or UI 1
Exception handling execution
or I 1, UI 1
Only NMI and address break
interrupt requests are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1
Rev. 2.00 Aug. 20, 2008 Page 97 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Figure 5.6 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or
when the I bit is set to 1 while the UI bit is cleared to 0.
An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.
When both the I and UI bits are set to 1, only NMI and address break interrupt requests are
accepted, and other interrupts are held pending.
When the I bit is cleared to 0, the UI bit is not affected.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address
break interrupts.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00 Aug. 20, 2008 Page 98 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Program execution state
No
Interrupt generated?
Yes
Yes
NMI
No
No
An interrupt with interrupt
control level 1?
Pending
Yes
IRQ0
Yes
No
No
IRQ0
No
Yes
IRQ1
No
IRQ1
Yes
Yes
EINT
EINT
Yes
Yes
I=0
No
I=0
Yes
No
UI = 0
No
Yes
Yes
Save PC and CCR
I
1, UI
1
Read vector address
Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 1
Rev. 2.00 Aug. 20, 2008 Page 99 of 1198
REJ09B0403-0200
REJ09B0403-0200
Rev. 2.00 Aug. 20, 2008 Page 100 of 1198
Figure 5.7 Interrupt Exception Handling
(2) (4)
(3)
(5)
(7)
(1)
Internal
data bus
(1)
(2)
(4)
(3)
Instruction prefetch address (Instruction is not executed.
Address is saved as PC contents, becoming return address.)
Instruction code (not executed)
Instruction prefetch address (Instruction is not executed.)
SP – 2
SP – 4
Internal write
signal
Internal read
signal
Internal
address bus
Interrupt
request signal
φ
Instruction
prefetch
Internal
processing
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
(7)
(8)
(9)
(10)
Vector fetch
(12)
(11)
Internal
processing
Saved PC and CCR
Vector address
Starting address of interrupt-handling routine (contents of vector address)
Starting address of interrupt-handling routine ((13) = (10) (12))
First instruction in interrupt-handling routine
(6)
Stack access
(14)
(13)
Prefetch of instruction in
interrupt-handling routine
5.6.3
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.7 are explained in table 5.8.
Table 5.7
No.
1
Interrupt Response Times
Execution Status
Advanced Mode
Interrupt priority determination*
1
3
2
2
Number of wait states until executing instruction ends*
1 to (19 + 2·SI)
3
PC, CCR stack save
2·SK
4
Vector fetch
2·SI
3
5
Instruction fetch*
6
Internal processing*
2·SI
4
2
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
Table 5.8
12 to 32
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6 + 2m
2
3+m
Branch address read SJ
Stack manipulation SK
[Legend]
m:
Number of wait states in external device access.
Rev. 2.00 Aug. 20, 2008 Page 101 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DTC
• Both of the above
For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer
Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller.
Interrupt
request
IRQ
interrupt
On-chip
peripheral
module
Interrupt source
clear signal
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC
Clear signal
DTVECR
SWDTE
clear signal
Interrupt controller
Determination of
priority
CPU interrupt
request vector
number
CPU
I, UI
Figure 5.8 Interrupt Control for DTC
The interrupt controller has three main functions in DTC control.
(1)
Selection of Interrupt Source
It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of
DTCERA to DTCERF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0
and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of
MRB in the DTC. When the DTC performs the specified number of data transfers and the transfer
counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt
request is sent to the CPU.
Rev. 2.00 Aug. 20, 2008 Page 102 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
(2)
Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.5, Location of Register Information and DTC
Vector Table, for the respective priorities.
(3)
Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to
the settings of the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in
the DTC.
Table 5.9
Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Source Selection/Clearing Control
DTCE
DISEL
0
X
×
∆
1
0
∆
×
1
DTC
CPU
∆
[Legend]
∆:
The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
:
The relevant interrupt is used. The interrupt source is not cleared.
×:
The relevant interrupt cannot be used.
X:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 103 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.7
Usage Notes
5.7.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.9
shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
TCR write cycle
by CPU
CMIA exception handling
φ
Internal
address bus
TCR address
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.9 Conflict between Interrupt Generation and Disabling
Rev. 2.00 Aug. 20, 2008 Page 104 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.7.3
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
5.7.4
EEPMOV.W
MOV.W
R4,R4
BNE
L1
IRQ Status Registers (ISR16, ISR)
Since IRQnF may be set to 1 according to the pin status after a reset, the ISR16 and the ISR
should be read after a reset, and then write 0 in IRQnF (n = 15 to 0).
Rev. 2.00 Aug. 20, 2008 Page 105 of 1198
REJ09B0403-0200
Section 5 Interrupt Controller
Rev. 2.00 Aug. 20, 2008 Page 106 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU, data transfer controller (DTC), and
Ethernet controller direct memory access controller (E-DMAC).
6.1
Features
• Extended modes
Two modes for external extension
Normal extended mode: Normal extension
(when ADMXE = 0 in SYSCR2 and OBE = 0 in PTCNT0)
Glueless extension
(when ADMXE = 0 in SYSCR2 and OBE = 1 in PTCNT0)
Address-data multiplex extended mode: Multiplex extension (when ADMXE = 1 in SYSCR2)
• Extended area division
Possible in normal extended mode
The external address space can be accessed as basic extended areas.
A 256-Kbyte extended area can be set and controlled independently of basic extended areas.
• Address pin reduction
In normal extended mode:
A 256-Kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address
pins and the CS256 signal.
A 2-Kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins
and the IOS signal.
In address-data multiplex extended mode:
The external address space can be accessed as the following two extended areas.
H'F80000 to H'F8FFFF
64 Kbytes
256-Kbyte extended area
H'FFF000 to H'FFF7FF
2 Kbytes
IOS extended area
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data
input/output pins.
• Control address hold signal and area select signal polarity
The output polarity of IOS, CS256, and AH can be inverted by the PNCCS and PNCAH bits in
LPWRCR
Rev. 2.00 Aug. 20, 2008 Page 107 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
• Multiplex bus interface
No Wait Inserted
Wait Inserted
Address
Data
Address
Data
2 states*
2 states
2 states*
(3 + wait) states
IOS extended area 2 states*
2 states
2 states*
(3 + wait) states
256-Kbyte
extended area
Note:
*
A wait cycle is inserted by the setting of the WC22 bit.
• Basic bus interface
2-state access or 3-state access can be selected for each area.
Program wait states can be inserted for each area.
• Burst ROM interface
In normal extended mode
A burst ROM interface can be set for basic extended areas.
1-state access or 2-state access can be selected for burst access.
• Idle cycle insertion
In normal extended mode
An idle cycle can be inserted for external write cycles immediately after external read cycles.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and E-DMAC.
Rev. 2.00 Aug. 20, 2008 Page 108 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus
controller
External bus control signals
Internal control signals
BCR
BCR2
WSCR
WSCR2
Internal data bus
Bus mode signal
Wait
controller
WAIT
Bus arbiter
CPU bus request signal
DTC bus request signal
E-DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
E-DMAC bus acknowledge signal
[Legend]
BCR:
BCR2:
WSCR:
WSCR2:
Bus control register
Bus control register 2
Wait state control register
Wait state control register 2
Figure 6.1 Block Diagram of Bus Controller
Rev. 2.00 Aug. 20, 2008 Page 109 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Symbol
I/O
Function
AS
Output
Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-Kbyte
extended area is accessed (the CS256E bit in SYSCR is 1).
IOS
Output
Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
CS256
Output
Chip select signal indicating that the 256-Kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
RD
Output
Strobe signal indicating that the external address space is
being read.
HWR
Output
Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is valid.
LWR
Output
Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is valid.
WAIT
Input
Wait request signal when accessing the external space.
WR
Output
Strobe signal indicating that the external address space is
being written to.
HBE
Output
Strobe signal indicating that the external address space is
being accessed, and the upper half (D15 to D8) of the data
bus is valid.
LBE
Output
Strobe signal indicating that the external address space is
being accessed, and the lower half (D7 to D0) of the data
bus is valid.
AH
Output
Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
AD15 to AD0
Input/Output
Address output and data input/output pins for address-data
multiplex extension.
Rev. 2.00 Aug. 20, 2008 Page 110 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.3
Register Descriptions
The following registers are provided for the bus controller. For the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR). For port control register 0
(PTCNT0), see section 8.3.2, Port Control Register 0 (PTCNT0).
• Bus control register (BCR)
• Bus control register 2 (BCR2)
• Wait state control register (WSCR)
• Wait state control register 2 (WSCR2)
• System control register 2 (SYSCR2)
6.3.1
Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space and the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit
Bit Name
Initial
Value
R/W
Description
7

1
R/W
Reserved
The initial value should not be changed.
6
ICIS
1
R/W
Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle cycle
between successive external read and external write
cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
5
BRSTRM
0
R/W
Valid only in the normal extended mode.
Burst ROM Enable
Selects the bus interface for the external address space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR is set to 1, burst ROM
interface cannot be selected for the 256-Kbyte extended
area.
Rev. 2.00 Aug. 20, 2008 Page 111 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
4
BRSTS1
1
R/W
Valid only in the normal extended mode.
Burst Cycle Select 1
Selects the number of states in the burst cycle of the burst
ROM interface.
0: 1 state
1: 2 states
3
BRSTS0
0
R/W
Valid only in the normal extended mode.
Burst Cycle Select 0
Selects the number of words that can be accessed by
burst access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
2

0
R/W
Reserved
The initial value should not be changed.
1
IOS1
1
R/W
0
IOS0
1
R/W
IOS Select 1 and 0
Select the address range where the IOS signal is output.
See table 6.12.
Rev. 2.00 Aug. 20, 2008 Page 112 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.3.2
Bus Control Register 2 (BCR2)
BCR2 is used to specify the access mode for the extended area.
Bit
Bit Name
Initial
Value
R/W
7, 6

All 0
R/W
Description
Reserved
The initial value should not be changed.
5, 4

All 1
R/W
Reserved
The initial value should not be changed.
3
ADFULLE
0
R/W
Address Output Full Enable
Controls the address output, A23 to A21, in access to the
extended area. See section 8, I/O Ports. This is not
supported while ADMXE = 1.
2
EXCKS
0
R/W
External Extension Clock Select
Selects the operating clock used in external extended
area access.
0: Medium-speed clock is selected as the operating clock
1: System clock (φ) is selected as the operating clock.
The operating clock is switched in the bus cycle prior to
external extended area access.
1

1
R/W
Reserved
The initial value should not be changed.
0

0
R/W
Reserved
The initial value should not be changed.
Rev. 2.00 Aug. 20, 2008 Page 113 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.3.3
Wait State Control Register (WSCR)
WSCR is used to specify the data bus width, the number of access states, the wait mode, and the
number of wait states for access to external address spaces (basic extended area and 256-Kbyte
extended area). The bus width and the number of access states for internal memory and internal
I/O registers are fixed regardless of the WSCR settings.
Bit
Bit Name
Initial
Value
R/W
Description
7
ABW256
1
R/W
256-Kbyte Extended Area Bus Width Control
Selects the bus width for access to the 256-Kbyte
extended area when the CS256E bit in SYSCR is set to 1.
0: 16-bit bus
1: 8-bit bus
6
AST256
1
R/W
256-Kbyte Extended Area Access State Control
Selects the number of states for access to the 256-Kbyte
extended area when the CS256E bit in SYSCR is set to 1.
This bit also enables or disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
5
ABW
1
R/W
Basic Extended Area Bus Width Control
Selects the bus width for access to the basic extended
area.
0: 16-bit bus
1: 8-bit bus
When the CS256E bit in SYSCR is set to 1, this bit setting
is ignored in access to the 256-Kbyte extended area.
Rev. 2.00 Aug. 20, 2008 Page 114 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
4
AST
1
R/W
Basic Extended Area Access State Control
Selects the number of states for access to the basic
extended area. This bit also enables or disables wait-state
insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion
enabled
When the CS256E bit in SYSCR is set to 1, this bit setting
is ignored in access to the 256-Kbyte extended area.
3
WMS1
0
R/W
Basic Extended Area Wait Mode Select 1 and 0
2
WMS0
0
R/W
Selects the wait mode for access to the basic extended
area when the AST bit is set to 1.
00: Program wait mode
01: Wait disabled mode
10: Pin wait mode
11: Pin auto-wait mode
When the CS256E bit in SYSCR is set to 1, this bit setting
is ignored in access to the 256-Kbyte extended area.
1
WC1
1
R/W
Basic Extended Area Wait Count 1 and 0
0
WC0
1
R/W
Selects the number of program wait states to be inserted
when the basic extended area is accessed when the AST
bit is set to 1. The program wait state is only inserted into
data cycles.
00: Program wait state is not inserted
01: 1 program wait state is inserted
10: 2 program wait states are inserted
11: 3 program wait states are inserted
When the CS256E bit in SYSCR is set to 1, this bit setting
is ignored in access to the 256-Kbyte extended area.
Rev. 2.00 Aug. 20, 2008 Page 115 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.3.4
Wait State Control Register 2 (WSCR2)
WSCR2 is used to specify the wait mode and number of wait states in access to the 256-Kbyte
extended area.
Bit
Bit Name
Initial
Value
R/W
Description
7
WMS10
0
R/W
256-Kbyte Extended Area Wait Mode Select 0
Selects the wait mode for access to the 256-Kbyte
extended area when the CS256E bit in SYSCR and the
AST256 bit in WSCR are set to 1.
0: Program wait mode
1: Wait disabled mode
6
WC11
1
R/W
256-Kbyte Extended Area Wait Count 1 and 0
5
WC10
1
R/W
Selects the number of program wait states to be inserted
into the data cycle for access to the 256-Kbyte extended
area when the CS256E bit in SYSCR and the AST256 bit
in WSCR are set to 1.
00: Program wait state is not inserted
01: 1 program wait state is inserted
10: 2 program wait states are inserted
11: 3 program wait states are inserted
4

All 0
R/W
3
Rev. 2.00 Aug. 20, 2008 Page 116 of 1198
REJ09B0403-0200
Reserved
Section 6 Bus Controller (BSC)
• When ADMXE = 0
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0

All 1
R/W
Reserved
• When ADMXE = 1
Bit
Bit Name
Initial
Value
R/W
Description
2
WC22
1
R/W
Address-Data Multiplex Extended Area Address Cycle
Wait Count 2
Selects the number of program wait states to be inserted
into the address cycle for access to the address-data
multiplex extended area.
0: Program wait state is not inserted
1: 1 program wait state is inserted in the address cycle
1, 0
6.3.5

All 1
R/W
Reserved
System Control Register 2 (SYSCR2)
SYSCR2 controls the address-data multiplex operation.
Bit
Bit Name
7 to 4 
Initial Value
R/W
All 0
R/W
Description
Reserved
The initial value should not be changed.
3
ADMXE
0
R/W
Address-Data Multiplex Bus Interface Enable
0: Normal extended bus interface
1: Address data multiplex extended bus interface
2 to 0 
All 0
R/W
Reserved
The initial value should not be changed.
Rev. 2.00 Aug. 20, 2008 Page 117 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.4
Bus Control
6.4.1
Bus Specifications
The external address space bus specifications consist of three elements: bus width, the number of
access states, and the wait mode and the number of program wait states. The bus width and the
number of access states for on-chip memory and internal I/O registers are fixed, and are not
affected by the bus controller settings.
(1)
In Normal Extended Mode
(a)
Bus Width
A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR.
(b)
Number of Access States
Two or three access states can be selected via the AST and AST256 bits in WSCR. When the 2state access space is designated, wait-state insertion is disabled.
In the burst ROM interface, the number of access states for the basic extended area is determined
regardless of the AST bit setting.
(c)
Wait Mode and Number of Program Wait States
When the basic extended area is specified as a 3-state access space by the AST bit in WSCR, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected.
When the 256-Kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. From 0 to 3 program wait states can
be selected.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC are to be delayed.
Tables 6.2 to 6.5 show each bit setting and external address space division in the address ranges of
the external address space, and the bus specifications for the basic bus interface of each area.
Rev. 2.00 Aug. 20, 2008 Page 118 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(d)
Glueless Extension
Setting the OBE bit in PTCNT0 selects glueless extension, which uses the RD, WR, HBE, and
LBE signals to allow connection to the external space without adding an external circuit.
Table 6.2
Address Ranges and External Address Spaces
Area
Address Range
H'080000 to H'F7FFFF
(15 Mbytes)
H'F80000 to H'FBFFFF
(256 Kbytes)
Basic Extended Area
256-Kbyte Extended Area

: No condition
∆: When CS256E = 0, used as
basic extended area.
256-Kbyte extended area
H'FC0000 to H'FEFFFF
(192 Kbytes)
H'FF0800 to H'FFBFFF
(46 Kbytes)
When WAIT pin function is not
selected while CS256E = 1,
CS256 is output and address
pins A17 to A0 are used.

: No condition
∆: When RAME = 0, used as
basic extended area.

H'FFC000 to H'FFDFFF
(8 Kbytes)
: No condition

H'FFE000 to H'FFE07F
(128 bytes)
: No condition.

H'FFE080 to H'FFEFFF
(3968 bytes)
H'FFF000 to H'FFF7FF
(2 Kbytes)
H'FFFF00 to H'FFFF7F
(128 bytes)
∆: When RAME = 0, used as
basic extended area.

No condition

When IOSE = 1, IOS is
output and address pins A10
to A0 are used.
∆ When RAME = 0, used as
basic extended area.

[Legend]
:
This address range is unconditionally accessed as the basic extended area.
∆:
Condition for making this address range accessed as the basic extended area.
:
This address range cannot be used as part of a 256-Kbyte extended area.
Rev. 2.00 Aug. 20, 2008 Page 119 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Table 6.3
Bit Settings and Bus Specifications of Basic Bus Interface
Areas
BRSTRM
CS256E
Basic Extended Area
256-Kbyte Extended Area
0
0
Used as basic extended area
1
Basic extended area
ABW, AST,
WMS1, WMS0,
WC1, WC0
0
Burst ROM interface*
1
ABW, AST, WMS0, WC1, WC0, ABW256, AST256, WMS10,
BRSTS1, BRSTS0
WC11, WC10
1
Note:
ABW256, AST256, WMS10,
WC11, WC10
Used as burst ROM interface
In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the
number of full access states (wait can be inserted) is specified by the AST bit in WSCR,
and the number of access cycles in burst access is specified regardless of the AST bit
setting.
*
Table 6.4
Bus Specifications for Basic Extended Area/Basic Bus Interface
Bus Specifications
ABW
AST
WMS1
WMS0
WC1
WC0
Bus Width
Number of
Access
States
0
0
X
X
X
X
16
2
1
0
1
X
X
16
0
0
Other than
WMS1 = 0 and
WMS0 = 1
1
1
Number of
Program
Wait
States
0
3
0
3
0
1
1
0
2
1
3
0
X
X
X
X
8
2
0
1
0
1
X
X
8
3
0
0
0
3
0
Other than
WMS1 = 0 and
WMS0 = 1
1
[Legend]
X:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 120 of 1198
REJ09B0403-0200
1
1
0
2
1
3
Section 6 Bus Controller (BSC)
Table 6.5
Bus Specifications for 256-Kbyte Extended Area/Basic Bus Interface
Bus Specifications
Number of
Program Wait
States
ABW256
AST256
WMS10
WC11
WC10
Bus Width
Number of
Access States
0
0
X
X
X
16
2
0
1
1
X
X
16
3
0
0
0
0
3
0
1
1
1
1
0
2
1
3
0
X
X
X
8
2
0
1
1
X
X
8
3
0
0
0
0
3
0
1
1
1
0
2
1
3
[Legend]
X:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 121 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(2)
In Address-Data Multiplex Extended Mode
(a)
Bus Width
A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR.
(b)
Number of Access States
Two or three states can be selected for data access via the AST and AST256 bits in WSCR. When
the 2-state access space is designated, wait-state insertion is disabled.
(c)
Wait Mode and Number of Program Wait States
• IOS Extended Area
When the IOS extended area is specified as a 3-state access space by the AST bit in WSCR,
the wait mode and the number of program wait states to be inserted automatically is selected
by the WMS1, WMS0, WC1, and WC0 bits in WSCR. Zero or one program wait state can be
inserted into address cycle. From zero to three program wait states can be selected for data
cycle.
• 256-Kbyte Extended Area
When the 256-Kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. Zero or one program wait state
can be inserted into address cycle. From zero to three program wait states can be selected for
data cycle.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC, are to be delayed.
Tables 6.6 to 6.11 show address-data multiplex address space and the bus specifications for the
basic bus interface of each area.
Rev. 2.00 Aug. 20, 2008 Page 122 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Table 6.6
Address-Data Multiplex Address Spaces
Address Range
Address-Data Multiplex Area
H'080000 to H'F7FFFF
(15 Mbytes)

No condition
256-Kbyte extended area
H'F80000 to H'F8FFFF
O
When the WAIT pin function is not selected and CS256E
= 1, CS256 is output and address AD15 to AD0 or AD7 to
AD0 are used.
256-Kbyte extended area
H'F90000 to H'F9FFFF
(64 Kbytes)

No condition
256-Kbyte extended area
H'FA0000 to H'FAFFFF
(64 Kbytes)

No condition
256-Kbyte extended area
H'FB0000 to H'FBFFFF
(64 Kbytes)

No condition
H'FC0000 to H'FFBFFF
(240 Kbytes)

No condition
H'FFC000 to H'FFDFFF
(8 Kbytes)

No condition
H'FFE000 to H'FFEFFF

No condition
IOS extended area
H'FFF000 to H'FFF7FF
(2 Kbytes)
O
When IOSE = 1, IOS is output and address pins AD15 to
AD0 or AD7 to AD0 are used.
H'FFFF00 to H'FFFF7F
(128 bytes)

No condition
(64 Kbytes)
(4 Kbytes)
[Legend]
:
This address range cannot be used as the address-data multiplex address space.
O:
Condition for making this address range accessed as the address-data multiplex address
space.
Rev. 2.00 Aug. 20, 2008 Page 123 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Table 6.7
Bit Settings and Bus Specifications of Basic Bus Interface
Area
IOSE
CS256E
IOS Extended Area
256-Kbyte Extended Area
1
0
ABW, AST, WMS1, WMS0,
WC1, WC0



1
0
0
ABW256, AST256, WMS10,
WC11, WC10
1
Table 6.8
ABW256, AST256, WMS10,
WC11, WC10
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Address
Cycle)
AST
WMS1
WMS0
WC22
WC1
WC0
Number of
Access
States



0


2
1


Table 6.9
Number of
Program
Wait States
0
1
Bus Specifications for IOS Extended Area/Multiplex Bus Interface (Data Cycle)
AST
WMS1
WMS0
WC1
WC0
Number of
Access
States
0




2
0
1
0
1


3
0
0
3
Other than WMS1 = 0 and 0
WMS0 = 1
1
Rev. 2.00 Aug. 20, 2008 Page 124 of 1198
REJ09B0403-0200
Number of
Program
Wait States
0
1
1
0
2
1
3
Section 6 Bus Controller (BSC)
Table 6.10 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Address Cycle)
AST256
WMS10
WC22
WC11
WC10
Number of
Access
States


0


2
1


Number of
Program
Wait States
0
1
Table 6.11 Bus Specifications for 256-Kbyte Extended Area/Multiplex Bus Interface
(Data Cycle)
AST256
WMS1
WC1
WC0
Number of
Program Wait
Number of
Access States States
0



2
0
1
1


3
0
0
0
0
3
0
1
1
1
0
2
1
3
6.4.2
Advanced Mode
The external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS
pin as an I/O strobe pin. The 256-Kbyte extended area (H'F80000 to H'FBFFFF) can be accessed
by the CS256 pin function.
The external address space is initialized as the basic bus interface and a 3-state access space. In
mode 2, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their
reserved areas is specified as the external address space. The on-chip RAM and its reserved area
are enabled when the RAME bit in SYSCR is set to 1, and disabled when the RAME bit is cleared
to 0. Addresses H'FF0800 to H'FFBFFF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F in
the on-chip RAM area and its reserved area are always specified as the external address space.
Rev. 2.00 Aug. 20, 2008 Page 125 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.4.3
I/O Select Signals
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding
external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Bus cycle
T1
T2
T3
φ
Address bus
External addresses selected by IOS
IOS
Figure 6.2 IOS Signal Output Timing
Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In the extended
mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE
bit to 1. For details, see section 8, I/O Ports.
The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR,
as shown in table 6.12.
Table 6.12 Address Range for IOS Signal Output
IOS1
IOS0
IOS Signal Output Range
0
0
H'FFF000 to H'FFF03F
1
H'FFF000 to H'FFF0FF
0
H'FFF000 to H'FFF3FF
1
H'FFF000 to H'FFF7FF
1
Rev. 2.00 Aug. 20, 2008 Page 126 of 1198
REJ09B0403-0200
(Initial value)
Section 6 Bus Controller (BSC)
6.5
Bus Interface
The normal extended bus interface enables direct connection to ROM and SRAM. For details on
selection of the bus specifications for the basic extended area and 256-Kbyte extended area, see
table 6.5.
The address-data multiplex extended bus interface enables direct connection to products that
supports this bus interface. For details on selection of the bus specifications for the IOS extended
area and 256-Kbyte extended area, see tables 6.8 to 6.11.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or
lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed,
according to the bus specifications for the area being accessed (8-bit access space or 16-bit access
space) and the data size.
(1)
8-Bit Access Space
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
The lower data bus (AD7 to AD0) is used in address-data multiplex extended mode.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
Longword
size
7
0
1st bus cycle
15
8
2nd bus cycle
7
0
1st bus cycle
31
24
2nd bus cycle
23
16
3rd bus cycle
15
8
4th bus cycle
7
0
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
Rev. 2.00 Aug. 20, 2008 Page 127 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(2)
16-Bit Access Space
Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus (D7 to D0/AD7 to AD0)
are used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for even addresses, and the lower data bus for odd
addresses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
· Even address
Byte size
· Odd address
8
7
0
15
8 7
0
1st bus cycle
31
24 23
16
2nd bus cycle
15
8 7
0
Word size
Longword
size
15
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)
Rev. 2.00 Aug. 20, 2008 Page 128 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.5.2
Valid Strobes
Table 6.13 shows the data buses used and valid strobes for each access space.
In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the
HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.13 Data Buses Used and Valid Strobes
Area
8-bit access
space
Access
Size
Read/
Write
Address
Valid
Strobe
Lower Data
Upper Data Bus Bus (D7 to
D0/AD7 to
(D15 to D8/
AD15 to AD8)
AD0)
Byte
Read

RD
Valid
Ports or others
Write

HWR
Read

RD
Ports or others
Valid
Write

HWR
Read
Even
RD
Valid
Invalid
Invalid
Valid
8-bit access
Byte
space
(in addressdata multiplex
extended
mode)
16-bit access
space
Byte
Odd
Even
HWR
Valid
Undefined
Odd
LWR
Undefined
Valid
Read

RD
Valid
Valid
Write

HWR, LWR
Write
Word
[Legend]
Undefined:
Undefined data is output.
Invalid:
Input state with the input value ignored.
Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the
data bus.
Rev. 2.00 Aug. 20, 2008 Page 129 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.5.3
Valid Strobes (in Glueless Extension)
Table 6.14 shows the data buses used and valid strobes for each access space.
The RD and WR signals are valid for both the upper and lower halves of the data bus. In a write,
the HBE signal is valid for the upper half of the data bus, and the LBE signal for the lower half.
Table 6.14 Data Buses Used and Valid Strobes (Gluless Extension)
Access
Size
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data
(D15 to D8)
Bus (D7 to D0)
8-bit access
space
Byte
Read

RD
Valid
Ports or others
Write

WR
16-bit access
space
Byte
Read
Even
RD, HBE
Valid
Invalid
Odd
RD, LBE
Invalid
Valid
Even
WR, HBE
Valid
Undefined
Odd
WR, LBE
Undefined
Valid
Read

RD, HBE,
LBE
Valid
Valid
Write

WR, HBE,
LBE
Area
Write
Word
[Legend]
Undefined:
Undefined data is output.
Invalid:
Input state with the input value ignored.
Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the
data bus.
Rev. 2.00 Aug. 20, 2008 Page 130 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.5.4
(1)
Basic Operation Timing in Normal Extended Mode
8-Bit, 2-State Access Space
Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
Rev. 2.00 Aug. 20, 2008 Page 131 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(2)
8-Bit, 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
Rev. 2.00 Aug. 20, 2008 Page 132 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(3)
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space
is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower
half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High level
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 133 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 134 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS * (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
Rev. 2.00 Aug. 20, 2008 Page 135 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High level
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 136 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 137 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS* (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
Rev. 2.00 Aug. 20, 2008 Page 138 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
φ
Address bus
(A23 to A0)
Even
CS
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS*
HBE
LBE
High level
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
WR
Write
D15 to D8
Valid
D7 to D0
Undefined
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)
Rev. 2.00 Aug. 20, 2008 Page 139 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
φ
Address bus
(A23 to A0)
Odd
CS
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS*
HBE
High level
LBE
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
WR
Write
D15 to D8
D7 to D0
Undefined
Valid
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0)
Rev. 2.00 Aug. 20, 2008 Page 140 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Bus cycle
φ
Address bus
(A23 to A0)
Even
CS
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS*
HBE
LBE
RD
Read
D15 to D8
valid
D7 to D0
valid
WR
Write
Note:
D15 to D8
Valid
D7 to D0
Valid
* For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.15 Glueless Extension Word Access (ADMXE = 0)
Rev. 2.00 Aug. 20, 2008 Page 141 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.5.5
(1)
Basic Operation Timing in Address-Data Multiplex Extended Mode
8-Bit, 2-State Data Access Space
Figures 6.16 and 6.17 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access
space is accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states cannot be
inserted.
Read Cycle
Write Cycle
Address
T1
TAW
Data
T2
T3
Address
T4
T1
TAW
Data
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Address
Data
Address
Data
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space
Rev. 2.00 Aug. 20, 2008 Page 142 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Read Cycle
Address
T1
Write Cycle
Data
T2
T3
Address
T4
T1
Data
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Data
Address
Data
Address
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space
(2)
8-Bit, 3-State Data Access Space
Figure 6.18 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states can be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
TDSW
T5
T1
TAW
Data
T2
T3
T4
TDSW
T5
φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Address
Data
Address
Data
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space
Rev. 2.00 Aug. 20, 2008 Page 143 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(3)
16-Bit, 2-State Data Access Space
Figures 6.19 to 6.24 show bus timings for a 16-bit, 2-state access space. When a 16-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and
the lower half (AD7 to AD0) for odd addresses. Wait states cannot be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
T1
TAW
Data
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Address
Data
Address
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 144 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Write Cycle
Read Cycle
Address
T1
Data
T2
T3
Address
T4
T1
Data
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Data
Address
Address
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
Data
Address
T4
T1
TAW
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Address
Data
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 145 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Write Cycle
Read Cycle
Data
Address
T1
T2
T3
Address
T4
T1
T2
Data
T3
T4
φ
CK2S
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Address
Data
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 146 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Write Cycle
Read Cycle
Address
T1
TAW
Data
T2
T3
Data
Address
T4
T1
TAW
T2
T3
T4
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)
Write Cycle
Read Cycle
Address
T1
T2
Data
T3
Address
T4
T1
T2
Data
T3
T4
φ
CP256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)
Rev. 2.00 Aug. 20, 2008 Page 147 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Data Access Space
Figures 6.25 to 6.27 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and
the lower half (AD7 to AD0) for odd addresses. Wait states can be inserted.
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
TDSW
T5
T1
TAW
Data
T2
T3
T4
TDSW
T5
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Data
Address
Data
Address
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)
Rev. 2.00 Aug. 20, 2008 Page 148 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
TDSW
T5
T1
Data
TAW
T2
T3
T4
TDSW
T5
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
AD7 to AD0
Address
Address
Data
Data
Address
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)
Write Cycle
Read Cycle
Address
T1
TAW
Address
Data
T2
T3
T4
TDSW
T5
T1
TAW
Data
T2
T3
T4
TDSW
T5
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
Address
Data
Address
Data
AD7 to AD0
Address
Data
Address
Data
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
Rev. 2.00 Aug. 20, 2008 Page 149 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.5.6
Wait Control
When accessing the external address space, this LSI can extend the bus cycle by inserting one or
more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin
wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin.
(1)
In Normal Extended Mode
(a)
Program Wait Mode
A specified number of wait states TW are always inserted between the T2 state and T3 state when
accessing the external address space. The number of wait states TW is specified by the settings of
the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in WSCR2 for the 256-Kbyte
extended area).
(b)
Pin Wait Mode
A specified number of wait states TW are always inserted between the T2 state and T3 state when
accessing the external address space. The number of wait states TW is specified by the settings of
the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of φ in the last T2 or TW state,
another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high.
Pin wait mode is useful when inserting four or more TW states, or when changing the number of TW
states to be inserted for each external device.
(c)
Pin Auto-Wait Mode
A specified number of wait states TW are inserted between the T2 state and T3 state when accessing
the external address space if the WAIT pin is low at the falling edge of φ in the last T2 state. The
number of wait states TW is specified by the settings of the WC1 and WC0 bits. Even if the WAIT
pin is held low, TW states are inserted only up to the specified number of states.
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.28 shows an example of wait state insertion timing in pin wait mode.
The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input
disabled.
Rev. 2.00 Aug. 20, 2008 Page 150 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
By program wait
T1
T2
TW
By WAIT pin
TW
TW
T3
φ
WAIT
Address bus
IOS (IOSE = 1)
AS * (IOSE = 0)
RD
Read
Data bus
Read data
WR
Write
Data bus
Write data
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
* For external address space access, this signal is not output when the 256-kbyte extended area
is accessed with CS256E = 1.
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode)
Rev. 2.00 Aug. 20, 2008 Page 151 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(2)
In Address-Data Multiplex Extended Mode
(a)
Program Wait Mode
Program wait mode includes address wait and data wait.
• 256-Kbyte extended area and IOS extended area
Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states
of data wait TDSW is inserted between T4 and T5 states.
(b)
Pin Wait Mode
When accessing the external address space, a specified number of wait states TDSW can be inserted
between the T4 state and T5 state of data state. The number of wait states TDSW is specified by the
settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of φ in the last T4,
TDSW, or TDOW state, another TDOW state is inserted. If the WAIT pin is held low, TDOW states are
inserted until it goes high.
Pin wait mode is useful when inserting four or more TDOW states, or when changing the number of
TDOW states to be inserted for each external device.
(c)
Pin Auto-Wait Mode
A specified number of wait states TDOW are inserted between the T4 state and T5 state when
accessing the external address space if the WAIT pin is low at the falling edge of φ in the last T4
state. The number of wait states TDOW is specified by the settings of the WC1 and WC0 bits. Even
if the WAIT pin is held low, TDOW states are inserted only up to the specified number of states.
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.29 shows an example of wait state insertion timing in pin wait mode.
Rev. 2.00 Aug. 20, 2008 Page 152 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Write Cycle
Read Cycle
Data
T3
T4
TDSW TDOW TDOW
Data
T5
T3
T4
TDSW TDOW TDOW
T5
φ
CS256
IOS
WAIT
AH
RD
HWR
LWR
AD15 to AD8
Data
Data
AD7 to AD0
Data
Data
Figure 6.29 Example of Wait State Insertion Timing
Rev. 2.00 Aug. 20, 2008 Page 153 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.6
Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM
bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four
or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected
for burst ROM access.
6.6.1
Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.30 and 6.31.
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Only lower address changes
Address bus
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
Rev. 2.00 Aug. 20, 2008 Page 154 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T1
T1
φ
Only lower
address changes
Address bus
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2
Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is
possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.6,
Wait Control. Wait states cannot be inserted in a burst cycle.
Rev. 2.00 Aug. 20, 2008 Page 155 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.7
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle
is inserted at the start of the write cycle.
Figure 6.32 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.32 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.32 (b), an idle cycle is inserted, thus preventing data collision.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T1
T2
φ
φ
Address bus
Address bus
RD
RD
WR
WR
Data bus
Data bus
T2
T3
Bus cycle B
TI
T1
Data collision
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.32 Examples of Idle Cycle Operation
Rev. 2.00 Aug. 20, 2008 Page 156 of 1198
REJ09B0403-0200
T2
Section 6 Bus Controller (BSC)
Table 6.15 shows the pin states in an idle cycle.
Table 6.15 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of immediately following bus cycle
D15 to D0
High impedance
AS, IOS, CS256
High
RD
High
HWR, LWR
High
6.8
Bus Arbitration
6.8.1
Overview
The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters – the
CPU, DTC, and E-DMAC – that perform read/write operations while they have bus mastership.
6.8.2
Operation
Each bus master requests the bus mastership by means of a bus mastership request signal. The bus
arbiter detects the bus mastership request signal from the bus masters, and if a bus request occurs,
it sends a bus mastership request acknowledge signal to the bus master that made the request at the
designated timing. If there are bus requests from more than one bus master, the bus mastership
request acknowledge signal is sent to the one with the highest priority. When a bus master receives
the bus mastership request acknowledge signal, it takes the bus mastership until that signal is
canceled. The order of bus master priority is as follows:
(High) E-DMAC > DTC > CPU (Low)
Rev. 2.00 Aug. 20, 2008 Page 157 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
6.8.3
Bus Mastership Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus mastership and is currently operating, the bus mastership is not
necessarily transferred immediately. Each bus master can relinquish the bus mastership at the
timings given below.
(1)
CPU
The CPU is the lowest-priority bus master, and if a bus mastership request is received from the
DTC or E-DMAC, the bus arbiter transfers the bus mastership to the DTC or E-DMAC. The
timing for transferring the bus mastership is as follows:
• Timing for transferring the bus mastership to the DTC
1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
in discrete operations, as in the case of a longword size access, the bus is not transferred at a
break between the operations. For details, see section 2.7, Bus States During Instruction
Execution in the H8S/2600 Series, H8S/2000 Series Software Manual.
2. If the CPU is in sleep mode, it transfers the bus mastership immediately.
• Timing for transferring the bus mastership to the E-DMAC
1. Bus mastership is transferred at a break between bus cycles. Even if bus cycle is executed in
discrete operations, as in the case of a longword size access, the bus can be transferred at a
break between bus cycles. For details, see section 21, Ethernet Controller Direct Memory
Access Controller (E-DMAC).
2. If the CPU is in sleep mode, it transfers the bus mastership immediately.
Rev. 2.00 Aug. 20, 2008 Page 158 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
(2)
DTC
The DTC sends the bus arbiter a request for the bus mastership when a request for DTC activation
occurs. The DTC releases the bus mastership after a series of processes has completed.
The DTC is the lower-priority bus master than the E-DMAC, and if a bus mastership request is
received from the E-DMAC, the bus arbiter transfers the bus mastership to the E-DMAC. The
timing for transferring the bus mastership is as follows:
• Timing for transferring the bus mastership to the E-DMAC
1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
in discrete operations, as in the case of a longword size access, the bus is not transferred at a
break between the operations. In addition, in the case of a 32-bit access by the DTC, the bus is
not transferred at a break between the operations. For details, see section 21, Ethernet
Controller Direct Memory Access Controller (E-DMAC).
2. If the CPU is in sleep mode, it transfers the bus mastership immediately.
(3)
E-DMAC
The E-DMAC is the highest-priority bus master, and sends the bus arbiter a request for the bus
when an activation request is generated. The E-DMAC does not release the bus until the
consecutive transfer cycles have completed. For details, see section 21, Ethernet Controller Direct
Memory Access Controller (E-DMAC).
Rev. 2.00 Aug. 20, 2008 Page 159 of 1198
REJ09B0403-0200
Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 160 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus
connects the DTC to addresses H'FFEC00 to H'FFEFFF in on-chip RAM (1 kbyte), enabling 32bit/1-state reading and writing of the DTC register information.
7.1
Features
•
Transfer is possible over any number of channels
•
Three transfer modes
 Normal, repeat, and block transfer modes are available
•
One activation source can trigger a number of data transfers (chain transfer)
•
Direct specification of 16 Mbytes address space is possible
•
Activation by software is possible
•
Transfer can be set in byte or word units
•
A CPU interrupt can be requested for the interrupt that activated the DTC
•
Module stop mode can be set
•
DTC operates in high-speed mode even when the LSI is in medium-speed mode
Rev. 2.00 Aug. 20, 2008 Page 161 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
Internal address bus
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF:
DTVECR:
Internal data bus
DTC mode register A, B
DTC transfer count register A, B
DTC source address register
DTC destination address register
DTC enable registers A to F
DTC vector register
Figure 7.1 Block Diagram of DTC
Rev. 2.00 Aug. 20, 2008 Page 162 of 1198
REJ09B0403-0200
Register information
MRA MRB
CRA
CRB
DAR
SAR
On-chip RAM
Control logic
DTC
DTC activation request
DTVECR
Interrupt
request
DTCERA
to
DTCERF
Interrupt controller
Section 7 Data Transfer Controller (DTC)
7.2
Register Descriptions
The DTC has the following registers.
•
DTC mode register A (MRA)
•
DTC mode register B (MRB)
•
DTC source address register (SAR)
•
DTC destination address register (DAR)
•
DTC transfer count register A (CRA)
•
DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
•
DTC enable registers (DTCER)
•
DTC vector register (DTVECR)
•
Keyboard comparator control register (KBCOMP)
•
Event counter control register (ECCR)
•
Event counter status register (ECS)
Rev. 2.00 Aug. 20, 2008 Page 163 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
SM1
Undefined

Source Address Mode 1 and 0
6
SM0
These bits specify an SAR operation after a data
transfer.
0*: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
5
DM1
4
DM0
Undefined

Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0*: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
3
MD1
2
MD0
Undefined

DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined

DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined

DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Note:
*
Don't care
Rev. 2.00 Aug. 20, 2008 Page 164 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
CHNE
Undefined

DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.6.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
6
DISEL
Undefined

DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. When this bit
is cleared to 0, a CPU interrupt request is generated
only when the specified number of data transfer ends.
5 to 0

Undefined

Reserved
These bits have no effect on DTC operation. The write
value should always be 0.
7.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Rev. 2.00 Aug. 20, 2008 Page 165 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
7.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7
DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERF. The correspondence between interrupt sources and DTCE bits is shown in
tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit
Bit Name
7 to 0
DTCE7 to
DTCE0
Initial
Value
R/W
All 0
R/W
Description
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
as a DTC activation source.
[Clearing conditions]
•
When data transfer has ended with the DISEL bit in
MRB set to 1
•
When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed
Rev. 2.00 Aug. 20, 2008 Page 166 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
Table 7.1
Correspondence between Interrupt Sources and DTCER
Register
Bit
Bit Name
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
DTCERF*
7
DTCEn7
(16)IRQ0


(86)TXI1

(115)USBINT0
6
DTCEn6
(17)IRQ1
(76)IICI2

(89)RXIS

(118)USBINT1
5
DTCEn5
(18)IRQ2
(94)IICI0

(90)TXIS


4
DTCEn4
(19)IRQ3

(29)EVENTI (78)IICI3


3
DTCEn3
(28)ADI


(98)IICI1
(104)ERR1 
2
DTCEn2


(81)RXI3

(105)IBFI1

1
DTCEn1


(82)TXI3

(106)IBFI2

0
DTCEn0


(85)RXI1

(107)IBFI3

[Legend]
n:
A to F
( ):
Vector number
:
Reserved. The write value should always be 0.
*:
Only in the H8S/2472
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
Initial
Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written to
this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified number of
transfers have not ended
•
When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number of
transfers has ended.
Rev. 2.00 Aug. 20, 2008 Page 167 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
Initial
Value
Bit
Bit Name
6 to 0
DTVEC6 to All 0
DTVEC0
R/W
Description
R/W
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to DTVEC0 =
H'10, the vector address is H'0420. When the SWDTE bit
is 0, these bits can be written to.
7.2.9
Keyboard Comparator Control Register (KBCOMP)
KBCOMP enables or disables the comparator scan function of event counter.
Bit
Bit Name
Initial
Value
R/W
7
EVENTE
0
R/W
Description
Event Count Enable
0: Disables event count function
1: Enables event count function
6, 5

All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
4 to 0

All 0
R/W
Reserved
The initial value should not be changed.
Rev. 2.00 Aug. 20, 2008 Page 168 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.2.10
Event Counter Control Register (ECCR)
ECCR selects the event counter channels for use and the detection edge.
Bit
Bit Name
Initial
Value
R/W
7
EDSB
0
R/W
Description
Event Counter Edge Select
Selects the detection edge for the event counter.
0: Counts the rising edges
1: Counts the falling edges
6 to 4

All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
3 to 0
ECSB3 to
ECSB0
All 0
R/W
Event Counter Channel Select 3 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
0000: EVENT0 is used
0001: EVENT0 to EVENT1 are used
0010: EVENT0 to EVENT2 are used
0011: EVENT0 to EVENT3 are used
0100: EVENT0 to EVENT4 are used
0101: EVENT0 to EVENT5 are used
0110: EVENT0 to EVENT6 are used
0111: EVENT0 to EVENT7 are used
1000: EVENT0 to EVENT8 are used
1001: EVENT0 to EVENT9 are used
1010: EVENT0 to EVENT10 are used
1011: EVENT0 to EVENT11 are used
1100: EVENT0 to EVENT12 are used
1101: EVENT0 to EVENT13 are used
1110: EVENT0 to EVENT14 are used
1111: EVENT0 to EVENT15 are used
Rev. 2.00 Aug. 20, 2008 Page 169 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.2.11
Event Counter Status Register (ECS)
ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be
incremented according to the state of this register. Reading this register allows the monitoring of
events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
Bit
Bit Name
15 to 0 E15 to E0
Initial
Value
R/W
Description
0
R
Event Monitor 15 to 0
These bits indicate processed/unprocessed states of the
events that are input to EVENT15 to EVENT0.
0: The corresponding event is already processed
1: The corresponding event is not yet processed
Rev. 2.00 Aug. 20, 2008 Page 170 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.3
DTC Event Counter
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below.
Table 7.2
DTC Event Counter Conditions
Register
Bit
Bit Name
MRA
7, 6
SM1, SM0 00: SAR is fixed.
5, 4
DM1, DM0 00: DAR is fixed.
3, 2
MD1, MD0 01: Repeat mode
1
DTS
0: Destination is repeat area
0
Sz
1: Word size transfer
7
CHNE
0: Chain transfer is disabled
6
DISEL
0: Interrupt request is generated when data is transferred by
the number of specified times
5 to 0

B'000000
SAR
23 to 0

Identical optional RAM address. Its lower five bits are B'00000.
DAR
23 to 0

The start address of 16 words is this address. They are
incremented every time an event is detected in EVENT0 to
EVENT15.
CRAH
7 to 0

H'FF
CRAL
7 to 0

H'FF
CRBH
7 to 0

H'FF
CRBL
7 to 0

H'FF
DTCERC
4
DTCEC4
1: DTC function of the event counter is enabled
KBCOMP
7
EVENTE
1: Event counter enable
RAM


(SAR, DAR) : Result of EVENT0 count
(SAR, DAR) + 2: Result of EVENT 1 count
(SAR, DAR) + 4: Result of EVENT 2 count
↓
(SAR, DAR) + 30: Result of EVENT 15 count
MRB
Description
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the
ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag
state, status/address codes are generated.
An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
Rev. 2.00 Aug. 20, 2008 Page 171 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the
same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced
with address code that is generated by the ECS flag status.
When the DTC transfer is completed, the ECS flag for transfer is cleared.
Table 7.3
Flag Status/Address Code
ECS
15
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
Code
1
B'00000
1
0
B'00010
1
0
0
B'00100
1
0
0
0
B'00110
1
0
0
0
0
B'01000
1
0
0
0
0
0
B'01010
1
0
0
0
0
0
0
B'01100
1
0
0
0
0
0
0
0
B'01110
1
0
0
0
0
0
0
0
0
B'10000
1
0
0
0
0
0
0
0
0
0
B'10010
1
0
0
0
0
0
0
0
0
0
0
B'10100
1
0
0
0
0
0
0
0
0
0
0
0
B'10110
1
0
0
0
0
0
0
0
0
0
0
0
0
B'11000
1
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11010
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11100
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B'11110
Rev. 2.00 Aug. 20, 2008 Page 172 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.3.1
Event Counter Handling Priority
EVENT0 to EVENT15 count handling is operated in the priority shown as below.
High
Low
EVENT0 > EVENT1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ EVENT14 > EVENT15
7.3.2
Usage Notes
There are following usage notes for this event counter because it uses the DTC.
1.
Continuous events that are input from the same pin and out of DTC handling are ignored
because the count up is operated by means of the DTC.
2.
If some events are generated in short intervals, the priority of event counter handling is not
ordered and events are not handled in order of arrival.
3.
If the counter overflows, this event counter counts from H'0000 without generating an
interrupt.
Rev. 2.00 Aug. 20, 2008 Page 173 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.4
Activation Sources
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt
request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last
consecutive transfer in the case of chain transfer), the interrupt flag that became the activation
source or the corresponding DTCER bit is cleared. The activation source flag, in the case of
RXI0, for example, is the RDRF flag in SCI_0.
When an interrupt has been designated as a DTC activation source, the existing CPU mask level
and interrupt controller priorities have no effect. If there is more than one activation source at the
same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block
diagram of DTC activation source control. For details on the interrupt controller, see section 5,
Interrupt Controller.
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
peripheral
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 7.2 Block Diagram of DTC Activation Source Control
Rev. 2.00 Aug. 20, 2008 Page 174 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.5
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
Register information should be located at an address that is a multiple of four within the range.
The method for locating the register information in address space is shown in figure 7.3. Locate
MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3, and the register information start address should be located at the
vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the
start address of the register information from the vector table set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register
information start address.
Lower address
0
Register
information
start address
Chain
transfer
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
MRA
SAR
MRB
DAR
Register information
for 2nd transfer in
chain transfer
CRB
CRA
4 bytes
Figure 7.3 DTC Register Information Location in Address Space
Rev. 2.00 Aug. 20, 2008 Page 175 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Activation
Source Origin
Activation Source
Vector
Number
DTC Vector
Address
Software
Write to DTVECR
DTVECR
H'0400 + (vector 
number x 2)
External pins
IRQ0
IRQ1
16
17
H'0420
H'0422
DTCEA7
DTCEA6
IRQ2
IRQ3
18
19
H'0424
H'0426
DTCEA5
DTCEA4
A/D converter
EVC
ADI
EVENTI
28
29
H'0438
H'043A
DTCEA3
DTCEC4
IIC_2
IIC_3
IICI2
IICI3
76
78
H'0498
H'049C
DTCEB6
DTCED4
SCI_3
RXI3
TXI3
81
82
H'04A2
H'04A4
DTCEC2
DTCEC1
SCI_1
RXI1
TXI1
85
86
H'04AA
H'04AC
DTCEC0
DTCED7
SSU
RXIS
TXIS
89
90
H'04B2
H'04B4
DTCED6
DTCED5
IIC_0
IIC_1
IICI0
IICI1
94
98
H'04BC
H'04C4
DTCEB5
DTCED3
LPC
ERRI
IBFI1
104
105
H'04D0
H'04D2
DTCEE3
DTCEE2
IBFI2
IBFI3
106
107
H'04D4
H'04D6
DTCEE1
DTCEE0
USB (only in the
H8S/2472)
Note:
*
DTCE*
Priority
High
USBINT0
115
H'04E6
DTCEF7
USBINT1
118
H'04EC
DTCEF6
Low
DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0.
Rev. 2.00 Aug. 20, 2008 Page 176 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6
Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register
information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated
register information back to on-chip RAM. The pre-storage of register information in memory
makes it possible to transfer data over any required number of channels. The transfer mode can be
specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it
possible to perform a number of transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1
Yes
No
Transfer counter = 0
or DISEL = 1
Yes
No
Clear an activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 7.4 DTC Operation Flowchart
Rev. 2.00 Aug. 20, 2008 Page 177 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6.1
Normal Mode
In normal mode, one activation source transfers one byte or one word of data. Table 7.5 lists the
register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified
number of transfers has been completed, a CPU interrupt can be requested.
Table 7.5
Register Functions in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register A
CRA
Transfer counter
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 7.5 Memory Mapping in Normal Mode
Rev. 2.00 Aug. 20, 2008 Page 178 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6.2
Repeat Mode
In repeat mode, one activation source transfers one byte or one word of data. Table 7.6 lists the
register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified
number of transfers has been completed, the initial states of the transfer counter and the address
register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the
transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when
the DISEL bit in MRB is cleared to 0.
Table 7.6
Register Functions in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Transfer Count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 7.6 Memory Mapping in Repeat Mode
Rev. 2.00 Aug. 20, 2008 Page 179 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6.3
Block Transfer Mode
In block transfer mode, one activation source transfers one block of data. Either the transfer source
or the transfer destination is designated as a block area. Table 7.7 lists the register functions in
block transfer mode. The block size can be between 1 and 256. When the transfer of one block
ends, the initial state of the block size counter and the address register that is specified as the block
area is restored. The other address register is then incremented, decremented, or left fixed
according to the register information. From 1 to 65,536 transfers can be specified. Once the
specified number of transfers has been completed, a CPU interrupt is requested.
Table 7.7
Register Functions in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Block size counter
DTC transfer count register B
CRB
Transfer counter
1st block
SAR
or
DAR
•
•
•
Block area
Transfer
N th block
Figure 7.7 Memory Mapping in Block Transfer Mode
Rev. 2.00 Aug. 20, 2008 Page 180 of 1198
REJ09B0403-0200
DAR
or
SAR
Section 7 Data Transfer Controller (DTC)
7.6.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the
register information start address stored at the DTC vector address, and then reads the first register
information at that start address. After the data transfer, the CHNE bit will be tested. When it has
been set to 1, DTC reads the next register information located in a consecutive area and performs
the data transfer. These sequences are repeated until the CHNE bit is cleared to 0.
In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated
at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
DTC vector
address
Register information
start address
Register information
CHNE = 1
Destination
Register information
CHNE = 0
Source
Destination
Figure 7.8 Chain Transfer Operation
Rev. 2.00 Aug. 20, 2008 Page 181 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and priority level control by the interrupt controller.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.6.6
Operation Timing
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write
Transfer information
read
Transfer information
write
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Rev. 2.00 Aug. 20, 2008 Page 182 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write Read Write
Transfer information
read
Transfer information
write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC request
Data transfer
Data transfer
Vector read
Address
Read
Read Write
Transfer information
read
Transfer
information
write
Transfer
information
read
Write
Transfer information
write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
Rev. 2.00 Aug. 20, 2008 Page 183 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.6.7
Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number
of states required for each execution status.
Table 7.8
DTC Execution Status
Mode
Register
Information
Vector Read Read/Write
I
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.9
Number of States Required for Each Execution Status
On-Chip RAM
On-Chip RAM (On-chip RAM area
On-
On-Chip
(H'FFEC00 to
other than H'FFEC00 to Chip
Object to be Accessed
H'FFEFFF)
H'FFEFFF)
ROM
Registers
External Devices
Bus width
32
16
16
8
16
8
8
16
16
Access states
1
1
1
2
2
2
3
2
3
—
1
—
—
4
6 + 2m
2
3+m
—
—
—
—
—
—
—
—
Byte data read SK 1
1
1
2
2
2
3+m
2
3+m
1
1
1
4
2
4
6 + 2m
2
3+m
Byte data write SL 1
1
1
2
2
2
3+m
2
3+m
1
1
1
4
2
4
6 + 2m
2
3+m
Internal operation 1
1
1
1
1
1
1
1
1
Execution Vector read
status
Register
SI —
1
I/O
information
read/write
SJ
Word data read
SK
Word data write
SL
SM
Rev. 2.00 Aug. 20, 2008 Page 184 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
7.7
Procedures for Using DTC
7.7.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After one data transfer has been completed, or after the specified number of data transfers have
been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to
continue transferring data, set the DTCE bit to 1.
7.7.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check that the SWDTE bit is 0.
4. Write 1 to the SWDTE bit and the vector number to DTVECR.
5. Check the vector number written to DTVECR.
6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not
requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the
SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have
been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
Rev. 2.00 Aug. 20, 2008 Page 185 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.8
Examples of Use of the DTC
7.8.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1
= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI, RDR address in SAR, the start address of the RAM area where the data will be received
in DAR, and 128 (H′0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at
1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine will perform wrap-up processing.
Rev. 2.00 Aug. 20, 2008 Page 186 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.8.2
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the transfer destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000)
in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is
transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform wrap-up processing.
Rev. 2.00 Aug. 20, 2008 Page 187 of 1198
REJ09B0403-0200
Section 7 Data Transfer Controller (DTC)
7.9
Usage Notes
7.9.1
Module Stop Mode Setting
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the
initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop
mode is set. Note that when the DTC is being activated, module stop mode cannot be specified.
For details, refer to section 28, Power-Down Modes.
7.9.2
On-Chip RAM
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.
7.9.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and
writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
7.9.4
DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter
Interrupt sources of the SCI, IIC, or A/D converter which activate the DTC are cleared when DTC
reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit.
Rev. 2.00 Aug. 20, 2008 Page 188 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Section 8 I/O Ports
8.1
I/O Ports for the H8S/2472 Group
Table 8.1 is a summary of the port functions. The pins of each port also function as input/output
pins of peripheral modules and interrupt input pins. Each input/output port includes a data
direction register (DDR) that controls input/output and a data register (DR) that stores output data.
DDR and DR are not provided for input-only ports.
Pins of ports 1 to 4, 6, and A and pins D0 to D5 of port D have built-in input pull-up MOSs. For
port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their
respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS
control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up
MOSs.
Port 3 pins and pins 47 to 44 and B3 to B0 have built-in de-bouncers (DBn) that eliminate noises
in the input signals.
Ports 4 and F are designed for retain state outputs (RSn), which retain the output values on the
pins even if a reset is generated when the watchdog timer has overflowed.
Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports
can drive a Darlington transistor in output mode. Port pins 80 to 83, C0 to C5, D6, and D7 are
NMOS push-pull output.
Rev. 2.00 Aug. 20, 2008 Page 189 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Table 8.1
Port Functions
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
Feature of
I/O
P17
P16
P15
P14
P13
P12
P11
P10
P17/A7/AD7
P16/A6/AD6
P15/A5/AD5
P14/A4/AD4
P13/A3/AD3
P12/A2/AD2
P11/A1/AD1
P10/A0/AD0
Built-in input
pull-up MOS
General I/O port
P27/DTR
multiplexed with SCIF P26/DSR
control I/O
P25/RI
P24/DCD
Same as left
Built-in input
pull-up MOS
General I/O port
multiplexed with
address output and
address-data
multiplex I/O
P23
P22
P21
P20
P23/A11/AD11
P22/A10/AD10
P21/A9/AD9
P20/A8/AD8
Port 3
General I/O port
multiplexed with debounced input and
bidirectional data bus
I/O
P37/ExDB7
P36/ExDB6
P35/ExDB5
P34/ExDB4
P33/ExDB3
P32/ExDB2
P31/ExDB1
P30/ExDB0
P37/ExDB7/D15
P36/ExDB6/D14
P35/ExDB5/D13
P34/ExDB4/D12
P33/ExDB3/D11
P32/ExDB2/D10
P31/ExDB1/D9
P30/ExDB0/D8
Built-in input
pull-up MOS
Port 4
General I/O port
multiplexed with
interrupt input, debounced input,
address output, and
address-data
multiplex I/O
P47/IRQ7/RS7/DB7/HC7
P46/IRQ6/RS6/DB6/HC6
P45/IRQ5/RS5/DB5/HC5
P44/IRQ4/RS4/DB4/HC4
P47/A15/AD15
P46/A14/AD14
P45/A13/AD13
P44/A12/AD12
Built-in input
pull-up MOS
General I/O port
multiplexed with
interrupt input and
bidirectional data
bus* I/O
P43/IRQ3/RS3/HC3
P42/IRQ2/RS2/HC2
P41/IRQ1/RS1/HC1
P40/IRQ0/RS0/HC0
Port
Description
Port 1
General I/O port
multiplexed with
address output and
address-data
multiplex I/O
Port 2
(sink current
12 mA)
Rev. 2.00 Aug. 20, 2008 Page 190 of 1198
REJ09B0403-0200
LED driving
capability
P43/IRQ3/RS3/HC3/D7*
P42/IRQ2/RS2/HC2/D6*
P41/IRQ1/RS1/HC1/D5*
P40/IRQ0/RS0/HC0/D4*
Section 8 I/O Ports
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
General I/O port
multiplexed with
interrupt input, bus
control output, system
clock output, SSU I/O,
and external subclock
input
P57
WR/HWR
P56/EXCL/φ
P55/IRQ13/SSI
P54/IRQ12/SSO
Same as left
General I/O port
multiplexed with
interrupt input, SCIF
and SCI_1 I/O
P53/IRQ11/RxD1
P52/IRQ10/TxD1
P51/IRQ9/RxDF
P50/IRQ8/TxDF
Same as left
General I/O port
multiplexed with
interrupt input, SCIF
control I/O and SSU
control I/O
P67/ExIRQ8/SSCK
P66/ExIRQ9/SCS
P65/ExIRQ10/RTS
P64/ExIRQ11/CTS
Same as left
General I/O port
multiplexed with
interrupt input, PWMX
output, and
bidirectional data
bus* I/O
P63/PWX3
P62/PWX2
P61/IRQ15/PWX1
P60/IRQ14/PWX0
P63/PWX3/D3*
P62/PWX2/D2*
P61/IRQ15/PWX1/D1*
P60/IRQ14/PWX0/D0*
Port
Description
Port 5
Port 6
Port 7
P77/AN7
General input port
multiplexed with A/D P76/AN6
converter analog input P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port 8
General I/O port
multiplexed with
interrupt input, A/D
converter external
trigger input, and
SCI_1 and SCI_3 I/O
P87/ExIRQ15/TxD3/
ADTRG
P86/ExIRQ14/RxD3
P85/ExIRQ13/SCK1
P84/ExIRQ12/SCK3
General I/O port
P83/SDA1
multiplexed with IIC_0 P82/SCL1
and IIC_1 I/O
P81/SDA0
P80/SCL0
Feature of
I/O
Built-in input
pull-up MOS
Same as left
Same as left
Same as left
NMOS
push-pull
output
Rev. 2.00 Aug. 20, 2008 Page 191 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Port
Description
Port 9
General I/O port
multiplexed with
PWMX output and
bus control I/O
Port A
Port B
Port C
General I/O port
multiplexed with
interrupt input, DTC
event counter input,
EtherC control I/O,
and address output
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
P97
P97/WAIT/CS256
P96
Same as left
P95
AS/IOS
P94/ExPWX1
P93/ExPWX0
Same as left
P92
P91
P90
P92/HBE
P91/AH
P90/LBE
PA7/ExIRQ7/EVENT7/EXOUT
PA7/ExIRQ7/EVENT7/A23
PA6/ExIRQ6/EVENT6/LNKSTA
PA6/ExIRQ6/EVENT6/A22/LNKSTA
PA5/ExIRQ5/EVENT5/WOL
PA5/ExIRQ5/EVENT5/A21/WOL
PA4/ExIRQ4/EVENT4
PA4/ExIRQ4/EVENT4/A20
PA3/ExIRQ3/EVENT3
PA3/ExIRQ3/EVENT3/A19
PA2/ExIRQ2/EVENT2
PA2/ExIRQ2/EVENT2/A18
PA1/ExIRQ1/EVENT1
PA1/ExIRQ1/EVENT1/A17
PA0/ExIRQ0/EVENT0
PA0/ExIRQ0/EVENT0/A16
General I/O port
multiplexed with DTC
event counter input
and EtherC control
I/O
PB7/EVENT15/RM_RX-ER
Same as left
General I/O port
multiplexed with debounced input, DTC
event counter input,
and EtherC control
I/O
PB3/DB3/EVENT11/RM_RXD1
General I/O port
multiplexed with bus
control output
PC7
PC6
Built-in input
pull-up MOS
PB6/EVENT14/RM_CRS-DV
PB5/EVENT13/ RM_REF-CLK
PB4/EVENT12/RM_TX-EN
Same as left
PB2/DB2/EVENT10/RM_RXD0
PB1/DB1/EVENT9/RM_TXD1
PB0/DB0/EVENT8/RM_TXD0
PC5/SDA4
General I/O port
multiplexed with IIC_2 PC4/SCL4
PC3/SDA3
to IIC_4 I/O
PC2/SCL3
PC1/SDA2
PC0/SCL2
Rev. 2.00 Aug. 20, 2008 Page 192 of 1198
REJ09B0403-0200
Feature of
I/O
RD
PC6/LWR
Same as left
NMOS
push-pull
output
Section 8 I/O Ports
Extended Mode
(EXPE = 1)
Feature of
I/O
General I/O port
PD7/SDA5
multiplexed with IIC_5 PD6/SCL5
I/O
Same as left
NMOS
push-pull
output
PD5/LPCPD
General I/O port
multiplexed with LPC PD4/CLKRUN
PD3/GA20
I/O
PD2/PME
PD1/LSMI
PD0/LSCI
Same as left
Built-in input
pull-up MOS
Port E
General I/O port
PE7/SERIRQ
multiplexed with LPC PE6/LCLK
I/O
PE5/LRESET
PE4/LFRAME
PE3/LAD3
PE2/LAD2
PE1/LAD1
PE0/LAD0
Same as left
Port F
General I/O port
multiplexed with
PWMX output and
EtherC control I/O
Same as left
Port
Description
Port D
Note:
*
Single-Chip Mode
(EXPE = 0)
PF6/ExPWX2/RS14
PF5/RS13
PF4/RS12
PF3/ExPWX3/RS11
PF2/RS10
PF1/RS9/MDC
PF0/RS8/MDIO
Available when configured for 16-bit data bus.
Rev. 2.00 Aug. 20, 2008 Page 193 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins can also function as the address bus and address-data
multiplex bus pins. The pin functions change according to the operating mode. Port 1 has the
following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 pull-up MOS control register (P1PCR)
(1)
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
•
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function as
address output pins; when cleared to 0, function
as input port pins.
•
Address-data multiplex extended mode (ADMXE =
1)
These bits correspond to the AD7 to AD0 pins of
the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as
input port pins.
Rev. 2.00 Aug. 20, 2008 Page 194 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
P1DR stores output data for the port 1 pins that are
used as the general output port.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
(3)
If this register is read, the P1DR values are read for
the bits with the corresponding P1DDR bits set to 1.
For the bits with the corresponding P1DDR bits
cleared to 0, the pin states are read.
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the port 1 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P17PCR
0
R/W
6
P16PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P1PCR bit is set to 1.
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
0
P10PCR
0
R/W
Do not change the initial value when using the
address-data multiplex extended bus mode.
Rev. 2.00 Aug. 20, 2008 Page 195 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Extended Mode (EXPE = 1)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR
0
1
ADMXE
0
ABW,
ABW256
X
Either bit is 0
(8/16-bit bus)
Both bits are
1 (8-bit bus)
X
Either bit is 0
(8/16-bit bus)
Both bits
are 1 (8-bit
bus)
P1n input
pin
ADn
input/output
pin
P1n input pin
An output
pin
Setting
prohibited
P1n output
pin
Pin function
1
0
1
[Legend] n = 7 to 0, X: Don't care.
(b)
Single-Chip Mode (EXPE = 0)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR
Pin function
0
1
P1n input pin
P1n output pin
[Legend] n = 7 to 0
(5)
Port 1 Input Pull-Up MOS
Port 1 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used regardless of the operating mode. Table 8.2 summarizes the input pull-up MOS states.
Table 8.2
Port 1 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 196 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins can also function as the SCIF modem control signal, address
bus, and address-data multiplex bus pins. The pin functions change according to the operating
mode. Port 2 has the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 pull-up MOS control register (P2PCR)
(1)
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as
input port pins.
5
P25DDR
0
W
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
•
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function
as address output pins; when cleared to 0,
function as input port pins.
The address output pins used are in accord
with the settings of the IOSE and CS256E bits
of SYSCR.
•
Address-data multiplex extended mode
(ADMXE = 1)
These bits correspond to the AD11 to AD8 pins
of the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function
as output port pins; when cleared to 0, function
as input port pins.
Rev. 2.00 Aug. 20, 2008 Page 197 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
P2DR stores output data for the port 2 pins that are
used as the general output port.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
(3)
If this register is read, the P2DR values are read
for the bits with the corresponding P2DDR bits set
to 1. For the bits with the corresponding P2DDR
bits cleared to 0, the pin states are read.
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P27PCR
0
R/W
6
P26PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P2PCR bit is set to 1.
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
0
P20PCR
0
R/W
Rev. 2.00 Aug. 20, 2008 Page 198 of 1198
REJ09B0403-0200
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P2PCR bit is set to 1.
Do not change the initial value when using the
address-data multiplex extended bus mode.
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Extended Mode (EXPE = 1)
• P27 to P24
The pin function is the same as that in single-chip mode.
• P23
The pin function is switched as shown below according to the combination of the CS256E and
IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P23DDR bit. Address
11 in the table below is expressed by the following logical expression.
Address 11 = 1: ADFULLE • CS256E • IOSE
P23DDR
0
1
ADMXE
0
1
Address 11
X
X
Pin function
0
1
0
1
X
P23 input pin AD11 input/output A11 output pin P23 output pin AD11 input/output
pin
pin
• P22 to P20
P2nDDR
0
ADMXE
Pin function
[Legend]
1
0
1
0
1
P2n input pin
ADm input/output
pin
Am output pin
ADm input/output
pin
m = 10 to 8, n = 2 to 0, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 199 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(b)
Single-Chip Mode (EXPE = 0)
• P27/DTR
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 of the LPC, the SCIFOE1 and SCIFOE0 bits in SCIFCR of the SCIF, and the P27DDR
bit.
SCIFE
0
SCIFOE1,
SCIFOE0
Other than 10
P27DDR
Pin function
1
10
0
1
X
P27 input pin
P27 output
pin
X1
0
DTR output P27 input pin
pin
X0
1
X
P27 output
pin
DTR output
pin
[Legend] X: Don't care.
• P26/DSR, P25/RI, P24/DCD
The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR
Pin function
0
1
P2n input pin
DSR/RI/DCD input pin
P2n output pin
[Legend] n = 6 to 4
• P23 to P20
The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR
Pin function
0
1
P2n input pin
P2n output pin
[Legend] n = 3 to 0
Rev. 2.00 Aug. 20, 2008 Page 200 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Port 2 Input Pull-Up MOS
Port 2 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used regardless of the operating mode. Table 8.3 summarizes the input pull-up MOS states.
Table 8.3
Port 2 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 201 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins can also function as the bidirectional data bus and debounced input pins. The pin functions change according to the operating mode. Port 3 has the
following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 pull-up MOS control register (P3PCR)
• Noise canceler enable register (P3NCE)
• Noise canceler mode control register (P3NCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the port 3 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 202 of 1198
REJ09B0403-0200
•
Normal extended mode (ADMXE = 0)
The pins function as bidirectional data bus pins.
•
Other modes
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Section 8 I/O Ports
(2)
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P37DR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
Since the port 3 pins function as bidirectional data
bus pins, the value of this register has no effect on
operation.
If this register is read, the P3DR values are read for
the bits with the corresponding P3DDR bits set to 1.
For the bits with the corresponding P3DDR bits
cleared to 0, 1 is read.
1
P31DR
0
0
P30DR
0
R/W •
R/W
Other modes
P3DR stores output data for the port 3 pins that are
used as the general output port.
If this register is read, the P3DR values are read for
the bits with the corresponding P3DDR bits set to 1.
For the bits with the corresponding P3DDR bits
cleared to 0, the pin states are read.
(3)
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W Description
7
P37PCR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36PCR
0
R/W
This register has no effect on operation.
5
P35PCR
0
R/W •
Other modes
4
P34PCR
0
R/W
3
P33PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P3PCR bit is set to 1.
2
P32PCR
0
R/W
1
P31PCR
0
R/W
0
P30PCR
0
R/W
Rev. 2.00 Aug. 20, 2008 Page 203 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit
Bit Name
Initial Value
R/W Description
7
P37NCE
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36NCE
0
R/W
5
P35NCE
0
R/W
The pins function as bidirectional data bus pins. Set
this register to 0.
4
P34NCE
0
R/W
3
P33NCE
0
R/W
2
P32NCE
0
R/W
1
P31NCE
0
R/W
0
P30NCE
0
R/W
(5)
•
Other modes
Enables the noise canceler circuit for the
corresponding pin and the pin state is fetched into
P3DR at the sampling cycle set by NCCS.
The operation changes according to the other
control bits.
Noise Canceler Mode Control Register (P3NCMC)
When the noise canceler is enabled, P3NCMC controls whether 1 or 0 is expected for the input
signal to port 3 in bit units.
Bit
Bit Name
Initial Value
R/W Description
7
P37NCMC
1
R/W •
Normal extended mode (ADMXE = 0)
6
P36NCMC
1
R/W
This register has no effect on operation.
Other modes
1 expected: 1 is stored in the port data register
while 1 is input stably.
5
P35NCMC
1
R/W •
4
P34NCMC
1
R/W
3
P33NCMC
1
R/W
2
P32NCMC
1
R/W
1
P31NCMC
1
R/W
0
P30NCMC
1
R/W
Rev. 2.00 Aug. 20, 2008 Page 204 of 1198
REJ09B0403-0200
0 expected: 0 is stored in the port data register
while 0 is input stably.
Section 8 I/O Ports
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name Initial Value R/W
Description
7 to 3 
Undefined
R/W
2
NCCK2
0
R/W These bits set the sampling cycle of the noise cancelers.
1
NCCK1
0
R/W •
When φ = 34 MHz
0
NCCK0
0
R/W
000: 0.06 µs
φ/2
100: 963.8 µs φ/32768
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
Reserved
Undefined value is read from these bits.
011: 240.9 µs φ/8192
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
Port data
register
∆t
Sampling clock
Figure 8.1 Noise Canceler Circuit
Rev. 2.00 Aug. 20, 2008 Page 205 of 1198
REJ09B0403-0200
Section 8 I/O Ports
P3n input
1 expected
P3nDR
0 expected
P3nDR
(n = 7 to 0)
Figure 8.2 Noise Canceler Operation
(7)
Pin Functions
(a)
Normal Extended Mode
Port 3 pins are automatically set to function as bidirectional data bus pins.
(b)
Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode.
(c)
Single-Chip Mode
The pin function is switched as shown below according to the combination of the P3nDDR bit and
the P3nNCE bit.
P3nDDR
P3nNCE
Pin function
0
1
X
P3n input pin
ExDBn input
P3n output pin
[Legend] n = 7 to 0, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 206 of 1198
REJ09B0403-0200
1
0
Section 8 I/O Ports
(8)
Port 3 Input Pull-Up MOS
Port 3 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used in single-chip mode and address-data multiplex extended mode. Table 8.4 summarizes
the input pull-up MOS states.
Table 8.4
Port 3 Input Pull-Up MOS States
Mode
Reset
Hardware
Standby Mode
Software Standby In Other
Mode
Operations
Normal extended mode
(EXPE = 1, ADMXE = 0)
Off
Off
Off
Off
Single-chip mode (EXPE = 0) Off
Off
On/Off
On/Off
Address-data multiplex
extended mode (EXPE = 1,
ADMXE = 1)
[Legend]
Off:
Always off.
On/Off: On when input state and P3PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 207 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins can also function as the external interrupt input, de-bounced
input, bidirectional data bus, address bus, and address-data multiplex bus pins. Port 4 has the
following registers.
• Port 4 data direction register (P4DDR)
• Port 4 data register (P4DR)
• Port 4 pull-up MOS control register (P4PCR)
• Noise canceler enable register (P4BNCE)
• Noise canceler mode control register (P4BNCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the port 4 pins. P4DDR is initialized
only by a system reset, and retains the value even if an internal reset signal of the WDT is
generated.
Bit
Bit Name
Initial Value
R/W Description
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
•
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function as
address output pins; when cleared to 0, function as
input port pins.
The address output pins used are in accord with the
settings of the IOSE and CS256E bits of SYSCR.
•
Address-data multiplex extended mode (ADMXE =
1)
These bits correspond to the AD15 to AD12 pins of
the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Rev. 2.00 Aug. 20, 2008 Page 208 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Bit
Bit Name
Initial Value
R/W Description
3
P43DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
0
P40DDR
0
W
(2)
•
Normal extended mode (16-bit bus)
These bits have no effect on operation.
•
Other modes
If port 4 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P4DDR bits are set to 1, and as input port
when cleared to 0.
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins. P4DR is initialized only by a system reset, and retains
the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
Initial Value
R/W Description
7
P47DR
0
6
P46DR
0
5
P45DR
0
4
P44DR
0
R/W These bits store output data for the port 4 pins that are
used as the general output port.
R/W
If this register is read, the P4DR values are read for the
R/W
bits with the corresponding P4DDR bits set to 1. For the
R/W bits with the corresponding P4DDR bits cleared to 0,
the pin states are read.
3
P43DR
0
R/W •
Normal extended mode (16-bit data bus)
2
P42DR
0
R/W
1
P41DR
0
R/W
0
P40DR
0
R/W
Since the corresponding pins function as
bidirectional data bus pins, the value in these bits
has no effect on operation.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, 1 is read.
•
Other modes
These bits store output data for the port 4 pins that
are used as the general output port.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, the pin states are read.
Rev. 2.00 Aug. 20, 2008 Page 209 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(3)
Port 4 Pull-Up MOS Control Register (P4PCR)
P4PCR controls the port 4 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W Description
7
P47PCR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P46PCR
0
R/W
This register has no effect on operation.
5
P45PCR
0
R/W •
Other modes
4
P44PCR
0
R/W
3
P43PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P4PCR bit is set to 1.
2
P42PCR
0
R/W
1
P41PCR
0
R/W
0
P40PCR
0
R/W
(4)
Noise Canceler Enable Register (P4BNCE)
The individual bits of P4BNCE enable or disable the noise canceler circuits for ports 4 and B.
Bit
Bit Name
Initial Value
R/W Description
7
P47NCE
0
6
P46NCE
0
5
P45NCE
0
4
P44NCE
0
R/W Enables the noise canceler circuit for the corresponding
pin and the pin state is fetched into P4DR at the
R/W
sampling cycle set by NCCS.
R/W
The operation changes according to the other control
R/W bits.
3 to 0 PB3NCE to All 0
PB0NCE
R/W Bits for port B setting
Rev. 2.00 Aug. 20, 2008 Page 210 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit
Bit Name
Initial Value
R/W Description
7
P47NCMC
1
R/W Expected value setting
6
P46NCMC
1
5
P45NCMC
1
4
P44NCMC
1
R/W 1 expected: 1 is stored in the port data register while 1
is input stably
R/W
0 expected: 0 is stored in the port data register while 0
R/W
is input stably
3 to 0 PB3NCMC
to
PB0NCMC
(6)
All 1
R/W Bits for port B setting
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name
7 to 3 
Initial Value
R/W
Description
Undefined
R/W
Reserved
Undefined value is read from these bits.
2
NCCK2
0
R/W
1
NCCK1
0
R/W
These bits set the sampling cycle of the noise
cancelers.
0
NCCK0
0
R/W
•
When φ = 34 MHz
000: 0.06 µs
φ/2
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
011: 240.9 µs φ/8192
100: 963.8 µs φ/32768
Rev. 2.00 Aug. 20, 2008 Page 211 of 1198
REJ09B0403-0200
Section 8 I/O Ports
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
Sampling clock
Figure 8.3 Noise Canceler Circuit
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
Figure 8.4 Noise Canceler Operation
Rev. 2.00 Aug. 20, 2008 Page 212 of 1198
REJ09B0403-0200
Port data
register
Section 8 I/O Ports
(7)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Normal Extended Mode
• P47 to P44
The pin function is switched as shown below according to the combination of the CS256E and
IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P4nDDR bit. Address 13 in
the table below is expressed by the following logical expression.
Address 13 = 1: ADFULLE • CS256E • IOSE
P4nDDR
0
Address 13
X
0
1
P4n input pin
Am output pin
P4n output pin
Pin
function
1
[Legend] m = 15 to 12, n = 7 to 4
X: Don't care.
• P43 to P40
Port pins 43 to 40 function as bidirectional data bus pins in 16-bit bus extension, and can be used
as general I/O port in 8-bit bus extension.
(b)
Address-Data Multiplex Extended Mode
Port pins 47 to 44 are automatically set to function as address bus pins. Port pins 43 to 40 can be
used as general I/O port pins.
Rev. 2.00 Aug. 20, 2008 Page 213 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(c)
Single-Chip Mode
The relationship between register setting values and pin functions are as follows.
• P47 to P44
The pin function is switched as shown below according to the P4nDDR bit and the P4nNCE bit.
When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is
set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the
P4nDDR bit to 0.
P4nDDR
0
P4nNCE
1
0
1
X
P4n input
DBn input
P4n output
IRQn input
IRQn input
(with the noise canceler)
Pin function
[Legend] n = 7 to 4
X: Don't care.
The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in
ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be
used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
• P43 to P40
P4nDDR
Pin function
0
1
P4n input pin
P4n output pin
IRQn input pin
[Legend] n = 3 to 0
Rev. 2.00 Aug. 20, 2008 Page 214 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(8)
Port 4 Input Pull-Up MOS
Port 4 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used in single-chip mode and address-data multiplex extended mode. Table 8.5 summarizes
the input pull-up MOS states.
Table 8.5
Port 4 Input Pull-Up MOS States
Mode
Reset
Hardware
Standby Mode
Software Standby In Other
Mode
Operations
Normal extended mode
(EXPE = 1, ADMXE = 0)
Off
Off
Off
Off
Single-chip mode (EXPE = 0) Off
Off
On/Off
On/Off
Address-data multiplex
extended mode (EXPE = 1,
ADMXE = 1)
[Legend]
Off:
Always off.
On/Off: On when input state and P4PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 215 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.5
Port 5
Port 5 is an 8-bit I/O port. Port 5 pins can also function as the SCIF, SCI_1, and SSU input/output,
bus control output, system clock output, external subclock input, and interrupt input pins. Port 5
has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
(1)
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DDR
0
W
If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.
6
P56DDR
0
W
The corresponding port 5 pin functions as the system
clock output pin (φ) when this bit is set to 1, and as
the general I/O port when cleared to 0.
5
P55DDR
0
W
4
P54DDR
0
W
3
P53DDR
0
W
If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 216 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DR
0
R/W
6
P56DR
Undefined*
R
P5DR stores output data for the port 5 pins that are
used as the general output port.
5
P55DR
0
R/W
4
P54DR
0
R/W
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
Note:
*
If this register is read, the P5DR values are read for
the bits with the corresponding P5DDR bits set to 1.
For the bits with the corresponding P5DDR bits
cleared to 0, the pin states are read.
The initial value is determined in accordance with the pin state of P56.
(3)
Pin Functions
(a)
Normal Extended Mode and Address-Data Multiplex Extended Mode
Port pin 57 is automatically set to function as a bus control output pin. The functions of port pins
56 to 50 are the same as those in single-chip mode.
(b)
Single-Chip Mode
Port 5 pins can operate as the SCIF, SCI_1, and SSU input/output, noise canceler input, or general
I/O port pins. The relationship between register setting values and pin functions are as follows.
• P57
The pin function is switched as shown below according to the P57DDR bit.
P57DDR
Pin function
0
1
P57 input pin
P57 output pin
Rev. 2.00 Aug. 20, 2008 Page 217 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P56/EXCL/φ
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P56DDR bit.
P56DDR
0
EXCLE
Pin function
1
0
1
X
P56 input pin
EXCL input pin
φ output pin
[Legend] X: Don't care.
• P55/IRQ13/SSI
The pin function is switched as shown below according to the RE bit in SSER of the SSU and
the P55DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of
the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin. To use as the
IRQ13 input pin, clear the P55DDR bit to 0.
RE
0
P55DDR
Pin function
1
0
1
X
P55 input pin
P55 output pin
SSI input pin
IRQ13 input pin
[Legend] X: Don't care.
• P54/IRQ12/SSO
The pin function is switched as shown below according to the TE bit in SSER of the SSU and
the P54DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of
the interrupt controller is set to 1, this pin can be used as the IRQ12 input pin. To use as the
IRQ12 input pin, clear the P54DDR bit to 0.
TE
0
P54DDR
Pin function
0
1
X
P54 input pin
P54 output pin
SSO output pin
IRQ12 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 218 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• P53/IRQ11/RxD1
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_1 and the P53DDR bit.
When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ11 input pin. To use as the IRQ11 input
pin, clear the P53DDR bit to 0.
RE
0
1
P53DDR
0
1
X
Pin function
P53 input pin
P53 output pin
RxD1 input pin
IRQ11 input pin
[Legend] X: Don't care.
• P52/IRQ10/TxD1
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_1 and the P52DDR bit.
When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ10 input pin. To use as the IRQ10 input
pin, clear the P52DDR bit to 0.
TE
0
P52DDR
Pin function
1
0
1
X
P52 input pin
P52 output pin
TxD1 output pin
IRQ10 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 219 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P51/IRQ9/RxDF
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P51DDR bit.
When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ9 input pin. To use as the IRQ9 input pin,
clear the P51DDR bit to 0.
SCIF
Disabled
P51DDR
Pin function
Enabled
0
1
X
P51 input pin
P51 output pin
RxDF input pin
IRQ9 input pin
[Legend] X: Don't care.
• P50/IRQ8/TxDF
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P50DDR bit.
When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ8 input pin. To use as the IRQ8 input pin,
clear the P50DDR bit to 0.
SCIF
Disabled
P50DDR
Pin function
0
1
X
P50 input pin
P50 output pin
TxDF output pin
IRQ8 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 220 of 1198
REJ09B0403-0200
Enabled
Section 8 I/O Ports
8.1.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins can also function as the bidirectional data bus, PWMX
output, SCIF and SSU control input/output, and interrupt input pins. The pin functions change
according to the operating mode. In addition, port 6 pins can also be used as the extended data bus
pins (D0 to D0). Port 6 has the following registers.
• Port 6 data direction register (P6DDR)
• Port 6 data register (P6DR)
• Port 6 pull-up MOS control register (P6PCR)
(1)
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
If port 6 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P6DDR bits are set to 1, and as input ports
when cleared to 0.
4
P64DDR
0
W
3
P63DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
•
Normal extended mode (16-bit bus)
These bits have no effect on operation.
•
Other modes
If port 6 pins are specified for use as the general
I/O port, the corresponding pins function as output
port when the P6DDR bits are set to 1, and as
input port when cleared to 0.
Rev. 2.00 Aug. 20, 2008 Page 221 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DR
0
R/W
6
P66DR
0
R/W
These bits store output data for the port 6 pins that
are used as the general output port.
5
P65DR
0
R/W
4
P64DR
0
R/W
If this register is read, the P6DR values are read for
the bits with the corresponding P6DDR bits set to 1.
For the bits with the corresponding P6DDR bits
cleared to 0, the pin states are read.
3
P63DR
0
R/W
•
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
Normal extended mode (16-bit data bus)
Since the corresponding pins function as
bidirectional data bus pins, the value in these bits
has no effect on operation.
If this register is read, the P6DR values are read
for the bits with the corresponding P6DDR bits set
to 1. For the bits with the corresponding P6DDR
bits cleared to 0, 1 is read.
•
Other modes
These bits store output data for the port 6 pins
that are used as the general output port.
If this register is read, the P6DR values are read
for the bits with the corresponding P6DDR bits set
to 1. For the bits with the corresponding P6DDR
bits cleared to 0, the pin states are read.
Rev. 2.00 Aug. 20, 2008 Page 222 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(3)
Port 6 Pull-Up MOS Control Register (P6PCR)
P6PCR controls the port 6 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P67PCR
0
R/W
•
6
P66PCR
0
R/W
5
P65PCR
0
R/W
4
P64PCR
0
R/W
3
P23PCR
0
R/W
2
P62PCR
0
R/W
1
P61PCR
0
R/W
0
P60PCR
0
R/W
(4)
Pin Functions
(a)
Normal Extended Mode
Normal extended mode (16-bit bus)
This register has no effect on operation.
•
Other modes
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P6PCR bit is set to 1.
• 16-bit bus mode
Port pins 63 to 60 are automatically set to function as bidirectional data bus pins.
• 8-bit bus mode
The operation is the same as that in single-chip mode.
(b)
Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode.
(c)
Single-Chip Mode
Port 6 pins can operate as the PWMX output, SCIF and SSU control input/output, interrupt input,
or general I/O port pins. The relationship between register setting values and pin functions are as
follows.
Rev. 2.00 Aug. 20, 2008 Page 223 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P67/ExIRQ8/SSCK
The pin function is switched as shown below according to the SCKS bit in SSCRH of the SSU
and the P67DDR bit. When the ISS8 bit in ISSR16 is set to 1, this pin can be used as the
ExIRQ8 input pin. To use as the ExIRQ8 input pin, clear the P67DDR bit to 0.
SCKS
0
P67DDR
Pin function
1
0
1
X
P67 input pin
P67 output pin
SSCK I/O pin
ExIRQ8 input pin
[Legend] X: Don't care.
• P66/ExIRQ9/SCS
The pin function is switched as shown below according to the CSS1 and CSS0 bits in SSCRH
of the SSU and the P66DDR bit. When the ISS9 bit in ISSR16 is set to 1, this pin can be used
as the ExIRQ9 input pin. To use as the ExIRQ9 input pin, clear the P66DDR bit to 0.
CSS1, CSS0
00
P66DDR
Pin function
01 or 1X
0
1
X
P66 input pin
P66 output pin
SCS I/O pin
ExIRQ9 input pin
[Legend] X: Don't care.
• P65/ExIRQ10/RTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P65DDR bit.
When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ10 input pin. To
use as the ExIRQ10 input pin, clear the P65DDR bit to 0.
SCIF
Disabled
P65DDR
Pin function
0
1
X
P65 input pin
P65 output pin
RTS output pin
IRQ10 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 224 of 1198
REJ09B0403-0200
Enabled
Section 8 I/O Ports
• P64/ExIRQ11/CTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P64DDR bit.
When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ11 input pin. To
use as the ExIRQ11 input pin, clear the P64DDR bit to 0.
SCIF
Disabled
P64DDR
Pin function
Enabled
0
1
X
P64 input pin
P64 output pin
CTS input pin
IRQ11 input pin
[Legend] X: Don't care.
• P63/PWX3
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P63DDR bit.
P63DDR
0
1
X
PWMXS
0
1
0
1
0
OEB
0
X
0
X
1
Pin function
P63 input pin
P63 output pin
PWX3 output pin
[Legend] X: Don't care.
• P62/PWX2
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P62DDR bit.
P62DDR
0
1
X
PWMXS
0
1
0
1
0
OEA
0
X
0
X
1
Pin function
P62 input pin
P62 output pin
PWX2 output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 225 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P61/IRQ15/PWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P61DDR bit. To use this pin as
the IRQ15 input pin, clear the P61DDR bit to 0.
P61DDR
0
1
X
PWMXS
0
1
0
1
0
OEB
0
X
0
X
1
Pin function
P61 input pin
P61 output pin
PWX1 output pin
IRQ15 input pin
[Legend] X: Don't care.
• P60/IRQ14/PWX1
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P60DDR bit. To use this pin as
the IRQ14 input pin, clear the P60DDR bit to 0.
P60DDR
0
1
X
PWMXS
0
1
0
1
0
OEA
0
X
0
X
1
Pin function
P60 input pin
P60 output pin
PWX0 output pin
IRQ14 input pin
[Legend] X: Don't care.
(5)
Port 6 Input Pull-Up MOS
Port 6 has built-in input pull-up MOSs that can be controlled by software. Table 8.6 summarizes
the input pull-up MOS states.
Table 8.6
Port 6 Input Pull-Up MOS States
Reset
Hardware Standby Mode
Software Standby Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when input state, P6DDR = 0, and P6PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 226 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins can also function as the A/D converter analog input pins.
Port 7 has the following register.
• Port 7 input data register (P7PIN)
(1)
Port 7 Input Data Register (P7PIN)
P7PIN indicates the states of the port 7 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P77PIN
Undefined*
R
When this register is read, the pin states are read.
6
P76PIN
Undefined*
R
5
P75PIN
Undefined*
R
Since this register is allocated to the same address as
PBDDR, writing to this register writes data to PBDDR
and the port B setting is changed.
4
P74PIN
Undefined*
R
3
P73PIN
Undefined*
R
2
P72PIN
Undefined*
R
1
P71PIN
Undefined*
R
0
P70PIN
Undefined*
R
Note:
*
(2)
The initial values are determined in accordance with the pin states of P77 to P70.
Pin Functions
Each pin of port 7 can also be used as the analog input pins of the A/D converter (AN0 to AN7).
• P77/AN7
The pin function is switched as shown below according to the CH2 to CH0 bits in ADCSR of
the A/D converter. Do not set these bits to other values than those shown in the following
table.
CH2 to CH0
B'111
Other than B'111
Pin function
AN7 input pin
P77 input pin
Rev. 2.00 Aug. 20, 2008 Page 227 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P76/AN6
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'110
Other than B'110
B'110 to B'111
B'000 to B'101
Pin function
AN6 input pin
P76 input pin
AN6 input pin
P76 input pin
• P75/AN5
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'101
Other than B'101
B'101 to B'111
B'000 to B'100
Pin function
AN5 input pin
P75 input pin
AN5 input pin
P75 input pin
• P74/AN4
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'100
Other than B'100
B'100 to B'111
B'000 to B'011
Pin function
AN4 input pin
P74 input pin
AN4 input pin
P74 input pin
Rev. 2.00 Aug. 20, 2008 Page 228 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P73/AN3
The pin function is switched as shown below according to the combination of the SCANE and
SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
1
0
1
CH2 to CH0
B'011
Other than
B'011
B'011
Other than
B'011
Pin function
AN3 input pin
P73 input pin
AN3 input pin
P73 input pin
B'011 to B'111 B'000 to B'010
AN3 input pin
P73 input pin
[Legend] X: Don't care.
• P72/AN2
The pin function is switched as shown below according to the combination of the SCANE and
SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
CH2 to CH0
Pin function
B'010
1
0
Other than
B'010
B'010 to B'011
AN2 input pin P72 input pin AN2 input pin
1
Other than B'010 to B'111
B'010 to B'011
P72 input pin
B'000 to
B'001
AN2 input pin
P72 input pin
[Legend] X: Don't care.
• P71/AN1
The pin function is switched as shown below according to the combination of the SCANE and
SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
CH2 to CH0
Pin function
B'001
1
0
Other than
B'001
B'001 to
B'011
1
Other than
B'001 to
B'011
B'001 to
B'111
B'000
AN1 input pin P71 input pin AN1 input pin P71 input pin AN1 input pin P71 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 229 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P70/AN0
The pin function is switched as shown below according to the combination of the SCANE and
SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
1
0
1
CH2 to CH0
B'000
Other than
B'000
B'000 to
B'011
Other than B'000 to
B'011
B'000 to B'111
Pin function
AN0 input pin
P70 input pin
AN0 input pin
P70 input pin
AN0 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 230 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.8
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins can also function as the A/D converter external trigger input,
SCI_1 and SCI_3 input/output, IIC_0 and IIC_1 input/output, and interrupt input pins. Pins 83 to
80 perform the NMOS push-pull output. Port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
(1)
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DDR
0
W
6
P86DDR
0
W
5
P85DDR
0
W
If port 8 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P8DDR bits are set to 1, and as input port
when cleared to 0.
4
P84DDR
0
W
3
P83DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
Since this register is allocated to the same address as
PBPIN, states of the port 8 pins are when this register
is read.
Rev. 2.00 Aug. 20, 2008 Page 231 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DR
0
R/W
6
P86DR
0
R/W
P8DR stores output data for the port 8 pins that are
used as the general output port.
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
(3)
If this register is read, the P8DR values are read for
the bits with the corresponding P8DDR bits set to 1.
For the bits with the corresponding P8DDR bits
cleared to 0, the pin states are read.
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P87/ExIRQ15/TxD3/ADTRG
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_3, the SMIF bit in SCMR, and the P87DDR bit.
When the TRGS1 and EXTRGS bits are both set to 1 and the TRGS0 bit is cleared to 0 in
ADCR of the A/D converter, this pin can be used as the ADTRG input pin.
When the ISS15 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ15 input pin. To
use this pin as the ExIRQ15 input pin, clear the P87DDR bit to 0.
P87DDR
0
1
SMIF
0
1
0
1
0
TE
0
X
0
X
1
Pin function
P87 input pin
ExIRQ15 input pin/
ADTRG input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 232 of 1198
REJ09B0403-0200
P87 output pin
TxD3 output pin
Section 8 I/O Ports
• P86/ExIRQ14/RxD3
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_3, the SMIF bit in SCMR, and the P86DDR bit.
When the ISS14 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ14 input pin. To
use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0.
P86DDR
0
SMIF
0
RE
Pin function
1
1
0
0
1
0
P86 input pin
RxD3 input pin RxD3 input/output pin
P86 output pin
ExIRQ14 input pin
• P85/ExIRQ13/SCK1
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit.
When the ISS13 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ13 input pin. To
use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0.
CKE1
0
C/A
0
CKE0
0
P85DDR
Pin function
1
1
X
1
X
X
0
1
X
X
X
P85 input pin
P85 output
pin
SCK1 output
pin
SCK1 output
pin
SCK1 input
pin
ExIRQ13 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 233 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P84/ExIRQ12/SCK3
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_3, the CKE1 and CKE0 bits in SCR, and the P84DDR bit.
When the ISS12 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ12 input pin. To
use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0.
CKE1
0
C/A
1
0
CKE0
0
P84DDR
Pin function
1
X
1
X
X
0
1
X
X
X
P84 input pin
P84 output
pin
SCK3 output
pin
SCK3 output
pin
SCK3 input
pin
ExIRQ12 input pin
[Legend] X: Don't care.
• P83/SDA1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P83DDR bit.
When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The
output format for SDA1 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P83DDR
Pin function
0
1
X
P83 input pin
P83 output pin
SDA1 input/output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 234 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• P82/SCL1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P82DDR bit.
When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The
output format for SCL1 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P82DDR
Pin function
1
0
1
X
P82 input pin
P82 output pin
SCL1 input/output pin
[Legend] X: Don't care.
• P81/SDA0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P81DDR bit.
When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The
output format for SDA0 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P81DDR
Pin function
1
0
1
X
P81 input pin
P81 output pin
SDA0 input/output pin
[Legend] X: Don't care.
• P80/SCL0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P80DDR bit.
When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The
output format for SCL0 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P80DDR
Pin function
1
0
1
X
P80 input pin
P80 output pin
SCL0 input/output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 235 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins can function as the bus control input/output pins. The pin
functions change according to the operating mode. Port 9 has the following registers.
• Port 9 data direction register (P9DDR)
• Port 9 data register (P9DR)
(1)
Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the port 9 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DDR
0
W
6
P96DDR
0
W
5
P95DDR
0
W
If port 9 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P9DDR bits are set to 1, and as input port
when cleared to 0.
4
P94DDR
0
W
3
P93DDR
0
W
2
P92DDR
0
W
1
P91DDR
0
W
0
P90DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 236 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DR
0
R/W
6
P96DR
0
R/W
P9DR stores output data for the port 9 pins that are
used as the general output port.
5
P95DR
0
R/W
4
P94DR
0
R/W
3
P93DR
0
R/W
2
P92DR
0
R/W
1
P91DR
0
R/W
0
P90DR
0
R/W
(3)
If this register is read, the P9DR values are read for
the bits with the corresponding P9DDR bits set to 1.
For the bits with the corresponding P9DDR bits
cleared to 0, the pin states are read.
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P97/WAIT/CS256
The pin function is switched as shown below according to the operating mode and the
combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR and the P97DDR bit.
Operating
mode
Extended mode
WMS1
0
CS256E
P97DDR
Pin function
0
0
1
P97 input pin P97 output
pin
Single-chip mode
1
X
1
X
X
X
X
CS256 output
pin
0
1
WAIT input P97 input pin P97 output
pin
pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 237 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P96
The pin function is switched as shown below according to the P96DDR bit.
P96DDR
Pin function
0
1
P96 input pin
P96 output pin
• P95/AS/IOS
The pin function is switched as shown below according to the operating mode and the
combination of the IOSE bit in SYSCR and the P95DDR bit.
Operating
mode
Extended mode
P95DDR
X
IOSE
Pin function
Single-chip mode
0
1
0
1
X
X
AS output pin
IOS output pin
P95 input pin
P95 output pin
[Legend] X: Don't care.
• P94/ExPWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P94DDR bit.
P94DDR
0
1
X
PWMXS
0
1
0
1
1
OEB
X
0
X
0
1
Pin function
P94 input pin
P94 output pin
ExPWX1 output pin
[Legend] X: Don't care.
• P93/ExPWX0
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P93DDR bit.
P93DDR
0
PWMXS
0
OEA
X
Pin function
1
1
0
1
0
X
0
P93 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 238 of 1198
REJ09B0403-0200
X
P93 output pin
1
1
ExPWX0 output pin
Section 8 I/O Ports
• P92/HBE
The pin function is switched as shown below according to the operating mode, the OBE bit in
PTCNT0, and the P92DDR bit.
Operating
mode
Extended mode
OBE
P92DDR
Pin function
0
1
0
P92 input pin
Single-chip mode
1
X
X
P92 output pin HBE output pin
0
1
P92 input pin
P92 output pin
[Legend] X: Don't care.
• P91/AH
The pin function is switched as shown below according to the operating mode, the ADMXE
bit in SYSCR2, and the P91DDR bit.
Operating
mode
Extended mode
ADMXE
0
P91DDR
Pin function
Single-chip mode
1
X
0
1
X
0
1
P91 input pin
P91 output pin
AH output pin
P91 input pin
P91 output pin
[Legend] X: Don't care.
• P90/LBE
The pin function is switched as shown below according to the operating mode, the OBE bit in
PTCNT0, and the P90DDR bit.
Operating
mode
Extended mode
OBE
0
P90DDR
Pin function
0
P90 input pin
Single-chip mode
1
1
X
X
P90 output pin LBE output pin
0
1
P90 input pin
P90 output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 239 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.10
Port A
Port A is an 8-bit I/O port. Port A pins can also function as the address output, event counter input,
EtherC control I/O, and interrupt input pins. Port A has the following registers. PADDR and
PAPIN are allocated to the same address.
• Port A data direction register (PADDR)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
(1)
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
6
PA6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 240 of 1198
REJ09B0403-0200
As the address of this register is the same as that of
PAPIN, reading from this register indicates the state
of port A.
Section 8 I/O Ports
(2)
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
PAODR stores output data for the port A pins that are
used as the general output port.
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
(3)
Port A Input Data Register (PAPIN)
PAPIN indicates the states of the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PIN
Undefined*
R
Pin states are read from this register.
6
PA6PIN
Undefined*
R
5
PA5PIN
Undefined*
R
As the address of this register is the same as that of
PADDR, writing to this register changes the settings
of port A, that have been written to PADDR.
4
PA4PIN
Undefined*
R
3
PA3PIN
Undefined*
R
2
PA2PIN
Undefined*
R
1
PA1PIN
Undefined*
R
0
PA0PIN
Undefined*
R
Note: The initial values are determined in accordance with the pin states of PA7 to PA0.
Rev. 2.00 Aug. 20, 2008 Page 241 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as
follows.
(a)
Normal Extended Mode
Port A pins can function as address output, interrupt input, event counter input, EtherC control I/O
or I/O port pins, and input or output can be specified in bit units.
Address 18 and address 13 in the following tables are expressed by the following logical
expressions according to the control bits of the bus controller or other module.
Address 18 = 1: ADFULLE
Address 13 = 1: ADFULLE • CS256E • IOSE
• PA7/ExIRQ7/EVENT7/A23/EXOUT
The pin function is switched as shown below according to the setting of address 18 and the
PA7DDR bit.
Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin.
When using the pin as the ExIRQ7 input or an EVENT input pin, clear the PA7DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 when
using the pin as the PA7 or A23 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the EXOUT output pin.
PA7DDR
0
1
1
Address 18
X
1
0
Pin function
PA7 input pin
PA7 output pin
A23 output pin
ExIRQ7 input pin/EVENT7 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 242 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA6/ExIRQ6/EVENT6/A22/LNKSTA
The pin function is switched as shown below according to the setting of address 18 and the
PA6DDR bit.
Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin.
When using the pin as the ExIRQ6 input, or an EVENT input pin, clear the PA6DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 when
using the pin as the PA6 or A22 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the LNKSTA input pin.
PA6DDR
0
Address 18
Pin function
1
1
1
PA6 input pin
0
PA6 output pin
A22 output pin
ExIRQ6 input pin/EVENT6 input pin
• PA5/ExIRQ5/EVENT5/A21/WOL
The pin function is switched as shown below according to the setting of the address 18, and the
PA5DDR bit.
Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin.
When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when
using the pin as the A21 or PA5 output pin.
When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as
the WOL output pin.
PA5DDR
0
1
1
Address 18
X
1
0
Pin function
PA5 input pin
PA5 output pin
A21 output pin
ExIRQ5 input pin/
EVENT5 input pin
Rev. 2.00 Aug. 20, 2008 Page 243 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18
The pin function is switched as shown below according to the setting of address 18 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when
using the pin as the PAn or Am output pin.
PAnDDR
0
1
1
Address 18
X
1
0
Pin function
PAn input pin
PAn output pin
Am output pin
ExIRQn input pin/EVENTn input pin
[Legend]
n = 4 to 2, m = 20 to 18
X: Don't care
• PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16
The pin function is switched as shown below according to the setting of address 13 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when
using the pin as the PAn or Am output pin.
PAnDDR
0
Address 13
X
1
0
Pin function
PAn input pin
PAn output pin
Am output pin
ExIRQn input pin/EVENTn input pin
[Legend]
n = 1, 0; m = 17, 16
X: Don't care
Rev. 2.00 Aug. 20, 2008 Page 244 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
(b)
Single-Chip Mode and Address-Data Multiplex Extended Mode
Port A pins can also function as interrupt input and event counter input pins.
• PA7/ExIRQ7/EVENT7/EXOUT
The pin function is switched as shown below according to the PA7DDR bit.
Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin.
When using this pin as the ExIRQ7 input or EVENT7 input pin, clear the PA7DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 to use
the pin as the PA7 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the EXOUT output pin.
PA7DDR
Pin function
0
1
PA7 input pin
PA7 output pin
ExIRQ7 input pin/EVENT7 input pin
• PA6/ExIRQ6/EVENT6/LNKSTA
The pin function is switched as shown below according to the PA6DDR bit.
Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin.
When using this pin as the ExIRQ6 input, EVENT6 input, input pin, clear the PA6DDR bit to
0. Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 to
use the pin as the PA6 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the LNKSTA input pin.
PA6DDR
Pin function
0
1
PA6 input pin
PA6 output pin
ExIRQ6 input pin/EVENT6 input pin
Rev. 2.00 Aug. 20, 2008 Page 245 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA5/ExIRQ5/EVENT5/WOL
The pin function is switched as shown below according to and the PA5DDR bit.
Setting the ISS5 bit in ISSR makes the pin to function as the ExIRQ5 input pin.
When using this pin as the ExIRQ5 input or EVENT5 input pin, clear the PA5DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 to use
the pin as the PA5 output pin.
When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as
the WOL output pin.
PA5DDR
Pin function
0
1
PA5 input pin
PA5 output pin
ExIRQ5 input pin/EVENT5 input pin
• PA4/ExIRQ4/EVENT4, PA3/ExIRQ3/EVENT3, PA2/ExIRQ2/EVENT2,
PA1/ExIRQ1/EVENT1, PA0/ExIRQ0/EVENT0
The pin function is switched as shown below according to the PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using this pin as the ExIRQn input or EVENTn input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use
the pin as the PAn output pin.
PAnDDR
Pin function
0
1
PAn input pin
PAn output pin
ExIRQn input pin/EVENTn input pin
[Legend]
n = 4 to 0
Rev. 2.00 Aug. 20, 2008 Page 246 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Input Pull-Up MOS
Port A has built-in input pull-up MOSs that can be controlled by software. This input pull-up
MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PAnDDR
0
PAnODR
PAn pull-up MOS
[Legend]
1
1
0
X
ON
OFF
OFF
n = 7 to 0, X: Don't care.
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.7 summarizes the input pull-up MOS states.
Table 8.7
Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 247 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.11
Port B
Port B is an 8-bit I/O port. Port B pins can also function as the bidirectional data bus, de-bounced
input, and EtherC control I/O pins. The pin functions change according to the operating mode.
Port B has the following registers.
• Port B data direction register (PBDDR)
• Port B output data register (PBODR)
• Port B input data register (PBPIN)
• Noise canceler enable register (P4BNCE)
• Noise canceler mode control register (P4BNCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit
Bit Name
Initial Value
R/W Description
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 248 of 1198
REJ09B0403-0200
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Section 8 I/O Ports
(2)
Port B Output Data Register (PBODR)
PBDR stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W Description
7
PB7DR
0
6
PB6DR
0
R/W PBODR stores output data for the port B pins that are
used as the general output port.
R/W
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
(3)
Port B Input Data Register (PBPIN)
PBPIN indicates the states of the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PB6PIN
Undefined*
R
5
PB5PIN
Undefined*
R
Since this register is allocated to the same address as
P8DDR, writing to this register writes data to P8DDR
and the port 8 setting is changed.
4
PB4PIN
Undefined*
R
3
PB3PIN
Undefined*
R
2
PB2PIN
Undefined*
R
1
PB1PIN
Undefined*
R
0
PB0PIN
Undefined*
R
Note:
*
The initial values are determined in accordance with the pin states of PB7 to PB0.
Rev. 2.00 Aug. 20, 2008 Page 249 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Noise Canceler Enable Register (P4BNCE)
P4BNCE enables or disables the noise canceler circuits of port 4 and port B pins in bit units.
Bit
Initial Value
R/W Description
7 to 4 P47NCE to
P44NCE
All 0
R/W Bits for port 4 setting
3
PB3NCE
0
2
PB2NCE
0
1
PB1NCE
0
0
PB0NCE
0
R/W Enables the noise canceler circuit for the corresponding
pin and the pin state is fetched into PBDR at the
R/W
sampling cycle set by NCCS.
R/W
The operation changes according to the other control
R/W bits. See section 8.1.11 (7), Pin Functions, for details.
(5)
Bit Name
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 and port B in bit
units.
Bit
Bit Name
Initial Value
R/W Description
7 to 4 P47NCMC
to
P44NCMC
All 1
R/W Bits for port 4 setting
3
PB3NCMC
1
R/W Expected value setting
2
PB2NCMC
1
1
PB1NCMC
1
0
PB0NCMC
1
R/W 1 expected: 1 is stored in the port data register while 1
is input stably.
R/W
0 expected: 0 is stored in the port data register while 0
R/W
is input stably.
Rev. 2.00 Aug. 20, 2008 Page 250 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name
Initial Value
R/W Description
7 to 3 
Undefined
R/W Reserved
2
NCCK2
0
1
NCCK1
0
R/W These bits set the sampling cycle of the noise
R/W cancelers.
0
NCCK0
0
R/W •
Undefined value is read from these bits.
When φ = 34 MHz
000: 0.06 µs
φ/2
100: 963.8 µs φ/32768
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
011: 240.9 µs φ/8192
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
Port data
register
∆t
Sampling clock
Figure 8.5 Noise Canceler Circuit
Rev. 2.00 Aug. 20, 2008 Page 251 of 1198
REJ09B0403-0200
Section 8 I/O Ports
PBn input
1 expected
PBnDR
0 expected
PBnDR
(n = 3 to 0)
Figure 8.6 Noise Canceler Operation
Rev. 2.00 Aug. 20, 2008 Page 252 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(7)
Pin Functions
• PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK
PB4/EVENT12/RM_TX-EN
The pin function is switched as shown below according to the PBnDDR bit. When using this
pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O
pins when the EtherC is enabled.
EtherC,
E-DMAC
Either of them is stopped
PBnDDR
0
Both of then are
stopped
1
X
Event
counter
Disabled
Enabled
X
X
Pin
function
PBn input pin
EVENTm input
pin
PBn output pin
RM_xxxx
EtherC I/O pin
[Legend]
Note: *
n = 7 to 4, m = 15 to 12, X: Don't care.
See section 7.3, DTC Event Counter, for the event counter settings.
• PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0,
PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC, E-DMAC, the PBnDDR bit and the PBnNCE bit.
EtherC,
E-DMAC
Either of them is stopped
PBnDDR
0
Event
counter
PBnNCE
Pin
function
[Legend]
Disabled
0
1
PBn input pin
Both of then are
stopped
1
X
Enabled
X
X
X
X
X
EVENTm input
pin
PBn output pin
RM_xxxx
EtherC I/O pin
n = 3 to 0, m = 11 to 8, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 253 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.12
Port C
Port C is an 8-bit I/O port. Port C pins can also function as the bus control output, and IIC_2,
IIC_3, and IIC_4 input/output pins. The output format of ports C0 to C5 is NMOS push-pull
output. Port C has the following registers.
• Port C data direction register (PCDDR)
• Port C output data register (PCODR)
• Port C input data register (PCPIN)
(1)
Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
6
PC6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 254 of 1198
REJ09B0403-0200
Since this register is allocated to the same address as
PCPIN, states of the port C pins are returned when
this register is read.
Section 8 I/O Ports
(2)
Port C Output Data Register (PCODR)
PCODR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
The PCODR register stores the output data for the
pins that are used as the general output port.
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
(3)
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states of port C.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PC6 PIN
Undefined*
R
5
PC5PIN
Undefined*
R
Since this register is allocated to the same address as
PCDDR, writing to this register writes data to PCDDR
and the port C setting is changed.
4
PC4 PIN
Undefined*
R
3
PC3 PIN
Undefined*
R
2
PC2 PIN
Undefined*
R
1
PC1 PIN
Undefined*
R
0
PC0 PIN
Undefined*
R
Note: The initial values are determined in accordance with the states of PC7 to PC0 pins.
Rev. 2.00 Aug. 20, 2008 Page 255 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
(a)
Normal Extended Mode and Address-Data Multiplex Extended Mode
Port C pins can also function as the bus control output and IIC_2, IIC_3, and IIC_4 input/output
pins. The relationship between register setting values and pin functions are as follows.
• PC7
The PC7 pin functions as a bus control output pin.
• PC6
When set for 16-bit bus width, the PC7 pin functions as a bus control output pin. When 8-bit
bus width, the pin function is the same as that in single-chip mode.
• PC5 to PC0
The pin functions are the same as those in single-chip mode.
(b)
Single-Chip Mode
• PC7, PC6
The pin function is switched as shown below according to the PCnDDR bit.
PCnDDR
Pin function
0
1
PCn input pin
PCn output pin
[Legend] n = 7, 6
• PC5/SDA4
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_4 and the PC5DDR bit.
ICE
0
PC5DDR
Pin function
1
X
PC5 input pin
PC5 output pin
SDA4 input/output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 256 of 1198
REJ09B0403-0200
1
0
Section 8 I/O Ports
• PC4/SCL4
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_4 and the PC4DDR bit.
ICE
0
PC4DDR
Pin function
[Legend]
1
0
1
X
PC4 input pin
PC4 output pin
SCL4 input/output pin
X: Don't care.
• PC3/SDA3
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_3 and the PC3DDR bit.
ICE
0
PC3DDR
Pin function
[Legend]
1
0
1
X
PC3 input pin
PC3 output pin
SDA3 input/output pin
X: Don't care.
• PC2/SCL3
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_3 and the PC2DDR bit.
ICE
0
PC2DDR
Pin function
[Legend]
1
0
1
X
PC2 input pin
PC2 output pin
SCL3 input/output pin
X: Don't care.
• PC1/SDA2
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_2 and the PC1DDR bit.
ICE
0
PC1DDR
Pin function
[Legend]
1
0
1
X
PC1 input pin
PC1 output pin
SDA2 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 257 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PC0/SCL2
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_2 and the PC0DDR bit.
ICE
0
PC0DDR
Pin function
[Legend]
0
1
X
PC0 input pin
PC0 output pin
SCL2 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 258 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
8.1.13
Port D
Port D is an 8-bit I/O port. Port D pins can also function as the IIC_5 input/output and LPC
input/output pins. The output format of PD7 and PD6 pins is NMOS push-pull output. Port D has
the following registers.
• Port D data direction register (PDDDR)
• Port D output data register (PDODR)
• Port D input data register (PDPIN)
(1)
Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
If port D pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the PDDDR bits are set to 1, and as input port
when cleared to 0.
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Since this register is allocated to the same address as
PDPIN, the states of the port D pins are returned
when this register is read.
Rev. 2.00 Aug. 20, 2008 Page 259 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7ODR
0
R/W
6
PD6ODR
0
R/W
The PCODR register stores the output data for the
pins that are used as the general output port.
5
PD5ODR
0
R/W
4
PD4ODR
0
R/W
3
PD3ODR
0
R/W
2
PD2ODR
0
R/W
1
PD1ODR
0
R/W
0
PD0ODR
0
R/W
(3)
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PD6 PIN
Undefined*
R
5
PD5PIN
Undefined*
R
Since this register is allocated to the same address as
PDDDR, writing to this register writes data to PDDDR
and the port D setting is changed.
4
PD4 PIN
Undefined*
R
3
PD3 PIN
Undefined*
R
2
PD2 PIN
Undefined*
R
1
PD1 PIN
Undefined*
R
0
PD0 PIN
Undefined*
R
Note: The initial values are determined in accordance with the states of PD7 to PD0 pins.
Rev. 2.00 Aug. 20, 2008 Page 260 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
Port D pins can also function as the LPC input/output and IIC_5 input/output pins. The
relationship between register setting values and pin functions are as follows.
The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in
HICR5 are cleared to 0.
• PD7/SDA5
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_5 and the PD7DDR bit.
ICE
0
PD7DDR
Pin function
[Legend]
1
0
1
X
PD7 input pin
PD7 output pin
SDA5 input/output pin
X: Don't care.
• PD6/SCL5
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_5 and the PD6DDR bit.
ICE
0
PD6DDR
Pin function
[Legend]
1
0
1
X
PD6 input pin
PD6 output pin
SCL5 input/output pin
X: Don't care.
• PD5/LPCPD
The pin function is switched as shown below according to the PD5DDR bit. This pin can be
used as the LPCPD input pin when the LPC is enabled.
LPC
PD5DDR
Pin function
Disabled
Enabled
0
1
0
PD5 input pin
PD5 output pin
LPCPD input pin
Rev. 2.00 Aug. 20, 2008 Page 261 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PD4/CLKRUN
The pin function is switched as shown below according to the PD4DDR bit. This pin can be
used as the CLKRUN input pin when the LPC is enabled.
LPC
PD4DDR
Pin function
Disabled
Enabled
0
1
0
PD4 input pin
PD4 output pin
CLKRUN input/output pin
• PD3/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
in HICR0 of the LPC and the PD3DDR bit.
FGA20E
PD3DDR
Pin function
0
1
0
1
0
PD3 input pin
PD3 output pin
GA20 output pin
• PD2/PME
The pin function is switched as shown below according to the combination of the PMEE bit in
HICR0 of the LPC and the PD2DDR bit.
PMEE
PD2DDR
Pin function
0
1
0
1
0
PD2 input pin
PD2 output pin
PME output pin
• PD1/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit in
HICR0 of the LPC and the PD1DDR bit.
LSMIE
PD1DDR
Pin function
0
0
1
0
PD1 input pin
PD1 output pin
LSMI output pin
Rev. 2.00 Aug. 20, 2008 Page 262 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• PD0/LSCI
The pin function is switched as shown below according to the combination of the LSCIE bit in
HICR0 of the LPC and the PD0DDR bit.
LSCIE
0
PD0DDR
Pin function
(5)
1
0
1
0
PD0 input pin
PD0 output pin
LSCI output pin
Input Pull-Up MOS
Port pins D5 to D0 have built-in input pull-up MOSs that can be controlled by software. This input
pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit
basis.
PDnDDR
0
PDnODR
PDn pull-up MOS
[Legend]
1
1
0
X
ON
OFF
OFF
n = 5 to 0, X: Don't care.
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.8 summarizes the input pull-up MOS states.
Table 8.8
Port D Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PDDDR = 0 and PDODR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 263 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.14
Port E
Port E is an 8-bit I/O port. Port E pins can also function as the LPC input/output pins. Port E has
the following registers.
• Port E data direction register (PEDDR)
• Port E output data register (PEODR)
• Port E input data register (PEPIN)
(1)
Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
6
PE6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
(2)
Since this register is allocated to the same address as
PEPIN, states of the port E pins are returned when
this register is read.
Port E Output Data Register (PEODR)
PEODR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7ODR
0
R/W
6
PE6ODR
0
R/W
The PEODR register stores the output data for the
pins that are used as the general output port.
5
PE5ODR
0
R/W
4
PE4ODR
0
R/W
3
PE3ODR
0
R/W
2
PE2ODR
0
R/W
1
PE1ODR
0
R/W
0
PE0ODR
0
R/W
Rev. 2.00 Aug. 20, 2008 Page 264 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(3)
Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PE6PIN
Undefined*
R
5
PE5PIN
Undefined*
R
Since this register is allocated to the same address as
PEDDR, writing to this register writes data to PEDDR
and the port E setting is changed.
4
PE4PIN
Undefined*
R
3
PE3PIN
Undefined*
R
2
PE2PIN
Undefined*
R
1
PE1PIN
Undefined*
R
0
PE0PIN
Undefined*
R
Note: The initial value of these pins is determined in accordance with the state of pins PE7 to
PE0.
(4)
Pin Functions
Port E pins can also function as LPC input/output pins. The pin function is switched according to
whether the LPC module is enabled or disabled. The LPC is disabled when all of the bits LPC1E,
LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0.
• PE7/SERIRQ
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE7DDR bit.
LPC
Disabled
PE7DDR
Pin function
[Legend]
Enabled
0
1
X
PE7 input pin
PE7 output pin
SERIRQ input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 265 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PE6/LCLK
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE6DDR bit.
LPC
Disabled
PE6DDR
Pin function
[Legend]
Enabled
0
1
X
PE6 input pin
PE6 output pin
LCLK input pin
X: Don't care.
• PE5/LRESET
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE5DDR bit.
LPC
Disabled
PE5DDR
Pin function
[Legend]
Enabled
0
1
X
PE5 input pin
PE5 output pin
LRESET input pin
X: Don't care.
• PE4/LFRAME
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE4DDR bit.
LPC
Disabled
PE4DDR
Pin function
[Legend]
Enabled
0
1
X
PE4 input pin
PE4 output pin
LFRAME input pin
X: Don't care.
• PE3/LAD3
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE3DDR bit.
LPC
Disabled
PE3DDR
Pin function
[Legend]
0
1
X
PE3 input pin
PE3 output pin
LAD3 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 266 of 1198
REJ09B0403-0200
Enabled
Section 8 I/O Ports
• PE2/LAD2
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE2DDR bit.
LPC
Disabled
PE2DDR
Pin function
[Legend]
Enabled
0
1
X
PE2 input pin
PE2 output pin
LAD2 input/output pin
X: Don't care.
• PE1/LAD1
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE1DDR bit.
LPC
Disabled
PE1DDR
Pin function
[Legend]
Enabled
0
1
X
PE1 input pin
PE1 output pin
LAD1 input/output pin
X: Don't care.
• PE0/LAD0
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE0DDR bit.
LPC
Disabled
PE0DDR
Pin function
[Legend]
Enabled
0
1
X
PE0 input pin
PE0 output pin
LAD0 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 267 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.1.15
Port F
Port F is a 7-bit I/O port. Port F pins can also function as the PWMX output and EtherC control
input/output pins. Port F has the following registers.
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
(1)
Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the port F pins. PFDDR is initialized
only by a system reset, and retains the value even if an internal reset signal of the WDT is
generated.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
6
PF6DDR
0
W
5
PF5DDR
0
W
4
PF4DDR
0
W
When set to 1, the corresponding pin functions as an
output port pin; when cleared to 0, functions as an
input port pin.
3
PF3DDR
0
W
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 268 of 1198
REJ09B0403-0200
Since this register is allocated to the same address as
PFPIN, states of the port F pins are returned when
this register is read.
Section 8 I/O Ports
(2)
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins. PEODR is initialized only by a system reset, and
retains the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
Undefined value is read from this bit.
6
PF6ODR
0
R/W
5
PF5ODR
0
R/W
4
PF4ODR
0
R/W
3
PF3ODR
0
R/W
2
PF2ODR
0
R/W
1
PF1ODR
0
R/W
0
PF0ODR
0
R/W
(3)
Stores the output data for the pin that is used as the
general output port.
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
Undefined value is read from this bit.
6
PF6PIN
Undefined*
R
When this register is read, the pin states are read.
5
PF5PIN
Undefined*
R
4
PF4PIN
Undefined*
R
3
PF3PIN
Undefined*
R
Since this register is allocated to the same address as
PFDDR, writing to this register writes data to PFDDR
and the port F setting is changed.
2
PF2PIN
Undefined*
R
1
PF1PIN
Undefined*
R
0
PF0PIN
Undefined*
R
Note: The initial value of these pins is determined in accordance with the state of pins PF6 to
PF0.
Rev. 2.00 Aug. 20, 2008 Page 269 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
Port F is a 7-bit I/O port. Port F pins can also function as the PWM output and EtherC control
input/output pins. The relationship between the register settings and the pin function is shown
below.
• PF6/ExPWX2/RS14
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the PF6DDR bit.
PF6DDR
0
1
X
PWMXS
0
1
0
1
1
OEA
X
0
X
0
1
Pin function
[Legend]
PF6 input pin
PF6 output pin
ExPWX2 output pin
X: Don't care.
• PF5/RS13
The pin function is switched as shown below according to the PF5DDR bit.
PF5DDR
Pin function
0
1
PF5 input pin
PF5 output pin
• PF4/RS12
The pin function is switched as shown below according to the PF4DDR bit.
PF4DDR
Pin function
0
1
PF4 input pin
PF4 output pin
• PF3/ExPWX3/RS11
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the PF3DDR bit.
PF3DDR
0
1
X
PWMXS
0
1
0
1
OEA
X
0
X
0
Pin function
[Legend]
PF3 input pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 270 of 1198
REJ09B0403-0200
PF3 output pin
1
1
ExPWX3 output pin
Section 8 I/O Ports
• PF2/RS10
The pin function is switched as shown below according to the PF2DDR bit.
PF2DDR
Pin function
0
1
PF2 input pin
PF2 output pin
• PF1/RS9/MDC, PF0/RS8/MDIO
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and E-DMAC and the PFnDDR bit.
EtherC,
E-DMAC
Ether of them is stopped
PFnDDR
Pin function
[Legend]
Both of them are stopped
0
1
X
PFn input pin
PFn output pin
MDC output pin/
MDIO input/output pin
X: Don't care. n = 1, 0
Rev. 2.00 Aug. 20, 2008 Page 271 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2
I/O Ports for the H8S/2463 Group and the H8S/2462 Group
Table 8.9 is a summary of the port functions. The pins of each port also function as input/output
pins of peripheral modules and interrupt input pins. Each input/output port includes a data
direction register (DDR) that controls input/output and a data register (DR) that stores output data.
DDR and DR are not provided for input-only ports.
Pins of ports 1 to 4, 6, and A and pins D0 to D5 of port D have built-in input pull-up MOSs. For
port A pins and D0 to D5 pins, the on/off status of the input pull-up MOS is controlled by their
respective DDR and the output data register (ODR). Ports 1 to 4, and 6 have an input pull-up MOS
control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up
MOSs.
Port 3 pins and pins 47 to 44 and B3 to B0 have built-in de-bouncers (DBn) that eliminate noises
in the input signals.
Ports 4 and F are designed for retain state outputs (RSn), which retain the output values on the
pins even if a reset is generated when the watchdog timer has overflowed.
Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports
can drive a Darlington transistor in output mode. Port pins 80 to 83, C0 to C5, D6, and D7 are
NMOS push-pull output.
Rev. 2.00 Aug. 20, 2008 Page 272 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Table 8.9
Port Functions
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
Feature of
I/O
P17
P16
P15
P14
P13
P12
P11
P10
P17/A7/AD7
P16/A6/AD6
P15/A5/AD5
P14/A4/AD4
P13/A3/AD3
P12/A2/AD2
P11/A1/AD1
P10/A0/AD0
Built-in input
pull-up MOS
General I/O port
P27/DTR
multiplexed with SCIF P26/DSR
control I/O
P25/RI
P24/DCD
Same as left
Built-in input
pull-up MOS
General I/O port
multiplexed with
address output and
address-data
multiplex I/O
P23
P22
P21
P20
P23/A11/AD11
P22/A10/AD10
P21/A9/AD9
P20/A8/AD8
Port 3
General I/O port
multiplexed with debounced input and
bidirectional data bus
I/O
P37/ExDB7
P36/ExDB6
P35/ExDB5
P34/ExDB4
P33/ExDB3
P32/ExDB2
P31/ExDB1
P30/ExDB0
P37/ExDB7/D15
P36/ExDB6/D14
P35/ExDB5/D13
P34/ExDB4/D12
P33/ExDB3/D11
P32/ExDB2/D10
P31/ExDB1/D9
P30/ExDB0/D8
Built-in input
pull-up MOS
Port 4
General I/O port
multiplexed with
interrupt input, debounced input,
address output, and
address-data
multiplex I/O
P47/IRQ7/RS7/DB7/HC7
P46/IRQ6/RS6/DB6/HC6
P45/IRQ5/RS5/DB5/HC5
P44/IRQ4/RS4/DB4/HC4
P47/A15/AD15
P46/A14/AD14
P45/A13/AD13
P44/A12/AD12
Built-in input
pull-up MOS
General I/O port
multiplexed with
interrupt input and
bidirectional data
bus* I/O
P43/IRQ3/RS3/HC3
P42/IRQ2/RS2/HC2
P41/IRQ1/RS1/HC1
P40/IRQ0/RS0/HC0
Port
Description
Port 1
General I/O port
multiplexed with
address output and
address-data
multiplex I/O
Port 2
LED driving
capability
(sink current
12 mA)
P43/IRQ3/RS3/HC3/D7*
P42/IRQ2/RS2/HC2/D6*
P41/IRQ1/RS1/HC1/D5*
P40/IRQ0/RS0/HC0/D4*
Rev. 2.00 Aug. 20, 2008 Page 273 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
General I/O port
multiplexed with
interrupt input, bus
control output, system
clock output, external
subclock input, and
SSU I/O
P57
WR/HWR
P56/EXCL/φ
P55/IRQ13/SSI
P54/IRQ12/SSO
Same as left
General I/O port
multiplexed with
interrupt input, SCIF
and SCI_1 I/O
P53/IRQ11/RxD1
P52/IRQ10/TxD1
P51/IRQ9/RxDF
P50/IRQ8/TxDF
Same as left
General I/O port
multiplexed with
interrupt input, SCIF
control I/O, and SSU
control I/O
P67/ExIRQ8/SSCK
P66/ExIRQ9/SCS
P65/ExIRQ10/RTS
P64/ExIRQ11/CTS
Same as left
General I/O port
multiplexed with
interrupt input, PWMX
output, and
bidirectional data
bus* I/O
P63/PWX3
P62/PWX2
P61/IRQ15/PWX1
P60/IRQ14/PWX0
P63/PWX3/D3*
P62/PWX2/D2*
P61/IRQ15/PWX1/D1*
P60/IRQ14/PWX0/D0*
Port
Description
Port 5
Port 6
Port 7
General input port
P77/AN7
multiplexed with A/D P76/AN6
converter analog input P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Same as left
Port 8
General I/O port
multiplexed with
interrupt input, A/D
converter external
trigger input, and
SCI_1 and SCI_3 I/O
Same as left
P87/ExIRQ15/TxD3/ADTRG
P86/ExIRQ14/RxD3
P85/ExIRQ13/SCK1
P84/ExIRQ12/SCK3
General I/O port
P83/SDA1
multiplexed with IIC_0 P82/SCL1
and IIC_1 I/O
P81/SDA0
P80/SCL0
Rev. 2.00 Aug. 20, 2008 Page 274 of 1198
REJ09B0403-0200
Same as left
Feature of
I/O
Built-in input
pull-up MOS
NMOS
push-pull
output
Section 8 I/O Ports
Port
Description
Port 9
General I/O port
multiplexed with
PWMX output and
bus control I/O
Port A
Port B
Port C
General I/O port
multiplexed with
interrupt input, DTC
event counter input,
EtherC control I/O,
and address output
Single-Chip Mode
(EXPE = 0)
Extended Mode
(EXPE = 1)
P97
P97/WAIT/CS256
P96
Same as left
P95
AS/IOS
P94/ExPWX1
P93/ExPWX0
Same as left
P92
P91
P90
P92/HBE
P91/AH
P90/LBE
Feature of
I/O
PA7/ExIRQ7/EVENT7
PA7/ExIRQ7/EVENT7/A23
PA6/ExIRQ6/EVENT6/LNKSTA
PA6/ExIRQ6/EVENT6/LNKSTA/A22
PA5/ExIRQ5/EVENT5/WOL
PA5/ExIRQ5/EVENT5/WOL/A21
PA4/ExIRQ4/EVENT4
PA4/ExIRQ4/EVENT4/A20
PA3/ExIRQ3/EVENT3
PA3/ExIRQ3/EVENT3/A19
PA2/ExIRQ2/EVENT2
PA2/ExIRQ2/EVENT2/A18
PA1/ExIRQ1/EVENT1
PA1/ExIRQ1/EVENT1/A17
PA0/ExIRQ0/EVENT0
PA0/ExIRQ0/EVENT0/A16
General I/O port
multiplexed with DTC
event counter input
and EtherC control
I/O
PB7/EVENT15/RM_RX-ER
Same as left
PB6/EVENT14/RM_CRS-DV
PB5/EVENT13/RM_REF-CLK
PB4/EVENT12/RM_TX-EN
General I/O port
multiplexed with debounced input, DTC
event counter input,
and EtherC control
I/O
PB3/DB3/EVENT11/RM_RXD1
General I/O port
multiplexed with bus
control output
PC7
PC6
Built-in input
pull-up MOS
Same as left
PB2/DB2/EVENT10/RM_RXD0
PB1/DB1/EVENT9/RM_TXD1
PB0/DB0/EVENT8/RM_TXD0
PC5/SDA4
General I/O port
multiplexed with IIC_2 PC4/SCL4
PC3/SDA3
to IIC_4 I/O
PC2/SCL3
PC1/SDA2
PC0/SCL2
RD
PC6/LWR
Same as left
NMOS
push-pull
output
Rev. 2.00 Aug. 20, 2008 Page 275 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Extended Mode
(EXPE = 1)
Feature of
I/O
General I/O port
PD7/SDA5
multiplexed with IIC_5 PD6/SCL5
I/O
Same as left
NMOS
push-pull
output
PD5/LPCPD
General I/O port
multiplexed with LPC PD4/CLKRUN
PD3/GA20
I/O
PD2/PME
PD1/LSMI
PD0/LSCI
Same as left
Built-in input
pull-up MOS
Port E
General I/O port
PE7/SERIRQ
multiplexed with LPC PE6/LCLK
I/O
PE5/LRESET
PE4/LFRAME
PE3/LAD3
PE2/LAD2
PE1/LAD1
PE0/LAD0
Same as left
Port F
General I/O port
multiplexed with
PWMX output and
EtherC control I/O
Same as left
Port
Description
Port D
Note:
*
Single-Chip Mode
(EXPE = 0)
PF6/ExPWX2/RS14
PF1/RS9/MDC
PF0/RS8/MDIO
Available when configured for 16-bit data bus.
Rev. 2.00 Aug. 20, 2008 Page 276 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins can also function as the address bus and address-data
multiplex bus pins. The pin functions change according to the operating mode. Port 1 has the
following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 pull-up MOS control register (P1PCR)
(1)
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
•
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function as
address output pins; when cleared to 0, function
as input port pins.
•
Address-data multiplex extended mode (ADMXE =
1)
These bits correspond to the AD7 to AD0 pins of
the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as
input port pins.
Rev. 2.00 Aug. 20, 2008 Page 277 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
P1DR stores output data for the port 1 pins that are
used as the general output port.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
(3)
If this register is read, the P1DR values are read for
the bits with the corresponding P1DDR bits set to 1.
For the bits with the corresponding P1DDR bits
cleared to 0, the pin states are read.
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the port 1 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P17PCR
0
R/W
6
P16PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P1PCR bit is set to 1.
5
P15PCR
0
R/W
4
P14PCR
0
R/W
3
P13PCR
0
R/W
2
P12PCR
0
R/W
1
P11PCR
0
R/W
0
P10PCR
0
R/W
Rev. 2.00 Aug. 20, 2008 Page 278 of 1198
REJ09B0403-0200
Do not change the initial value when using the
address-data multiplex extended bus mode.
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Extended Mode (EXPE = 1)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR
0
1
ADMXE
0
ABW,
ABW256
X
Either bit is 0
(8/16-bit bus)
Both bits are
1 (8-bit bus)
X
Either bit is 0
(8/16-bit bus)
Both bits
are 1 (8-bit
bus)
P1n input
pin
ADn
input/output
pin
P1n input pin
An output
pin
Setting
prohibited
P1n output
pin
Pin function
1
0
1
[Legend] n = 7 to 0, X: Don't care.
(b)
Single-Chip Mode (EXPE = 0)
The pin function is switched as shown below according to the P1nDDR bit.
P1nDDR
Pin function
0
1
P1n input pin
P1n output pin
[Legend] n = 7 to 0
(5)
Port 1 Input Pull-Up MOS
Port 1 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used regardless of the operating mode. Table 8.10 summarizes the input pull-up MOS
states.
Table 8.10 Port 1 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 279 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins can also function as the SCIF modem control signal, address
bus, and address-data multiplex bus pins. The pin functions change according to the operating
mode. Port 2 has the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 pull-up MOS control register (P2PCR)
(1)
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as
input port pins.
5
P25DDR
0
W
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
•
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function
as address output pins; when cleared to 0,
function as input port pins.
The address output pins used are in accord
with the settings of the IOSE and CS256E bits
of SYSCR.
•
Address-data multiplex extended mode
(ADMXE = 1)
These bits correspond to the AD11 to AD8 pins
of the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function
as output port pins; when cleared to 0, function
as input port pins.
Rev. 2.00 Aug. 20, 2008 Page 280 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
P2DR stores output data for the port 2 pins that are
used as the general output port.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
(3)
If this register is read, the P2DR values are read
for the bits with the corresponding P2DDR bits set
to 1. For the bits with the corresponding P2DDR
bits cleared to 0, the pin states are read.
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P27PCR
0
R/W
6
P26PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P2PCR bit is set to 1.
5
P25PCR
0
R/W
4
P24PCR
0
R/W
3
P23PCR
0
R/W
2
P22PCR
0
R/W
1
P21PCR
0
R/W
0
P20PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P2PCR bit is set to 1.
Do not change the initial value when using the
address-data multiplex extended bus mode.
Rev. 2.00 Aug. 20, 2008 Page 281 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Extended Mode (EXPE = 1)
• P27 to P24
The pin function is the same as that in single-chip mode.
• P23
The pin function is switched as shown below according to the combination of the CS256E and
IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P23DDR bit. Address
11 in the table below is expressed by the following logical expression.
Address 11 = 1: ADFULLE • CS256E • IOSE
P23DDR
0
1
ADMXE
0
1
Address 11
X
X
Pin function
0
1
0
1
X
P23 input pin AD11 input/output A11 output pin P23 output pin AD11 input/output
pin
pin
• P22 to P20
P2nDDR
0
ADMXE
Pin function
[Legend]
1
0
1
0
1
P2n input pin
ADm input/output
pin
Am output pin
ADm input/output
pin
m = 10 to 8, n = 2 to 0, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 282 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(b)
Single-Chip Mode (EXPE = 0)
• P27/DTR
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 of the LPC, the SCIFOE1 and SCIFOE0 bits in SCIFCR of the SCIF, and the P27DDR
bit.
SCIFE
0
SCIFOE1,
SCIFOE0
Other than 10
P27DDR
Pin function
[Legend]
1
10
0
1
X
P27 input pin
P27 output
pin
X1
0
DTR output P27 input pin
pin
X0
1
X
P27 output
pin
DTR output
pin
X: Don't care.
• P26/DSR, P25/RI, P24/DCD
The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR
Pin function
0
1
P2n input pin
DSR/RI/DCD input pin
P2n output pin
[Legend] n = 6 to 4
• P23 to P20
The pin function is switched as shown below according to the P2nDDR bit.
P2nDDR
Pin function
0
1
P2n input pin
P2n output pin
[Legend] n = 3 to 0
Rev. 2.00 Aug. 20, 2008 Page 283 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Port 2 Input Pull-Up MOS
Port 2 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used regardless of the operating mode. Table 8.11 summarizes the input pull-up MOS
states.
Table 8.11
Port 2 Input Pull-Up MOS States
Reset
Hardware Standby Software Standby
Mode
Mode
In Other Operations
Off
Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 284 of 1198
REJ09B0403-0200
On/Off
Section 8 I/O Ports
8.2.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins can also function as the bidirectional data bus and debounced input pins. The pin functions change according to the operating mode. Port 3 has the
following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 pull-up MOS control register (P3PCR)
• Noise canceler enable register (P3NCE)
• Noise canceler mode control register (P3NCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the port 3 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P37DDR
0
W
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
•
Normal extended mode (ADMXE = 0)
The pins function as bidirectional data bus pins.
•
Other modes
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Rev. 2.00 Aug. 20, 2008 Page 285 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W Description
7
P37DR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
Since the port 3 pins function as bidirectional data
bus pins, the value of this register has no effect on
operation.
If this register is read, the P3DR values are read for
the bits with the corresponding P3DDR bits set to 1.
For the bits with the corresponding P3DDR bits
cleared to 0, 1 is read.
1
P31DR
0
0
P30DR
0
R/W •
R/W
Other modes
P3DR stores output data for the port 3 pins that are
used as the general output port.
If this register is read, the P3DR values are read for
the bits with the corresponding P3DDR bits set to 1.
For the bits with the corresponding P3DDR bits
cleared to 0, the pin states are read.
(3)
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W Description
7
P37PCR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36PCR
0
R/W
This register has no effect on operation.
5
P35PCR
0
R/W •
Other modes
4
P34PCR
0
R/W
3
P33PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P3PCR bit is set to 1.
2
P32PCR
0
R/W
1
P31PCR
0
R/W
0
P30PCR
0
R/W
Rev. 2.00 Aug. 20, 2008 Page 286 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit
Bit Name
Initial Value
R/W Description
7
P37NCE
0
R/W •
Normal extended mode (ADMXE = 0)
6
P36NCE
0
R/W
5
P35NCE
0
R/W
The pins function as bidirectional data bus pins. Set
this register to 0.
4
P34NCE
0
R/W
3
P33NCE
0
R/W
2
P32NCE
0
R/W
1
P31NCE
0
R/W
0
P30NCE
0
R/W
(5)
•
Other modes
Enables the noise canceler circuit for the
corresponding pin and the pin state is fetched into
P3DR at the sampling cycle set by NCCS.
The operation changes according to the other
control bits. See section 8.2.3 (7), Pin Functions, for
details.
Noise Canceler Mode Control Register (P3NCMC)
When the noise canceler is enabled, P3NCMC controls whether 1 or 0 is expected for the input
signal to port 3 in bit units.
Bit
Bit Name
Initial Value
R/W Description
7
P37NCMC
1
R/W •
Normal extended mode (ADMXE = 0)
6
P36NCMC
1
R/W
This register has no effect on operation.
5
P35NCMC
1
R/W •
Other modes
4
P34NCMC
1
R/W
3
P33NCMC
1
R/W
1 expected: 1 is stored in the port data register
while 1 is input stably.
2
P32NCMC
1
R/W
1
P31NCMC
1
R/W
0
P30NCMC
1
R/W
0 expected: 0 is stored in the port data register
while 0 is input stably.
Rev. 2.00 Aug. 20, 2008 Page 287 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name Initial Value R/W
Description
7 to 3 
Undefined
R/W
2
NCCK2
0
R/W These bits set the sampling cycle of the noise cancelers.
1
NCCK1
0
R/W •
When φ = 34 MHz
0
NCCK0
0
R/W
000: 0.06 µs
φ/2
100: 963.8 µs φ/32768
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
Reserved
Undefined value is read from these bits.
011: 240.9 µs φ/8192
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
∆t
Sampling clock
Figure 8.7 Noise Canceler Circuit
Rev. 2.00 Aug. 20, 2008 Page 288 of 1198
REJ09B0403-0200
Port data
register
Section 8 I/O Ports
P3n input
1 expected
P3nDR
0 expected
P3nDR
(n = 7 to 0)
Figure 8.8 Noise Canceler Operation
(7)
Pin Functions
(a)
Normal Extended Mode
Port 3 pins are automatically set to function as bidirectional data bus pins.
(b)
Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode.
(c)
Single-Chip Mode
The pin function is switched as shown below according to the P3nDDR bit and the P3nNCE bit.
P3nDDR
P3nNCE
Pin function
0
1
0
1
X
P3n input pin
DBn input
P3n output pin
[Legend] n = 7 to 0, X: Don't care
Rev. 2.00 Aug. 20, 2008 Page 289 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(8)
Port 3 Input Pull-Up MOS
Port 3 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used in single-chip mode and address-data multiplex extended mode. Table 8.12
summarizes the input pull-up MOS states.
Table 8.12 Port 3 Input Pull-Up MOS States
Mode
Reset
Hardware
Standby Mode
Software Standby In Other
Mode
Operations
Normal extended mode
(EXPE = 1, ADMXE = 0)
Off
Off
Off
Off
Single-chip mode (EXPE = 0) Off
Off
On/Off
On/Off
Address-data multiplex
extended mode (EXPE = 1,
ADMXE = 1)
[Legend]
Off:
Always off.
On/Off: On when input state and P3PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 290 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins can also function as the external interrupt input, de-bounced
input, bidirectional data bus, address bus, and address-data multiplex bus pins. Port 4 has the
following registers.
• Port 4 data direction register (P4DDR)
• Port 4 data register (P4DR)
• Port 4 pull-up MOS control register (P4PCR)
• Noise canceler enable register (P4BNCE)
• Noise canceler mode control register (P4BNCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the port 4 pins. P4DDR is initialized
only by a system reset, and retains the value even if an internal reset signal of the WDT is
generated.
Bit
Bit Name
Initial Value
R/W Description
7
P47DDR
0
W
6
P46DDR
0
W
5
P45DDR
0
W
4
P44DDR
0
W
•
Normal extended mode (ADMXE = 0)
When set to 1, the corresponding pins function as
address output pins; when cleared to 0, function as
input port pins.
The address output pins used are in accord with the
settings of the IOSE and CS256E bits of SYSCR.
•
Address-data multiplex extended mode (ADMXE =
1)
These bits correspond to the AD15 to AD12 pins of
the address-data multiplex bus.
•
Single-chip mode
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Rev. 2.00 Aug. 20, 2008 Page 291 of 1198
REJ09B0403-0200
Section 8 I/O Ports
Bit
Bit Name
Initial Value
R/W Description
3
P43DDR
0
W
2
P42DDR
0
W
1
P41DDR
0
W
0
P40DDR
0
W
(2)
•
Normal extended mode (16-bit bus)
These bits have no effect on operation.
•
Other modes
If port 4 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P4DDR bits are set to 1, and as input port
when cleared to 0.
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins. P4DR is initialized only by a system reset, and retains
the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
Initial Value
R/W Description
7
P47DR
0
6
P46DR
0
5
P45DR
0
4
P44DR
0
R/W These bits store output data for the port 4 pins that are
used as the general output port.
R/W
If this register is read, the P4DR values are read for the
R/W
bits with the corresponding P4DDR bits set to 1. For the
R/W bits with the corresponding P4DDR bits cleared to 0,
the pin states are read.
3
P43DR
0
R/W •
Normal extended mode (16-bit data bus)
2
P42DR
0
R/W
1
P41DR
0
R/W
0
P40DR
0
R/W
Since the corresponding pins function as
bidirectional data bus pins, the value in these bits
has no effect on operation.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, 1 is read.
•
Other modes
These bits store output data for the port 4 pins that
are used as the general output port.
If this register is read, the P4DR values are read for
the bits with the corresponding P4DDR bits set to 1.
For the bits with the corresponding P4DDR bits
cleared to 0, the pin states are read.
Rev. 2.00 Aug. 20, 2008 Page 292 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(3)
Port 4 Pull-Up MOS Control Register (P4PCR)
P4PCR controls the port 4 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W Description
7
P47PCR
0
R/W •
Normal extended mode (ADMXE = 0)
6
P46PCR
0
R/W
This register has no effect on operation.
5
P45PCR
0
R/W •
Other modes
4
P44PCR
0
R/W
3
P43PCR
0
R/W
When the pins are in the input state, the
corresponding input pull-up MOS is turned on when
a P4PCR bit is set to 1.
2
P42PCR
0
R/W
1
P41PCR
0
R/W
0
P40PCR
0
R/W
(4)
Noise Canceler Enable Register (P4BNCE)
The individual bits of P4BNCE enable or disable the noise canceler circuits for ports 4 and B.
Bit
Bit Name
Initial Value
R/W Description
7
P47NCE
0
6
P46NCE
0
5
P45NCE
0
4
P44NCE
0
R/W Enables the noise canceler circuit for the corresponding
pin and the pin state is fetched into P4DR at the
R/W
sampling cycle set by NCCS.
R/W
The operation changes according to the other control
R/W bits. See section 8.2.4 (7), Pin Functions, for details.
3 to 0 PB3NCE to All 0
PB0NCE
R/W Bits for port B setting
Rev. 2.00 Aug. 20, 2008 Page 293 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit
Bit Name
Initial Value
R/W Description
7
P47NCMC
1
R/W Expected value setting
6
P46NCMC
1
5
P45NCMC
1
4
P44NCMC
1
R/W 1 expected: 1 is stored in the port data register while 1
is input stably
R/W
0 expected: 0 is stored in the port data register while 0
R/W
is input stably
3 to 0 PB3NCMC
to
PB0NCMC
(6)
All 1
R/W Bits for port B setting
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name
7 to 3 
Initial Value
R/W Description
Undefined
R/W Reserved
Undefined value is read from these bits.
2
NCCK2
0
1
NCCK1
0
R/W These bits set the sampling cycle of the noise
R/W cancelers.
0
NCCK0
0
R/W •
When φ = 34 MHz
000: 0.06 µs
φ/2
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
011: 240.9 µs φ/8192
Rev. 2.00 Aug. 20, 2008 Page 294 of 1198
REJ09B0403-0200
100: 963.8 µs φ/32768
Section 8 I/O Ports
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
Port data
register
Sampling clock
Figure 8.9 Noise Canceler Circuit
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
Figure 8.10 Noise Canceler Operation
Rev. 2.00 Aug. 20, 2008 Page 295 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(7)
Pin Functions
The relationship between the register settings and the pin function is shown below.
(a)
Normal Extended Mode
• P47 to P44
The pin function is switched as shown below according to the combination of the CS256E and
IOSE bits in SYSCR, the ADFULLE bit in BCR2 of the BSC, and the P4nDDR bit. Address 13 in
the table below is expressed by the following logical expression.
Address 13 = 1: ADFULLE • CS256E • IOSE
P4nDDR
0
Address 13
X
0
1
P4n input pin
Am output pin
P4n output pin
Pin
function
1
[Legend] n = 15 to 12, n = 7 to 4, X: Don't care
• P43 to P40
Port pins 43 to 40 function as bidirectional data bus pins in 16-bit bus extension, and can be used
as general I/O port pins in 8-bit bus extension.
(b)
Address-Data Multiplex Extended Mode
Port pins 47 to 44 are automatically set to function as address bus pins. Port pins 43 to 40 can be
used as general I/O port pins.
Rev. 2.00 Aug. 20, 2008 Page 296 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(c)
Single-Chip Mode
The relationship between register setting values and pin functions are as follows.
• P47 to P40
The pin function is switched as shown below according to the P4nDDR bit and P4nNCE bit.
When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is
set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the
P4nDDR bit to 0.
P4nDDR
P4nNCE
Pin function
0
1
0
1
X
P4n input
DBn input
P4n output pin
IRQn input
IRQn input
(with the noise canceler)
[Legend] n = 7 to 4, X: Don't care
• P44 to P40
The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in
ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be
used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
P4nDDR
Pin function
0
1
P4n input pin
P4n output pin
IRQn input pin
[Legend] n = 3 to 0, X: Don't care
Rev. 2.00 Aug. 20, 2008 Page 297 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(8)
Port 4 Input Pull-Up MOS
Port 4 has built-in input pull-up MOSs that can be controlled by software. The input pull-up MOS
can be used in single-chip mode and address-data multiplex extended mode. Table 8.13
summarizes the input pull-up MOS states.
Table 8.13 Port 4 Input Pull-Up MOS States
Mode
Reset
Hardware
Standby Mode
Software Standby In Other
Mode
Operations
Normal extended mode
(EXPE = 1, ADMXE = 0)
Off
Off
Off
Off
Single-chip mode (EXPE = 0) Off
Off
On/Off
On/Off
Address-data multiplex
extended mode (EXPE = 1,
ADMXE = 1)
[Legend]
Off:
Always off.
On/Off: On when input state and P4PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 298 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.5
Port 5
Port 5 is an 8-bit I/O port. Port 5 pins can also function as the SCIF, SCI_1, and SSU input/output,
bus control output, system clock output, external subclock input, and interrupt input pins. Port 5
has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
(1)
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DDR
0
W
If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.
6
P56DDR
0
W
The corresponding port 5 pin functions as the system
clock output pin (φ) when this bit is set to 1, and as
the general I/O port when cleared to 0.
5
P55DDR
0
W
4
P54DDR
0
W
3
P53DDR
0
W
If port 5 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P5DDR bits are set to 1, and as input port
when cleared to 0.
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 299 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P57DR
0
R/W
6
P56DR
Undefined*
R
P5DR stores output data for the port 5 pins that are
used as the general output port.
5
P55DR
0
R/W
4
P54DR
0
R/W
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
Note:
*
If this register is read, the P5DR values are read for
the bits with the corresponding P5DDR bits set to 1.
For the bits with the corresponding P5DDR bits
cleared to 0, the pin states are read.
The initial value is determined in accordance with the pin state of P56.
(3)
Pin Functions
(a)
Normal Extended Mode and Address-Data Multiplex Extended Mode
Port pin 57 is automatically set to function as a bus control output pin. The functions of port pins
56 to 50 are the same as those in single-chip mode.
(b)
Single-Chip Mode
Port 5 pins can operate as the SCIF, SCI_1, and SSU input/output, noise canceler input, or general
I/O port pins. The relationship between register setting values and pin functions are as follows.
• P57
The pin function is switched as shown below according to the P57DDR bit.
P57DDR
Pin function
0
1
P57 input pin
P57 output pin
Rev. 2.00 Aug. 20, 2008 Page 300 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P56/EXCL/φ
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P56DDR bit.
P56DDR
0
EXCLE
Pin function
1
0
1
X
P56 input pin
EXCL input pin
φ output pin
[Legend] X: Don't care.
• P55/IRQ13/SSI
The pin function is switched as shown below according to the RE bit in SSER of the SSU and
the P55DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of
the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin. To use as the
IRQ13 input pin, clear the P55DDR bit to 0.
RE
0
P55DDR
Pin function
1
0
1
X
P55 input pin
P55 output pin
SSI input pin
IRQ13 input pin
[Legend] X: Don't care.
• P54/IRQ12/SSO
The pin function is switched as shown below according to the TE bit in SSER of the SSU and
the P54DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of
the interrupt controller is set to 1, this pin can be used as the IRQ12 input pin. To use as the
IRQ12 input pin, clear the P54DDR bit to 0.
TE
0
P54DDR
Pin function
1
0
1
X
P54 input pin
P54 output pin
SSO output pin
IRQ12 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 301 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P53/IRQ11/RxD1
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_1 and the P53DDR bit.
When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ11 input pin. To use as the IRQ11 input
pin, clear the P53DDR bit to 0.
RE
0
P53DDR
Pin function
1
0
1
X
P53 input pin
P53 output pin
RxD1 input pin
IRQ11 input pin
[Legend] X: Don't care.
• P52/IRQ10/TxD1
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_1 and the P52DDR bit.
When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ10 input pin. To use as the IRQ10 input
pin, clear the P52DDR bit to 0.
TE
0
P52DDR
Pin function
0
1
X
P52 input pin
P52 output pin
TxD1 output pin
IRQ10 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 302 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• P51/IRQ9/RxDF
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P51DDR bit.
When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ9 input pin. To use as the IRQ9 input pin,
clear the P51DDR bit to 0.
SCIF
Disabled
P51DDR
Pin function
Enabled
0
1
X
P51 input pin
P51 output pin
RxDF input pin
IRQ9 input pin
[Legend] X: Don't care.
• P50/IRQ8/TxDF
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P50DDR bit.
When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt
controller is set to 1, this pin can be used as the IRQ8 input pin. To use as the IRQ8 input pin,
clear the P50DDR bit to 0.
SCIF
Disabled
P50DDR
Pin function
Enabled
0
1
X
P50 input pin
P50 output pin
TxDF output pin
IRQ8 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 303 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins can also function as the bidirectional data bus, PWMX
output, SCIF and SSU control input/output, and interrupt input pins. The pin functions change
according to the operating mode. In addition, port 6 pins can also be used as the extended data bus
pins (D0 to D0). Port 6 has the following registers.
• Port 6 data direction register (P6DDR)
• Port 6 data register (P6DR)
• Port 6 pull-up MOS control register (P6PCR)
(1)
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DDR
0
W
6
P66DDR
0
W
5
P65DDR
0
W
If port 6 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P6DDR bits are set to 1, and as input ports
when cleared to 0.
4
P64DDR
0
W
3
P63DDR
0
W
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 304 of 1198
REJ09B0403-0200
•
Normal extended mode (16-bit bus)
These bits have no effect on operation.
•
Other modes
If port 6 pins are specified for use as the general
I/O port, the corresponding pins function as output
port when the P6DDR bits are set to 1, and as
input port when cleared to 0.
Section 8 I/O Ports
(2)
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P67DR
0
R/W
6
P66DR
0
R/W
These bits store output data for the port 6 pins that
are used as the general output port.
5
P65DR
0
R/W
4
P64DR
0
R/W
If this register is read, the P6DR values are read for
the bits with the corresponding P6DDR bits set to 1.
For the bits with the corresponding P6DDR bits
cleared to 0, the pin states are read.
3
P63DR
0
R/W
•
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
Normal extended mode (16-bit data bus)
Since the corresponding pins function as
bidirectional data bus pins, the value in these bits
has no effect on operation.
If this register is read, the P6DR values are read
for the bits with the corresponding P6DDR bits set
to 1. For the bits with the corresponding P6DDR
bits cleared to 0, 1 is read.
•
Other modes
These bits store output data for the port 6 pins
that are used as the general output port.
If this register is read, the P6DR values are read
for the bits with the corresponding P6DDR bits set
to 1. For the bits with the corresponding P6DDR
bits cleared to 0, the pin states are read.
Rev. 2.00 Aug. 20, 2008 Page 305 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(3)
Port 6 Pull-Up MOS Control Register (P6PCR)
P6PCR controls the port 6 built-in input pull-up MOSs.
Bit
Bit Name
Initial Value
R/W
Description
7
P67PCR
0
R/W
•
6
P66PCR
0
R/W
5
P65PCR
0
R/W
4
P64PCR
0
R/W
3
P23PCR
0
R/W
2
P62PCR
0
R/W
1
P61PCR
0
R/W
0
P60PCR
0
R/W
(4)
Pin Functions
(a)
Normal Extended Mode
Normal extended mode (16-bit bus)
This register has no effect on operation.
•
Other modes
When the pins are in the input state, the
corresponding input pull-up MOS is turned on
when a P6PCR bit is set to 1.
• 16-bit bus mode
Port pins 63 to 60 are automatically set to function as bidirectional data bus pins.
• 8-bit bus mode
The operation is the same as that in single-chip mode.
(b)
Address-Data Multiplex Extended Mode
The operation is the same as that in single-chip mode.
Rev. 2.00 Aug. 20, 2008 Page 306 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(c)
Single-Chip Mode
Port 6 pins can operate as the PWMX output, SCIF and SSU control input/output, interrupt input,
or general I/O port pins. The relationship between register setting values and pin functions are as
follows.
• P67/ExIRQ8/SSCK
The pin function is switched as shown below according to the SCKS bit in SSCRH of the SSU
and the P67DDR bit. When the ISS8 bit in ISSR16 is set to 1, this pin can be used as the
ExIRQ8 input pin. To use as the ExIRQ8 input pin, clear the P67DDR bit to 0.
SCKS
0
P67DDR
Pin function
1
0
1
X
P67 input pin
P67 output pin
SSCK I/O pin
ExIRQ8 input pin
[Legend] X: Don't care.
• P66/ExIRQ9/SCS
The pin function is switched as shown below according to the CSS1 and CSS0 bits in SSCRH
of the SSU and the P66DDR bit. When the ISS9 bit in ISSR16 is set to 1, this pin can be used
as the ExIRQ9 input pin. To use as the ExIRQ9 input pin, clear the P66DDR bit to 0.
CSS1, CSS0
00
P66DDR
Pin function
01 or 1X
0
1
X
P66 input pin
P66 output pin
SCS I/O pin
ExIRQ9 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 307 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P65/ExIRQ10/RTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P65DDR bit.
When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ10 input pin. To
use as the ExIRQ10 input pin, clear the P65DDR bit to 0.
SCIF
Disabled
P65DDR
Pin function
Enabled
0
1
X
P65 input pin
P65 output pin
RTS output pin
IRQ10 input pin
[Legend] X: Don't care.
• P64/ExIRQ11/CTS
The pin function is switched as shown below according to the combination of the
enable/disable setting of the SCIF and the P64DDR bit.
When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ11 input pin. To
use as the ExIRQ11 input pin, clear the P64DDR bit to 0.
SCIF
Disabled
P64DDR
Pin function
Enabled
0
1
X
P64 input pin
P64 output pin
CTS input pin
IRQ11 input pin
[Legend] X: Don't care.
• P63/PWX3
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P63DDR bit.
P63DDR
0
1
X
PWMXS
0
1
0
1
0
OEB
0
X
0
X
1
Pin function
P63 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 308 of 1198
REJ09B0403-0200
P63 output pin
PWX3 output pin
Section 8 I/O Ports
• P62/PWX2
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_1 and the P62DDR bit.
P62DDR
0
1
X
PWMXS
0
1
0
1
0
OEA
0
X
0
X
1
Pin function
P62 input pin
P62 output pin
PWX2 output pin
[Legend] X: Don't care.
• P61/IRQ15/PWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P61DDR bit. To use this pin as
the IRQ15 input pin, clear the P61DDR bit to 0.
P61DDR
0
1
X
PWMXS
0
1
0
1
OEB
0
X
0
X
Pin function
P61 input pin
P61 output pin
0
1
PWX1 output pin
IRQ15 input pin
[Legend] X: Don't care.
• P60/IRQ14/PWX1
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P60DDR bit. To use this pin as
the IRQ14 input pin, clear the P60DDR bit to 0.
P60DDR
0
1
X
PWMXS
0
1
0
1
0
OEA
0
X
0
X
1
Pin function
P60 input pin
P60 output pin
PWX0 output pin
IRQ14 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 309 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(5)
Port 6 Input Pull-Up MOS
Port 6 has built-in input pull-up MOSs that can be controlled by software. Table 8.14 summarizes
the input pull-up MOS states.
Table 8.14 Port 6 Input Pull-Up MOS States
Reset
Hardware Standby Mode
Software Standby Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when input state, P6DDR = 0, and P6PCR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 310 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins can also function as the A/D converter analog input pins.
Port 7 has the following register.
• Port 7 input data register (P7PIN)
(1)
Port 7 Input Data Register (P7PIN)
P7PIN indicates the states of the port 7 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P77PIN
Undefined*
R
When this register is read, the pin states are read.
6
P76PIN
Undefined*
R
5
P75PIN
Undefined*
R
Since this register is allocated to the same address as
PBDDR, writing to this register writes data to PBDDR
and the port B setting is changed.
4
P74PIN
Undefined*
R
3
P73PIN
Undefined*
R
2
P72PIN
Undefined*
R
1
P71PIN
Undefined*
R
0
P70PIN
Undefined*
R
Note:
*
The initial values are determined in accordance with the pin states of P77 to P70.
Rev. 2.00 Aug. 20, 2008 Page 311 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Pin Functions
Each pin of port 7 can also be used as the analog input pins of the A/D converter (AN0 to AN7).
• P77/AN7
The pin function is switched as shown below according to the CH2 to CH0 bits in ADCSR of
the A/D converter. Do not set these bits to other values than those shown in the following
table.
CH2 to CH0
B'111
Other than B'111
Pin function
AN7 input pin
P77 input pin
• P76/AN6
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'110
Other than B'110
B'110 to B'111
B'000 to B'101
Pin function
AN6 input pin
P76 input pin
AN6 input pin
P76 input pin
• P75/AN5
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'101
Other than B'101
B'101 to B'111
B'000 to B'100
Pin function
AN5 input pin
P75 input pin
AN5 input pin
P75 input pin
Rev. 2.00 Aug. 20, 2008 Page 312 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P74/AN4
The pin function is switched as shown below according to the combination of the SCANE bit
in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set these bits to
other values than those shown in the following table.
SCANE
0
1
CH2 to CH0
B'100
Other than B'100
B'100 to B'111
B'000 to B'011
Pin function
AN4 input pin
P74 input pin
AN4 input pin
P74 input pin
• P73/AN3
The pin function is switched as shown below according to the combination of the SCANE and
SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
1
0
1
CH2 to CH0
B'011
Other than
B'011
B'011
Other than
B'011
Pin function
AN3 input pin
P73 input pin
AN3 input pin
P73 input pin
B'011 to B'111 B'000 to B'010
AN3 input pin
P73 input pin
[Legend] X: Don't care.
• P72/AN2
The pin function is switched as shown below according to the combination of the SCANE and
SCANE bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
CH2 to CH0
Pin function
B'010
1
0
Other than
B'010
B'010 to B'011
AN2 input pin P72 input pin AN2 input pin
1
Other than B'010 to B'111
B'010 to B'011
P72 input pin
AN2 input pin
B'000 to
B'001
P72 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 313 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P71/AN1
The pin function is switched as shown below according to the combination of the SCANE and
SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
CH2 to CH0
Pin function
B'001
1
0
Other than
B'001
B'001 to
B'011
1
Other than
B'001 to
B'011
B'001 to
B'111
B'000
AN1 input pin P71 input pin AN1 input pin P71 input pin AN1 input pin P71 input pin
[Legend] X: Don't care.
• P70/AN0
The pin function is switched as shown below according to the combination of the SCANE and
SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A/D converter. Do not set
these bits to other values than those shown in the following table.
SCANE
0
SCANS
X
1
0
1
CH2 to CH0
B'000
Other than
B'000
B'000 to
B'011
Other than B'000 to
B'011
B'000 to B'111
Pin function
AN0 input pin
P70 input pin
AN0 input pin
P70 input pin
AN0 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 314 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.8
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins can also function as the A/D converter external trigger input,
SCI_1 and SCI_3 input/output, IIC_0 and IIC_1 input/output, and interrupt input pins. Pins 83 to
80 perform the NMOS push-pull output. Port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
(1)
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DDR
0
W
6
P86DDR
0
W
5
P85DDR
0
W
If port 8 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P8DDR bits are set to 1, and as input port
when cleared to 0.
4
P84DDR
0
W
3
P83DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
Since this register is allocated to the same address as
PBPIN, states of the port 8 pins are when this register
is read.
Rev. 2.00 Aug. 20, 2008 Page 315 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P87DR
0
R/W
6
P86DR
0
R/W
P8DR stores output data for the port 8 pins that are
used as the general output port.
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
(3)
If this register is read, the P8DR values are read for
the bits with the corresponding P8DDR bits set to 1.
For the bits with the corresponding P8DDR bits
cleared to 0, the pin states are read.
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P87/ExIRQ15/TxD3/ADTRG
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_3, the SMIF bit in SCMR, and the P87DDR bit.
When the TRGS1 and EXTRGS bits are both set to 1 and the TRGS0 bit is cleared to 0 in
ADCR of the A/D converter, this pin can be used as the ADTRG input pin.
When the ISS15 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ15 input pin. To
use this pin as the ExIRQ15 input pin, clear the P87DDR bit to 0.
P87DDR
0
1
SMIF
0
1
0
1
0
TE
0
X
0
X
1
Pin function
P87 input pin
ExIRQ15 input pin/
ADTRG input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 316 of 1198
REJ09B0403-0200
P87 output pin
TxD3 output pin
Section 8 I/O Ports
• P86/ExIRQ14/RxD3
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_3, the SMIF bit in SCMR, and the P86DDR bit.
When the ISS14 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ14 input pin. To
use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0.
P86DDR
0
SMIF
0
RE
Pin function
1
1
0
0
1
0
P86 input pin
RxD3 input pin RxD3 input/output pin
P86 output pin
ExIRQ14 input pin
• P85/ExIRQ13/SCK1
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit.
When the ISS13 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ13 input pin. To
use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0.
CKE1
0
C/A
0
CKE0
0
P85DDR
Pin function
1
1
X
1
X
X
0
1
X
X
X
P85 input pin
P85 output
pin
SCK1 output
pin
SCK1 output
pin
SCK1 input
pin
ExIRQ13 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 317 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P84/ExIRQ12/SCK3
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_3, the CKE1 and CKE0 bits in SCR, and the P84DDR bit.
When the ISS12 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ12 input pin. To
use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0.
CKE1
0
C/A
1
0
CKE0
0
P84DDR
Pin function
1
X
1
X
X
0
1
X
X
X
P84 input pin
P84 output
pin
SCK3 output
pin
SCK3 output
pin
SCK3 input
pin
ExIRQ12 input pin
[Legend] X: Don't care.
• P83/SDA1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P83DDR bit.
When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The
output format for SDA1 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P83DDR
Pin function
0
1
X
P83 input pin
P83 output pin
SDA1 input/output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 318 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• P82/SCL1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1 and the P82DDR bit.
When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The
output format for SCL1 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P82DDR
Pin function
1
0
1
X
P82 input pin
P82 output pin
SCL1 input/output pin
[Legend] X: Don't care.
• P81/SDA0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P81DDR bit.
When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The
output format for SDA0 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P81DDR
Pin function
1
0
1
X
P81 input pin
P81 output pin
SDA0 input/output pin
[Legend] X: Don't care.
• P80/SCL0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P80DDR bit.
When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The
output format for SCL0 is NMOS open-drain output, which allows direct bus drive.
ICE
0
P80DDR
Pin function
1
0
1
X
P80 input pin
P80 output pin
SCL0 input/output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 319 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins can function as the bus control input/output pins. The pin
functions change according to the operating mode. Port 9 has the following registers.
• Port 9 data direction register (P9DDR)
• Port 9 data register (P9DR)
(1)
Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the port 9 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DDR
0
W
6
P96DDR
0
W
5
P95DDR
0
W
If port 9 pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the P9DDR bits are set to 1, and as input port
when cleared to 0.
4
P94DDR
0
W
3
P93DDR
0
W
2
P92DDR
0
W
1
P91DDR
0
W
0
P90DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 320 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P97DR
0
R/W
6
P96DR
0
R/W
P9DR stores output data for the port 9 pins that are
used as the general output port.
5
P95DR
0
R/W
4
P94DR
0
R/W
3
P93DR
0
R/W
2
P92DR
0
R/W
1
P91DR
0
R/W
0
P90DR
0
R/W
(3)
If this register is read, the P9DR values are read for
the bits with the corresponding P9DDR bits set to 1.
For the bits with the corresponding P9DDR bits
cleared to 0, the pin states are read.
Pin Functions
The relationship between register setting values and pin functions are as follows.
• P97/WAIT/CS256
The pin function is switched as shown below according to the operating mode and the
combination of the CS256E bit in SYSCR, the WMS1 bit in WSCR and the P97DDR bit.
Operating
mode
Extended mode
WMS1
0
CS256E
P97DDR
Pin function
0
0
1
P97 input pin P97 output
pin
Single-chip mode
1
X
1
X
X
X
X
CS256 output
pin
0
1
WAIT input P97 input pin P97 output
pin
pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 321 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• P96
The pin function is switched as shown below according to the P96DDR bit.
P96DDR
Pin function
0
1
P96 input pin
P96 output pin
• P95/AS/IOS
The pin function is switched as shown below according to the operating mode and the
combination of the IOSE bit in SYSCR and the P95DDR bit.
Operating
mode
Extended mode
P95DDR
X
IOSE
Pin function
Single-chip mode
0
1
0
1
X
X
AS output pin
IOS output pin
P95 input pin
P95 output pin
[Legend] X: Don't care.
• P94/ExPWX1
The pin function is switched as shown below according to the combination of the OEB bit in
DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P94DDR bit.
P94DDR
0
1
X
PWMXS
0
1
0
1
1
OEB
X
0
X
0
1
Pin function
P94 input pin
P94 output pin
ExPWX1 output pin
[Legend] X: Don't care.
• P93/ExPWX0
The pin function is switched as shown below according to the combination of the OEA bit in
DACR and the PWMXS bit in PTCNT0 of the PWMX_0 module and the P93DDR bit.
P93DDR
0
PWMXS
0
OEA
X
Pin function
1
1
0
1
0
X
0
P93 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 322 of 1198
REJ09B0403-0200
X
P93 output pin
1
1
ExPWX0 output pin
Section 8 I/O Ports
• P92/HBE
The pin function is switched as shown below according to the operating mode, the OBE bit in
PTCNT0, and the P92DDR bit.
Operating
mode
Extended mode
OBE
P92DDR
Pin function
0
1
0
P92 input pin
Single-chip mode
1
X
X
P92 output pin HBE output pin
0
1
P92 input pin
P92 output pin
[Legend] X: Don't care.
• P91/AH
The pin function is switched as shown below according to the operating mode, the ADMXE
bit in SYSCR2, and the P91DDR bit.
Operating
mode
Extended mode
ADMXE
P91DDR
Pin function
0
Single-chip mode
1
X
0
1
X
0
1
P91 input pin
P91 output pin
AH output pin
P91 input pin
P91 output pin
[Legend] X: Don't care.
• P90/LBE
The pin function is switched as shown below according to the operating mode, the OBE bit in
PTCNT0, and the P90DDR bit.
Operating
mode
Extended mode
OBE
P90DDR
Pin function
0
0
P90 input pin
Single-chip mode
1
1
X
X
P90 output pin LBE output pin
0
1
P90 input pin
P90 output pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 323 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.10
Port A
Port A is an 8-bit I/O port. Port A pins can also function as the address output, event counter input,
interrupt input, and EtherC control input/output pins. Port A has the following registers. PADDR
and PAPIN are allocated to the same address.
• Port A data direction register (PADDR)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
(1)
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
6
PA6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 324 of 1198
REJ09B0403-0200
As the address of this register is the same as that of
PAPIN, reading from this register indicates the state
of port A.
Section 8 I/O Ports
(2)
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
PAODR stores output data for the port A pins that are
used as the general output port.
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
(3)
Port A Input Data Register (PAPIN)
PAPIN indicates the states of the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PIN
Undefined*
R
Pin states are read from this register.
6
PA6PIN
Undefined*
R
5
PA5PIN
Undefined*
R
As the address of this register is the same as that of
PADDR, writing to this register changes the settings
of port A, that have been written to PADDR.
4
PA4PIN
Undefined*
R
3
PA3PIN
Undefined*
R
2
PA2PIN
Undefined*
R
1
PA1PIN
Undefined*
R
0
PA0PIN
Undefined*
R
Note: *
The initial values are determined in accordance with the pin states of PA7 to PA0.
Rev. 2.00 Aug. 20, 2008 Page 325 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as
follows.
(a)
Normal Extended Mode
Port A pins can function as address output, interrupt input, event counter input, EtherC control
input/output, or I/O port pins, and input or output can be specified in bit units.
Address 18 and address 13 in the following tables are expressed by the following logical
expressions according to the control bits of the bus controller or other module.
Address 18 = 1: ADFULLE
Address 13 = 1: ADFULLE • CS256E • IOSE
• PA7/ExIRQ7/EVENT7/A23/EXOUT
The pin function is switched as shown below according to the setting of address 18 and the
PA7DDR bit.
Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin.
When using the pin as the ExIRQ7 input or an EVENT input pin, clear the PA7DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 when
using the pin as the PA7 or A23 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the EXOUT output pin.
PA7DDR
0
1
1
Address 18
X
1
0
Pin function
PA7 input pin
PA7 output pin
A23 output pin
ExIRQ7 input pin/EVENT7 input pin
[Legend] X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 326 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA6/ExIRQ6/EVENT6/A22/LNKSTA
The pin function is switched as shown below according to the setting of address 18 and the
PA6DDR bit.
Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin.
When using the pin as the ExIRQ6 input, or an EVENT input pin, clear the PA6DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 when
using the pin as the PA6 or A22 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the LNKSTA input pin.
PA6DDR
0
Address 18
Pin function
1
1
1
0
PA6 input pin
PA6 output pin
A22 output pin
ExIRQ6 input pin/EVENT6 input pin
• PA5/ExIRQ5/EVENT5/A21/WOL
The pin function is switched as shown below according to the setting of the MPDE bit in
ECMR in EtherC, the address 18, and the PA5DDR bit.
Setting the ISS5 bit in ISSR to 1 makes the pin function as the ExIRQ5 input pin.
When using the pin as the ExIRQ5 input, or an EVENT input pin, clear the PA5DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 when
using the pin as the A21 or PA5 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the WOL output pin.
MPDE
0
PA5DDR
0
1
1
Address 18
X
1
0
Pin function
PA5 input pin
PA5 output pin
A21 output pin
ExIRQ5 input pin/
EVENT5 input pin
Rev. 2.00 Aug. 20, 2008 Page 327 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18
The pin function is switched as shown below according to the setting of address 18 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when
using the pin as the PAn or Am output pin.
PAnDDR
0
1
1
Address 18
X
1
0
Pin function
PAn input pin
PAn output pin
Am output pin
ExIRQn input pin/EVENTn input pin
[Legend] n = 4 to 2, m = 20 to 18, X: Don't care.
• PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16
The pin function is switched as shown below according to the setting of address 13 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input, clear the PAnDDR bit to 0. When using the pin as an
EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin
have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR
0
Address 13
X
1
0
Pin function
PAn input pin
PAn output pin
Am output pin
ExIRQn input pin/EVENTn input pin
[Legend]
n = 1, 0; m = 17, 16, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 328 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
(b)
Single-Chip Mode and Address-Data Multiplex Extended Mode
Port A pins can also function as interrupt input, EtherC control input/output, and event counter
input pins.
• PA7/ExIRQ7/EVENT7/EXOUT
The pin function is switched as shown below according to the PA7DDR bit.
Setting the ISS7 bit in ISSR makes the pin to function as the ExIRQ7 input pin.
When using this pin as the ExIRQ7 input or EVENT7 input pin, clear the PA7DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA7DDR bit to 1 to use
the pin as the PA7 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the EXOUT output pin.
PA7DDR
Pin function
0
1
PA7 input pin
PA7 output pin
ExIRQ7 input pin/EVENT7 input pin
• PA6/ExIRQ6/EVENT6/LNKSTA
The pin function is switched as shown below according to the PA6DDR bit.
Setting the ISS6 bit in ISSR makes the pin to function as the ExIRQ6 input pin.
When using this pin as the ExIRQ6 input, or EVENT6 input pin, clear the PA6DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA6DDR bit to 1 to use
the pin as the PA6 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the LNKSTA input pin.
PA6DDR
Pin function
0
1
PA6 input pin
PA6 output pin
ExIRQ6 input pin/EVENT6 input pin
Rev. 2.00 Aug. 20, 2008 Page 329 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PA5/ExIRQ5/EVENT5/WOL
The pin function is switched as shown below according to the setting of the and the PA5DDR
bit.
Setting the ISS5 bit in ISSR makes the pin to function as the ExIRQ5 input pin.
When using this pin as the ExIRQ5 input, or EVENT5 input pin, clear the PA5DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 to use
the pin as the PA5 output pin.
When the module stop mode is cleared in both the EtherC and E-DMAC, this pin functions as
the WOL output pin.
PA5DDR
Pin function
0
1
PA5 input pin
PA5 output pin
ExIRQ5 input pin/EVENT5 input pin
• PA4/ExIRQ4/EVENT4, PA3/ExIRQ3/EVENT3, PA2/ExIRQ2/EVENT2,
PA1/ExIRQ1/EVENT1, PA0/ExIRQ0/EVENT0
The pin function is switched as shown below according to the PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using this pin as the ExIRQn input or EVENTn input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use
the pin as the PAn output pin.
PAnDDR
Pin function
0
1
PAn input pin
PAn output pin
ExIRQn input pin/EVENTn input pin
[Legend]
(5)
n = 4 to 0
Input Pull-Up MOS
Port A has built-in input pull-up MOSs that can be controlled by software. This input pull-up
MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
PAnDDR
0
PAnODR
PAn pull-up MOS
[Legend]
1
0
X
ON
OFF
OFF
n = 7 to 0, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 330 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.15 summarizes the input pull-up MOS states.
Table 8.15 Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 331 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.11
Port B
Port B is an 8-bit I/O port. Port B pins can also function as the event counter input, de-bounced
input, and EtherC control input/output pins. The pin functions change according to the operating
mode. Port B has the following registers.
• Port B data direction register (PBDDR)
• Port B output data register (PBODR)
• Port B input data register (PBPIN)
• Noise canceler enable register (P4BNCE)
• Noise canceler mode control register (P4BNCMC)
• Noise cancel cycle setting register (NCCS)
(1)
Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit
Bit Name
Initial Value
R/W Description
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 332 of 1198
REJ09B0403-0200
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
Section 8 I/O Ports
(2)
Port B Output Data Register (PBODR)
PBDR stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W Description
7
PB7DR
0
6
PB6DR
0
R/W PBODR stores output data for the port B pins that are
used as the general output port.
R/W
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
(3)
Port B Input Data Register (PBPIN)
PBPIN indicates the states of the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PB6PIN
Undefined*
R
5
PB5PIN
Undefined*
R
Since this register is allocated to the same address as
P8DDR, writing to this register writes data to P8DDR
and the port 8 setting is changed.
4
PB4PIN
Undefined*
R
3
PB3PIN
Undefined*
R
2
PB2PIN
Undefined*
R
1
PB1PIN
Undefined*
R
0
PB0PIN
Undefined*
R
Note:
*
The initial values are determined in accordance with the pin states of PB7 to PB0.
Rev. 2.00 Aug. 20, 2008 Page 333 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Noise Canceler Enable Register (P4BNCE)
P4BNCE enables or disables the noise canceler circuits of port 4 and port B pins in bit units.
Bit
Initial Value
R/W Description
7 to 4 P47NCE to
P44NCE
All 0
R/W Bits for port 4 setting
3
PB3NCE
0
2
PB2NCE
0
1
PB1NCE
0
0
PB0NCE
0
R/W Enables the noise canceler circuit for the corresponding
pin and the pin state is fetched into PBDR at the
R/W
sampling cycle set by NCCS.
R/W
The operation changes according to the other control
R/W bits. See section 8.2.11 (7), Pin Functions, for details.
(5)
Bit Name
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 and port B in bit
units.
Bit
Bit Name
Initial Value
R/W Description
7 to 4 P47NCMC
to
P44NCMC
All 1
R/W Bits for port 4 setting
3
PB3NCMC
1
R/W Expected value setting
2
PB2NCMC
1
1
PB1NCMC
1
0
PB0NCMC
1
R/W 1 expected: 1 is stored in the port data register while 1
is input stably.
R/W
0 expected: 0 is stored in the port data register while 0
R/W
is input stably.
Rev. 2.00 Aug. 20, 2008 Page 334 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name
Initial Value
R/W Description
7 to 3 
Undefined
R/W Reserved
2
NCCK2
0
1
NCCK1
0
R/W These bits set the sampling cycle of the noise
R/W cancelers.
0
NCCK0
0
R/W •
Undefined value is read from these bits.
When φ = 34 MHz
000: 0.06 µs
φ/2
100: 963.8 µs φ/32768
001: 0.94 µs
φ/32
101: 1.9 ms
φ/65536
010: 15.1 µs
φ/512
110: 3.9 ms
φ/131072
111: 7.7 ms
φ/262144
011: 240.9 µs φ/8192
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
∆t
Pin input
Latch
Latch
Latch
Match
detection
circuit
Port data
register
∆t
Sampling clock
Figure 8.11 Noise Canceler Circuit
Rev. 2.00 Aug. 20, 2008 Page 335 of 1198
REJ09B0403-0200
Section 8 I/O Ports
PBn input
1 expected
PBnDR
0 expected
PBnDR
(n = 3 to 0)
Figure 8.12 Noise Canceler Operation
(7)
Pin Functions
• PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK
PB4/EVENT12/RM_TX-EN
The pin function is switched as shown below according to the PBnDDR bit. When using this
pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O
pins when the EtherC is enabled.
EtherC,
E-DMAC
Either of them is stopped
PBnDDR
0
Both of them are
stopped
1
X
Event
counter
Disabled
Enabled
X
X
Pin
function
PBn input pin
EVENTm input
pin
PBn output pin
RM_xxxx
EtherC I/O pin
[Legend]
Note: *
n = 7 to 4, m = 15 to 8, X: Don't care.
See section 7.3, DTC Event Counter, for the event counter settings.
Rev. 2.00 Aug. 20, 2008 Page 336 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0,
PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and E-DMAC and the PBnDDR bit.
EtherC,
E-DMAC
Either of them is stopped
PBnDDR
0
Event
counter
Disabled
Enabled
Both of them are
stopped
1
X
X
X
PBnNCE
0
1
X
X
X
Pin
function
PBn
input
DBn
input
EVENTm input
PBn output pin
RM_xxxx
EtherC I/O pin
[Legend]
n = 3 to 0, m = 11 to 8, X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 337 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.12
Port C
Port C is an 8-bit I/O port. Port C pins can also function as the bus control output, and IIC_2,
IIC_3, and IIC_4 input/output pins. The output format of ports C0 to C5 is NMOS push-pull
output. Port C has the following registers.
• Port C data direction register (PCDDR)
• Port C output data register (PCODR)
• Port C input data register (PCPIN)
(1)
Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
6
PC6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 338 of 1198
REJ09B0403-0200
Since this register is allocated to the same address as
PCPIN, states of the port C pins are returned when
this register is read.
Section 8 I/O Ports
(2)
Port C Output Data Register (PCODR)
PCODR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
The PCODR register stores the output data for the
pins that are used as the general output port.
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
(3)
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states of port C.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PC6 PIN
Undefined*
R
5
PC5PIN
Undefined*
R
Since this register is allocated to the same address as
PCDDR, writing to this register writes data to PCDDR
and the port C setting is changed.
4
PC4 PIN
Undefined*
R
3
PC3 PIN
Undefined*
R
2
PC2 PIN
Undefined*
R
1
PC1 PIN
Undefined*
R
0
PC0 PIN
Undefined*
R
Note: The initial values are determined in accordance with the states of PC7 to PC0 pins.
Rev. 2.00 Aug. 20, 2008 Page 339 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
(a)
Normal Extended Mode and Address-Data Multiplex Extended Mode
Port C pins can also function as the bus control output and IIC_2, IIC_3, and IIC_4 input/output
pins. The relationship between register setting values and pin functions are as follows.
• PC7
The PC7 pin functions as a bus control output pin.
• PC6
When set for 16-bit bus width, the PC7 pin functions as a bus control output pin. When 8-bit
bus width, the pin function is the same as that in single-chip mode.
• PC5 to PC0
The pin functions are the same as those in single-chip mode.
Rev. 2.00 Aug. 20, 2008 Page 340 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(b)
Single-Chip Mode
• PC7, PC6
The pin function is switched as shown below according to the PCnDDR bit.
PCnDDR
Pin function
0
1
PCn input pin
PCn output pin
[Legend] n = 7, 6
• PC5/SDA4
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_4 and the PC5DDR bit.
ICE
0
PC5DDR
Pin function
1
0
1
X
PC5 input pin
PC5 output pin
SDA4 input/output pin
[Legend] X: Don't care.
• PC4/SCL4
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_4 and the PC4DDR bit.
ICE
0
PC4DDR
Pin function
[Legend]
1
0
1
X
PC4 input pin
PC4 output pin
SCL4 input/output pin
X: Don't care.
• PC3/SDA3
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_3 and the PC3DDR bit.
ICE
0
PC3DDR
Pin function
[Legend]
1
0
1
X
PC3 input pin
PC3 output pin
SDA3 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 341 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PC2/SCL3
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_3 and the PC2DDR bit.
ICE
0
PC2DDR
Pin function
[Legend]
1
0
1
X
PC2 input pin
PC2 output pin
SCL3 input/output pin
X: Don't care.
• PC1/SDA2
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_2 and the PC1DDR bit.
ICE
0
PC1DDR
Pin function
[Legend]
1
0
1
X
PC1 input pin
PC1 output pin
SDA2 input/output pin
X: Don't care.
• PC0/SCL2
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_2 and the PC0DDR bit.
ICE
0
PC0DDR
Pin function
[Legend]
0
1
X
PC0 input pin
PC0 output pin
SCL2 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 342 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
8.2.13
Port D
Port D is an 8-bit I/O port. Port D pins can also function as the IIC_5 input/output and LPC
input/output pins. The output format of PD7 and PD6 pins is NMOS push-pull output. Port D has
the following registers.
• Port D data direction register (PDDDR)
• Port D output data register (PDODR)
• Port D input data register (PDPIN)
(1)
Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
If port D pins are specified for use as the general I/O
port, the corresponding pins function as output port
when the PDDDR bits are set to 1, and as input port
when cleared to 0.
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Since this register is allocated to the same address as
PDPIN, the states of the port D pins are returned
when this register is read.
Rev. 2.00 Aug. 20, 2008 Page 343 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7ODR
0
R/W
6
PD6ODR
0
R/W
The PCODR register stores the output data for the
pins that are used as the general output port.
5
PD5ODR
0
R/W
4
PD4ODR
0
R/W
3
PD3ODR
0
R/W
2
PD2ODR
0
R/W
1
PD1ODR
0
R/W
0
PD0ODR
0
R/W
(3)
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PD6PIN
Undefined*
R
5
PD5PIN
Undefined*
R
Since this register is allocated to the same address as
PDDDR, writing to this register writes data to PDDDR
and the port D setting is changed.
4
PD4PIN
Undefined*
R
3
PD3PIN
Undefined*
R
2
PD2PIN
Undefined*
R
1
PD1PIN
Undefined*
R
0
PD0PIN
Undefined*
R
Note: The initial values are determined in accordance with the states of PD7 to PD0 pins.
Rev. 2.00 Aug. 20, 2008 Page 344 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
Port D pins can also function as the LPC input/output and IIC_5 input/output pins. The
relationship between register setting values and pin functions are as follows.
The LPC is disabled when all of the bits LPC1E, LPC2E, and LPC3E in HICR0 and SCIFE in
HICR5 are cleared to 0.
• PD7/SDA5
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_5 and the PD7DDR bit.
ICE
0
PD7DDR
Pin function
[Legend]
1
0
1
X
PD7 input pin
PD7 output pin
SDA5 input/output pin
X: Don't care.
• PD6/SCL5
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of the IIC_5 and the PD6DDR bit.
ICE
0
PD6DDR
Pin function
[Legend]
1
0
1
X
PD6 input pin
PD6 output pin
SCL5 input/output pin
X: Don't care.
• PD5/LPCPD
The pin function is switched as shown below according to the PD5DDR bit. This pin can be
used as the LPCPD input pin when the LPC is enabled.
LPC
PD5DDR
Pin function
Disabled
Enabled
0
1
0
PD5 input pin
PD5 output pin
LPCPD input pin
Rev. 2.00 Aug. 20, 2008 Page 345 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PD4/CLKRUN
The pin function is switched as shown below according to the PD4DDR bit. This pin can be
used as the CLKRUN input pin when the LPC is enabled.
LPC
PD4DDR
Pin function
Disabled
Enabled
0
1
0
PD4 input pin
PD4 output pin
CLKRUN input/output pin
• PD3/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
in HICR0 of the LPC and the PD3DDR bit.
FGA20E
PD3DDR
Pin function
0
1
0
1
0
PD3 input pin
PD3 output pin
GA20 output pin
• PD2/PME
The pin function is switched as shown below according to the combination of the PMEE bit in
HICR0 of the LPC and the PD2DDR bit.
PMEE
PD2DDR
Pin function
0
1
0
1
0
PD2 input pin
PD2 output pin
PME output pin
• PD1/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit in
HICR0 of the LPC and the PD1DDR bit.
LSMIE
PD1DDR
Pin function
0
0
1
0
PD1 input pin
PD1 output pin
LSMI output pin
Rev. 2.00 Aug. 20, 2008 Page 346 of 1198
REJ09B0403-0200
1
Section 8 I/O Ports
• PD0/LSCI
The pin function is switched as shown below according to the combination of the LSCIE bit in
HICR0 of the LPC and the PD0DDR bit.
LSCIE
0
PD0DDR
Pin function
(5)
1
0
1
0
PD0 input pin
PD0 output pin
LSCI output pin
Input Pull-Up MOS
Port pins D5 to D0 have built-in input pull-up MOSs that can be controlled by software. This input
pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit
basis.
PDnDDR
0
PDnODR
PDn pull-up MOS
[Legend]
1
1
0
X
ON
OFF
OFF
n = 5 to 0, X: Don't care.
The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior
state is retained in software standby mode.
Table 8.16 summarizes the input pull-up MOS states.
Table 8.16 Port D Input Pull-Up MOS States
Reset
Hardware Standby
Mode
Software Standby
Mode
In Other Operations
Off
Off
On/Off
On/Off
[Legend]
Off:
Always off.
On/Off: On when PDDDR = 0 and PDODR = 1; otherwise off.
Rev. 2.00 Aug. 20, 2008 Page 347 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.2.14
Port E
Port E is an 8-bit I/O port. Port E pins can also function as the LPC input/output pins. Port E has
the following registers.
• Port E data direction register (PEDDR)
• Port E output data register (PEODR)
• Port E input data register (PEPIN)
(1)
Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
6
PE6DDR
0
W
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Rev. 2.00 Aug. 20, 2008 Page 348 of 1198
REJ09B0403-0200
Since this register is allocated to the same address as
PEPIN, states of the port E pins are returned when
this register is read.
Section 8 I/O Ports
(2)
Port E Output Data Register (PEODR)
PEODR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7ODR
0
R/W
6
PE6ODR
0
R/W
The PEODR register stores the output data for the
pins that are used as the general output port.
5
PE5ODR
0
R/W
4
PE4ODR
0
R/W
3
PE3ODR
0
R/W
2
PE2ODR
0
R/W
1
PE1ODR
0
R/W
0
PE0ODR
0
R/W
(3)
Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7PIN
Undefined*
R
When this register is read, the pin states are read.
6
PE6PIN
Undefined*
R
5
PE5PIN
Undefined*
R
Since this register is allocated to the same address as
PEDDR, writing to this register writes data to PEDDR
and the port E setting is changed.
4
PE4PIN
Undefined*
R
3
PE3PIN
Undefined*
R
2
PE2PIN
Undefined*
R
1
PE1PIN
Undefined*
R
0
PE0PIN
Undefined*
R
Note: The initial value of these pins is determined in accordance with the state of pins PE7 to
PE0.
Rev. 2.00 Aug. 20, 2008 Page 349 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
Port E pins can also function as LPC input/output pins. The pin function is switched according to
whether the LPC module is enabled or disabled. The LPC is disabled when all of the bits LPC1E,
LPC2E, and LPC3E in HICR0 and SCIFE in HICR5 are cleared to 0.
• PE7/SERIRQ
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE7DDR bit.
LPC
Disabled
PE7DDR
Pin function
[Legend]
Enabled
0
1
X
PE7 input pin
PE7 output pin
SERIRQ input/output pin
X: Don't care.
• PE6/LCLK
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE6DDR bit.
LPC
Disabled
PE6DDR
Pin function
[Legend]
Enabled
0
1
X
PE6 input pin
PE6 output pin
LCLK input pin
X: Don't care.
• PE5/LRESET
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE5DDR bit.
LPC
Disabled
PE5DDR
Pin function
[Legend]
0
1
X
PE5 input pin
PE5 output pin
LRESET input pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 350 of 1198
REJ09B0403-0200
Enabled
Section 8 I/O Ports
• PE4/LFRAME
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE4DDR bit.
LPC
Disabled
PE4DDR
Pin function
[Legend]
Enabled
0
1
X
PE4 input pin
PE4 output pin
LFRAME input pin
X: Don't care.
• PE3/LAD3
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE3DDR bit.
LPC
Disabled
PE3DDR
Pin function
[Legend]
Enabled
0
1
X
PE3 input pin
PE3 output pin
LAD3 input/output pin
X: Don't care.
• PE2/LAD2
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE2DDR bit.
LPC
Disabled
PE2DDR
Pin function
[Legend]
Enabled
0
1
X
PE2 input pin
PE2 output pin
LAD2 input/output pin
X: Don't care.
• PE1/LAD1
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE1DDR bit.
LPC
Disabled
PE1DDR
Pin function
[Legend]
Enabled
0
1
X
PE1 input pin
PE1 output pin
LAD1 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 351 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• PE0/LAD0
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE0DDR bit.
LPC
Disabled
PE0DDR
Pin function
[Legend]
0
1
X
PE0 input pin
PE0 output pin
LAD0 input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 352 of 1198
REJ09B0403-0200
Enabled
Section 8 I/O Ports
8.2.15
Port F
Port F is a 3-bit I/O port. Port F pins can also function as the PWMX output and EtherC control
I/O pins. Port F has the following registers.
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
(1)
Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the port F pins. PFDDR is initialized
only by a system reset, and retains the value even if an internal reset signal of the WDT is
generated.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
6
PF6DDR
0
W
When set to 1, the corresponding pin functions as an
output port pin; when cleared to 0, functions as an
input port pin.
Since this register is allocated to the same address as
PFPIN, states of the port F pins are returned when
this register is read.
5 to 2 


Reserved
1
PF1DDR
0
W
0
PF0DDR
0
W
When set to 1, the corresponding pin functions as an
output port pin; when cleared to 0, functions as an
input port pin.
Since this register is allocated to the same address as
PFPIN, states of the port F pins are returned when
this register is read.
Rev. 2.00 Aug. 20, 2008 Page 353 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(2)
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins. PEODR is initialized only by a system reset, and
retains the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
Undefined value is read from this bit.
6
PF6ODR
5 to 2 
0
R/W
Stores the output data for the pin that is used as the
general output port.


Reserved
Undefined values are read from these bits.
1
PF1ODR
0
R/W
0
PF0ODR
0
R/W
(3)
Store the output data for the pins that are used as the
general output port.
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit
Bit Name
Initial Value
R/W
Description
7



Reserved
Undefined value is read from this bit.
6
PF6PIN
Undefined*
R
When this register is read, the pin states are read.
Since this register is allocated to the same address as
PFDDR, writing to this register writes data to PFDDR
and the port F setting is changed.
5 to 2 


1
PF1PIN
Undefined*
R
When this register is read, the pin states are read.
0
PF0PIN
Undefined*
R
Since this register is allocated to the same address as
PFDDR, writing to this register writes data to PFDDR
and the port F setting is changed.
Reserved
Undefined values are read from these bits.
Note: * The initial value of these pins is determined in accordance with the state of pins PF6,
PF1, and PF0.
Rev. 2.00 Aug. 20, 2008 Page 354 of 1198
REJ09B0403-0200
Section 8 I/O Ports
(4)
Pin Functions
Port F is a 3-bit I/O port. Port F pins can also function as PWMX output pins and EtherC control
I/O pins. The relationship between the register settings and the pin function is shown below.
• PF6/ExPWX2/RS14
The pin function is switched as shown below according to the combination of the OEA bit in
DACR, the PWMXS bit in PTCNT0 of PWMX_1, and the PF6DDR bit.
PF6DDR
0
1
X
PWMXS
0
1
0
1
1
OEA
X
0
X
0
1
Pin function
[Legend]
PF6 input pin
PF6 output pin
ExPWX2 output pin
X: Don't care.
• PF1/RS9/MDC
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and e-DMAC and the PF1DDR bit.
EtherC, E-DMAC
Either of them is stopped
PF1DDR
Pin function
[Legend]
Both of them are stopped
0
1
X
PF1 input pin
PF1 output pin
MDC output pin
X: Don't care.
• PF0/RS0/MDIO
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC and e-DMAC and the PF0DDR bit.
EtherC, E-DMAC
Either of them is stopped
PF0DDR
Pin function
[Legend]
Both of them are stopped
0
1
X
PF0 input pin
PF0 output pin
MDIO input/output pin
X: Don't care.
Rev. 2.00 Aug. 20, 2008 Page 355 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.3
Change of Peripheral Function Pins
The pin function assignments for the external interrupt inputs and 14-bit PWM timer outputs can
be changed between multiplexed I/O ports.
I/O port pins for external interrupt inputs are changed by the setting of ISSR16 and ISSR. I/O port
pins for 14-bit PWM timer outputs are changed by the setting of PTCNT0. A pin name of the
peripheral function after the assignment has been changed is indicated by adding ‘Ex’ at the head
of the original pin name. In each peripheral function description, the original pin name is used.
8.3.1
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
ISSR16 and ISSR select pins for the IRQ15 to IRQ0 inputs.
• ISSR16
Bit
Bit Name
Initial Value
R/W
Description
15
ISS15
0
R/W
0: P61/IRQ15 is selected
14
ISS14
0
R/W
1: P87/ExIRQ15 is selected
0: P60/IRQ14 is selected
1: P86/ExIRQ14 is selected
13
ISS13
0
R/W
0: P55/IRQ13 is selected
1: P85/ExIRQ13 is selected
12
ISS12
0
R/W
0: P54/IRQ12 is selected
1: P84/ExIRQ12 is selected
11
ISS11
0
R/W
0: P53/IRQ11 is selected
1: P64/ExIRQ11 is selected
10
ISS10
0
R/W
0: P52/IRQ10 is selected
1: P65/ExIRQ10 is selected
9
ISS9
0
R/W
0: P51/IRQ9 is selected
1: P66/ExIRQ9 is selected
8
ISS8
0
R/W
0: P50/IRQ8 is selected
1: P67/ExIRQ8 is selected
Rev. 2.00 Aug. 20, 2008 Page 356 of 1198
REJ09B0403-0200
Section 8 I/O Ports
• ISSR
Bit
Bit Name
Initial Value
R/W
Description
7
ISS7
0
R/W
0: P47/IRQ7 is selected
1: PA7/ExIRQ7 is selected
6
ISS6
0
R/W
0: P46/IRQ6 is selected
1: PA6/ExIRQ6 is selected
5
ISS5
0
R/W
0: P45/IRQ5 is selected
1: PA5/ExIRQ5 is selected
4
ISS4
0
R/W
0: P44/IRQ4 is selected
1: PA4/ExIRQ4 is selected
3
ISS3
0
R/W
0: P43/IRQ3 is selected
1: PA3/ExIRQ3 is selected
2
ISS2
0
R/W
0: P42/IRQ2 is selected
1: PA2/ExIRQ2 is selected
1
ISS1
0
R/W
0
ISS0
0
R/W
0: P41/IRQ1 is selected
1: PA1/ExIRQ1 is selected
0: P40/IRQ0 is selected
1: PA0/ExIRQ0 is selected
Rev. 2.00 Aug. 20, 2008 Page 357 of 1198
REJ09B0403-0200
Section 8 I/O Ports
8.3.2
Port Control Register 0 (PTCNT0)
PTCNT0 selects pins for 14-bit PWM timer outputs and the control mode for external extension.
Bit
Bit Name
Initial Value
7
SCPFSEL1 0
R/W
Description
R/W
Controls the internal connection of TxD1 and RxD1
with the SCI_1 as the smart card interface.
0: TxD1 and RxD1 are not internally connected.
1: TxD1 and RxD1 are internally connected.
6
SCPFSEL3 0
R/W
Controls the internal connection of TxD3 and RxD3
with the SCI_3 as the smart card interface.
0: TxD3 and RxD3 are not internally connected.
1: TxD3 and RxD3 are internally connected.
5, 4

All 0
R/W
Reserved
The initial value should not be changed.
3
PWMXS
0
R/W
Selects pins for 14-bit PWM timer outputs.
0: P60/PWX0, P61/PWX1, P62/PWX2, P63/PWX3
are selected
1: P93/ExPWX0, P94/ExPWX1, PF6/ExPWX2,
PF3/ExPWX3* are selected
2

0
R/W
Reserved
The initial value should not be changed.
1
OBE
0
R/W
Selects glueless extension.
0: Control by RD, HWR, LWR
1: Control by RD, WR, HBE, LBE
(glueless extension)
0

0
R/W
Reserved
The initial value should not be changed.
Note: * The PF3/EXPWX3 pin is available only in the H8S/2472 Group.
Rev. 2.00 Aug. 20, 2008 Page 358 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
Section 9 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with four output channels. It
can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
9.1
Features
• Division of pulse into multiple base cycles to reduce ripple
• Eight resolution settings
The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
• Two base cycle settings
The base cycle can be set equal to T × 64 or T × 256, where T is the resolution.
• Sixteen operation clocks (by combination of eight resolution settings and two base cycle
settings)
Figure 9.1 shows a block diagram of the PWM (D/A) module.
Internal clock
Select clock
φ
φ/2, φ/64, φ/128, φ/256,
φ/1024, φ/4096, φ/16384
Clock
Internal data bus
Bus interface
Base cycle compare match A
PWX0
Fine–adjustment pulse addition A
PWX1
Base cycle compare match B
Fine–adjustment pulse addition B
Comparator A
DADRA
Comparator B
DADRB
Control
logic
Base cycle overflow
DACNT
DACR
[Legend]
DACR:
DADRA:
DADRB:
DACNT:
Module data bus
PWMX D/A control register (6 bits)
PWMX D/A data register A (15 bits)
PWMX D/A data register B (15 bits)
PWMX D/A counter (14 bits)
Figure 9.1 PWMX (D/A) Block Diagram
Rev. 2.00 Aug. 20, 2008 Page 359 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.2
Input/Output Pins
Table 9.1 lists the PWMX (D/A) module input and output pins.
Table 9.1
Pin Configuration
Name
Abbreviation I/O
Function
PWMX output pin 0
PWX0
Output
PWM timer pulse output of PWMX_0 channel A
PWMX output pin 1
PWX1
Output
PWM timer pulse output of PWMX_0 channel B
PWMX output pin 2
PWX2
Output
PWM timer pulse output of PWMX_1 channel A
PWMX output pin 3
PWX3
Output
PWM timer pulse output of PWMX_1 channel B
9.3
Register Descriptions
The PWMX (D/A) module has the following registers. For details on the module stop control
register, see section 28.1.3, Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL,
MSTPCRA).
• PWMX (D/A) counter (DACNT)
• PWMX (D/A) data register A (DADRA)
• PWMX (D/A) data register B (DADRB)
• PWMX (D/A) control register (DACR)
• Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.
Rev. 2.00 Aug. 20, 2008 Page 360 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.3.1
PWMX (D/A) Counter (DACNT)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select
bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed
in 8-bit units. DACNT should always be accessed in 16-bit units. For details, see section 9.4, Bus
Master Interface.
• DACNT
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8 UC7 to UC0
All 0
R/W
Lower Up-Counter
7 to 2
UC8 to UC13
All 0
R/W
Upper Up-Counter
1

1
R
Reserved
This bit is always read as 1 and cannot be modified.
0
REGS
1
R/W
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 2.00 Aug. 20, 2008 Page 361 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The
DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed
in 16-bit units. For details, see section 9.4, Bus Master Interface.
• DADRA
Bit
Bit Name
Initial
Value
15 to 2 DA13 to DA0 All 1
R/W
Description
R/W
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must be
set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by fixing
DA0 and DA1 to 0. The two data bits are not compared
with UC12 and UC13 of DACNT.
1
CFS
1
R/W
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
The range of DA13 to DA0: H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
The range of DA13 to DA0: H'0040 to H'3FFF
0

1
R
Reserved
This bit is always read as 1 and cannot be modified.
Rev. 2.00 Aug. 20, 2008 Page 362 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
• DADRB
Bit
Bit Name
Initial
Value
15 to 2 DA13 to DA0 All 1
R/W
Description
R/W
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with UC12 and UC13 of DACNT.
1
CFS
1
R/W
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
DA13 to DA0 range = H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
DA13 to DA0 range = H'0040 to H'3FFF
0
REGS
1
R/W
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed. When changing the
register to be accessed, set this bit in advance.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
Rev. 2.00 Aug. 20, 2008 Page 363 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.3.3
PWMX (D/A) Control Register (DACR)
DACR enables the PWM outputs, and selects the output phase and operating speed.
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R/W
Reserved
6
PWME
0
R/W
The initial value should not be changed.
PWMX Enable
Starts or stops the PWM D/A counter (DACNT).
0: DACNT operates as a 14-bit up-counter
1: DACNT halts at H'0003
5, 4

All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
3
OEB
0
R/W
Output Enable B
Enables or disables output on PWMX (D/A) channel B.
0: PWMX (D/A) channel B output (at the PWX1, PWX3
pins) is disabled
1: PWMX (D/A) channel B output (at the PWX1, PWX3
pins) is enabled
2
OEA
0
R/W
Output Enable A
Enables or disables output on PWMX (D/A) channel A.
0: PWMX (D/A) channel A output (at the PWX0, PWX2
pin) is disabled
1: PWMX (D/A) channel A output (at the PWX0, PWX2
pins) is enabled
1
OS
0
R/W
Output Select
Selects the phase of the PWMX (D/A) output.
0: Direct PWMX (D/A) output
1: Inverted PWMX (D/A) output
0
CKS
0
R/W
Clock Select
Selects the PWMX (D/A) resolution. Eight kinds of
resolution can be selected.
0: Operates at resolution (T) = system clock cycle time
(tcyc)
1: Operates at resolution (T) = system clock cycle time
(tcyc) × 2, × 64, × 128, × 256, × 1024, × 4096, and ×
16384.
Rev. 2.00 Aug. 20, 2008 Page 364 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.3.4
Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit
Bit Name
Initial
Value
R/W
Description
7
PWCKX1B
0
R/W
PWMX_1 Clock Select
6
PWCKX1A
0
R/W
These bits select a clock cycle with the CKS bit of DACR
of PWMX_1 being 1.
See table 9.2.
5
PWCKX0B
0
R/W
PWMX_0 Clock Select
4
PWCKX0A
0
R/W
These bits select a clock cycle with the CKS bit of DACR
of PWMX_0 being 1.
See table 9.2.
3
PWCKX1C
0
R/W
PWMX_1 Clock Select
This bit selects a clock cycle with the CKS bit of DACR of
PWMX_1 being 1.
See table 9.2.
2

0
R/W
Reserved
1

0
R/W
The initial value should not be changed.
0
PWCKX0C
0
R/W
PWMX_0 Clock Select
This bit selects a clock cycle with the CKS bit of DACR of
PWMX_0 being 1.
See table 9.2.
Table 9.2
Clock Select of PWMX_1 and PWMX_0
PWCKX0C
PWCKX1C
PWCKX0B
PWCKX1B
PWCKX0A
PWCKX1A
Resolution (T)
0
0
0
Operates on the system clock cycle (tcyc) x 2
0
0
1
Operates on the system clock cycle (tcyc) x 64
0
1
0
Operates on the system clock cycle (tcyc) x 128
0
1
1
Operates on the system clock cycle (tcyc) x 256
1
0
0
Operates on the system clock cycle (tcyc) x 1024
1
0
1
Operates on the system clock cycle (tcyc) x 4096
1
1
0
Operates on the system clock cycle (tcyc) x 16384
1
1
1
Setting prohibited
Rev. 2.00 Aug. 20, 2008 Page 365 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.4
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written to and read from as follows.
• Write
When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written to, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read from, the upper-byte value is transferred to the CPU and the
lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper
byte should always be accessed before the lower byte. Correct data will not be transferred if only
the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction
cannot be used to access these registers.
Example 1: Write to DACNT
MOV.W R0, @DACNT
; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
; Copy contents of DADRA to R0
Rev. 2.00 Aug. 20, 2008 Page 366 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
9.5
Operation
A PWM waveform like the one shown in figure 9.2 is output from the PWX pin. DA13 to DA0 in
DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle
(256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly
output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value
corresponds to the total width (TH) of the high (1) output pulses. Figures 9.3 and 9.4 show the
types of waveform output available.
1 conversion cycle
(T × 214 (= 16384))
tf
Base cycle
(T × 64 or T × 256)
tL
T: Resolution
m
TL = Σ tLn (OS = 0)
n=1
(When CFS = 0, m = 256
When CFS = 1, m = 64)
Figure 9.2 PWMX (D/A) Operation
Table 9.3 summarizes the relationships between the CKS and CFS bit settings and the resolution,
base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR
contain at least a certain minimum value. The relationship between the OS bit and the output
waveform is shown in figures 9.3 and 9.4.
Rev. 2.00 Aug. 20, 2008 Page 367 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
Settings and Operation (Examples when φ = 34 MHz)
Table 9.3
PCSR
Fixed DADR Bits
ResoConver-
A
CKS (µs)
 

0
0.03
CFS Cycle
0
(φ)
1.88 µs
Bit Data
sion
TL/TH
Precision
Cycle
(OS = 0/OS = 1)
(Bits)
481.88 µs Always low/high output
DA13 to 0 = H'0000 to H'00FF
531.3 kHz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
7.53 µs
481.88 µs Always low/high output
DA13 to 0 = H'0000 to H'003F
132.8 kHz
0
0
0
1
0.06
0
(φ/2)
3.76 µs
(Data value) × T
0.964 ms
265.6 kHz
1
15.06 µs
66.4 kHz
14
10
Always low/high output
14
DA13 to 0 = H'0040 to H'3FFF
0
0
1
1
1.88
0
(φ/64)
120.5 µs
30.840 ms Always low/high output
DA13 to 0 = H'0000 to H'00FF
8.3 kHz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
481.9 µs
30.840 ms Always low/high output
DA13 to 0 = H'0000 to H'003F
2.1 kHz
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
0
1
0
1
3.76
0
(φ/128)
240.9 µs
61.681 ms Always low/high output
DA13 to 0 = H'0000 to H'00FF
4.2 kHz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
963.8 µs
61.681 ms Always low/high output
1.0 kHz
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
Rev. 2.00 Aug. 20, 2008 Page 368 of 1198
REJ09B0403-0200
0
120.47 µs
0
0
30.12 µs
481.88 µs
0
0
0
0
0
120.47 µs
0
0
30.12 µs
0
0
0.241 ms
0
0
0.060 ms
0.964 ms
12
10
0
0.964 ms
12
DA13 to 0 = H'0100 to H'3FFF
(Data value) × T
0
12
Always low/high output
DA13 to 0 = H'0000 to H'003F
0
0
14
10
(Data value) × T
0.964 ms
12
10
0
0
0
0
0.241 ms
0
0
0.060 ms
14
30.840 ms
12
10
0
0
0
0
7.710 ms
0
0
1.928 ms
14
30.840 ms
12
10
0
0
0
0
7.710 ms
0
0
1.928 ms
0
0
15.420 ms
0
0
3.855 ms
14
61.681 ms
12
10
0
0
14
61.681 ms
12
10
Cycle*
481.88 µs
14
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
Conversion
DA0
B
C
Base
DA1
T
DA2
lution
PWCKX1
DA3
PWCKX0
0
0
0
0
15.420 ms
0
0
3.855 ms
Section 9 14-Bit PWM Timer (PWMX)
PCSR
Fixed DADR Bits
ResoConver-
B
A
CKS (µs)
0
1
1
1
7.53
CFS Cycle
0
(φ/256)
481.9 µs
sion
Cycle
Bit Data
TL/TH
Precision
(OS = 0/OS = 1)
(Bits)
123.36 ms Always low/high output
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
1927.5 µs 123.36 ms Always low/high output
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
1
0
0
1
30.12
0
(φ/1024)
1.93 ms
493.45 ms Always low/high output
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
7.71 ms
493.45 ms Always low/high output
1
0
1
1
120.47
0
(φ/4096)
7.71 ms
(Data value) × T
1.974 s
1
1
1
0
1
481.88
0
(φ/16384)
1
123.36
10
Always low/high output
14
7.895 s
0
0
7.71 ms
0
0
30.84 ms
0
0
7.71 ms
493.45 ms
0
0
0
0
123.36 ms
0
0
30.84 ms
493.45 ms
0
0
10
Always low/high output
14
0
0
10
Always low/high output
14
0
123.36 ms
0
0
30.84 ms
0
0
0.493 s
0
0
0.123 s
1.974 s
0
0
0
0
0.493 s
0
0
0.123 s
7.895 s
12
DA13 to 0 = H'0100 to H'3FFF
0
1.974 s
12
DA13 to 0 = H'0040 to H'3FFF
(Data value) × T
ms
0
12
DA13 to 0 = H'0100 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
32.4 Hz
0
123.36 ms
12
14
(Data value) × T
30.84 ms 7.895 s
10
Always low/high output
DA13 to 0 = H'0000 to H'003F
32.4 Hz
0
12
10
(Data value) × T
30.84 ms 1.974 s
0
12
10
DA13 to 0 = H'0040 to H'3FFF
DA13 to 0 = H'0000 to H'00FF
129.7 Hz
10
14
DA13 to 0 = H'0000 to H'003F
129.7 Hz
30.84 ms
14
DA13 to 0 = H'0000 to H'00FF
518.8 Hz
0
Cycle*
123.36 ms
12
14
DA13 to 0 = H'0000 to H'003F
0.5 kHz
0
14
DA13 to 0 = H'0000 to H'00FF
2.1 kHz
Conversion
DA0
C
Base
DA1
T
DA2
lution
PWCKX1
DA3
PWCKX0
0
0
0
0
1.974 s
0
0
0.493 s
7.895 s
DA13 to 0 = H'0000 to H'003F
(Data value) × T
8.1 Hz
12
0
0
1.974 s
0.493 s
DA13 to 0 = H'0040 to H'3FFF
1
1
1
1
Setting




10
0
0
0
0




 
prohibited
Note:
*
Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.
Rev. 2.00 Aug. 20, 2008 Page 369 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
1 conversion cycle
tf1
tL1
tf2
tf255
tL2
tL3
tL255
tf256
tL256
tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64
tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tL1
tf2
tL2
tf63
tL3
tL63
tf64
tL64
tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256
tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to TL)
Rev. 2.00 Aug. 20, 2008 Page 370 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
1 conversion cycle
tf1
tH1
tf2
tf255
tH2
tH3
tf256
tH255
tH256
tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64
tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tH1
tf2
tf63
tH2
tH3
tf64
tH63
tH64
tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256
tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to TH)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.5.
Table 9.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
DA8
Duty cycle of base pulse
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Location of additional pulses
CFS
1
1
Figure 9.5 D/A Data Register Configuration when CFS = 1
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 9.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Rev. 2.00 Aug. 20, 2008 Page 371 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 9.4. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
1 conversion cycle
Base cycle
No. 0
Base cycle
Base cycle
No. 1
No. 63
Base pulse
High width: 2/256 × (T)
Additional pulse output location
Base pulse
2/256 × (T)
Additional pulse
1/256 × (T)
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1)
However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is
determined by the upper six bits and the locations of the additional pulses by the subsequent eight
bits with a method similar to as above.
Rev. 2.00 Aug. 20, 2008 Page 372 of 1198
REJ09B0403-0200
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Lower 6 bits
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0
Base pulse No.
1 2 3 4 5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Section 9 14-Bit PWM Timer (PWMX)
Table 9.4
Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
Rev. 2.00 Aug. 20, 2008 Page 373 of 1198
REJ09B0403-0200
Section 9 14-Bit PWM Timer (PWMX)
Rev. 2.00 Aug. 20, 2008 Page 374 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
Section 10 16-Bit Free-Running Timer (FRT)
This LSI has a 16-bit free-running timer (FRT).
10.1
Features
• Selection of four clock sources
 One of the three internal clocks (φ/2, φ/8, or φ/32) can be selected.
• Two independent comparators
• Counter clearing
 The free-running counters can be cleared on compare-match A.
• Three independent interrupts
 Two compare-match interrupts and one overflow interrupt can be requested independently.
• Special functions provided by automatic addition function
 The contents of OCRAR and OCRAF can be added to the contents of OCRA
automatically, enabling a periodic waveform to be generated without software intervention.
Rev. 2.00 Aug. 20, 2008 Page 375 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 is a block diagram of the FRT.
Internal clock
OCRAR/F
φ/2
φ/8
φ/32
Clock
OCRA
Comparator A
Overflow
FRC
Clear
Compare-match B
Control logic
Comparator B
Bus interface
Compare-match A
Module data bus
Clock selector
Internal data bus
OCRB
TCSR
TIER
TCR
TOCR
OCIA
OCIB
FOVI
Interrupt signal
[Legend]
OCRA, OCRB:
OCRAR,OCRAF:
FRC:
TCSR:
TIER:
TCR:
TOCR:
Output compare registers A and B (16 bits)
Output compare registers AR and AF (16 bits)
Free-running counter (16 bits)
Timer control/status register (8 bits)
Timer interrupt enable register (8 bits)
Timer control register (8 bits)
Timer output compare control register (8 bits)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer
Rev. 2.00 Aug. 20, 2008 Page 376 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2
Register Descriptions
The FRT has the following registers.
• Free-running counter (FRC)
• Output compare register A (OCRA)
• Output compare register B (OCRB)
• Output compare register AR (OCRAR)
• Output compare register AF (OCRAF)
• Timer interrupt enable register (TIER)
• Timer control/status register (TCSR)
• Timer control register (TCR)
• Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS
bit in TOCR.
10.2.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit
units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.
10.2.2
Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is
set to 1 in TCSR. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit
units. OCR is initialized to H'FFFF.
Rev. 2.00 Aug. 20, 2008 Page 377 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2.3
Output Compare Registers AR and AF (OCRAR and OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. They are accessed when the ICRS bit
in TOCR is set to 1. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is
changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are
automatically added alternately to OCRA, and the result is written to OCRA. The write operation
is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the
OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to
whether the compare-match follows addition of OCRAR or OCRAF.
When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC
input clock together with a set value of H'0001 or less for OCRAR (or OCRAF).
OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units.
OCRAR and OCRAF are initialized to H'FFFF.
Rev. 2.00 Aug. 20, 2008 Page 378 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2.4
Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit
Bit Name
Initial
Value
R/W
7 to 4

All 0
R
Description
Reserved
These bits are always read as 0 and cannot be modified.
3
OCIAE
0
R/W
Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled
2
OCIBE
0
R/W
Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
1
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
0

0
R
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 2.00 Aug. 20, 2008 Page 379 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2.5
Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit
Bit Name
Initial
Value
R/W
7 to 4

All 0
R
Description
Reserved
These bits are always read as 0 and cannot be modified.
3
OCFA
0
R/(W)* Output Compare Flag A
Indicates that the FRC value matches the OCRA value.
[Setting condition]
When FRC = OCRA
[Clearing condition]
Read OCFA when OCFA = 1, then write 0 to OCFA
2
OCFB
0
R/(W)* Output Compare Flag B
Indicates that the FRC value matches the OCRB value.
[Setting condition]
When FRC = OCRB
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 to OCFB
1
OVF
0
R/(W)* Overflow Flag
Indicates that the FRC has overflowed.
[Setting condition]
When FRC overflows (changes from H'FFFF to H'0000)
[Clearing condition]
Read OVF when OVF = 1, then write 0 to OVF
0
CCLRA
0
R/W
Counter Clear A
Selects whether the FRC is to be cleared on comparematch A (when the FRC and OCRA values match).
0: FRC clearing is disabled
1: FRC is cleared on compare-match A
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 380 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2.6
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2

All 0
R
Reserved
1
CKS1
0
R/W
Clock Select 1 and 0
0
CKS0
0
R/W
Select clock source for FRC.
These bits are always read as 0 and cannot be modified.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: Reserved
Rev. 2.00 Aug. 20, 2008 Page 381 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.2.7
Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access
between output compare registers A and B, and controls the OCRA operating modes.
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R
Reserved
6
OCRAMS
0
R/W
This bit is always read as 0 and cannot be modified.
Output Compare A Mode Select
Specifies whether OCRA is used in the normal operating
mode or in the operating mode using OCRAR and
OCRAF.
0: The normal operating mode is specified for OCRA
1: The operating mode using OCRAR and OCRAF is
specified for OCRA
5
ICRS
0
R/W
Input Capture Register Select
Controls the access to OCRAR and OCRAF.
0: Access is disabled
1: Access is enabled
4
OCRS
0
R/W
Output Compare Register Select
OCRA and OCRB share the same address. When this
address is accessed, the OCRS bit selects which register
is accessed. The operation of OCRA or OCRB is not
affected.
0: OCRA is selected
1: OCRB is selected
3 to 0

All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
Rev. 2.00 Aug. 20, 2008 Page 382 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.3
Operation Timing
10.3.1
FRC Increment Timing
Figure 10.2 shows the FRC increment timing with an internal clock source.
φ
Internal clock
FRC input
clock
FRC
N–1
N
N+1
Figure 10.2 Increment Timing with Internal Clock Source
10.3.2
Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). Figure 10.3 shows the timing of this operation
for compare-match A.
φ
FRC
N
OCRA
N
N+1
N
N+1
N
Compare-match
A signal
Figure 10.3 Timing of Output Compare A Output
Rev. 2.00 Aug. 20, 2008 Page 383 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.3.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 10.4 shows the timing of this
operation.
φ
Compare-match
A signal
FRC
N
H'0000
Figure 10.4 Clearing of FRC by Compare-Match A Signal
10.3.4
Timing of Output Compare Flag (OCF) Setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 10.5 shows the timing of setting the OCFA or OCFB flag.
φ
FRC
N
OCRA, OCRB
N+1
N
Compare-match
signal
OCFA, OCFB
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting
Rev. 2.00 Aug. 20, 2008 Page 384 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.3.5
Timing of FRC Overflow Flag (OVF) Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 10.6 shows the timing of setting the OVF flag.
φ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 10.6 Timing of Overflow Flag (OVF) Setting
Rev. 2.00 Aug. 20, 2008 Page 385 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.3.6
Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs, a write to
OCRA is performed. Figure 10.7 shows the OCRA write timing.
φ
FRC
N
N +1
OCRA
N
N+A
OCRAR, OCRAF
A
Compare-match
signal
Figure 10.7 OCRA Automatic Addition Timing
10.4
Interrupt Sources
The free-running timer can request three interrupts: OCIA, OCIB, and FOVI. Each interrupt can
be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt
controller for each interrupt. Table 10.1 lists the sources and priorities of these interrupts.
The OCIA and OCIB interrupts can be used as the on-chip DTC activation sources.
Table 10.1 FRT Interrupt Sources
Interrupt
Interrupt Source
Interrupt Flag
DTC Activation
Priority
OCIA
Compare match of OCRA
OCFA
Possible
High
OCIB
Compare match of OCRB
OCFB
Possible
FOVI
Overflow of FRC
OVF
Not possible
Rev. 2.00 Aug. 20, 2008 Page 386 of 1198
REJ09B0403-0200
Low
Section 10 16-Bit Free-Running Timer (FRT)
10.5
Usage Notes
10.5.1
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 10.8 shows the timing for this type of
conflict.
Write cycle of FRC
T1
T2
φ
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 10.8 Conflict between FRC Write and Clear
Rev. 2.00 Aug. 20, 2008 Page 387 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.5.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 10.9 shows the timing for this type of conflict.
Write cycle of FRC
T1
T2
φ
Address
FRC address
Internal write
signal
FRC input
clock
FRC
N
M
Write data
Figure 10.9 Conflict between FRC Write and Increment
Rev. 2.00 Aug. 20, 2008 Page 388 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
10.5.3
Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 10.10 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 10.11 shows the timing of this type of
conflict.
Write cycle of OCR
T1
T2
φ
Address
OCR address
Internal write
signal
FRC
N
OCR
N
N+1
M
Write data
Compare-match
signal
Disabled
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)
Rev. 2.00 Aug. 20, 2008 Page 389 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
φ
Address
OCRAR (OCRAF)
address
Internal write signal
OCRAR (OCRAF)
Compare-match signal
Old data
New data
Disabled
FRC
N
OCR
N
N+1
Automatic addition is not performed
because compare-match signals are disabled.
Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)
10.5.4
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may source FRC to increment. This depends
on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table
10.2.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 10.2, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also source FRC to increment.
Rev. 2.00 Aug. 20, 2008 Page 390 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
Table 10.2 Switching of Internal Clock and FRC Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
low to low
FRC Operation
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N+1
N
CKS bit rewrite
2
Switching from
low to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
3
Switching from
high to low
Clock before
switchover
Clock after
switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Rev. 2.00 Aug. 20, 2008 Page 391 of 1198
REJ09B0403-0200
Section 10 16-Bit Free-Running Timer (FRT)
No.
4
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
high to high
FRC Operation
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated because the switchover is assumed to take place on a falling edge, and
FRC is incremented.
Rev. 2.00 Aug. 20, 2008 Page 392 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
Section 11 8-Bit Timer (TMR)
This LSI has two channels of 8-bit timer modules (TMR_0 and TMR_1) which operate on the 8bit counter.
This LSI also has two channels of similar 8-bit timer modules (TMR_Y and TMR_X).
11.1
Features
• Selection of clock sources
 TMR_0, TMR_1: The counter input clock can be selected from six internal clocks.
 TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks.
• Selection of two ways to clear the counters
 The counters can be cleared on compare-match A and compare-match B.
• Cascading of TMR_0 and TMR_1
(Cascading of TMR_Y and TMR_X is not allowed)
 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1
as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare
match occurrences (compare-match count mode).
• Multiple interrupt sources for each channel
 TMR_0, TMR_1, TMR_Y and TMR_X:
compare-match B, and overflow
Three interrupts: Compare-match A,
Rev. 2.00 Aug. 20, 2008 Page 393 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
Figures 11.1 and 11.2 are block diagrams of 8-bit timers.
Internal clock
TMR_0
φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024
TMR_1
φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048
Clock 1
Clock 0
Compare match A1
Compare match A0
Overflow 1
Overflow 0
TCORA_0
TCORA_1
Comparator A_0
Comparator A_1
TCNT_0
TCNT_1
Clear 0
Clear 1
Control logic
Compare match B1
Compare match B0
Comparator B_0
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
[Legend]
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)
Rev. 2.00 Aug. 20, 2008 Page 394 of 1198
REJ09B0403-0200
Internal bus
Select clock
Section 11 8-Bit Timer (TMR)
Internal clock
TMR_X
φ, φ/2, φ/4
TMR_Y
φ/4, φ/256, φ/2048
Clock X
Clock Y
Select clock
Compare match AX
Compare match AY
TCORA_Y
TCORA1_X
Comparator A_Y
Comparator A_X
TCNT_Y
TCNT_X
Overflow X
Overflow Y
Clear Y
Control logic
Compare match BX
Compare match BY
Internal bus
Clear X
Comparator B_Y
Comparator B_X
TCORB_Y
TCORB_X
TCOR_Y
TCSR_X
TCR_Y
TCR_X
Interrupt signals
[Legend]
TCORA_Y:
TCORB_Y:
TCNT_Y:
TCSR_Y:
TCR_Y:
CMIAX
CMIBX
OVIX
CMIAY
CMIBY
OVIY
Time constant register A_Y
Time constant register B_Y
Timer counter_Y
Timer control / status register_Y
Timer control register_Y
TCORA_X:
TCORB_X:
TCNT_X:
TCSR_X:
TCR_X:
TCORC:
Time constant register A_X
Time constant register B_X
Timer counter_X
Timer control / status register_X
Timer control register_X
Tme constant registerC
Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
Rev. 2.00 Aug. 20, 2008 Page 395 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.2
Register Descriptions
The TMR has the following registers for each channel. For details on the serial timer control
register, see section 3.2.3, Serial Timer Control Register (STCR).
• Timer counter (TCNT)
• Time constant register A (TCORA)
• Time constant register B (TCORB)
• Timer control register (TCR)
• Timer control/status register (TCSR)
• Timer connection register S (TCONRS)*
Notes:
Some of the registers of TMR_X and TMR_Y use the same address. The registers can
be switched by the TMRX/Y bit in TCONRS.
* TCONRS is only provided for TMR_X
11.2.1
Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the
CKS2 to CKS0 bits in TCR. TCNT can be cleared by a compare-match A signal or comparematch B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR.
When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is
initialized to H'00.
TCNT_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCNT_X can be accessed
when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S
(TCONRS).
Rev. 2.00 Aug. 20, 2008 Page 396 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.2.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register, so they can be accessed together by word access. TCORA is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA)
in TCSR is set to 1. However, comparison is disabled during the T2 state of a TCORA write cycle.
TCORA is initialized to H'FF.
TCORA_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCORA_X can be accessed
when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S
(TCONRS).
11.2.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_ 1 comprise a single 16-bit
register, so they can be accessed together by word access. TCORB is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB)
in TCSR is set to 1. However, comparison is disabled during the T2 state of a TCORB write cycle.
TCORB is initialized to H'FF.
TCORB_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCORB_X can be accessed
when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S
(TCONRS).
Rev. 2.00 Aug. 20, 2008 Page 397 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.2.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when
the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
Bit
Bit Name
Initial
Value
R/W
Description
7
CMIEB
0
R/W
Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
6
CMIEA
0
R/W
Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set to
1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
4
CCLR1
0
R/W
Counter Clear 1 and 0
3
CCLR0
0
R/W
Specify the clearing conditions of TCNT.
00: Counter clear is disabled
01: Counter clear is enabled on compare-match A
10: Counter clear is enabled on compare-match B
11: Setting prohibited
2 to 0
CKS2 to
CKS0
All 0
R/W
Rev. 2.00 Aug. 20, 2008 Page 398 of 1198
REJ09B0403-0200
Clock Select 2 to 0
Select the clock input to TCNT and count condition,
together with the ICKS1 and ICKS0 bits in STCR. For
details, see table 11.1.
Section 11 8-Bit Timer (TMR)
Table 11.1 (1)
Clock Input to TCNT and Count Condition (TMR_0)
TCR
STCR
CKS2
CKS1
CKS0
ICKS0
Description
0
0
0
X
Disables clock input
0
0
1
0
Increments at falling edge of internal clock φ/8
0
0
1
1
Increments at falling edge of internal clock φ/2
0
1
0
0
Increments at falling edge of internal clock φ/64
0
1
0
1
Increments at falling edge of internal clock φ/32
0
1
1
0
Increments at falling edge of internal clock φ/1024
0
1
1
1
Increments at falling edge of internal clock φ/256
1
0
0
X
Increments at overflow signal from TCNT_1*
1
0
1
X
Setting prohibited
1
1
X
X
Setting prohibited
Note:
*
[Legend]
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should be avoided.
X: Don't care
Rev. 2.00 Aug. 20, 2008 Page 399 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
Table 11.1 (2)
Clock Input to TCNT and Count Condition (TMR_1)
TCR
CKS2
STCR
CKS1
CKS0
ICKS1
Description
0
0
0
X
Disables clock input
0
0
1
0
Increments at falling edge of internal clock φ/8
0
0
1
1
Increments at falling edge of internal clock φ/2
0
1
0
0
Increments at falling edge of internal clock φ/64
0
1
0
1
Increments at falling edge of internal clock φ/128
0
1
1
0
Increments at falling edge of internal clock φ/1024
0
1
1
1
Increments at falling edge of internal clock φ/2048
1
0
0
X
Increments at compare-match A from TCNT_0*
1
0
1
X
Setting prohibited
1
1
X
X
Setting prohibited
Note:
*
[Legend]
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should be avoided.
X: Don't care
Table 11.1 (3)
Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)
TCR
Channel
CKS2
CKS1
CKS0
Description
TMR_Y
0
0
0
Disables clock input
0
0
1
Increments at falling edge of internal clock φ/4
0
1
0
Increments at falling edge of internal clock φ/256
TMR_Y
0
1
1
Increments at falling edge of internal clock φ/2048
1
X
X
Setting prohibited
0
0
0
Disables clock input
0
0
1
Increments at falling edge of internal clock φ
0
1
0
Increments at falling edge of internal clock φ/2
0
1
1
Increments at falling edge of internal clock φ/4
1
X
X
Setting prohibited
Rev. 2.00 Aug. 20, 2008 Page 400 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.2.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. See section 11.2.6, Timer
Connection Register S (TCONRS) for details on the TCSR_Y and TCSR_X accesses.
• TCSR_0
Bit
Bit Name
Initial
Value
R/W
7
CMFB
0
R/(W)* Compare-Match Flag B
Description
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H′00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ADTE
0
R/W
A/D Trigger Enable
Selects whether the A/D conversion start request on
compare match A is enabled or disabled.
0: A/D conversion start request is disabled
1: A/D conversion start request is enabled
3 to 0

All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 401 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
• TCSR_1
Bit
Bit Name
Initial
Value
R/W
7
CMFB
0
R/(W)* Compare-Match Flag B
Description
[Setting condition]
When the values of TCNT_1 and TCORB_1 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_1 and TCORA_1 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_1 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 to 0

All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 402 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
• TCSR_Y
This register can be accessed when the TMRX/Y bit in TCONRS is 1.
Bit
Bit Name
Initial
Value
R/W
7
CMFB
0
R/(W)* Compare-Match Flag B
Description
[Setting condition]
When the values of TCNT_Y and TCORB_Y match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_Y and TCORA_Y match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_Y overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 to 0

All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 403 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
• TCSR_X
This register can be accessed when the TMRX/Y bit in TCONRS is 0.
Bit
Bit Name
Initial
Value
R/W
7
CMFB
0
R/(W)* Compare-Match Flag B
Description
[Setting condition]
When the values of TCNT_X and TCORB_X match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_X and TCORA_X match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_X overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 to 0

All 1
R
Reserved
These bits are always read as 1 and cannot be modified.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 404 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.2.6
Timer Connection Register S (TCONRS)
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit
Bit Name
Initial
Value
R/W
Description
7
TMRX/Y
0
R/W
TMR_X/TMR_Y Access Select
For details, see table 11.2.
0: The TMR_X registers are accessed at addresses
H'FFFFF0 to H'FFFFF5
1: The TMR_Y registers are accessed at addresses
H'FFFFF0 to H'FFFFF5
6 to 0

All 0
R/W
Reserved
The initial values should not be changed.
Table 11.2 Registers Accessible by TMR_X/TMR_Y
TMRX/Y
H'FFFFF0 H'FFFFF1 H'FFFFF2 H'FFFFF3 H'FFFFF4 H'FFFFF5 H'FFFFF6 H'FFFFF7
0
TMR_X
TMR_X
TCR_X
TCSR_X
TMR_Y
TMR_Y
TMR_Y
TCR_Y
TCSR_Y
TCORA_Y TCORB_Y TCNT_Y
1
TMR_X
TMR_X
TMR_X
TMR_X
TCNT_X
TMR_Y
TMR_Y
TMR_X
TMR_X
TCORA_X TCORB_X
TMR_Y
Rev. 2.00 Aug. 20, 2008 Page 405 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.3
Operation Timing
11.3.1
TCNT Count Timing
Figure 11.3 shows the TCNT count timing with an internal clock source.
φ
External clock
input pin
TCNT input
clock
TCNT
N–1
N
N+1
Figure 11.3 Count Timing for Internal Clock Input
11.3.2
Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 11.4
shows the timing of CMF flag setting.
φ
TCNT
N
TCOR
N
N+1
Compare-match
signal
CMF
Figure 11.4 Timing of CMF Setting at Compare-Match
Rev. 2.00 Aug. 20, 2008 Page 406 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.3.3
Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 11.5 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
N
TCNT
H'00
Figure 11.5 Timing of Counter Clear by Compare-Match
11.3.4
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
11.6 shows the timing of OVF flag setting.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 11.6 Timing of OVF Flag Setting
Rev. 2.00 Aug. 20, 2008 Page 407 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.4
TMR_0 and TMR_1 Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected.
11.4.1
16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits.
• Setting of compare-match flags
 The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
• Counter clear specification
 If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when
counter clear by the TMI0 pin has been set.
 The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
be cleared independently.
11.4.2
Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B′100, TCNT_1 counts the occurrence of compare-match
A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the
CMF flag, generation of interrupts, and counter clearing are in accordance with the settings for
each channel.
Rev. 2.00 Aug. 20, 2008 Page 408 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.5
Interrupt Sources
TMR_0, TMR_1, TMR_Y and TMR_X can generate three types of interrupts: CMIA, CMIB, and
OVI.
Table 11.3 shows the interrupt sources and priorities. Each interrupt source can be enabled or
disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to
the interrupt controller for each interrupt.
The CMIA and CMIB interrupts can be used as on-chip DTC activation interrupt sources.
Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
Interrupt
Priority
TMR_X
CMIAX
TCORA_X compare-match
CMFA
Possible
High
CMIBX
TCORB_X compare-match
CMFB
Possible
OVIX
TCNT_X overflow
OVF
Not possible
CMIA0
TCORA_0 compare-match
CMFA
Possible
CMIB0
TCORB_0 compare-match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
CMIA1
TCORA_1 compare-match
CMFA
Possible
CMIB1
TCORB_1 compare-match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
CMIAY
TCORA_Y compare-match
CMFA
Possible
CMIBY
TCORB_Y compare-match
CMFB
Possible
OVIY
TCNT_Y overflow
OVF
Not possible
TMR_0
TMR_1
TMR_Y
Low
Rev. 2.00 Aug. 20, 2008 Page 409 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.6
Usage Notes
11.6.1
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure
11.7, the counter clear takes priority and the write is not performed.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 11.7 Conflict between TCNT Write and Counter Clear
Rev. 2.00 Aug. 20, 2008 Page 410 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.6.2
Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure
11.8, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.8 Conflict between TCNT Write and Increment
Rev. 2.00 Aug. 20, 2008 Page 411 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.6.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 11.9, the
TCOR write takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare-match signal
Disabled
Figure 11.9 Conflict between TCOR Write and Compare-Match
Rev. 2.00 Aug. 20, 2008 Page 412 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
11.6.4
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 11.8 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 11.4, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.
Table 11.4 Switching of Internal Clocks and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Clock switching from low
1
to low level*
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
CKS bit rewrite
2
Clock switching from low
2
to high level∗
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
Rev. 2.00 Aug. 20, 2008 Page 413 of 1198
REJ09B0403-0200
Section 11 8-Bit Timer (TMR)
No.
3
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Clock switching from high
3
to low level∗
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
*4
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
4
Clock switching from high
to high level
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
N
N+1
N+2
CKS bit rewrite
Notes: 1.
2.
3.
4.
11.6.5
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating.
Simultaneous setting of these two modes should be avoided.
Rev. 2.00 Aug. 20, 2008 Page 414 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
This LSI has two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output
an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the
timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal
or an internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 are shown in figure 12.1.
12.1
Features
• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
•
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
• When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
Internal Timer Mode:
•
If the counter overflows, an internal timer interrupt (WOVI) is generated.
Rev. 2.00 Aug. 20, 2008 Page 415 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
Internal NMI
(Interrupt request signal*2)
Interrupt
control
Overflow
Clock
Clock
selection
Reset
control
RESO signal*1
Internal reset signal*1
TCNT_0
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
Internal bus
WOVI0
(Interrupt request signal)
TCSR_0
Bus
interface
Module bus
WDT_0
Internal NMI
(Interrupt request signal*2)
RESO signal*1
Interrupt
control
Overflow
Clock
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
selection
Reset
control
Internal reset signal*1
Internal clock
TCNT_1
TCSR_1
Module bus
Bus
interface
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Internal bus
WOVI1
(Interrupt request signal)
WDT_1
[Legend]
TCSR_0:
TCNT_0:
TCSR_1:
TCNT_1:
Timer control/status register_0
Timer counter_0
Timer control/status register_1
Timer counter_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is
generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal
first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Figure 12.1 Block Diagram of WDT
Rev. 2.00 Aug. 20, 2008 Page 416 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.2
Input/Output Pins
The WDT has the pins listed in table 12.1.
Table 12.1 Pin Configuration
Name
Symbol
I/O
Function
Reset output pin
RESO
Output
Outputs the counter overflow signal in
watchdog timer mode
Input
Inputs the clock pulses to the WDT_1
prescaler counter
External sub-clock input EXCL
pin
12.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 12.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
12.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
timer control/status register (TCSR) is cleared to 0.
Rev. 2.00 Aug. 20, 2008 Page 417 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Bit
Bit Name
Initial
Value
R/W
7
OVF
0
R/(W)* Overflow Flag
Description
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing conditions]
6
WT/IT
0
R/W
•
When TCSR is read when OVF = 1, then 0 is written to
OVF
•
When 0 is written to TME
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4

0
R/W
Reserved
The initial value should not be changed.
3
RST/NMI
0
R/W
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 2.00 Aug. 20, 2008 Page 418 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
Bit
Bit Name
2 to 0
CKS2 to
CKS0
Initial
Value
R/W
Description
All 0
R/W
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
period for φ = 34 MHz is enclosed in parentheses.
000: φ/2 (period: 15.1 µs)
001: φ/64 (period: 481.9 µs)
010: φ/128 (period: 963.8 µs)
011: φ/512 (period: 3.856 ms)
100: φ/2048 (period: 15.42 ms)
101: φ/8192 (period: 61.68 ms)
110: φ/32768 (period: 246.7 ms)
111: φ/131072 (period: 986.9 ms)
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 419 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
• TCSR_1
Bit
7
Bit Name
OVF
Initial
Value
0
R/W
Description
1
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
•
When TCNT overflows (changes from H'FF to H'00)
•
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing conditions]
6
WT/IT
0
R/W
•
When TCSR is read when OVF = 1* , then 0 is written
to OVF
•
When 0 is written to TME
2
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00. When PSS = 1, TCNT is not initialized.
Write H'00 to TCNT to initialize TCNT.
4
PSS
0
R/W
Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
3
RST/NMI
0
R/W
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 2.00 Aug. 20, 2008 Page 420 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
Bit
Bit Name
2 to 0
CKS2 to
CKS0
Initial
Value
R/W
Description
All 0
R/W
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
cycle for φ = 34 MHz and φSUB = 32.768 kHz is enclosed
in parentheses.
When PSS = 0:
000: φ/2 (cycle: 15.1 µs)
001: φ/64 (cycle: 481.9 µs)
010: φ/128 (cycle: 963.8 µs)
011: φ/512 (cycle: 3.856 ms)
100: φ/2048 (cycle: 15.42 ms)
101: φ/8192 (cycle: 61.68 ms)
110: φ/32768 (cycle: 246.7 ms)
111: φ/131072 (cycle: 986.9 ms)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Notes: 1. Only 0 can be written to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Rev. 2.00 Aug. 20, 2008 Page 421 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.4
Operation
12.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
RESO pin for 132 states, as shown in figure 12.2. If the RST/NMI bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin
remains high.
An internal reset request from the watchdog timer and a reset input from the RES pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 2.00 Aug. 20, 2008 Page 422 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
Write H'00 to
TCNT
OVF = 1*
WT/IT = 1 Write H'00 to
TME = 1 TCNT
Internal reset signal
518 system clocks
WT/IT:
TME:
OVF:
Timer mode select bit
Timer enable bit
Overflow flag
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation
Rev. 2.00 Aug. 20, 2008 Page 423 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.4.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows, as shown in figure 12.3. Therefore, an interrupt can be generated at
intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is
requested at the same time the OVF bit of TCSR is set to 1. The timing is shown in figure 12.4.
TCNT value
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WOVI
WOVI
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI : Interval timer interrupt request occurrence
Figure 12.3 Interval Timer Mode Operation
φ
TCNT
H'FF
Overflow signal
(internal signal)
OVF
Figure 12.4 OVF Flag Set Timing
Rev. 2.00 Aug. 20, 2008 Page 424 of 1198
REJ09B0403-0200
H'00
Section 12 Watchdog Timer (WDT)
RESO Signal Output Timing
12.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 12.5.
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
132 states
518 states
Figure 12.5 Output Timing of RESO signal
This LSI has retain state pins, which are only initialized by a system reset. The outputs on these
pins are retained even when an internal reset is generated by the overflow signal of the WDT. For
more information, see section 8, I/O Ports.
Rev. 2.00 Aug. 20, 2008 Page 425 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow
Table 12.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Not possible
Rev. 2.00 Aug. 20, 2008 Page 426 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.6
Usage Notes
12.6.1
Notes on Register Access
The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more
difficult to write to. The procedures for writing to and reading from these registers are given
below.
Writing to TCNT and TCSR (Example of WDT_0):
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 12.6 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain
the value H'5A and the lower bytes must contain the write data. To write to TCSR, the higher
bytes must contain the value H'A5 and the lower bytes must contain the write data.
<TCNT write>
15
8 7
H'5A
Address : H'FFA8
0
Write data
<TCSR write>
15
Address : H'FFA8
8 7
H'A5
0
Write data
Figure 12.6 Writing to TCNT and TCSR (WDT_0)
Reading from TCNT and TCSR (Example of WDT_0):
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR
and H'FFA9 for TCNT.
Rev. 2.00 Aug. 20, 2008 Page 427 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 12.7 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.7 Conflict between TCNT Write and Increment
12.6.3
Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of CKS2 to CKS0 bits.
12.6.4
Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the
operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of
PSS bit.
Rev. 2.00 Aug. 20, 2008 Page 428 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
12.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is
operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
12.6.6
System Reset by RESO Signal
Inputting the RESO output signal to the RES pin of this LSI prevents the LSI from being
initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI.
To reset the entire system by the RESO signal, use the circuit as shown in figure 12.8.
This LSI
Reset input
Reset signal for entire system
RES
RESO
Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal
Rev. 2.00 Aug. 20, 2008 Page 429 of 1198
REJ09B0403-0200
Section 12 Watchdog Timer (WDT)
Rev. 2.00 Aug. 20, 2008 Page 430 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Section 13 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clock synchronous serial communication. Asynchronous serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function). The SCI also supports the smart card (IC
card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous
communication function.
13.1
Features
• Choice of asynchronous or clock synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
The external clock can be selected as a transfer clock source (except for the smart card
interface).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources  transmit-end, transmit-data-empty, receive-data-full, and receive
error  that can issue requests.
The transmit-data-empty and receive-data-full interrupt sources can activate DTC.
• Module stop mode availability
Rev. 2.00 Aug. 20, 2008 Page 431 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Asynchronous Mode:
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
Clock Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception
• Data can be automatically re-transmitted on detection of a error signal during transmission
• Both direct convention and inverse convention are supported
Rev. 2.00 Aug. 20, 2008 Page 432 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Module data bus
RDR
TDR
BRR
SCMR
SSR
φ
SCR
RxD1/RxD3
RSR
TSR
Baud rate
generator
SMR
φ/4
φ/16
Transmission/
reception control
TxD1/TxD3
Parity generation
Internal data bus
Bus interface
Figure 13.1 is a block diagram of SCI_1 and SCI_3.
φ/64
Clock
Parity check
External clock
SCK1/SCK3
[Legend]
RSR:
Receive shift register
RDR: Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
TEI
TXI
RXI
ERI
SCR:
SSR:
SCMR:
BRR:
Serial control register
Serial status register
Smart card mode register
Bit rate register
Figure 13.1 Block Diagram of SCI_1 and SCI_3
Rev. 2.00 Aug. 20, 2008 Page 433 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.2
Input/Output Pins
Table 13.1 shows the input/output pins for each SCI channel.
Table 13.1 Pin Configuration
Channel
Symbol*
Input/Output
Function
1
SCK1
Input/Output
Channel 1 clock input/output
RxD1
Input
Channel 1 receive data input
Input/Output
Channel 1 transmit/receive data input/output (when
smart card interface is selected)
TxD1
Output
Channel 1 transmit data output
SCK3
Input/Output
Channel 3 clock input/output
RxD3
Input
Channel 3 receive data input
Input/Output
Channel 3 transmit/receive data input/output (when
smart card interface is selected)
Output
Channel 3 transmit data output
3
TxD3
Note:
13.3
*
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Register Descriptions
The SCI has the following registers for each channel. Some bits in the serial mode register (SMR),
serial status register (SSR), and serial control register (SCR) have different functions in different
modesnormal serial communication interface mode and smart card interface mode; therefore,
the bits are described separately for each mode in the corresponding register sections.
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit data register (TDR)
• Transmit shift register (TSR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Smart card mode register (SCMR)
• Bit rate register (BRR)
Rev. 2.00 Aug. 20, 2008 Page 434 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one
frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly
accessed by the CPU.
13.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can
receive the next data. Since RSR and RDR function as a double buffer in this way, continuous
receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR
for only once. RDR cannot be written to by the CPU.
13.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after
confirming that the TDRE bit in SSR is set to 1.
13.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
Rev. 2.00 Aug. 20, 2008 Page 435 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial
Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed and
the MSB of TDR is not transmitted in transmission.
In clock synchronous mode, a fixed data length of 8 bits is
used.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. For a multiprocessor format, parity bit addition
and checking are not performed regardless of the PE bit
setting.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the next
transmit frame.
2
MP
0
R/W
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E bit
settings are invalid in multiprocessor mode.
Rev. 2.00 Aug. 20, 2008 Page 436 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 1 and 0
0
CKS0
0
R/W
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 13.3.9, Bit Rate Register (BRR)).
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
Bit Name
Initial
Value
R/W
Description
7
GM
0
R/W
GSM Mode
Setting this bit to 1 allows GSM mode operation. In GSM
mode, the TEND set timing is put forward to 11.0 etu*
from the start and the clock output control function is
appended. For details, see section 13.7.8, Clock Output
Control.
6
BLK
0
R/W
5
PE
0
R/W
Setting this bit to 1 allows block transfer mode operation.
For details, see section 13.7.3, Block Transfer Mode.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. Set this bit to 1 in smart card interface mode.
4
O/E
0
R/W
Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card interface
mode, see section 13.7.2, Data Format (Except in Block
Transfer Mode).
Rev. 2.00 Aug. 20, 2008 Page 437 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
3
BCP1
0
R/W
Basic Clock Pulse 1 and 0
2
BCP0
0
R/W
These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 13.7.4, Receive Data Sampling
Timing and Reception Margin. S is described in section
13.3.9, Bit Rate Register (BRR).
1
CKS1
0
R/W
Clock Select 1 and 0
0
CKS0
0
R/W
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 13.3.9, Bit Rate Register (BRR)).
Note:
*
etu: Element Time Unit (time taken to transfer one bit)
Rev. 2.00 Aug. 20, 2008 Page 438 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, see section
13.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card
interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, see section 13.5, Multiprocessor
Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Rev. 2.00 Aug. 20, 2008 Page 439 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKE1
0
R/W
Clock Enable 1 and 0
0
CKE0
0
R/W
These bits select the clock source and SCK pin function.
Asynchronous mode:
00: Internal clock
(SCK pin functions as I/O port.)
01: Internal clock
(Outputs a clock of the same frequency as the bit rate
from the SCK pin.)
1x: External clock
(Inputs a clock with a frequency 16 times the bit rate
from the SCK pin.)
Clock synchronous mode:
0x: Internal clock (SCK pin functions as clock output.)
1x: External clock (SCK pin functions as clock input.)
[Legend]
x:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 440 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
Bit Name
Initial
Value
R/W
7
TIE
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests are
enabled.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the MP
bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
2
TEIE
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
1
CKE1
0
R/W
Clock Enable 1 and 0
0
CKE0
0
R/W
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched. For
details, see section 13.7.8, Clock Output Control.
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1x: Reserved
When GM in SMR = 1
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output
[Legend]
x:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 441 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
Initial
Value
R/W
7
TDRE
1
R/(W)* Transmit Data Register Empty
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and TDR is
ready for data write
[Clearing conditions]
6
RDRF
0
•
When 0 is written to TDRE after reading TDRE = 1
•
When a TXI interrupt request is issued allowing DTC to
write data to TDR
R/(W)* Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive data is
transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When an RXI interrupt request is issued allowing DTC to
read data from RDR
The RDRF flag is not affected and retains its previous value
when the RE bit in SCR is cleared to 0.
Rev. 2.00 Aug. 20, 2008 Page 442 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
Value
R/W
5
ORER
0
R/(W)* Overrun Error
Description
[Setting condition]
When the next serial reception is completed while RDRF =
1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4
FER
0
R/(W)* Framing Error
[Setting condition]
When the stop bit is 0
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading TDRE = 1
•
When a TXI interrupt request is issued allowing DTC
to write data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive frame.
When the RE bit in SCR is cleared to 0, its previous state
is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit frame.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 443 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
7
Bit Name
TDRE
Initial
Value
1
R/W
Description
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR, and TDR
can be written to.
[Clearing conditions]
6
RDRF
0
•
When 0 is written to TDRE after reading TDRE = 1
•
When a TXI interrupt request is issued allowing DTC to
write data to TDR
1
R/(W)* Receive Data Register Full
Indicates whether the receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When an RXI interrupt request is issued allowing DTC
to read data from RDR
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
5
ORER
0
1
R/(W)* Overrun Error
[Setting condition]
When the next serial reception is completed while RDRF =
1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4
ERS
0
1
R/(W)* Error Signal Status
[Setting condition]
When a low error signal is sampled
[Clearing condition]
When 0 is written to ERS after reading ERS = 1
Rev. 2.00 Aug. 20, 2008 Page 444 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Bit
3
Bit Name
PER
Initial
Value
0
R/W
Description
1
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
TEND is set to 1 when the receiving end acknowledges no
error signal and the next transmit data is ready to be
transferred to TDR.
[Setting conditions]
•
When both TE in SCR and ERS are 0
•
When ERS = 0 and TDRE = 1 after a specified time
passed after the start of 1-byte data transfer. The set
timing depends on the register setting as follows.
2
When GM = 0 and BLK = 0, 2.5 etu* after
transmission start
2
When GM = 0 and BLK = 1, 1.5 etu* after
transmission start
2
When GM = 1 and BLK = 0, 1.0 etu* after
transmission start
2
When GM = 1 and BLK = 1, 1.0 etu* after
transmission start
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading
TDRE = 1
•
When a TXI interrupt request is issued allowing DTC
to write the next data to TDR
Multiprocessor Bit
Not used in smart card interface mode.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Notes: 1. Only 0 can be written to clear the flag.
2. etu: Element Time Unit (time taken to transfer one bit)
Rev. 2.00 Aug. 20, 2008 Page 445 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.8
Smart Card Mode Register (SCMR)
SCMR selects smart card interface mode and its format.
Bit
Bit Name
Initial
Value
R/W
7 to 4

All 1
R
Description
Reserved
These bits are always read as 1 and cannot be modified.
3
SDIR
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: TDR contents are transmitted with LSB-first.
Stores receive data as LSB first in RDR.
1: TDR contents are transmitted with MSB-first.
Stores receive data as MSB first in RDR.
The SDIR bit is valid only when the 8-bit data format is
used for transmission/reception; when the 7-bit data
format is used, data is always transmitted/received with
LSB-first.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. When the
parity bit is inverted, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive data
is stored as it is in RDR.
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in RDR.
1

1
R
Reserved
This bit is always read as 1 and cannot be modified.
0
SMIF
0
R/W
Smart Card Interface Mode Select
When this bit is set to 1, smart card interface mode is
selected.
0: Normal asynchronous or clock synchronous mode
1: Smart card interface mode
Rev. 2.00 Aug. 20, 2008 Page 446 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clock synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it
can be read from or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Bit Rate
Error
Asynchronous mode
φ × 106
B=
64 × 2
Clock synchronous mode
8×2
B × 64 × 2
× (N + 1)
– 1 } × 100
2n – 1
× (N + 1)

2n – 1
Smart card interface mode
× (N + 1)
φ × 106
B=
S×2
[Legend]
B:
N:
φ:
n and S:
2n – 1
φ × 106
B=
φ × 106
Error (%) = {
2n + 1
φ × 106
Error (%) = {
B×S×2
× (N + 1)
2n + 1
–1 } × 100
× (N + 1)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate settable for each frequency. Table 13.6 and 13.8 show sample N settings in
BRR in clock synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. Tables 13.5
and 13.7 show the maximum bit rates with external clock input.
Rev. 2.00 Aug. 20, 2008 Page 447 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
20
25
34
Bit Rate (bit/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
3
88
–0.25
3
110
–0.02
3
150
–0.05
150
3
64
0.16
3
80
–0.47
3
110
–0.29
300
2
129
0.16
2
162
0.15
2
220
0.16
600
2
64
0.16
2
80
–0.47
2
110
–0.29
1200
1
129
0.16
1
162
0.15
1
220
0.16
2400
1
64
0.16
1
80
–0.47
1
110
–0.29
4800
0
129
0.16
0
162
0.15
0
220
0.16
9600
0
64
0.16
0
80
–0.47
0
110
–0.29
19200
0
32
–1.36
0
40
–0.76
0
54
0.62
31250
0
19
0.00
0
24
0.00
0
33
0.00
38400
0
15
1.73
0
19
1.73
0
27
–1.18
Note:
Make the settings so that the error does not exceed 1%.
Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
20
625000
0
0
25
781250
0
0
34
1062500
0
0
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
20
5.0000
312500
25
6.2500
390625
34
8.0000
531250
Rev. 2.00 Aug. 20, 2008 Page 448 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency φ (MHz)
20
24
34
n
N
n
N
n
N
500






1k






2.5 k
2
124
2
149
2
212
5k
1
249
2
74
2
105
10 k
1
124
1
149
1
212
25 k
0
199
0
239
1
84
50 k
0
99
0
119
0
169
100 k
0
49
0
59
0
84
250 k
0
19
0
23
0
33
500 k
0
9
0
11
0
16
1M
0
4
0
5
2.5 M
0
1
5M
0
0*
Bit Rate (bit/s)
110
250
[Legend]
Blank: Setting prohibited.
:
Can be set, but there will be a degree of error.
*:
Continuous transfer or reception is not possible.
Rev. 2.00 Aug. 20, 2008 Page 449 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
20
3.3333
3333333.3
25
4.1667
4166666.7
34
5.6667
5666666.7
Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372)
Operating Frequency φ (MHz)
20.00
21.4272
25
34
Bit Rate
(bit/s)
n
N
Error (%)
n
N
Error(%)
n
N
Error (%)
n
N
Error (%)
9600
2
–6.65
0
2
0.00
0
3
–12.49
0
4
–4.79
0
Table 13.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
20.00
26882
0
0
21.4272
28800
0
0
25.00
33602
0
0
34.00
45699
0
0
Rev. 2.00 Aug. 20, 2008 Page 450 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4
Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the transmission line is usually held in the mark
state (high level). The SCI monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer and reception.
Idle state
(mark state)
1
Serial
data
LSB
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity
bit
Stop bit
1 bit or
none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 2.00 Aug. 20, 2008 Page 451 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4.1
Data Transfer Format
Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, see section 13.5, Multiprocessor Communication Function.
Table 13.10 Serial Transfer Formats (Asynchronous Mode)
Serial Transmit/Receive Format and Frame Length
SMR Settings
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB:
Multiprocessor bit
Rev. 2.00 Aug. 20, 2008 Page 452 of 1198
REJ09B0403-0200
2
3
4
5
6
7
8
9
10
11
12
Section 13 Serial Communication Interface (SCI)
13.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse
of the basic clock, data is latched at the middle of each bit, as shown in figure 13.3. Thus the
reception margin in asynchronous mode is determined by formula (1) below.
M = } (0.5 –
1
2N
)–
D – 0.5
(1+F) – (L – 0.5) F } × 100
N
[%]
... Formula (1)
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16) } × 100
[%] = 46.875 %
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 2.00 Aug. 20, 2008 Page 453 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4.
SCK
0
TxD
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)
Rev. 2.00 Aug. 20, 2008 Page 454 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 13.5. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR,
or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completion>
Figure 13.5 Sample SCI Initialization Flowchart
Rev. 2.00 Aug. 20, 2008 Page 455 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4.5
Serial Data Transmission (Asynchronous Mode)
Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt service routine
TEI interrupt
request generated
1 frame
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 2.00 Aug. 20, 2008 Page 456 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start transmission
[2]
Read TDRE flag in SSR
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
[3] Serial transmission continuation
procedure:
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and clear
the TDRE flag to 0. However, the
TDRE flag is checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.7 Sample Serial Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 457 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.4.6
Serial Data Reception (Asynchronous Mode)
Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
1 frame
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 2.00 Aug. 20, 2008 Page 458 of 1198
REJ09B0403-0200
ERI interrupt request
generated by framing
error
Section 13 Serial Communication Interface (SCI)
Table 13.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample
flowchart for serial data reception.
Table 13.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
Rev. 2.00 Aug. 20, 2008 Page 459 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing and break
detection:
[2]
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
Yes
appropriate error processing, ensure
PER ∨ FER ∨ ORER = 1
that the ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot be
No
Error processing
resumed if any of these flags are set to
1. In the case of a framing error, a
(Continued on next page)
break can be detected by reading the
value of the input port corresponding to
[4]
Read RDRF flag in SSR
the RxD pin.
Read ORER, PER, and
FER flags in SSR
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
However, the RDRF flag is cleared
automatically when the DTC is initiated
by an RXI interrupt and reads data from
RDR.
[Legend]
∨ : Logical add (OR)
Figure 13.9 Sample Serial Reception Flowchart (1)
Rev. 2.00 Aug. 20, 2008 Page 460 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
[3]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
No
PER = 1
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.9 Sample Serial Reception Flowchart (2)
Rev. 2.00 Aug. 20, 2008 Page 461 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle for
the specified receiving station. The multiprocessor bit is used to differentiate between the ID
transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID
transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure
13.10 shows an example of inter-processor communication using the multiprocessor format. The
transmitting station first sends the ID code of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving
station compares that data with its own ID. The station whose ID matches then receives the data
sent next. Stations whose ID does not match continue to skip data until data with a 1
multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the RDRF, FER, and
ORER status flags in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 2.00 Aug. 20, 2008 Page 462 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
[Legend]
MPB: Multiprocessor bit
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Rev. 2.00 Aug. 20, 2008 Page 463 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.5.1
Multiprocessor Serial Data Transmission
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
[1]
Initialization
Start transmission
[2]
Read TDRE flag in SSR
No
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 464 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.5.2
Multiprocessor Serial Data Reception
Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
13.12 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data 1)
D0
D1
Stop
MPB bit
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
D0
D1
Stop
MPB bit
D7
1
1
Start
bit
0
Data (Data 2)
D0
D1
D7
Stop
MPB bit
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID2
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
Data 2
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 13.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 2.00 Aug. 20, 2008 Page 465 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Initialization
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[1]
Start reception
Set MPIE bit in SCR to 1
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[2]
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
Yes
Read receive data in RDR
No
This station’s ID?
Yes
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
[4]
value.
No
[Legend]
∨ : Logical add (OR)
RDRF = 1
Yes
Read receive data in RDR
No
All data received?
[5]
Error processing
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 2.00 Aug. 20, 2008 Page 466 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 2.00 Aug. 20, 2008 Page 467 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.6
Operation in Clock Synchronous Mode
Figure 13.14 shows the general format for clock synchronous communication. In clock
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one
falling edge of the synchronization clock to the next. In data reception, the SCI receives data in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit
is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that the next transmit data can be written during transmission or the
previous receive data can be read during reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Synchronization
clock
MSB
LSB
Bit 0
Serial data
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 13.14 Data Format in Synchronous Communication (LSB-First)
13.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1
and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock
is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one
character, and when no transfer is performed the clock is fixed high.
Rev. 2.00 Aug. 20, 2008 Page 468 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.6.2
SCI Initialization (Clock Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is
set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER
flags in SSR, or RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR and
SCMR.
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. This step is not necessary
if an external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 13.15 Sample SCI Initialization Flowchart
Rev. 2.00 Aug. 20, 2008 Page 469 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.6.3
Serial Data Transmission (Clock Synchronous Mode)
Figure 13.16 shows an example of SCI operation for transmission in clock synchronous mode. In
serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Rev. 2.00 Aug. 20, 2008 Page 470 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Figure 13.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Transfer direction
Synchronization
clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
TXI interrupt
request generated
TEI interrupt request
generated
1 frame
Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode
Rev. 2.00 Aug. 20, 2008 Page 471 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Initialization
[1]
Start transmission
[2]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DTC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR.
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 13.17 Sample Serial Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 472 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.6.4
Serial Data Reception (Clock Synchronous Mode)
Figure 13.18 shows an example of SCI operation for reception in clock synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the receive data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RXI interrupt
request generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 13.18 Example of SCI Receive Operation in Clock Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample flowchart
for serial data reception.
Rev. 2.00 Aug. 20, 2008 Page 473 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
[1]
Initialization
Start reception
[2]
Read ORER flag in SSR
Yes
ORER = 1
[3]
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
However, the RDRF flag is cleared
automatically when the DTC is
initiated by a receive data full interrupt
(RXI) and reads data from RDR.
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 13.19 Sample Serial Reception Flowchart
Rev. 2.00 Aug. 20, 2008 Page 474 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.6.5
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits
to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive
mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking
that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0,
simultaneously set the TE and RE bits to 1 with a single instruction.
Rev. 2.00 Aug. 20, 2008 Page 475 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Initialization
[1]
[1]
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2]
SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Start transmission/reception
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3]
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
Yes
[3]
Error processing
[4]
[4]
SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
Read receive data in RDR, and
reception, before the MSB (bit 7) of
clear RDRF flag in SSR to 0
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0. Also,
No
before the MSB (bit 7) of the current
All data received?
[5]
frame is transmitted, read 1 from the
TDRE flag to confirm that writing is
Yes
possible. Then write data to TDR and
clear the TDRE flag to 0.
However, the TDRE flag is checked
Clear TE and RE bits in SCR to 0
and cleared automatically when the
DTC is initiated by a transmit data
empty interrupt (TXI) request and
<End>
writes data to TDR. Similarly, the
RDRF flag is cleared automatically
when the DTC is initiated by a receive
Note: When switching from transmit or receive operation to simultaneous
data full interrupt (RXI) and reads
transmit and receive operations, first clear the TE bit and RE bit to 0,
data from RDR.
then set both these bits to 1 simultaneously.
Yes
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
Rev. 2.00 Aug. 20, 2008 Page 476 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.7
Smart Card Interface Description
The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification
Card) standard as an enhanced serial communication interface function. Smart card interface mode
can be selected using the appropriate register.
13.7.1
Sample Connection
Figure 13.21 shows a sample connection between the smart card and this LSI. This LSI
communicates with the IC card using a single transmission line. When the SMIF bit in SCMR is
set to 1, the TxD and RxD pins are interconnected inside the LSI, which makes the RxD pin
function as an I/O pin. Pull up the data transmission line to Vcc using a resistor. Setting the RE
and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception
allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input
the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output
port of this LSI.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Main unit of the device
to be connected
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Figure 13.21 Pin Connection for Smart Card Interface
13.7.2
Data Format (Except in Block Transfer Mode)
Figure 13.22 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
is secured as a guard time after the end of the parity bit before the start of the next frame.
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
has passed from the start bit.
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
after two or more etu.
Rev. 2.00 Aug. 20, 2008 Page 477 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D7
Dp
Output from the transmitting station
When a parity error is generated
Ds
D0
D1
D2
D3
D4
D5
D6
DE
Output from the transmitting station
Output from
the receiving station
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 13.22 Data Formats in Normal Smart Card Interface Mode
For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z) state
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0)
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 13.23. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z) state
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)
Rev. 2.00 Aug. 20, 2008 Page 478 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 13.24. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
13.7.3
Block Transfer Mode
Block transfer mode is different from normal smart card interface mode in the following respects.
• If a parity error is detected during reception, no error signal is output. Since the PER bit in
SSR is set by error detection, clear the bit before receiving the parity bit of the next frame.
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
before the start of the next frame.
• Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set
11.5 etu after transmission start.
• Although the ERS flag in block transfer mode displays the error signal status as in normal
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
Rev. 2.00 Aug. 20, 2008 Page 479 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a
basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and
BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 13.25. The reception margin here is determined by the following formula.
M =  (0.5 –
1
) – (L – 0.5) F –
2N
 D – 0.5  (1 + F)  × 100 [%]
N
... Formula (1)
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1/2 x 372) x 100 [%] = 49.866%
Rev. 2.00 Aug. 20, 2008 Page 480 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
372 clock cycles
186 clock
cycles
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate)
13.7.5
Initialization
Before starting transmitting and receiving data, initialize the SCI using the following procedure.
Initialization is also necessary before switching from transmission to reception and vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ORER, ERS, and PER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set
the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the
TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high
impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and
TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output
clock pulses.
7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval.
Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.
Rev. 2.00 Aug. 20, 2008 Page 481 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
To switch from reception to transmission, first verify that reception has completed, and initialize
the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception
completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from
transmission to reception, first verify that transmission has completed, and initialize the SCI. At
the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission
completion can be verified by reading the TEND flag.
13.7.6
Serial Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data is
re-transmitted. Figure 13.26 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
re-transferred from TDR to TSR allowing automatic data retransmission.
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this
case, one frame of data is determined to have been transmitted including re-transfer, and the
TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is
set to 1. Writing transmit data to TDR starts transmission of the next data.
Figure 13.28 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DTC. In transmission, the
TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request
when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of
transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand.
The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error
occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains
as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the
specified number of bytes, including re-transmission in the case of error occurrence. However, the
ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE
bit to 1 to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable it prior to making SCI
settings. See section 7, Data Transfer Controller (DTC) for DTC settings.
Rev. 2.00 Aug. 20, 2008 Page 482 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
(n + 1) th
transfer frame
Retransfer frame
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
Transfer from TDR to TSR
Transfer from TDR to TSR
TEND
[2]
[3]
FER/ERS
[1]
[3]
Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 13.27.
Ds
I/O data
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard time
TXI
(TEND interrupt)
12.5 etu
GM = 0
11.0 etu
GM = 1
[Legend]
Ds:
Start bit
D0 to D7:Data bits
Dp:
Parity bit
DE:
Error signal
etu:
Element Time Unit (time taken to transfer one bit)
Figure 13.27 TEND Flag Set Timings during Transmission
Rev. 2.00 Aug. 20, 2008 Page 483 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR and clear
TDRE flag in SSR to 0
No
All data transmitted?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
End
Figure 13.28 Sample Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 484 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.7.7
Serial Data Reception (Except in Block Transfer Mode)
Data reception in smart card interface mode is identical to that in normal serial communication
interface mode. Figure 13.29 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined
to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt
request is generated if the RIE bit in SCR is set.
Figure 13.30 shows a sample flowchart for reception. All the processing steps are automatically
performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1
allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates
DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is
specified as a source of DTC activate beforehand. The RDRF flag is automatically cleared to 0 at
data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set
to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be
cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number
of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is
set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read.
Note:
For operations in block transfer mode, see section 13.4, Operation in Asynchronous Mode.
(n + 1) th
transfer frame
Retransfer frame
n th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[3]
[1]
[3]
PER
Figure 13.29 Data Re-transfer Operation in SCI Reception Mode
Rev. 2.00 Aug. 20, 2008 Page 485 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Start
Initialization
Start reception
ORER = 0
and PER = 0?
No
Yes
Error processing
No
RDRF = 1?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 13.30 Sample Reception Flowchart
Rev. 2.00 Aug. 20, 2008 Page 486 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 13.31 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 13.31 Clock Output Fixing Timing
At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty ratio.
At Power-On:
To secure the appropriate clock duty ratio simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
4. Set the CKE0 bit in SCR to 1 to start clock output.
Rev. 2.00 Aug. 20, 2008 Page 487 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
At Transition from Smart Card Interface Mode to Software Standby Mode:
1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK
pins to the values for the output fixed state in software standby mode.
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the
CKE1 bit to the value for the output fixed state in software standby mode.
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
specified level with the duty ratio retained.
5. Make the transition to software standby mode.
At Transition from Software Standby Mode to Smart Card Interface Mode:
1. Cancel software standby mode.
2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty
ratio is then generated.
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[1]
[2]
Figure 13.32 Clock Stop and Restart Procedure
Rev. 2.00 Aug. 20, 2008 Page 488 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.8
Interrupt Sources
13.8.1
Interrupts in Normal Serial Communication Interface Mode
Table 13.12 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data
transfer by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 13.12 SCI Interrupt Sources
Channel
3
1
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
High
ERI3
Receive error
ORER, FER, PER
Not possible
RXI3
Receive data full
RDRF
Possible
TXI3
Transmit data empty
TDRE
Possible
TEI3
Transmit end
TEND
Not possible
ERI1
Receive error
ORER, FER, PER
Not possible
RXI1
Receive data full
RDRF
Possible
TXI1
Transmit data empty
TDRE
Possible
TEI1
Transmit end
TEND
Not possible
Low
Rev. 2.00 Aug. 20, 2008 Page 489 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.8.2
Interrupts in Smart Card Interface Mode
Table 13.13 shows the interrupt sources in smart card interface mode. A TEI interrupt request
cannot be used in this mode.
Table 13.13 SCI Interrupt Sources
Channel Name
3
1
Interrupt Source
Interrupt Flag
DTC Activation
Priority
ERI3
Receive error, error
signal detection
ORER, PER, ERS
Not possible
High
RXI3
Receive data full
RDRF
Possible
TXI3
Transmit data empty
TEND
Possible
ERI1
Receive error, error
signal detection
ORER, PER, ERS
Not possible
RXI1
Receive data full
RDRF
Possible
TXI1
Transmit data empty
TEND
Possible
Low
Data transmission/reception using the DTC is also possible in smart card interface mode, similar
to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously
set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request
thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC
activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer
by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and
DTC automatically transmit the specified number of bytes, including re-transmission in the case of
error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not
automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1
to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to
making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI
interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is
automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set
but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued
to the CPU instead; the error flag must be cleared.
Rev. 2.00 Aug. 20, 2008 Page 490 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.9
Usage Notes
13.9.1
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 28, Power-Down Modes.
13.9.2
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
13.9.3
Mark State and Break Sending
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark
state (high level) or send a break during serial data transmission. To maintain the communication
line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at
this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break
during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the
TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the
TxD pin becomes an I/O port, and 0 is output from the TxD pin.
13.9.4
Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
13.9.5
Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data
is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
Rev. 2.00 Aug. 20, 2008 Page 491 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.9.6
Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
13.33).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode
Rev. 2.00 Aug. 20, 2008 Page 492 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.9.7
SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop or software standby mode, stop all
transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output
pins during each mode depend on the port settings, and the pins output a high-level signal after
mode cancellation. If the transition is made during data transmission, the data being transmitted
will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 13.34 shows a sample flowchart for mode transition during transmission. Figures 13.35 and
13.36 show the pin states during transmission.
Before making the transition from the transmission mode using DTC transfer to module stop or
software standby mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting TE and TIE to
1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC.
Rev. 2.00 Aug. 20, 2008 Page 493 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Transmission
No
All data transmitted?
[1]
[1] Data being transmitted is lost
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation; however, if the DTC
has been initiated, the data
remaining in DTC RAM will be
transmitted when TE and TIE are
set to 1.
Yes
Read TEND flag in SSR
No
TEND = 1
Yes
TE = 0
[2]
[2] Also clear TIE and TEIE to 0
when they are 1.
[3]
Make transition to software standby mode etc.
[3] Module stop mode is included.
Cancel software standby mode etc.
No
Change operating mode?
Yes
Initialization
TE = 1
Start transmission
Figure 13.34 Sample Flowchart for Mode Transition during Transmission
Transmission start
Transition to
Software standby
Transmission end software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
High output
Start
Port
SCI TxD output
Stop
Port input/output
Port
Figure 13.35 Pin States during Transmission in Asynchronous Mode
(Internal Clock)
Rev. 2.00 Aug. 20, 2008 Page 494 of 1198
REJ09B0403-0200
High output
SCI
TxD output
Section 13 Serial Communication Interface (SCI)
Transmission start
Transmission end
Transition to
Software standby
software standby mode cancelled
mode
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port
input/output
Marking output
Port
Last TxD bit retained
Port input/output
SCI TxD output
Port
High output*
SCI
TxD output
Note: Initialized in software standby mode
Figure 13.36 Pin States during Transmission in Clock Synchronous Mode
(Internal Clock)
Reception: Before making the transition to module stop or software standby mode, stop reception
(RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being
received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 13.37 shows a sample flowchart for mode transition during reception.
Rev. 2.00 Aug. 20, 2008 Page 495 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
Reception
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Data being received will be invalid.
Yes
Read receive data in RDR
[2] Module stop mode is included.
RE = 0
[2]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
No
Yes
Initialization
RE = 1
Start reception
Figure 13.37 Sample Flowchart for Mode Transition during Reception
Rev. 2.00 Aug. 20, 2008 Page 496 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
13.9.8
Notes on Switching from SCK Pins to Port Pins
When SCK pins are switched to port pins after transmission has completed, pins are enabled for
port output after outputting a low pulse of half a cycle as shown in figure 13.38.
Low pulse of half a cycle
SCK/Port
1. Transmission end
Data
Bit 6
4. Low pulse output
Bit 7
2. TE = 0
TE
3. C/A = 0
C/A
CKE1
CKE0
Figure 13.38 Switching from SCK Pins to Port Pins
To prevent the low pulse output that is generated when switching the SCK pins to the port pins,
specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure
below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1.
1. End serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 (switch to port output)
5. CKE1 bit = 0
Rev. 2.00 Aug. 20, 2008 Page 497 of 1198
REJ09B0403-0200
Section 13 Serial Communication Interface (SCI)
High output
SCK/Port
1. Transmission end
Data
Bit 6
Bit 7
TE
2. TE = 0
4. C/A = 0
C/A
3. CKE1 = 1
CKE1
5. CKE1 = 0
CKE0
Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
Rev. 2.00 Aug. 20, 2008 Page 498 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
Section 14 CRC Operation Circuit (CRC)
This LSI has a cyclic redundancy check (CRC) operation circuit to enhance the reliability of data
transfer in high-speed communications, etc. The CRC operation circuit detects errors in data
blocks.
14.1
Features
The features of the CRC operation circuit are listed below.
• CRC code generated for any desired data length in an 8-bit unit
• CRC operation executed on eight bits in parallel
• One of three generating polynomials selectable
• CRC code generation for LSB-first or MSB-first communication selectable
Figure 14.1 is a block diagram of the CRC operation circuit.
Internal bus
CRCCR
Control
signal
CRCDIR
CRC code
generation
circuit
CRCDOR
[Legend]
CRCCR: CRC control register
CRCDIR: CRC data input register
CRCDOR: CRC data output register
Figure 14.1 Block Diagram of CRC Operation Circuit
Rev. 2.00 Aug. 20, 2008 Page 499 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
14.2
Register Descriptions
The CRC operation circuit has the following registers.
• CRC control register (CRCCR)
• CRC data input register (CRCDIR)
• CRC data output register (CRCDOR)
14.2.1
CRC Control Register (CRCCR)
CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the
generating polynomial.
Bit
Bit Name
Initial
Value
R/W
Description
7
DORCLR
0
W
CRCDOR Clear
Setting this bit to 1 clears CRCDOR to H′0000.
6 to 3

All 0
R
Reserved
The initial value should not be changed.
2
LMS
0
R/W
CRC Operation Switch
Selects CRC code generation for LSB-first or MSB-first
communication.
0: Performs CRC operation for LSB-first communication.
The lower byte (bits 7 to 0) is first transmitted when
CRCDOR contents (CRC code) are divided into two
bytes to be transmitted in two parts.
1: Performs CRC operation for MSB-first communication.
The upper byte (bits 15 to 8) is first transmitted when
CRCDOR contents (CRC code) are divided into two
bytes to be transmitted in two parts.
1
G1
0
R/W
CRC Generating Polynomial Select
0
G0
0
R/W
These bits select the polynomial.
00: Reserved
8
2
01: X + X + X + 1
16
15
2
16
12
5
10: X + X + X + 1
11: X + X + X + 1
Rev. 2.00 Aug. 20, 2008 Page 500 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
14.2.2
CRC Data Input Register (CRCDIR)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
The result is obtained in CRCDOR.
14.2.3
CRC Data Output Register (CRCDOR)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the
bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC
operation result is additionally written to the bytes to which CRC operation is to be performed, the
CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in
CRCCR are set to G1 = 0 and G0 = 1, respectively, the lower byte of this register contains the
result.
14.3
CRC Operation Circuit Operation
The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An
16
12
5
example in which a CRC code for hexadecimal data H'F0 is generated using the X + X + X + 1
polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
1. Write H'83 to CRCCR
2. Write H'F0 to CRCDIR
7
CRCCR
1
7
0
0
0
0
0
CRCDIR
1 1
0
0
1
1
1
1
0
0 0
CRC code generation
CRCDOR clearing
0
7
0
0
7
CRCDORH
0
0
0
0
0
0
0 0
CRCDORH
1
1
1
1
0
1
1 1
CRCDORL
0
0
0
0
0
0
0 0
CRCDORL
1
0
0
0
1
1
1 1
3. Read from CRCDOR
CRC code = H'F78F
4. Serial transmission (LSB first)
Data
CRC code
7
1
1
1
F
1
0
1
1
7
0
7
1
1
0
0
8
0
1
1
1
F
0
7
1
1
0
1
1
1
F
0
0
0
0
Output
0
Figure 14.2 LSB-First Data Transmission
Rev. 2.00 Aug. 20, 2008 Page 501 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
1. Write H'87 to CRCCR
2. Write H'F0 to CRCDIR
7
CRCCR
7
0
0
1
0
0
0
1
CRCDIR
1 1
CRCDOR clearing
0
7
0
1
1
1
1
0
0
0
0
CRC code generation
0
7
CRCDORH
0
0
0
0
0
0
0 0
CRCDORH
1
1
1
0
1
1
1
1
CRCDORL
0
0
0
0
0
0
0 0
CRCDORL
0
0
0
1
1
1
1
1
3. Read from CRCDOR
CRC code = H'EF1F
4. Serial transmission (MSB first)
CRC code
Data
7
Output
1
1
1
F
1
0
0
0
0
0
7
0
1
1
1
E
0
1
1
1
0
7
1
0
F
Figure 14.3 MSB-First Data Transmission
Rev. 2.00 Aug. 20, 2008 Page 502 of 1198
REJ09B0403-0200
0
0
0
1
1
1
1
1
F
1
Section 14 CRC Operation Circuit (CRC)
1. Serial reception (LSB first)
Data
CRC code
7
1
1
1
1
0
1
1
F
0
7
1
1
0
7
0
0
8
2. Write H'83 to CRCCR
1
1
1
7
1
1
F
1
1
0
0
F
0
0
0
0
0
0
0
0
1
1
CRCDIR
1
0
1
1
1
CRCDOR clearing
0
0
CRC code generation
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
1
1
1
1
0
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
1
0
0
0
1
1
1
1
1
0
1
1
1
4. Write H'8F to CRCDIR
5. Write H'F7 to CRCDIR
7
CRCDIR
1
7
0
0
Input
0
7
0
0
0
1
3. Write H'F0 to CRCDIR
7
CRCCR
1
0
0
0
1
1
1
1
CRCDIR
1
0
1
1
CRC code generation
CRC code generation
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
0
0
0
0
0
0
0
0
CRCDORL
1
1
1
1
0
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
6. Read from CRCDOR
CRC code = H'0000 → No error
Figure 14.4 LSB-First Data Reception
Rev. 2.00 Aug. 20, 2008 Page 503 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
1. Serial reception (MSB first)
Data
CRC code
7
Input
1
1
1
1
0
0
0
F
0
7
0
1
0
2. Write H'87 to CRCCR
1
1
0
1
1
E
0
7
1
0
0
0
F
0
1
1
1
0
0
0
1
1
1
CRCDIR
1
0
1
1
1
CRCDOR clearing
0
0
0
0
CRC code generation
0
7
0
7
CRCDORH
0
0
0
0
0
0
0
0
CRCDORH
1
1
1
0
1
1
1
1
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
1
1
1
1
1
1
1
1
1
1
4. Write H'EF to CRCDIR
5. Write H'1F to CRCDIR
7
CRCDIR
1
7
0
1
1
0
1
1
1
1
CRCDIR
0
0
0
0
CRC code generation
CRC code generation
0
7
0
7
CRCDORH
0
0
0
1
1
1
1
1
CRCDORH
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
0
0
0
0
0
CRCDORL
0
0
0
0
0
0
0
0
6. Read from CRCDOR
CRC code = H'0000 → No error
Figure 14.5 MSB-First Data Reception
Rev. 2.00 Aug. 20, 2008 Page 504 of 1198
REJ09B0403-0200
1
1
F
7
0
0
1
3. Write H'F0 to CRCDIR
7
CRCCR
1
1
Section 14 CRC Operation Circuit (CRC)
14.4
Note on CRC Operation Circuit
Note that the sequence to transmit the CRC code differs between LSB-first transmission and
MSB-first transmission.
1. CRC code generation
After specifying the operation method, write data to CRCDIR in the sequence of (1) → (2) → (3) → (4).
7
0
(1) → (2) → (3) → (4)
CRCDIR
CRC code generation
0
7
CRCDORH
(5)
CRCDORL
(6)
2. Transmission data
(i) LSB-first transmission
CRC code
7
07
07
(6)
(5)
07
(4)
07
07
(3)
(2)
0
Output
(1)
(ii) MSB-first transmission
CRC code
7
Output
07
(1)
07
(2)
07
(3)
0 7
(4)
07
(5)
0
(6)
Figure 14.6 LSB-First and MSB-First Transmit Data
Rev. 2.00 Aug. 20, 2008 Page 505 of 1198
REJ09B0403-0200
Section 14 CRC Operation Circuit (CRC)
Rev. 2.00 Aug. 20, 2008 Page 506 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Section 15 Serial Communication Interface with FIFO
(SCIF)
This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that
supports asynchronous serial communication.
The SCIF enables asynchronous serial communication with standard asynchronous
communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART). The SCIF
also has independent 16-stage FIFO buffers for transmission and reception to provide efficient
high-speed continuous communication.
In addition, the SCIF can be connected to the LPC interface for direct control from the LPC host.
15.1
Features
• Full-duplex communication:
The transmitter and receiver are independent, enabling transmission and reception to be
executed simultaneously. Both the transmitter and receiver use 16-stage FIFO buffering,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• Modem control function
• Data length: Selectable from 5, 6, 7, and 8 bits
• Parity: Selectable from even parity, odd parity, and no parity
• Stop bit length: Selectable from 1, 1.5, and 2 bits
• Receive error detection: Parity, overrun, and framing errors
• Break detection
Rev. 2.00 Aug. 20, 2008 Page 507 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
LPC
interface
FIER
FIIR
FFCR
FLCR
FMCR
FLSR
FMSR
FSCR
Bus interface
Internal data bus
Figure 15.1 shows a block diagram of the SCIF.
P25/RI
P24/DCD
P26/DSR
P27/DTR
P64/CTS
P65/RTS
Modem
controller
FTHR
Transmit FIFO
(16 bytes)
SCIFCR
SCIF
interrupt
request
Register
transmission/
reception
control
Transmission
(1 byte)
FTSR
P50/TxDF
FRSR
P51/RxDF
FRBR
Receive FIFO
(16 bytes)
Reception
(1 byte)
FDLH
FDLL
System clock
LCLK
Clock
selection/
divider
circuit
SCLK
[Legend]
FRSR:
Receive shift register
FTSR:
Transmitter shift register
FRBR:
Receive buffer register
FTHR:
Transmitter holding register
FDLH, FDLL: Divisor latch H, L
FIER:
Interrupt enable register
FIIR:
Interrupt identification register
Transfer clock
Baud rate
generator
FFCR:
FLCR:
FMCR:
FLSR:
FMSR:
FSCR:
SCIFCR:
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
Scratch pad register
SCIF control register
Figure 15.1 Block Diagram of SCIF
Rev. 2.00 Aug. 20, 2008 Page 508 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.2
Input/Output Pins
Table 15.1 lists the SCIF input/output pins.
Table 15.1 Pin Configuration
Pin Name
Port
Input/Output
Function
TxDF
P50
Output
Transmit data output
RxDF
P51
Input
Receive data input
RI
P25
Input
Ring indicator input
DCD
P24
Input
Data carrier detect input
DSR
P26
Input
Data set ready input
DTR
P27
Output
Data terminal ready output
CTS
P64
Input
Transmission permission input
RTS
P65
Output
Transmission request output
Rev. 2.00 Aug. 20, 2008 Page 509 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3
Register Descriptions
The SCIF has the following registers. The register configuration of the SCIF is shown below.
Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in SUBMSTPBL. For
details, see table 15.2. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and
SERIRQ control register 4 (SIRQCR4), see section 19, LPC Interface (LPC).
• Host interface control register 5 (HICR5)
• Sub-chip module stop control register BL (SUBMSTPBL)
• Receive buffer register (FRBR)
• Transmitter holding register (FTHR)
• Divisor latch L (FDLL)
• Interrupt enable register (FIER)
• Divisor latch H (FDLH)
• Interrupt identification register (FIIR)
• FIFO control register (FFCR)
• Line control register (FLCR)
• Modem control register (FMCR)
• Line status register (FLSR)
• Modem status register (FMSR)
• Scratch pad register (FSCR)
• SCIF control register (SCIFCR)
• SCIF address register H (SCIFADRH)
• SCIF address register L (SCIFADRL)
• SERIRQ control register 4 (SIRQCR4)
Table 15.2 Register Access
SCIFE Bit in HICR5
0
1
Bit 3 in SUBMSTPBL 0
1
0
1
SCIFCR
H8S CPU
2
access*
Access disabled
H8S CPU
2
access*
Access disabled
Other than SCIFCR
H8S CPU
2
access*
Access disabled
LPC access*
1
LPC access*
1
Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF.
2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00.
Rev. 2.00 Aug. 20, 2008 Page 510 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.1
Receive Shift Register (FRSR)
FRSR is a register that receives data and converts serial data input from the RxDF pin to parallel
data. It stores the data in the order received from the LSB (bit 0). When one frame of serial data
has been received, the data is transferred to FRBR.
FRSR cannot be read from the CPU/LPC interface.
15.3.2
Receive Buffer Register (FRBR)
FRBR is an 8-bit read-only register that stores received serial data. It can read data correctly when
the DR bit in FLSR is set.
When the FIFO is disabled, the data in FRBR must be read before the next data is received. If new
data is received before the remaining data is read, the data is overwritten, resulting in an overrun
error.
When this register is read with the FIFO enabled, the first buffer of the receive FIFO is read.
When the receive FIFO becomes full, the subsequent receive data is lost, resulting in an overrun
error.
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
Bit 7 to
bit 0
All 0
R
Stores received serial data.
15.3.3
The data is 16 bytes when the FIFO is enabled.
Transmitter Shift Register (FTSR)
FTSR is a register that converts parallel data from the TxDF pin to serial data and then transmits
the serial data. When one frame transmission of serial data is completed, the next data is
transferred from FTHR. The serial data is transmitted from the LSB (bit 0).
FTSR cannot be written from the H8S CPU/LPC interface.
Rev. 2.00 Aug. 20, 2008 Page 511 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.4
Transmitter Holding Register (FTHR)
FTHR is an 8-bit write-only register that stores serial transmit data. It is accessible when the
DLAB bit in FLCR is 0. Write transmit data while the THRE bit in FLCR is set to 1.
Data can be written to FTHR when the THRE bit is set with the FIFO disabled. If data is written to
FTHR when the THRE bit is not set, the data is overwritten.
While the THRE bit is set with the FIFO enabled, up to 16 bytes of data can be written. If data is
written with the FIFO full, the written data is lost.
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
Bit 7 to
bit 0

W
Stores serial data to be transmitted.
15.3.5
The data is 16 bytes when the FIFO is enabled.
Divisor Latch H, L (FDLH, FDLL)
The FDLH and FDLL are registers used to set the baud rate. They are accessible when the DLAB
16
bit in FLCR is 1. Frequency division ranging from 1 to (2 − 1) can be set with these registers.
The frequency divider circuit stops when both of FDLH and FDLL are 0 (initial value).
• FDLH
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
Bit 7 to
bit 0
All 0
R/W
Upper 8 bits of divisor latch
• FDLL
Bit
Bit Name
Initial Value
R/W
Description
7 to 0
Bit 7 to
bit 0
All 0
R/W
Lower 8 bits of divisor latch
Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value)
Rev. 2.00 Aug. 20, 2008 Page 512 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.6
Interrupt Enable Register (FIER)
FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR
is 0.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4

All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
3
EDSSI
0
R/W
Modem Status Interrupt Enable
0: Modem status interrupt disabled
1: Modem status interrupt enabled
2
ELSI
0
R/W
Receive Line Status Interrupt Enable
0: Receive line status interrupt disabled
1: Receive line status interrupt enabled
1
ETBEI
0
R/W
FTHR Empty Interrupt Enable
0: FTHR empty interrupt disabled
1: FTHR empty interrupt enabled
0
ERBFI
0
R/W
Receive Data Ready Interrupt Enable
A character timeout interrupt is included when the
FIFO is enabled.
0: Receive data ready interrupt disabled
1: Receive data ready interrupt enabled
Rev. 2.00 Aug. 20, 2008 Page 513 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.7
Interrupt Identification Register (FIIR)
FIIR consists of bits that identify interrupt sources. For details, see table 15.3.
Bit
Bit Name
Initial Value
R/W
Description
7
FIFOE1
0
R
FIFO Enable 0, 1
6
FIFOE0
0
R
These bits indicate the transmit/receive FIFO
setting.
00: Transmit/receive FIFOs disabled
11: Transmit/receive FIFOs enabled
5, 4

All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
3
INTID2
0
R
Interrupt ID2, ID1, ID0
2
INTID1
0
R
1
INTID0
0
R
These bits Indicate the interrupt of the highest
priority among the pending interrupts.
000: Modem status
001: FTHR empty
010: Receive data ready
011: Receive line status
110: Character timeout (when the FIFO is enabled)
0
INTPEND
1
R
Interrupt Pending
Indicates whether one or more interrupts are
pending.
0: Interrupt pending
1: No interrupt pending
Rev. 2.00 Aug. 20, 2008 Page 514 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.3 Interrupt Control Function
FIIR
Setting/Clearing of Interrupt
INTID
2
1
0
INTPEND Priority Type of Interrupt
Interrupt Source
Clearing of
Interrupt

0
0
0
1

No interrupt
None
0
1
1
0
1 (high)
Receive line status
Overrun error,
FLSR read
parity error, framing
error, break
interrupt
0
1
0
0
2
Receive data ready Receive data
remaining,
FIFO trigger level
FRBR read or
receive FIFO is
below trigger
level.
1
1
0
0
2
Character timeout No data is input to FRBR read
(with FIFO enabled) or output from the
receive FIFO for the
4-character time
period while one or
more characters
remain in the
receive FIFO.
0
0
1
0
3
FTHR empty
FTHR empty
0
0
0
0
4 (low)
Modem status
CTS, DSR, RI, DCD FMSR read
FIIR read or
FTHR write
Rev. 2.00 Aug. 20, 2008 Page 515 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8
FIFO Control Register (FFCR)
FFCR is a write-only register that controls transmit/receive FIFOs.
Bit
Bit Name
Initial Value R/W Description
7
RCVRTRIG1
0
W
Receive FIFO Interrupt Trigger Level 1, 0
6
RCVRTRIG0
0
W
These bits set the trigger level of the receive FIFO
interrupt.
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes
5, 4



Reserved
These bits cannot be modified.
3
DMAMODE
0

DMA Mode
This bit is not supported. The initial value should not
be changed.
2
XMITFRST
0
W
Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
1
RCVRFRST
0
W
Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
0
FIFOE
0
W
FIFO Enable
0: Transmit/receive FIFOs disabled
All bytes of these FIFOs are cleared.
1: Transmit/receive FIFOs enabled
Rev. 2.00 Aug. 20, 2008 Page 516 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.9
Line Control Register (FLCR)
FLCR sets formats of the transmit/receive data.
Bit
Bit Name
Initial Value
R/W Description
7
DLAB
0
R/W Divisor Latch Address
FDLL and FDLH are placed at the same addresses as
the FRBR/FTHR and FIER addresses. This bit selects
which register is to be accessed.
0: FRBR/FTHR and FIER access enabled
1: FDLL and FDLH access enabled
6
BREAK
0
R/W Break Control
Generates a break by driving the serial output signal
TxDF low.
The break state is released by clearing this bit.
0: Break released
1: Break generated
5
STICK
PARITY
0
R
Stick Parity
This bit is not supported in this LSI.
This bit is always read as 0. The initial value should
not be changed.
4
EPS
0
R/W Parity Select
Selects even or odd parity when the PEN bit is 1.
0: Odd parity
1: Even parity
3
PEN
0
R/W Parity Enable
Selects whether to add a parity bit for data
transmission and whether to perform a parity check for
data reception.
0: No parity bit added/parity check disabled
1: Parity bit added/parity check enabled
Rev. 2.00 Aug. 20, 2008 Page 517 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value
R/W
Description
2
STOP
0
R/W
Stop Bit
Specifies the stop bit length for data transmission. For
data reception, only the first stop bit is checked
regardless of the setting.
0: 1 stop bit
1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data
length: 6 to 8 bits)
1
CLS1
0
R/W
Character Length Select 0, 1
0
CLS0
0
R/W
These bits specify transmit/receive character data
length.
00: Data length is 5 bits
01: Data length is 6 bits
10: Data length is 7 bits
11: Data length is 8 bits
15.3.10 Modem Control Register (FMCR)
FMCR controls output signals.
Bit
Bit Name
Initial Value
R/W
Description
7 to 5

All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
4
LOOP
BACK
0
R/W
Loopback Test
The transmit data output is internally connected to the
receive data input, and the transmit data output pin
(RxDF) becomes 1. The receive data input pin is
disconnected from external sources. The four modem
control input pins (DSR, CTS, RI, and DCD) are
disconnected from external sources, and the pins are
internally connected to the four modem control output
signals (DTR, RTS, OUT1, and OUT2), respectively.
The transmit data is received immediately in loopback
mode. Enabling/disabling of interrupts is set by the
OUT2LOOP bit in SCIFCR and FIER.
0: Loopback function disabled
1: Loopback function enabled
Rev. 2.00 Aug. 20, 2008 Page 518 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value
R/W
Description
3
OUT2
0
R/W
OUT2
•
Normal operation
Enables or disables the SCIF interrupt.
0: Interrupt disabled
1: Interrupt enabled
•
Loopback test
Internally connected to the DCD input pin.
2
OUT1
0
R/W
OUT1
•
Normal operation
No effect on operation
•
Loopback test
Internally connected to the RI input pin.
1
RTS
0
R/W
Request to Send
Controls the RTS output.
0: RTS output is high level
1: RTS output is low level
0
DTR
0
R/W
Data Terminal Ready
Controls the DTR output.
0: DTR output is high level
1: DTR output is low level
Rev. 2.00 Aug. 20, 2008 Page 519 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.11 Line Status Register (FLSR)
FLSR is a read-only register that indicates the status information of data transmission.
Bit
Bit Name
Initial Value R/W
Description
7
RXFIFOERR
0
Receive FIFO Error
R
Indicates that at least one data error (parity error,
framing error, or break interrupt) has occurred when
the FIFO is enabled.
0: No receive FIFO error
[Clearing condition]
When FRBR is read or FLSR is read while there is
no remaining data that could cause an error after an
FIFO clear.
1: A receive FIFO error
[Setting condition]
When at least one data error (parity error, framing
error, or break interrupt) has occurred in the FIFO
6
TEMT
1
R
Transmitter Empty
Indicates whether transmit data remains.
•
When the FIFO is disabled
0: Transmit data remains in FTHR or FTSR.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in FTHR and FTSR.
[Setting condition]
When no transmit data remains in FTHR and FTSR.
•
When the FIFO is enabled
0: Transmit data remains in the transmit FIFO or
FTSR.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in the transmit FIFO and
FTSR.
[Setting condition]
When no transmit data remains in the transmit FIFO
and FTSR
Rev. 2.00 Aug. 20, 2008 Page 520 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
5
THRE
1
FTHR Empty
R
Indicates that FTHR is ready to accept new data for
transmission.
•
When the FIFO is enabled
0: Transmit data of one or more bytes remains in the
transmit FIFO.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in the transmit FIFO.
[Setting condition]
When the transmit FIFO becomes empty
•
When the FIFO is disabled
0: Transmit data remains in FTHR.
[Clearing condition]
Transmit data is written to FTHR
1: No transmit data in FTHR
[Setting condition]
When data transfer from FTHR to FTSR is
completed
4
BI
0
R
Break Interrupt
Indicates detection of the receive data break signal.
When the FIFO is enabled, a break interrupt occurs
in any receive data in the FIFO, and this bit is set
when the receive data is in the first FIFO buffer.
Reception of the next data starts after the input
receive data becomes mark and a valid start bit is
received.
0: Break signal not detected
[Clearing condition]
FLSR read
1: Break signal detected
[Setting condition]
When input receive data stays at space (low level)
for a reception time exceeding the length of one
frame
Rev. 2.00 Aug. 20, 2008 Page 521 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
3
FE
0
Framing Error
R
Indicates that the stop bit of the receive data is
invalid. When the FIFO is enabled, this error occurs
in any receive data in the FIFO, and this bit is set
when the receive data is in the first FIFO buffer. The
UART attempts resynchronization after a framing
error occurs. The UART, which assumes that the
framing error is due to the next start bit, samples the
start bit and treats it as a start bit.
0: No framing error
[Clearing condition]
FLSR read
1: A framing error
[Setting condition]
Invalid stop bit in the receive data
2
PE
0
R
Parity Error
This bit indicates a parity error in the receive data
when the PEN bit in FLCR is 1. When the FIFO is
enabled, this error occurs in any receive data in the
FIFO, and this bit is set when the receive data is in
the first FIFO buffer.
0: No parity error
[Clearing condition]
FLSR read
If this bit is set during an overrun error, read FLSR
twice.
1: A parity error
[Setting condition]
Detection of parity error in receive data
Rev. 2.00 Aug. 20, 2008 Page 522 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
1
OE
0
Overrun Error
R
Indicates occurrence of an overrun error.
•
When the FIFO is disabled
When reception of the next data has been completed
without the receive data in FRBR having been read,
an overrun error occurs and the previous data is lost.
•
When the FIFO is enabled
When the FIFO is full and reception of the next data
has been completed, an overrun error occurs. The
FIFO data is retained, but the last received data is
lost.
0: No overrun error
[Clearing condition]
FLSR read
1: An overrun error
[Setting condition]
Occurrence of an overrun error
0
DR
0
R
Data Ready
Indicates that receive data is stored in FRBR or the
FIFO.
0: No receive data
[Clearing condition]
FRBR is read or all of the FIFO data is read.
1: Receive data remains.
[Setting condition]
Reception of data
Rev. 2.00 Aug. 20, 2008 Page 523 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.12 Modem Status Register (FMSR)
FMSR is a read-only register that indicates the status of or a change in the modem control pins.
Bit
Bit Name
Initial Value R/W
Description
7
DCD
0
R
Data Carrier Detect
6
RI
0
R
Indicates the inverted state of the DCD input pin.
Ring Indicator
Indicates the inverted state of the RI input pin.
5
DSR
0
R
Data Set Ready
Indicates the inverted state of the DSR input pin.
4
CTS
0
R
Clear to Send
Indicates the inverted state of the CTS input pin.
3
DDCD
0
R
Delta Data Carrier Indicator
Indicates a change in the DCD input signal after the
DDCD bit is read.
0: No change in the DCD input signal after FMSR
read
[Clearing condition]
FMSR read
1: A change in the DCD input signal after FMSR read
[Setting condition]
A change in the DCD input signal
2
TERI
0
R
Trailing Edge Ring Indicator
Indicates a rise in the RI input signal after the TERI
bit is read.
0: No change in the RI input signal after FMSR read
[Clearing condition]
FMSR read
1: A rise in the RI input signal after FMSR read
[Setting condition]
A rise in the RI input pin
Rev. 2.00 Aug. 20, 2008 Page 524 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
1
DDSR
0
Delta Data Set Ready Indicator
R
Indicates a change in the DSR input signal after the
DDSR bit is read.
0: No change in the DSR input signal after FMSR
read
[Clearing condition]
FMSR read
1: A change in the DSR input signal after FMSR
read
[Setting condition]
A change in the DSR input signal
0
DCTS
0
R
Delta Clear to Send Indicator
Indicates a change in the CTS input signal after the
DCTS bit is read.
0: No change in the CTS input signal after FMSR
read
[Clearing condition]
FMSR read
1: A change in the CTS input signal after FMSR read
[Setting condition]
A change in the CTS input signal
15.3.13 Scratch Pad Register (FSCR)
FSCR is not used for SCIF control, but is used to temporarily store program data.
Bit
Bit Name
Initial Value R/W
Description
7 to 0
Bit 7 to bit 0
All 0
Temporarily stores program data.
R/W
Rev. 2.00 Aug. 20, 2008 Page 525 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.14 SCIF Control Register (SCIFCR)
SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit
Bit Name
Initial Value R/W
Description
7
SCIFOE1
0
R/W
6
SCIFOE0
0
R/W
These bits enable or disable PORT output of the
SCIF. The PORT function differs according to the
combination with the SCIF bit in HICR5 of the LPC.
For details, see table 15.4.
5

0
R/W
Reserved
Do not change the initial value.
4
OUT2LOOP
0
R/W
Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
3
CKSEL1
0
R/W
2
CKSEL0
0
R/W
These bits select the clock (SCLK) to be input to the
baud rate generator.
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
1
SCIFRST
0
R/W
Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
0
REGRST
0
R/W
Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset
Rev. 2.00 Aug. 20, 2008 Page 526 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.4 SCIF Output Setting
Bit SCIFE in
HICR5
0
SCIFOE1
0
1
1
0
1
SCIFOE0
0
1
0
1
0
1
0
1
P65 pin
PORT
PORT
RTS
PORT
RTS
PORT
RTS
PORT
P27 pin
PORT
PORT
DTR
PORT
DTR
PORT
DTR
PORT
P50 pin
PORT
PORT
TxDF
TxDF
TxDF
TxDF
TxDF
TxDF
Note: P51, P24 to P26, and P64 are input to the SCIF even when the outputs on the P27, P50,
and P65 pins are set to PORT.
Rev. 2.00 Aug. 20, 2008 Page 527 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.4
Operation
15.4.1
Baud Rate
The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH,
FDLL, and the CKSEL bit in SCIFCR. Table 15.5 shows an example of baud rate settings.
Table 15.5 Example of Baud Rate Settings
CKSEL1,
CKSEL0
Baud rate
00
01
LCLK
System Clock
(33 MHz) divided by 18
(34 MHz) divided by 11
FDLH, FDLL
(Hex)
Error (%)
FDLH, FDLL
(Hex)
Error (%)
50
0900
-0.54%
H'0F18
-0.01%
75
0600
-0.54%
H'0A10
-0.01%
110
0417
-0.51%
H'06DC
0.01%
300
0180
-0.54%
H'0284
-0.01%
600
00C0
-0.54%
H'0142
-0.01%
1200
0060
-0.54%
H'00A1
-0.01%
1800
0040
-0.54%
H'006B
0.30%
2400
0030
-0.54%
H'0050
0.62%
4800
0018
-0.54%
H'0028
0.62%
9600
000C
-0.54%
H'0014
0.62%
14400
0008
-0.54%
H'000D

19200
0006
-0.54%
H'000A
0.62%
38400
0003
-0.54%
H'0005
0.62%
57600
0002
-0.54%
H'0003

115200
0001
-0.54%
H'0002

Rev. 2.00 Aug. 20, 2008 Page 528 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.2
Operation in Asynchronous Communication
Figure 15.2 illustrates the typical format for asynchronous serial communication. One frame
consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least
significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the
transmission line is usually held high in the mark state (high level). The SCIF monitors the
transmission line, and when it detects the space state (low level), recognizes a start bit and starts
serial communication. Inside the SCIF, the transmitter and receiver are independent units,
enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage
FIFO buffered structure so that data can be read or written during transmission or reception,
enabling continuous data transmission and reception.
Idle state (mark state)
1
Serial data
1
0
Start
bit
1 bit
D0
D1
D2
D3
D4
D5
Transmit/receive data
5, 6, 7, or 8 bits
D6
D7
0/1
1
1
Parity
bit
Stop bit
1 bit
or
none
1, 1.5,
or
2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Serial Transmission/Reception
(Example with 8-Bit Data, Parity and 2 Stop Bits)
Rev. 2.00 Aug. 20, 2008 Page 529 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.3
(1)
Initialization of the SCIF
Initialization of the SCIF
Use an example of the flowchart in figure 15.3 to initialize the SCIF before transmitting or
receiving data.
[1] Select an input clock with the CKSEL1 and
CKSEL0 bits in SCIFCR. Set the SCIF input/
output pins with the SCIFOE1 and SCIFOE0
bits in SCIFCR.
Start initialization
Clear module stop
Set SCIFCR
[1]
[2] Set the DLAB bit in FLCR to 1 to enable
access to FDLL and FDLH.
Set DLAB bit in FLCR to 1
[2]
[3] The initial value of FDLL and FDLH is 0.
Set a value within the range from 1 to 65535.
Set FDLH and FDLL
[3]
[4] Clear the DLAB bit in FLCR to 0 to disable
access to FDLL and FDLH.
Clear DLAB bit in FLCR to 0
[4]
Set data transfer format in FLCR
[5]
[5] Select parity with the EPS and PEN bits in
FLCR, and set the stop bit with the STOP bit
in FLCR. Then, set the data length with the
CLS1 and CLS0 bits in FLCR.
FIFOs used?
Yes
No
Set FIFOE bit in FFCR to 1
[6]
Set receive FIFO trigger level in FFCR
[7]
Set XMITFRST and RCVRFRST bits
in FFCR to 1 to reset FIFOs
[8]
[6] When FIFOs are used, set the FIFOE bit in
FFCR to 1.
Set interrupt enable bits in FIER
End of Initialization
[9]
[7] Set the receive FIFO trigger level with the
RCVRTRIG1 and RCVRTRIG0 bits in FFCR.
[8] Set the XMITFRST and RCVRFRST bits in
FFCR to 1 to reset the FIFOs.
[9] Enable or disable an interrupt with the
EDSSI, ELSI, ETBEI, and ERBFI bits in
FIER and the OUT2 bit in FMCR.
Figure 15.3 Example of Initialization Flowchart
Rev. 2.00 Aug. 20, 2008 Page 530 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(2)
Serial Data Transmission
Figure 15.4 shows an example of the data transmission flowchart.
Initialization
Start transmission
[1]
Read THRE flag in FLSR
THRE = 1?
[1] Confirm that the THRE flag in FLSR is 1, and write transmit
data to FTHR. When FIFOs are used, write 1-byte to 16-byte
transmit data. When the OUT2 bit in FMCR and the ETBEI bit
in FIER are set to 1, an FTHR empty interrupt occurs. When
data is written to FTHR, it is transferred automatically to FTSR.
The data is then transmitted from the TxDF pin in the order of
the start bit, transmit data, parity bit, and stop bit.
[2] Read the TEMT flag in FLSR, and confirm that TEMT is set to
1 to ensure that all transmit data has been transmitted.
No
[3] To output a break at the end of serial transmission, set the
BREAK bit in FLCR to 1. After completion of the break time,
clear the BREAK bit in FLCR to 0 to clear the break.
Yes
Write transmit data to FTHR
No
All data written
Yes
[2]
Read TEMT flag in FLSR
TEMT = 1
No
Yes
Break output
No
[3]
Yes
Set BREAK bit in FLCR to 1
Break time completed
Yes
Clear BREAK bit in FLCR to 0
(End of transmission or transmission standby)
Figure 15.4 Example of Data Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 531 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(3)
Serial Data Reception
Figure 15.5 shows an example of the data reception flowchart.
[1]
Initialization
Confirm that the DR flag in FLSR is 1 to ensure that
receive data is in the buffer. When the OUT2 bit in
FMCR and the ERBFI bit in FIER are set to 1, a
receive data ready interrupt occurs.
Start reception
[2]
Read DR flag in FLSR
Read the RXFIFOERR, BI, FE, PE, and OE flags in
FLSR to ensure that no error has occurred. If an
[1]
error has occurred, perform error processing. When
the OUT2 bit in FMCR and the ELSI bit in FIER are
set to 1, a receive line status interrupt occurs.
No
DR = 1
[3]
Read the receive data in FRBR.
[4]
Check the DR flag in FLSR. When the DR flag is
Yes
Read RXFIFOERR, BI, PE and OE
[2]
flag in FLSR
cleared to 0 and all data has been read, data reception
is complete.
RXFIFOERR = 1,
BI = 1, FE = 1,
PE = 1, or OE = 1
No
Yes
Error processing
Read FRBR
[3]
Read DR flag in FLSR
[4]
No
DR = 0
Yes
No
All data read
Yes
(End of reception or reception standby)
Figure 15.5 Example of Data Reception Flowchart
Rev. 2.00 Aug. 20, 2008 Page 532 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.4
Data Transmission/Reception with Flow Control
The following shows examples of data transmission/reception for flow control using CTS and
RTS.
(1)
Initialization
Figure 15.6 shows an example of the initialization flowchart.
Start initialization
[1] Select an input clock with the CKSEL1 and CKSEL0
bits in SCIFCR. Set the SCIF input/output pins with
the SCIFOE1 and SCIFOE0 bits in SCIFCR.
Clear module stop
Set SCIFCR
[1]
[2] Set the DLAB bit in FLCR to 1 to enable access to
FDLL and FDLH.
Set DLAB bit in FLCR to 1
[2]
[3] The initial value of FDLL and FDLH is 0. Set a value
within the range from 1 to 65535.
Set FDLH and FDLL
[3]
[4] Clear the DLAB bit in FLCR to 0 to disable access to
FDLL and FDLH.
Clear DLAB bit in FLCR to 0
[4]
Set data transfer format in FLCR
[5]
Set FIFO with FFCR
[6]
Set interrupt enable bits in FIER
[7]
[7] Set the EDSSI and ERBFI bits in FIER to 1 to enable a
modem status interrupt and receive data ready interrupt.
Set RTS bit in FMCR to 1
[8]
[8] Set the RTS bit in FMCR to 1.
[5] Select parity with the EPS and PEN bits in FLCR, and
set the stop bit with the STOP bit in FLCR. Then, set
the data length with the CLS1 and CLS0 bits in FLCR.
Set the FIFOE bit in FFCR to 1 to enable the FIFO.
[6] Set the receive FIFO trigger level with the RCVRTRIG1
and RCVRTRIG0 bits in FFCR. Select the best trigger
level to prevent an overflow of the receive FIFO.
(Transmission/reception standby flow)
Figure 15.6 Example of Initialization Flowchart
Rev. 2.00 Aug. 20, 2008 Page 533 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(2)
Data Transmission/Reception Standby
Figure 15.7 shows an example of the data transmission/reception standby flowchart.
[1] When a receive data ready interrupt
occurs, go to the reception flow.
Initialization
Receive data
ready interrupt?
Yes
[2] When transmit data exists, go to the
transmission flow.
[1]
(Reception flow)
No
Yes
Transmit data exists?
[2]
No
(Transmission flow)
Figure 15.7 Example of Data Transmission/Reception Standby Flowchart
Rev. 2.00 Aug. 20, 2008 Page 534 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(3)
Data Transmission
Figure 15.8 shows an example of the data transmission flowchart.
[1] Confirm that the CTS flag in FMSR is 1.
Transmission/reception standby
[2] Confirm that the THRE flag in FLSR is 1 to
ensure that the transmit FIFO is empty.
[1]
Read CTS flag in FMSR
CTS = 1
[3] Write up to 16 bytes of transmit data in the
transmit FIFO. If the transmit data is 17 bytes
or more, return to step [2] to write transmit
data in the transmit FIFO again.
No
[4] When all of the data has been written, go
to the transmission/reception standby flow.
Yes
Read THRE flag in FLSR
[2]
THRE = 1
No
Yes
i←0
Write transmit data to transmit FIFO
[3]
i←i+1
Yes
All data written
No
Yes
No
i < 16?
[4]
(End of transmission or transmission standby)
Figure 15.8 Example of Data Transmission Flowchart
Rev. 2.00 Aug. 20, 2008 Page 535 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(4)
Suspension of Data Transmission
Figure 15.9 shows an example of the data transmission suspension flowchart.
Modem status change interrupt
[1]
Read DCTS flag in FMSR
[1] Read the DCTS flag in FMSR in the modem
status change interrupt processing routine.
If the DCTS flag is set to 1, the transmission
suspension processing starts.
[2] Suspend data write to the transmit FIFO.
DCTS = 1
Yes
No
[3] Set the XMITFRST bit in FFCR to 1.
(Other processing)
Suspend data write to transmit FIFO
[2]
Set XMITFRST bit in FFCR to 1
[3]
Prepare for retransmission
[4]
[4] Prepare for retransmission of data and go to
the transmission flow.
(Transmission flow)
Figure 15.9 Example of Data Transmission Suspension Flowchart
Rev. 2.00 Aug. 20, 2008 Page 536 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(5)
Data Reception
Figure 15.10 shows an example of the data reception flowchart.
[1] When data is received, a receive data ready
interrupt occurs. Go to the data reception flow
by using this interrupt trigger.
Receive data ready interrupt
Read FLSR
BI = 1, FE = 1,
PE = 1, or OE = 1
[1]
Yes
No
Error processing
Read receive FIFO
[2]
Read FLSR
[3]
DR = 0
[4]
[2] Confirm that the BI, FE, PE, and OE flags in
FLSR are all cleared. If any one of these flags
is set to 1, perform error processing.
[3] Read the receive FIFO.
[4] Check the DR flag in FLSR. When the DR flag
is cleared and all of the data has been read, data
reception is complete.
(Transmission/reception standby flow)
Figure 15.10 Example of Data Reception Flowchart
Rev. 2.00 Aug. 20, 2008 Page 537 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
(6)
Suspension of Data Reception
Figure 15.11 shows an example of the data reception suspension flowchart.
Receive FIFO trigger level interrupt
[1]
Clear RTS bit in FMCR to 0
[2]
[1] When data is received at a trigger level higher than
the receive FIFO trigger level specified in the
initialization flow, a receive FIFO trigger level interrupt
occurs.
[2] Clear the RTS bit in FMCR to 0.
Read receive FIFO
[3]
Read FLSR
DR = 0
[3] Read the receive FIFO until the DR flag is cleared to 0.
[4] Set the RTS bit in FMCR to 1, and then go to the
transmission/reception standby flow.
No
Yes
Set RTS bit in FMCR to 1
[4]
(Transmission/reception standby flow)
Figure 15.11 Example of Data Reception Suspension Flowchart
Rev. 2.00 Aug. 20, 2008 Page 538 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.4.5
Data Transmission/Reception Through the LPC Interface
As shown in table 15.2, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to
be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the
SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception
shown in figures 15.3 to 15.5 to be made from the LPC interface. Table 15.6 shows the
correspondence between LPC interface I/O address and access to the SCIF registers. For details of
the LPC interface settings, see section 19, LPC interface (LPC).
Table 15.6 Correspondence Between LPC Interface I/O Address and the SCIF Registers
LPC Interface I/O Address
Bits 15 to 3
Bit 2
Bit 1
Bit 0
R/W
Condition
SCIF
Register
SCIFADR (bits 15 to 3)
0
0
0
R
FLCR[7] = 0
FRBR
W
FLCR[7] = 0
FTHR
R/W
FLCR[7] = 1
FDLL
R/W
FLCR[7] = 0
FIER
R/W
FLCR[7] = 1
FDLH
R

FIIR
SCIFADR (bits 15 to 3)
0
0
1
SCIFADR (bits 15 to 3)
0
1
0
W

FFCR
SCIFADR (bits 15 to 3)
0
1
1
R/W

FLCR
SCIFADR (bits 15 to 3)
1
0
0
R/W

FMCR
SCIFADR (bits 15 to 3)
1
0
1
R

FLSR
SCIFADR (bits 15 to 3)
1
1
0
R

FMSR
SCIFADR (bits 15 to 3)
1
1
1
R/W

FSCR
Rev. 2.00 Aug. 20, 2008 Page 539 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.7 shows the register states related to data transmission/reception through the LPC
interface.
Table 15.7 Register States
Register
System Reset
LPC Reset
LPC Shutdown LPC Abort
SCIFADRH
Bits 15 to 8
Initialized
Retained
Retained
Retained
SCIFADRL
Bits 7 to 0
Initialized
Retained
Retained
Retained
HICR5
SCIFE
Initialized
Retained
Retained
Retained
SIRQCR4
Bits 7 to 4
Initialized
Retained
Retained
Retained
SCSIRQ3
Initialized
Retained
Retained
Retained
SCSIRQ2
Initialized
Retained
Retained
Retained
SCSIRQ1
Initialized
Retained
Retained
Retained
SCSIRQ0
Initialized
Retained
Retained
Retained
Rev. 2.00 Aug. 20, 2008 Page 540 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
15.5
Interrupt Sources
Table 15.8 lists the interrupt sources. A common interrupt vector is assigned to each interrupt
source.
When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU.
The SERIRQ signal of the LPC interface transmits an interrupt request to the host.
Table 15.8 Interrupt Sources
Interrupt Name
Interrupt Source
Priority
Receive line status
Overrun error, parity error, framing error, break interrupt
Receive data ready
Acceptance of receive data, FIFO trigger level
Character timeout
(when FIFO is enabled)
No data is input to or output from the receive FIFO for the 4character time period while one or more characters remain in
the receive FIFO.
FTHR empty
FTHR empty
Modem status
CTS, DSR, RI, DCD
High
Low
Table 15.9 shows the interrupt source, vector address, and interrupt priority.
Table 15.9 Interrupt Source, Vector Address, and Interrupt Priority
Interrupt
Origin of Interrupt Source
Interrupt Name
Vector
Number
Vector
Address
ICR
SCIF
SCIF (SCIF interrupt)
82
H'000148
ICRC7
15.6
Usage Note
15.6.1
Power-Down Mode When LCLK is Selected for SCLK
To switch to software standby mode when LCLK divided by 18 has been selected for SCLK, use
the shutdown function of the LPC interface to stop LCLK.
Rev. 2.00 Aug. 20, 2008 Page 541 of 1198
REJ09B0403-0200
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Aug. 20, 2008 Page 542 of 1198
REJ09B0403-0200
Section 16 Serial Pin Multiplexed Modes
Section 16 Serial Pin Multiplexed Modes
Three serial communication I/F modules (SCIF, SCI_1 and SCI_3) can be configured for five
types of COM port assignments and internal connections (serial pin multiplexed modes) in this
LSI. Two registers are provided for controlling the serial pin multiplexed modes: serial
multiplexed mode register 0 (SMR0) and serial multiplexed mode register 1 (SMR1).
16.1
Features
Internal connection of serial modules to COM ports can be configured to make a software bridge
for IPMI applications.
• Five serial pin multiplexed modes
 Mode 0: Each COM port is used for its respective serial communication module: COM1
for SCIF, COM2 for SCI_1 and COM3 for SCI_3 (default mode)
 Mode 1: COM1 snoop mode with use of SCI_1 and internal registers
 Mode 2: SCIF-and-SCI_1 bridge mode in which internal registers provide software flow
control.
 Mode 3: COM port switched mode in which COM1 is connected to SCI_1 and COM2 is
connected to SCIF. Internal registers provide flow control for SCI_1.
 Mode 4: SCIF-and-SCI_3 bridge mode providing the same functionality as mode 3.
Please refer to section 13, Serial Communication Interface (SCI) for details on SCI_1 and SCI_3,
and section 15, Serial Communication Interface with FIFO (SCIF), for details on SCIF.
Rev. 2.00 Aug. 20, 2008 Page 543 of 1198
REJ09B0403-0200
Section 16 Multiplex Mode
16.2
Input/Output Pins
Table 16.1 lists input/output pins involved in serial pin multiplexed modes.
Table 16.1 Pin Configuration
Module
Symbol
I/O
Function
Port Pin
SCIF
TxDF
Output
Transmit data
P50
RxDF
Input
Receive data
P51
RI
Input
Ring Indicator detect
P25
DCD
Input
Data carrier detect
P24
DSR
Input
Data set ready
P26
DTR
Output
Data terminal ready
P27
CTS
Input
Transmission permission
P64
RTS
Output
Transmission request
P65
Rev. 2.00 Aug. 20, 2008 Page 544 of 1198
REJ09B0403-0200
Section 16 Serial Pin Multiplexed Modes
16.3
Register Descriptions
Two registers are provided for serial pin multiplexed modes. Serial multiplexed mode register 0
(SMR0) enables or disables the serial pin multiplexing function, selects a serial pin multiplexed
mode out of 5 modes, and provides bits for port monitoring. Serial multiplexed mode register 1
(SMR1) provides bits for port monitoring and controls outputs on the relevant port pins.
• Serial multiplexed mode register 0 (SMR0)
• Serial multiplexed mode register 1 (SMR1)
16.3.1
Serial Multiplexed Mode Register 0 (SMR0)
Bit
Bit Name
Initial
Value
R/W
Description
7
DCD1

R
Monitors the state of the DCD line in modes 1, 3, and
4.
6
RI1

R
Monitors the state of the RI line in modes 1, 3, and 4.
5
DSR1

R
Monitors the state of the DSR line in modes 1, 3, and
4.
4
SME
0
R/W
Serial Pin Multiplex Enable
0: Pin multiplexing disabled
1: Pin multiplexing enabled
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
SM2
0
R/W
Serial Pin Multiplexed Mode Select
1
SM1
0
R/W
0
SM0
0
R/W
These bits select a serial pin multiplexed mode. This
selection is only enabled when SME bit is 1.
000: Serial multiplexed mode 0
001: Serial multiplexed mode 1
010: Serial multiplexed mode 2
011: Serial multiplexed mode 3
100: Serial multiplexed mode 4
101: Reserved (Do not modify)
110: Reserved (Do not modify)
111: Reserved (Do not modify)
Rev. 2.00 Aug. 20, 2008 Page 545 of 1198
REJ09B0403-0200
Section 16 Multiplex Mode
16.3.2
Serial Multiplexed Mode Register 1 (SMR1)
SMR1 is a register that monitors the port and controls the port output. In mode 2, this register
monitors the status of the RTS pin of SCIF.
Bit
Bit Name
Initial
Value
R/W
Description
7
CTS1

R
Monitors the state of the CTS pin of COM1 in mode 1.
6
DTR1
1
R/W
Controls the output on the DTR pin of COM1 in modes 3
and 4.
Monitors the state of the RTS pin of SCIF in mode 2.
0: 0 is output
1: 1 is output
5
RTS1
1
R/W
Controls the output on the RTS pin of COM1.
Controls the input on the CTS pin of SCIF in mode 2.
0: 0 is output
1: 1 is output
4
CTS3

R
Monitors the state of the RTS pin input of SCIF in mode
4.
3


R
Reserved
2
RTS3
1
R/W
Controls the output on the CTS pin of SCIF.
0: 0 is output
1: 1 is output
1,0


R/W
Rev. 2.00 Aug. 20, 2008 Page 546 of 1198
REJ09B0403-0200
Reserved
Section 16 Serial Pin Multiplexed Modes
16.4
Operation of Serial Pin Multiplexed Modes
16.4.1
Serial Pin Multiplexed Mode 0
(Default; SMR0 Register [bits SM2, SM1, SM0] = [0 0 0])
This mode is the default configuration and each COM port is used for its respective serial
communication module: COM1 works with SCIF, COM2 with SCI_1, and COM3 with SCI_3.
DCD, RI, DSR, DTR, CTS, RTS, RxDF, and TxDF of SCIF are connected to the corresponding
pins of COM1. Tx/Rx of COM1 are tied across to RxDF/TxDF (cross connection).
RxD1 and TxD1 of SCI_1 are cross-connected to COM2. RxD3 and TxD3 of SCI_3 are crossconnected to COM3.
Figure 16.1 illustrates the pin connection in serial pin multiplexed mode 0.
SCI_1
SCIF
Tx
P87
TxD3
P86
Rx
COM3
RxD3
TxD1
P52
Rx
RxD1
P53
P24
P25
P26
P27
P64
P65
P51
P50
DCD
RI
DSR
DTR
CTS
RTS
RxDF
TxDF
Tx
COM2
DCD
RI
DSR
DTR
CTS
RTS
Rx
Tx
COM1
SCI_3
BMC (H8S)
Figure 16.1 Serial Pin Multiplexed Mode 0
Rev. 2.00 Aug. 20, 2008 Page 547 of 1198
REJ09B0403-0200
Section 16 Multiplex Mode
16.4.2
Serial Pin Multiplexed Mode 1
(SMR0 Register [bits SM2, SM1, SM0] = [0 0 1])
This mode is "COM1 snoop mode" with use of SCI_1 and internal registers. DCD, RI, DSR, DTR,
CTS, RTS, RxDF and TxDF of SCIF are connected to COM1. RxD1 of SCI_1 is connected to
RxDF of SCIF internally and TxD1 of SCI_1 is unused.
So, COM2 is not available (N/A) and Rx of COM2 is fixed at 1. RxD3 and TxD3 of SCI_3 are
cross-connected to COM3.
The pin states of DCD, RI, and DSR of COM1 are reflected in bits DCD1, RI1, and DSR1 of the
SMR0 register. The pin state of CTS of COM1 is reflected in bit CTS1 of the SMR1 register.
Figure 16.2 illustrates the pin connection in serial pin multiplexed mode 1.
SCI_1
SCIF
BMC (H8S)
Figure 16.2 Serial Pin Multiplexed Mode 1
Rev. 2.00 Aug. 20, 2008 Page 548 of 1198
REJ09B0403-0200
Tx
TxD3
P87
P86
Rx
COM3
RxD3
Tx
P52
P53
Rx
COM2
TxD1
DCD
RI
DSR
DTR
CTS
RTS
RxDF
TxDF
SMR1
CTS1
DTR1
RTS1
CTS3
RTS3
RxD1
DCD
RI
DSR
DTR
CTS
RTS
Rx
Tx
COM1
P24
P25
P26
P27
P64
P65
P51
P50
SMR0
DCD1
RI1
DSR1
SCI_3
Section 16 Serial Pin Multiplexed Modes
16.4.3
Serial Pin Multiplexed Mode 2
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 0])
In this mode, SCIF and SCI_1 are internally connected. COM1 is not available (N/A) and
DTR/RTS/Rx of COM1 are fixed at 1. DCD, RI, DSR, DTR, CTS, RTS, RxDF, and TxDF of
SCIF are disconnected from COM1. DCD/RI/DSR of SCIF is fixed at 1, and RxDF/TxDF of SCIF
are cross-connected to TxD1/RxD1 of SCI_1 internally.
COM2 is not available (N/A) and Rx of COM2 is fixed at 1. RxD3 and TxD3 of SCI_3 are
connected to Tx and Rx of COM3.
The value written to bit RTS1 of the SMR1 register is reflected in the CTS input of SCIF. The
state of RTS of SCIF is reflected in bit CTS1 of the SMR1 register.
Figure 16.3 illustrates the pin connection in serial pin multiplexed mode 2.
P87
Rx
P86
P52
P53
SCI_1
SCIF
TxD3
RxD3
TxD1
1 Open
RxD1
1
DCD
RI
DSR
DTR
CTS
RTS
RxDF
TxDF
1
Tx
COM3
SMR1
CTS1
DTR1
RTS1
CTS3
RTS3
P24
P25
P26
P27
P64
P65
P51
P50
SMR0
DCD1
RI1
DSR1
SCI_3
BMC (H8S)
Figure 16.3 Serial Pin Multiplexed Mode 2
Rev. 2.00 Aug. 20, 2008 Page 549 of 1198
REJ09B0403-0200
Section 16 Multiplex Mode
16.4.4
Serial Pin Multiplexed Mode 3
(SMR0 Register [bits SM2, SM1, SM0] = [0 1 1])
This mode enables the use of COM2 by SCIF and COM1 by SCI_1. Since SCI_1 doesn't use any
hardware pins for flow control, emulation is possible using the internal registers.
Tx/Rx of COM1 are connected to RxD1/TxD1 of SCI_1, and other COM1 port signals are
controlled or monitored through bits in the internal registers. RxDF/TxDF of SCIF are connected
to Tx/Rx of COM2 and other SCIF signals are not used. DCD/RI/DSR/CTS of SCIF are fixed at 1.
RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3.
The states of DCD/RI/DSR of COM1 are reflected in bits DCD1/RI1/DSR1 of the SMR0 register,
and CTS of COM1 is reflected in bit CTS1 of the SMR1 register.
The values written to bits DTR1/RTS1 of the SMR1 register are output to DTR/RTS of COM1.
Figure 16.4 illustrates the pin connection in serial pin multiplexed mode 3.
SCI_1
BMC (H8S)
Figure 16.4 Serial Pin Multiplexed Mode 3
Rev. 2.00 Aug. 20, 2008 Page 550 of 1198
Tx
P87
Rx
TxD3
RxD3
TxD1
1 Open 1 Open
SCIF
REJ09B0403-0200
COM3
P86
Tx
P52
Rx
COM2
RxD1
1
DCD
RI
DSR
DTR
CTS
RTS
RxDF
TxDF
1
SMR1
CTS1
DTR1
RTS1
CTS3
RTS3
P53
DCD
RI
DSR
DTR
CTS
RTS
Rx
Tx
COM1
P24
P25
P26
P27
P64
P65
P51
P50
SMR0
DCD1
RI1
DSR1
SCI_3
Section 16 Serial Pin Multiplexed Modes
16.4.5
Serial Pin Multiplexed Mode 4
(SMR0 Register [bits SM2, SM1, SM0] = [1 0 0])
Mode 4 provides the same function as mode 3, but the data lines of SCI_3 and SCIF are crossconnected.
RxD1/TxD1 of SCI_1 are connected to Tx/Rx of COM1, and internal register bits emulate other
signals of COM1. DCD/RI/DSR/CTS of SCIF are fixed at 1. COM2 is not available (N/A) and Rx
for COM2 is fixed at 1. COM3 is not available (N/A) and Rx for COM3 is fixed at 1. RxD3/TxD3
of SCI_3 are cross-connected to TxDF/RxDF of SCIF internally.
The states of DCD/RI/DSR of COM1 are reflected in bits DCD1/RI1/DSR1 of the SMR0 register,
and CTS of COM1 is reflected to CTS1 bit of SMR1 register.
The values written to bits DTR1/RTS1 of the SMR1 register are output to DTR/RTS of COM1.
The value written to bit RTS3 of SMR1 is reflected in CTS of SCIF, and the state of RTS of SCIF
is reflected in bit CTS3 of SMR1, allowing SCI_3 and SCIF to communicate each other with
virtual flow control.
Figure 16.5 illustrates the pin connection in serial pin multiplexed mode 4.
Rx
Tx
P87
P86
Rx
Tx
P52
COM3
SCI_1
SCIF
TxD3
RxD3
1 Open
TxD1
1
COM2
RxD1
1
SMR1
CTS1
DTR1
RTS1
CTS3
RTS3
P53
P24
P25
P26
P27
P64
P65
P51
P50
DCD
RI
DSR
DTR
CTS
RTS
Rx
Tx
COM1
DCD
RI
DSR
DTR
CTS
RTS
RxDF
TxDF
SMR0
DCD1
RI1
DSR1
SCI_3
BMC (H8S)
Figure 16.5 Serial Pin Multiplexed Mode 4
Rev. 2.00 Aug. 20, 2008 Page 551 of 1198
REJ09B0403-0200
Section 16 Multiplex Mode
16.5
Serial Port Pin Configuration
(a)
SME = 1: SCI (SCIF) with serial pin multiplexed mode enabled
(b)
SME = 0: SCI (SCIF) with serial pin multiplexed mode disabled
Rev. 2.00 Aug. 20, 2008 Page 552 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Section 17 Synchronous Serial Communication Unit (SSU)
This LSI has synchronous serial communication unit (SSU) channels. The SSU has master mode
in which this LSI outputs clocks as a master device for synchronous serial communication and
slave mode in which clocks are input from an external device for synchronous serial
communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase. Figure 17.1 is a block diagram of the SSU.
17.1
Features
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of clock sources
φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, or an external clock
• Five interrupt sources
Transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error
• Module stop mode can be set.
Rev. 2.00 Aug. 20, 2008 Page 553 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Module data bus
SSCRH
Bus interface
Figure 17.1 shows a block diagram of the SSU.
Internal data bus
SSTDR 0
SSRDR 0
SSCRL
OEI
SSTDR 1
SSRDR 1
SSMR
CEI
SSTDR 2
SSRDR 2
SSER
RXI
SSTDR 3
SSRDR 3
SSSR
TXI
Control circuit
TEI
Clock
Clock
selector
Shiftin
Shiftout
SSTRSR
φ
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
Selector
SSI
SSO
SCS
SSCK (External clock)
[Legend]
SSCRH:
SSCRL:
SSCR2:
SSMR:
SSER:
SSSR:
SSTDR0 to SSTDR3:
SSRDR0 to SSRDR3:
SSTRSR:
SS control register H
SS control register L
SS control register 2
SS mode register
SS enable register
SS status register
SS transmit data registers 0 to 3
SS receive data registers 0 to 3
SS shift register
Figure 17.1 Block Diagram of SSU
Rev. 2.00 Aug. 20, 2008 Page 554 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.2
Input/Output Pins
Table 17.1 shows the SSU pin configuration.
Table 17.1 Pin Configuration
Pin Name
I/O
Function
SSCK
I/O
SSU clock input/output
SSI
I/O
SSU data input/output
SSO
I/O
SSU data input/output
SCS
I/O
SSU chip select input/output
17.3
Register Descriptions
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS control register 2 (SSCR2)
• SS transmit data register 0 (SSTDR0)
• SS transmit data register 1 (SSTDR1)
• SS transmit data register 2 (SSTDR2)
• SS transmit data register 3 (SSTDR3)
• SS receive data register 0 (SSRDR0)
• SS receive data register 1 (SSRDR1)
• SS receive data register 2 (SSRDR2)
• SS receive data register 3 (SSRDR3)
• SS shift register (SSTRSR)
Rev. 2.00 Aug. 20, 2008 Page 555 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.1
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSS
0
R/W
Master/Slave Device Select
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
6
BIDE
0
R/W
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
17.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
output)
1: Bidirectional mode (one pin is used for data input and
output)
5

0
R/W
Reserved
This bit is always read as 0. The initial value should not
be changed.
Rev. 2.00 Aug. 20, 2008 Page 556 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
4
SOL
0
R/W
Serial Data Output Value Select
The serial data output retains its level of the last bit
after completion of transmission. The output level
before or after transmission can be specified by setting
this bit. When specifying the output level, use the MOV
instruction after clearing the SOLP bit to 0. Since writing
to this bit during data transmission causes malfunctions,
this bit should not be changed.
0: Serial data output is changed to low.
1: Serial data output is changed to high.
3
SOLP
1
R/W
SOL Bit Write Protect
When changing the output level of serial data, set the
SOL bit to 1 or clear the SOL bit to 0 after clearing the
SOLP bit to 0 using the MOV instruction.
0: Output level can be changed by the SOL bit
1: Output level cannot be changed by the SOL bit. This
bit is always read as 1.
2
SCKS
0
R/W
SSCK Pin Select
Selects that the SSCK pin functions as a port or a serial
clock pin. When the SSCK pin is used as a serial clock
pin, this bit must be set to 1.
0: Functions as an I/O port.
1: Functions as a serial clock.
1
CSS1
0
R/W
SCS Pin Select
0
CSS0
0
R/W
Select that the SCS pin functions as a port or SCS input
or output. However, when MSS = 0, the SCS pin
functions as an input pin regardless of the CSS1 and
CSS0 settings.
00: I/O port
01: Function as SCS input
10: Function as SCS automatic input/output (function as
SCS input before and after transfer and output a
low level during transfer)
11: Function as SCS automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
Rev. 2.00 Aug. 20, 2008 Page 557 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.2
SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R/W
Reserved
This bit is always read as 0. The initial value should not
be changed.
6
SSUMS
0
R/W
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
5
SRES
0
R/W
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
4 to 2

All 0
R/W
Reserved
These bits are always read as 0. The initial value
should not be changed.
1
DATS1
0
R/W
Transmit/Receive Data Length Select
0
DATS0
0
R/W
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
Rev. 2.00 Aug. 20, 2008 Page 558 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.3
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
6
CPOS
0
R/W
5
CPHS
0
R/W
4, 3

All 0
R/W
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Reserved
These bits are always read as 0. The initial value
should not be changed.
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
100: φ/32
001: φ/4
101: φ/64
010: φ/8
110: φ/128
011: φ/16
111: φ/256
Rev. 2.00 Aug. 20, 2008 Page 559 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.4
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit
Bit Name
Initial
Value
R/W
Description
7
TE
0
R/W
Transmit Enable
6
RE
0
R/W
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
5, 4

All 0
R/W
Reserved
These bits are always read as 0. The initial value
should not be changed.
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an RXI interrupt request and
an OEI interrupt request are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
Rev. 2.00 Aug. 20, 2008 Page 560 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.5
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

6
ORER
0
R/W
5, 4

All 0
R/W
3
TEND
1
R
Reserved
This bit is always read as 0. The initial value should not
be changed.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The initial value
should not be changed.
Transmit End
[Setting condition]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR
Rev. 2.00 Aug. 20, 2008 Page 561 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
2
TDRE
1
R/W
1
RDRF
0
R/W
0
CE
0
R/W
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. Data reception does not
continue while the CE bit is set to 1. Serial transmission
also does not continue. Reset the SSU internal
sequencer by setting the SRES bit in SSCRL to 1
before resuming transfer after incomplete error.
[Setting condition]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
Rev. 2.00 Aug. 20, 2008 Page 562 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.6
SS Control Register 2 (SSCR2)
SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit
Bit Name
Initial
Value
R/W
Description
7
SDOS
0
R/W
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
CMOS or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, 14.4.3, Relationship between Data Input/Output
Pins and Shift Register.
0: CMOS output
1: NMOS open drain output
6
SSCKOS
0
R/W
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a CMOS or
an NMOS open drain output.
0: CMOS output
1: NMOS open drain output
5
SCSOS
0
R/W
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a CMOS or an
NMOS open drain output.
0: CMOS output
1: NMOS open drain output
4
TENDSTS 0
R/W
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
Rev. 2.00 Aug. 20, 2008 Page 563 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
SCSATS
0
R/W
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc
1: Min. values of tLEAD and tLAG are 3/2 × tSUcyc
2
SSODTS
0
R/W
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
1, 0

All 0
R/W
Reserved
These bits are always read as 0. The initial value
should not be changed.
17.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Rev. 2.00 Aug. 20, 2008 Page 564 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.3.8
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
17.3.9
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to
perform serial data transmission.
In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB
(bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
Rev. 2.00 Aug. 20, 2008 Page 565 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.4
Operation
17.4.1
Transfer Clock
A transfer clock can be selected from eight internal clocks and an external clock. When using this
module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS
bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When
transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output
from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an
input pin.
17.4.2
Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR. Figure 17.2 shows the relationship. When SSUMS = 1, the CPHS
setting is invalid although the CPOS setting is valid.
Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data
is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the
LSB.
(1) When CPHS = 0
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 1
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 17.2 Relationship of Clock Phase, Polarity, and Data
Rev. 2.00 Aug. 20, 2008 Page 566 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.4.3
Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 17.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 17.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 17.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 17.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 17.3 (5) and (6)).
(1) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 1, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSO
(2) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 0, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSI
SSI
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 1, and either TE or RE = 1
SSCK
Shift register
(SSTRSR)
SSO
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 0, and either TE or RE = 1
SSCK
Shift register
(SSTRSR)
SSO
SSI
SSI
(6) When SSUMS = 1 and MSS = 0
(5) When SSUMS = 1 and MSS = 1
SSCK
SSCK
Shift register
(SSTRSR)
SSO
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
Figure 17.3 Relationship between Data Input/Output Pins and the Shift Register
Rev. 2.00 Aug. 20, 2008 Page 567 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.4.4
Communication Modes and Pin Functions
The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the
communication modes and register settings. When a pin is used as an input pin, set the
corresponding bit in the input buffer control register (ICR) to 1. The relationship of
communication modes and input/output pin functions are shown in tables 17.2 to 17.4.
Table 17.2 Communication Modes and Pin States of SSI and SSO Pins
Communication
Mode
SSU communication
mode
Register Setting
SSUMS
BIDE
MSS
TE
RE
SSI
SSO
0
0
0
0
1

Input
1
0
Output

1
Output
Input
0
1
Input

1
0

Output
1
Input
Output
0
1

Input
1
0

Output
0
1

Input
1
0

Output
0
1
Input

1
0

Output
1
Input
Output
0
1
Input

1
0

Output
1
Input
Output
1
SSU (bidirectional)
0
communication mode
1
0
1
Clock synchronous
1
communication mode
0
0
1
[Legend]
: Not used as SSU pin (can be used as I/O port)
Rev. 2.00 Aug. 20, 2008 Page 568 of 1198
REJ09B0403-0200
Pin State
Section 17 Synchronous Serial Communication Unit (SSU)
Table 17.3 Communication Modes and Pin States of SSCK Pin
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
MSS
SCKS
SSCK
0
0
0

1
Input
0

1
Output
0

1
Input
1
Clock synchronous
1
communication mode
0
1
0

1
Output
[Legend]
: Not used as SSU pin (can be used as I/O port)
Table 17.4 Communication Modes and Pin States of SCS Pin
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
MSS
CSS1
CSS0
SCS
0
0
×
×
Input
1
0
0

0
1
Input
1
0
Automatic
input/output
1
1
Output
×
×

Clock synchronous
1
communication mode
×
[Legend]
×: Don't care
: Not used as SSU pin (can be used as I/O port)
Rev. 2.00 Aug. 20, 2008 Page 569 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.4.5
SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1)
Initial Settings in SSU Mode
Figure 17.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Set a bit in ICR to 1
[2]
Specify MSS, BIDE, SOL, SCKS, CSS1,
and CSS0 bits in SSCRH
[1] When the pin is used as an input.
[2] Specify master/slave mode selection, bidirectional mode enable,
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
[3] Selects SSU mode and specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock polarity selection,
clock phase selection, and transfer clock rate selection.
[3]
Clear SSUMS in SSCRH to 0 and
specify bits DATS1 and DATS0
[4]
Specify MLS, CPOS, CPHS, CKS2,
CKS1, and CKS0 bits in SSMR
[5]
Specify TEIE, TIE, RIE,
and CEIE bits in SSER
[5] Enables/disables interrupt request to the CPU.
End
Figure 17.4 Example of Initial Settings in SSU Mode
Rev. 2.00 Aug. 20, 2008 Page 570 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(2)
Data Transmission
Figure 17.5 shows an example of transmission operation, and figure 17.6 shows a flowchart
example of data transmission.
When transmitting data, the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal
is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in
synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the
SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
Rev. 2.00 Aug. 20, 2008 Page 571 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
1 frame
SSCK
SSO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
7
SSTDR0
(LSB first transmission)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SSTDR0
(MSB first transmission)
TDRE
TEND
TXI interrupt
TXI interrupt
generated
Data written to SSTDR0
TEI interrupt
generated
LSI operation
generated
User operation Data written to SSTDR0
TEI interrupt
generated
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
Bit
1
Bit
2
SSO
(MSB first)
Bit
7
Bit
6
Bit
5
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
SSTDR1
Bit
4
Bit
3
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
2
Bit
1
Bit
0
SSTDR0
SSTDR0
Bit
4
Bit
3
SSTDR1
TDRE
TEND
LSI operation
TXI interrupt generated
User operation Data written to SSTDR0 and SSTDR1
TEI interrupt generated
(3) When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2, and SSTDR3 are valid)
with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
SSO
(MSB first)
Bit
7
to
Bit
7
SSTDR3
to
Bit
0
SSTDR0
Bit
0
to
Bit
7
SSTDR2
Bit
7
to
Bit
0
SSTDR1
Bit
0
to
Bit
7
SSTDR1
Bit
7
to
Bit
0
SSTDR2
Bit
0
to
Bit
7
SSTDR0
Bit
7
to
Bit
0
SSTDR3
TDRE
TEND
LSI operation
TXI interrupt generated TEI interrupt generated
User operation Data written to SSTDR0, SSTDR1, SSTDR2, and SSTDR3
Figure 17.5 Example of Transmission Operation (SSU Mode)
Rev. 2.00 Aug. 20, 2008 Page 572 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
[1] Initial setting:
Specify the transmit data format.
Initial setting
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
TE = 1 (transmission enabled)
[2]
Read TDRE in SSSR
TDRE = 1?
No
Yes
Write transmit data to SSTDR
TDRE automatically cleared
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Consecutive data transmission?
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
[4]
One bit time
quantum elapsed?
Yes
No
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 17.6 Flowchart Example of Data Transmission (SSU Mode)
Rev. 2.00 Aug. 20, 2008 Page 573 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(3)
Data Reception
Figure 17.7 shows an example of reception operation, and figure 17.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Rev. 2.00 Aug. 20, 2008 Page 574 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
1 frame
SSCK
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSI
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
SSTDR0 (LSB first transmission)
SSTDR0 (MSB first transmission)
RDRF
RXI interrupt
generated
LSI operation
User operation Dummy-read SSRDR0
RXI interrupt
generated
Read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSI
(LSB first)
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSI
(MSB first)
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSRDR1
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
SSRDR0
SSRDR1
RDRF
LSI operation
User operation
RXI interrupt generated
Dummy-read SSRDR0 and SSRDR1
(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid)
with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
(LSB first)
Bit
0
SSI
(MSB first)
Bit
7
to
Bit Bit
7
0
SSRDR3
to
Bit Bit
7
0
SSRDR2
Bit Bit
0
7
SSRDR0
to
to
Bit
0
SSRDR1
to
Bit
7
SSRDR1
Bit
7
to
Bit
0
Bit
7
SSRDR0
Bit Bit
0
7
SSRDR2
to
to
Bit
0
SSRDR3
RDRF
LSI operation
User operation Dummy-read SSRDR0
RXI interrupt generated
Figure 17.7 Example of Reception Operation (SSU Mode)
Rev. 2.00 Aug. 20, 2008 Page 575 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
RE = 1 (reception started)
[2]
[1]
Initial setting:
Specify the receive data format.
[2]
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
Initial setting
Dummy-read SSRDR
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes
[3]
[4]
To continue single reception:
When continuing single reception, wait for time of tSUcyc
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
[5]
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
[4]
Consecutive data
reception?
Yes
No
Read received data in SSRDR
RDRF automatically cleared
[5]
RE = 0
Read receive data in SSRDR
End reception
[6]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.8 Flowchart Example of Data Reception (SSU Mode)
(4)
Data Transmission/Reception
Figure 17.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Rev. 2.00 Aug. 20, 2008 Page 576 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
Start
[1]
[1] Initial setting:
Specify the transmit/receive data format.
Initial setting
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
Transmission/reception started
(TE = 1, RE = 1)
Read TDRE in SSSR.
[2]
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Read SSSR
[3]
No
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
RDRF = 1?
Yes
ORER = 1?
Yes [4]
No
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Clear TEND in SSSR to 0
Yes [5]
Error processing
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
Rev. 2.00 Aug. 20, 2008 Page 577 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
SCS Pin Control and Conflict Error
17.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The arbitration
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
Data written
to SSTDR
CE
SCS output
(Hi-Z)
Conflict error
detection period
Worst time for
internally clocking SCS
Figure 17.10 Conflict Error Detection Timing (Before Transfer)
φ
SCS
(Hi-Z)
MSS
Internal signal for
transfer enable
Transfer
end
CE
Conflict error detection period
Figure 17.11 Conflict Error Detection Timing (After Transfer End)
Rev. 2.00 Aug. 20, 2008 Page 578 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.4.7
Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Initial Settings in Clock Synchronous Communication Mode
Figure 17.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Set a bit in ICR to 1
[2]
Specify MSS and SCKS in SSCRH
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[3]
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
[4]
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
[5]
Specify TEIE, TIE, RIE,
and CEIE bits in SSER
[5] Enables/disables interrupt request to the CPU.
End
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode
Rev. 2.00 Aug. 20, 2008 Page 579 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(2)
Data Transmission
Figure 17.13 shows an example of transmission operation, and figure 17.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
SSCK
SSO
Bit 0
Bit 1
Bit 7
Bit 0
1 frame
Bit 1
Bit 7
1 frame
TDRE
TEND
LSI operation
User operation
TXI interrupt
generated
Data written
to SSTDR
TXI interrupt
generated
Data written
to SSTDR
Figure 17.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
Rev. 2.00 Aug. 20, 2008 Page 580 of 1198
REJ09B0403-0200
TEI interrupt
generated
Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
[4][1] Initial setting:
Specify the transmit data format.
Initial setting
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
TE = 1 (transmission enabled)
[2]
Read TDRE in SSSR
TDRE = 1?
No
Yes
Write transmit data to SSTDR
TDRE automatically cleared
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Consecutive data transmission?
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
[4]
One bit time
quantum elapsed?
Yes
No
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 17.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)
Rev. 2.00 Aug. 20, 2008 Page 581 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
(3)
Data Reception
Figure 17.15 shows an example of reception operation, and figure 17.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
SSCK
SSO
Bit 0
Bit 7
Bit 0
1 frame
Bit 7
Bit 0
Bit 7
1 frame
RDRF
LSI operation
RXI interrupt
generated
User operation Dummy-read SSRDR
RXI interrupt
generated
Read data from SSRDR
Figure 17.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
Rev. 2.00 Aug. 20, 2008 Page 582 of 1198
REJ09B0403-0200
RXI interrupt
generated
Read data from SSRDR
Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
RE = 1 (reception started)
Initial setting:
Specify the receive data format.
[2]
Start reception:
When setting the RE bit to 1, reception is started.
[3], [5] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
Read SSSR
No
[1]
RDRF = 1?
[4]
Yes
ORER = 1?
Yes [3]
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
Consecutive data reception?
No
Yes
Read received data in SSRDR
RDRF automatically cleared
[4]
RE = 0
Read receive data in SSRDR
End reception
[5]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)
(4)
Data Transmission/Reception
Figure 17.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Rev. 2.00 Aug. 20, 2008 Page 583 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
Start
[1]
[1] Initial setting:
Specify the transmit/receive data format.
Initial setting
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE bit
is automatically cleared to 0 and transmission is started
by writing data to SSTDR.
Transmission/reception started
(TE = 1, RE = 1)
Read TDRE in SSSR.
[2]
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Read SSSR
[3]
No
RDRF = 1?
Yes
ORER = 1?
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
Yes [4]
No
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Clear TEND in SSSR to 0
Yes [5]
Error processing
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)
Rev. 2.00 Aug. 20, 2008 Page 584 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
17.5
Interrupt Requests
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, a transmit data register empty, and a transmit end interrupts can activate the
DTC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 17.5 lists the
interrupt sources.
When an interrupt condition shown in table 17.5 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DTC data transfer.
Table 17.5 Interrupt Sources
Abbreviation Interrupt Source
Symbol
Interrupt Condition
DTC Activation
SSERI
Overrun error
OEI
(RIE = 1) • (ORER = 1)

Conflict error
CEI
(CEIE = 1) • (CE = 1)

SSRXI
Receive data register full
RXI
(RIE = 1) • (RDRF = 1)
Yes
SSTXI
Transmit data register empty
TXI
(TIE = 1) • (TDRE = 1)
Yes
Transmit end
TEI
(TEIE = 1) • (TEND = 1)
Yes
17.6
Usage Note
17.6.1
Setting of Module Stop Mode
The SSU can be enabled/disabled by the module stop control register setting and is disabled by the
initial value. Canceling module stop mode enables to access the SSU registers. For details, see
section 28, Power-Down Modes.
Rev. 2.00 Aug. 20, 2008 Page 585 of 1198
REJ09B0403-0200
Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 2.00 Aug. 20, 2008 Page 586 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
Section 18 I C Bus Interface (IIC)
2
2
This LSI has six-channels of I C bus interface (IIC). The I C bus interface conforms to and
2
provides a subset of the Philips I C bus (inter-IC bus) interface functions. However, the register
2
configuration that controls the I C bus differs partly from the Philips configuration.
18.1
Features
• Selection of addressing format or non-addressing format
 I C bus format: addressing format with acknowledge bit, for master/slave operation
2
 Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master operation only
• Conforms to Philips I C bus interface (I C bus format)
2
2
• Two ways of setting slave address (I C bus format)
2
• Start and stop conditions generated automatically in master mode (I C bus format)
2
• Selection of acknowledge output levels when receiving (I C bus format)
2
• Automatic loading of acknowledge bit when transmitting (I C bus format)
2
• Wait function in master mode (I C bus format)
2
 A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
 The wait can be cleared by clearing the interrupt flag.
• Wait function (I C bus format)
2
 A wait request can be generated by driving the SCL pin low after data transfer.
 The wait request is cleared when the next transfer becomes possible.
• Interrupt sources
 Data transfer end (including when a transition to transmit mode with I C bus format occurs,
when ICDR data is transferred, or during a wait state)
2
 Address match: when any slave address matches or the general call address is received in
2
slave receive mode with I C bus format (including address reception after loss of master
arbitration)
 Arbitration loss
 Start condition detection (in master mode)
 Stop condition detection (in slave mode)
• Selection of 32 internal clocks (in master mode)
• Direct bus drive
Rev. 2.00 Aug. 20, 2008 Page 587 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
 Pins SCL0 to SCL5 and SDA0 to SDA5 (normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
2
Figure 18.1 shows a block diagram of the I C bus interface. Figure 18.2 shows an example of I/O
2
pin connections to external circuits. Since I C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 31, Electrical Characteristics.
ICXR
PS
SCL
Noise
canceler
ICCR
Clock
control
ICMR
Bus state
decision
circuit
SDA
ICSR
Arbitration
decision
circuit
ICDRT
Output data
control
circuit
ICDRS
Internal data bus
φ
ICDRR
Noise
canceler
Address comparator
SAR, SARX
Interrupt
generator
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
ICXR:
SAR:
SARX:
PS:
I2C bus control register
I2C bus mode register
I2C bus status register
I2C bus data register
I2C bus extended control register
Slave address register
Slave address register X
Prescaler
2
Figure 18.1 Block Diagram of I C Bus Interface
Rev. 2.00 Aug. 20, 2008 Page 588 of 1198
REJ09B0403-0200
Interrupt
generator
Section 18 I2C Bus Interface (IIC)
VCC
VDD
VCC
SCL
SCL
SDA
SDA
SCL in
SDA out
(Master)
SCL in
This LSI
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
SCL in
SCL
SDA
SDA in
SCL
SDA
SCL out
(Slave 2)
2
Figure 18.2 I C Bus Interface Connections (Example: This LSI as Master)
Rev. 2.00 Aug. 20, 2008 Page 589 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.2
Input/Output Pins
2
Table 18.1 summarizes the input/output pins used by the I C bus interface.
Table 18.1 Pin Configuration
Channel
Symbol*
Input/Output
Function
0
SCL0
Input/Output
Clock input/output pin of channel IIC_0
SDA0
Input/Output
Data input/output pin of channel IIC_0
SCL1
Input/Output
Clock input/output pin of channel IIC_1
SDA1
Input/Output
Data input/output pin of channel IIC_1
SCL2
Input/Output
Clock input/output pin of channel IIC_2
SDA2
Input/Output
Data input/output pin of channel IIC_2
SCL3
Input/Output
Clock input/output pin of channel IIC_3
SDA3
Input/Output
Data input/output pin of channel IIC_3
SCL4
Input/Output
Clock input/output pin of channel IIC_4
SDA4
Input/Output
Data input/output pin of channel IIC_4
SCL5
Input/Output
Clock input/output pin of channel IIC_5
SDA5
Input/Output
Data input/output pin of channel IIC_5
1
2
3
4
5
Note:
*
In the text, the channel subscript is omitted, and only SCL and SDA are used.
Rev. 2.00 Aug. 20, 2008 Page 590 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3
Register Descriptions
2
The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed.
• I C bus data register (ICDR)
2
• Slave address register (SAR)
• Second slave address register (SARX)
• I C bus mode register (ICMR)
2
• I C bus transfer rate select register (IICX3)
2
• I C bus control register (ICCR)
2
• I C bus status register (ICSR)
2
• I C bus extended control register (ICXR)
2
• I C SMbus control register (ICSMBCR)
2
18.3.1
2
I C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in accordance with changes in the bus state, and they
affect the status of internal flags such as ICDRE and ICDRF.
2
In master transmit mode with the I C bus format, writing transmit data to ICDR should be
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If IIC is in transmit mode (TRS = 1) and the next data is in ICDRT (the ICDRE flag is 0), data is
transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If IIC is in receive mode
(TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
Rev. 2.00 Aug. 20, 2008 Page 591 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
18.3.2
Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. When the LSI is in slave mode
2
with the I C bus format selected, if the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Bit
Bit Name
Initial
Value
R/W
Description
7
SVA6
All 0
R/W
Slave Addresses 6 to 0
6
SVA5
5
SVA4
4
SVA3
3
SVA2
2
SVA1
1
SVA0
0
FS
Set a slave address.
0
R/W
Format Select
Selects the communication format together with the FSX
bit in SARX. Refer to table 18.2.
This bit should be set to 0 when general call address
recognition is performed.
Rev. 2.00 Aug. 20, 2008 Page 592 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.3
Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
2
second slave address. When the LSI is in slave mode with the I C bus format selected, if the FSX
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7
SVAX6
All 0
R/W
Second Slave Addresses 6 to 0
6
SVAX5
5
SVAX4
4
SVAX3
3
SVAX2
2
SVAX1
1
SVAX0
0
FSX
Set the second slave address.
1
R/W
Format Select X
Selects the communication format together with the FS bit
in SAR. Refer to table 18.2.
Rev. 2.00 Aug. 20, 2008 Page 593 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Table 18.2 Transfer Format
SAR
SARX
FS
FSX
Operating Mode
0
0
I C bus format
1
1
0
1
2
•
SAR and SARX slave addresses recognized
•
General call address recognized
2
I C bus format
•
SAR slave address recognized
•
SARX slave address ignored
•
General call address recognized
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
•
General call address ignored
Clocked synchronous serial format
•
SAR and SARX slave addresses ignored
•
General call address ignored
• I C bus format: addressing format with acknowledge bit
2
• Clocked synchronous serial format: non-addressing format without acknowledge bit, for
master mode only
Rev. 2.00 Aug. 20, 2008 Page 594 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.4
2
I C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
2
Set this bit to 0 when the I C bus format is used.
6
WAIT
0
R/W
Wait Insertion Bit
2
This bit is valid only in master mode with the I C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th
clock), the IRIC flag is set to 1 in ICCR, and a wait state
begins (with SCL at the low level). When the IRIC flag
is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
For details, refer to section 18.4.7, IRIC Setting Timing
and SCL Control.
5
CKS2
4
CKS1
These bits are used only in master mode.
3
CKS0
These bits select the required transfer clock rate, together
with bits IICX5 (channel 5), IICX4 (channel 4), and IICX3
(channel 3) in the IICX3 register and bits IICX2 (channel
2), IICX1 (channel 1), and IICX0 (channel 0) in the STCR
register. Refer to table 18.3.
All 0
R/W
Transfer Clock Select
Rev. 2.00 Aug. 20, 2008 Page 595 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
2
BC2
All 0
R/W
Bit Counter
1
BC1
0
BC0
These bits specify the number of bits to be transferred
next. Bit BC2 to BC0 settings should be made during an
interval between transfer frames. If bits BC2 to BC0 are
set to a value other than B'000, the setting should be
made while the SCL line is low.
The bit counter is initialized to B'000 when a start
condition is detected. The value returns to B'000 at the
end of a data transfer.
2
I C Bus Format
Rev. 2.00 Aug. 20, 2008 Page 596 of 1198
REJ09B0403-0200
Clocked Synchronous Serial Mode
B'000: 9 bits
B'000: 8 bits
B'001: 2 bits
B'001: 1 bits
B'010: 3 bits
B'010: 2 bits
B'011: 4 bits
B'011: 3 bits
B'100: 5 bits
B'100: 4 bits
B'101: 6 bits
B'101: 5 bits
B'110: 7 bits
B'110: 6 bits
B'111: 8 bits
B'111: 7 bits
Section 18 I2C Bus Interface (IIC)
18.3.5
2
I C Bus Transfer Rate Select Register (IICX3)
IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channel 3.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
These bits cannot be modified. The read values are
undefined.
3
TCSS
0
R/W
Transfer Rate Clock Source Select
2
This bit selects a clock rate to be applied to the I C bus
transfer rate.
0: φ/2
1: φ/4
2
IICX5
0
R/W
IIC Transfer Rate Select 5, 4, 3
1
IICX4
0
R/W
0
IICX3
0
R/W
These bits are used to control IIC_5 to IIC_3 operation.
These bits select the transfer rate in master mode,
together with the CKS2 to CKS0 bits in ICMR. For the
transfer rate, see table 18.3.
Rev. 2.00 Aug. 20, 2008 Page 597 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
Table 18.3 I C bus Transfer Rate (1)
• TCSS = 0
STCR/
ICMR
IICX3
Bit 5
Bit 4
Bit 3
IICXn
CKS2
CKS1
CKS0
Clock
φ = 20 MHz
φ = 25 MHz
φ = 34 MHz
0
0
0
0
φ/28
714.3 kHz*
892.9 kHz*
1214.3 kHz*
1
φ/40
500.0 kHz*
625.0 kHz*
850.0 kHz*
0
φ/48
416.7 kHz*
520.8 kHz*
708.3 kHz*
1
φ/64
312.5 kHz
390.6 kHz
531.3 kHz*
0
φ/80
250.0 kHz
312.5 kHz
425.0 kHz*
1
φ/100
200.0 kHz
250.0 kHz
340.0 kHz
0
φ/112
178.6 kHz
223.2 kHz
303.6 kHz
1
φ/128
156.3 kHz
195.3 kHz
265.6 kHz
0
φ/56
357.1 kHz
446.4 kHz*
607.1 kHz*
1
φ/80
250.0 kHz
312.5 kHz
425.0 kHz*
0
φ/96
208.3 kHz
260.4 kHz
354.2 kHz
1
φ/128
156.3 kHz
195.3 kHz
265.6 kHz
0
φ/160
125.0 kHz
156.3 kHz
212.5 kHz
1
φ/200
100.0 kHz
125.0 kHz
170.0 kHz
0
φ/224
89.3 kHz
111.6 kHz
151.8 kHz
1
φ/256
78.1 kHz
97.7 kHz
132.8 kHz
1
1
0
1
1
0
0
1
1
0
1
Note:
*
Transfer Rate
2
The correct operation cannot be guaranteed since the value is outside the I C bus
interface specifications (high-speed mode: max. 400 kHz).
(n = 0 to 5)
Rev. 2.00 Aug. 20, 2008 Page 598 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
Table 18.3 I C bus Transfer Rate (2)
• TCSS = 1
STCR/
ICMR
IICX3
Bit 5
Bit 4
Bit 3
IICXn
CKS2
CKS1
CKS0
Clock
φ = 20 MHz
φ = 25 MHz
φ = 34 MHz
0
0
0
0
φ/56
357.1 kHz
446.4 kHz*
607.1 kHz*
1
φ/80
250.0 kHz
312.5 kHz
425.0 kHz*
0
φ/96
208.3 kHz
260.4 kHz
345.2 kHz
1
φ/128
156.3 kHz
195.3 kHz
265.6 kHz
0
φ/160
125.0 kHz
156.3 kHz
212.5 kHz
1
φ/200
100.0 kHz
125.0 kHz
170.0 kHz
0
φ/224
89.3 kHz
111.6 kHz
151.8 kHz
1
φ/256
78.1 kHz
97.7 kHz
132.8 kHz
0
φ/112
178.6 kHz
223.2 kHz
303.6 kHz
1
φ/160
125.0 kHz
156.3 kHz
212.5 kHz
0
φ/190
104.2 kHz
130.2 kHz
177.1 kHz
1
φ/256
78.1 kHz
97.7 kHz
132.8 kHz
0
φ/320
62.5 kHz
78.1 kHz
106.3 kHz
1
φ/400
50.0 kHz
62.5 kHz
85.0 kHz
0
φ/448
44.6 kHz
55.8 kHz
75.9 kHz
1
φ/512
39.1 kHz
48.8 kHz
66.4 kHz
1
1
0
1
1
0
0
1
1
0
1
Note:
*
Transfer Rate
2
The correct operation cannot be guaranteed since the value is outside the I C bus
interface specifications (high-speed mode: max. 400 kHz).
(n = 0 to 5)
Rev. 2.00 Aug. 20, 2008 Page 599 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.6
2
I C Bus Control Register (ICCR)
2
ICCR controls the I C bus interface and performs interrupt flag confirmation.
Bit
Bit Name
Initial
Value
R/W
Description
7
ICE
0
R/W
I C Bus Interface Enable
2
2
2
0: I C bus interface modules are stopped and I C bus
interface module internal state is initialized. SAR and
SARX can be accessed.
2
1: I C bus interface modules can perform transfer and
reception, they are connected to the SCL and SDA pins,
2
and the I C bus can be driven. ICMR and ICDR can be
accessed.
6
IEIC
0
R/W
2
I C Bus Interface Interrupt Enable
2
0: Disables interrupts from the I C bus interface to the
CPU.
2
1: Enables interrupts from the I C bus interface to the
CPU.
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
2
lose in a bus contention in master mode of the I C bus
2
format. In slave receive mode with I C bus format, the R/W
bit in the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
Rev. 2.00 Aug. 20, 2008 Page 600 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
5
MST
0
R/W
[MST clearing conditions]
4
TRS
0
R/W
(1) When 0 is written by software
2
(2) When lost in bus contention in I C bus format master
mode
[MST setting conditions]
(1) When 1 is written by software (for MST clearing
condition 1)
(2) When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
(1) When 0 is written by software (except for TRS setting
condition 3)
(2) When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
2
(3) When lost in bus contention in I C bus format master
mode
[TRS setting conditions]
(1) When 1 is written by software (except for TRS clearing
condition 3)
(2) When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
(3) When 1 is received as the R/W bit after the first frame
2
address matching in I C bus format slave mode
3
ACKE
0
R/W
Acknowledge Bit Decision Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the acknowledge bit is 1, continuous transfer is
halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
Rev. 2.00 Aug. 20, 2008 Page 601 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
2
BBSY
0
R/W*
Bus Busy
0
SCP
1
W
Start Condition/Stop Condition Prohibit
In master mode
•
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
•
Writing 1 in BBSY and 0 in SCP: A start condition and
a restart condition are issued
In slave mode
•
Writing to the BBSY flag is disabled.
[BBSY setting condition]
•
When the SDA level changes from high to low under
the condition of SCL = high, assuming that the start
condition has been issued.
[BBSY clearing conditions]
•
When the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued.
To issue a start/stop condition, use the MOV instruction.
2
The I C bus interface must be set in master transmit mode
before the issue of a start condition. Set MST to 1 and
TRS to 1 before writing 1 in BBSY and 0 in SCP.
2
The BBSY flag can be read to check whether the I C bus
(SCL, SDA) is busy or free.
Note:
*
Even if the BBSY bit is written to, the value of the flag does not change.
Rev. 2.00 Aug. 20, 2008 Page 602 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value R/W
1
IRIC
0
Description
2
R/(W)* I C Bus Interface Interrupt Request Flag
2
Indicates that the I C bus interface has issued an interrupt
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR and the WAIT bit in ICMR. See section 18.4.7, IRIC
Setting Timing and SCL Control. The conditions under
which IRIC is set also differ depending on the setting of the
ACKE bit in ICCR.
[Setting conditions]
2
I C bus format master mode:
• When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
•
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
•
At the end of data transfer (rise of the 9th
transmit/receive clock)
•
When a slave address is received after bus mastership
is lost
•
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
• When the AL flag is set to 1 after bus mastership is lost
while the ALIE bit is 1
2
I C bus format slave mode:
• When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th clock)
• When the general call address is detected (when the 0
is received for R/W bit, and ADZ flag in ICSR is set to
1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (rise of the 9th receive clock)
• When 1 is received as an acknowledge bit while the
ACKE bit is 1 (when the ACKB bit is set to 1)
•
When a stop condition is detected while the STOPIM bit
is 0 (when the STOP or ESTP flag in ICSR is set to 1)
Rev. 2.00 Aug. 20, 2008 Page 603 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
1
Bit Name
IRIC
Initial
Value
0
R/W
Description
1
R/(W)* At the end of data transfer in clock synchronous serial
format (rise of the 8th transmit/receive clock)
When a start condition is detected with serial format
selected
When a condition occurs in which the ICDRE or ICDRF
flag is set to 1.
•
When a start condition is detected in transmit mode
(when a start condition is detected and the ICDRE flag
is set to 1)
•
When transmitting the data in the ICDR register buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or data
is transferred from ICDRS to ICDRR in receive mode
and the ICDRF flag is set to 1.)
[Clearing conditions]
Note:
*
•
When 0 is written in IRIC after reading IRIC = 1
•
When ICDR is accessed by DTC * (This may not be a
clearing condition. For details, see the description of
the DTC operation on the next page.
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 604 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
2
When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the
DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission
2
start condition or stop condition after a slave address (SVA) or general call address match in I C
bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The
IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous
transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified
number of ICDR reads or writes have been completed.
Tables 18.4 and 18.5 show the relationship between the flags and the transfer states.
Rev. 2.00 Aug. 20, 2008 Page 605 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Table 18.4 Flags and Transfer States (Master Mode)
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
1
1
0
0
0
0
0↓
0
0↓
0↓
0

0
Idle state (flag
clearing
required)
1
1
1↑
0
0
1↑
0
0
0
0
0

1↑
Start condition
detected
1

1
0
0

0
0
0
0



Wait state
1
1
1
0
0

0
0
0
0
1↑


Transmission
end (ACKE=1
and ACKB=1)
1
1
1
0
0
1↑
0
0
0
0
0

1↑
Transmission
end with
ICDRE=0
1
1
1
0
0

0
0
0
0
0

0↓
ICDR write with
the above state
1
1
1
0
0

0
0
0
0
0

1
Transmission
end with
ICDRE=1
1
1
1
0
0

0
0
0
0
0

0↓
ICDR write with
the above state
or after start
condition
detected
1
1
1
0
0
1↑
0
0
0
0
0

1↑
Automatic data
transfer from
ICDRT to ICDRS
with the above
state
1
0
1
0
0
1↑
0
0
0
0

1↑

Reception end
with ICDRF=0
1
0
1
0
0

0
0
0
0

0↓

ICDR read with
the above state
1
0
1
0
0

0
0
0
0

1

Reception end
with ICDRF=1
1
0
1
0
0

0
0
0
0

0↓

ICDR read with
the above state
1
0
1
0
0
1↑
0
0
0
0

1↑

Automatic data
transfer from
ICDRS to
ICDRR with the
above state
0↓
0↓
1
0
0

0
1↑
0
0



Arbitration lost
1

0↓
0
0

0
0
0
0


0↓
Stop condition
detected
[Legend]
0: 0-state retained
0↓: Cleared to 0
1: 1-state retained
1↑: Set to 1
Rev. 2.00 Aug. 20, 2008 Page 606 of 1198
REJ09B0403-0200
: Previous state retained
Section 18 I2C Bus Interface (IIC)
Table 18.5 Flags and Transfer States (Slave Mode)
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
0
0
0
0
0
0
0
0
0
0
0

0
Idle state (flag
clearing
required)
0
0
1↑
0
0
0
0↓
0
0
0
0

1↑
Start condition
detected
0
1↑/0
*1
1
0
0
0
0

1↑
0
0
1↑
1
SAR match in
first frame
(SARX≠SAR)
0
0
1
0
0
0
0

1↑
1↑
0
1↑
1
General call
address
match in first
frame
(SARX≠H'00)
0
1↑/0
*1
1
0
0
1↑
1↑

0
0
0
1↑
1
SAR match in
first frame
(SAR≠SARX)
0
1
1
0
0




0
1↑


Transmission
end (ACKE=1
and ACKB=1)
0
1
1
0
0
1↑/0
*1



0
0

1↑
Transmission
end with
ICDRE=0
0
1
1
0
0


0↓
0↓
0
0

0↓
ICDR write
with the above
state
0
1
1
0
0




0
0

1
Transmission
end with
ICDRE=1
0
1
1
0
0


0↓
0↓
0
0

0↓
ICDR write
with the above
state
0
1
1
0
0
1↑/0
*2

0
0
0
0

1↑
Automatic
data transfer
from ICDRT to
ICDRS with
the above
state
0
0
1
0
0
1↑/0
*2





1↑

Reception end
with ICDRF=0
0
0
1
0
0


0↓
0↓
0↓

0↓

ICDR read
with the above
state
Rev. 2.00 Aug. 20, 2008 Page 607 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
MST
TRS
BBSY
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
ICDRF
ICDRE
State
0
0
1
0
0






1

Reception
end with
ICDRF=1
0
0
1
0
0


0↓
0↓
0↓

0↓

ICDR read
with the
above state
0
0
1
0
0
1↑/0
*2

0
0
0

1↑

Automatic
data transfer
from ICDRS
to ICDRR
with the
above state
0

0↓
1↑/0
*3
0/1↑
3
*







0↓
Stop
condition
detected
[Legend]
0: 0-state retained 1: 1-state retained : Previous state retained
0↓: Cleared to 0
1↑: Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
Rev. 2.00 Aug. 20, 2008 Page 608 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.7
2
I C Bus Status Register (ICSR)
ICSR consists of status flags. Refer to tables 18.4 and 18.5 as well.
Bit
Bit Name
Initial
Value
R/W
7
ESTP
0
R/(W)* Error Stop Condition Detection Flag
Description
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame transfer.
[Clearing conditions]
6
STOP
0
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag in ICCR is cleared to 0
R/(W)* Normal Stop Condition Detection Flag
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer is
completed.
[Clearing conditions]
5
IRTR
0
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag is cleared to 0
R/(W)* I2C Bus Interface Continuous Transfer Interrupt Request
Flag
2
Indicates that the I C bus interface has issued an interrupt
request to the CPU, and the source is completion of
reception/transmission of one frame in continuous
transmission/reception for which DTC activation is
possible. When the IRTR flag is set to 1, the IRIC flag is
also set to 1 at the same time.
[Setting conditions]
2
I C bus format slave mode:
•
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
2
I C bus format master mode or clocked synchronous serial
format mode:
•
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
•
When 0 is written after reading IRTR = 1
•
When the IRIC flag is cleared to 0 while ICE is 1
Rev. 2.00 Aug. 20, 2008 Page 609 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
4
AASX
0
R/(W)* Second Slave Address Recognition Flag
Description
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition matches bits
SVAX6 to SVAX0 in SARX.
[Setting condition]
When the second slave address is detected in slave
receive mode and FSX = 0 in SARX
[Clearing conditions]
3
AL
0
•
When 0 is written in AASX after reading AASX = 1
•
When a start condition is detected
•
In master mode
R/(W)* Arbitration Lost Flag
Indicates that arbitration was lost in master mode.
[Setting conditions]
When ALSL=0
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
If the internal SCL line is high at the fall of SCL in
master mode
When ALSL=1
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
If the SDA pin is driven low by another device before
2
the I C bus interface drives the SDA pin low, after the
start condition instruction was executed in master
transmit mode
[Clearing conditions]
Rev. 2.00 Aug. 20, 2008 Page 610 of 1198
REJ09B0403-0200
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in AL after reading AL = 1
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
2
AAS
0
R/(W)* Slave Address Recognition Flag
Description
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address
(H'00) is detected.
[Setting condition]
When the slave address or general call address (one
frame including a R/W bit is H'00) is detected in slave
receive mode and FS = 0 in SAR
[Clearing conditions]
1
ADZ
0
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in AAS after reading AAS = 1
•
In master mode
R/(W)* General Call Address Recognition Flag
2
In I C bus format slave receive mode, this flag is set to 1 if
the first frame following a start condition is the general call
address (H'00).
[Setting condition]
When the general call address (one frame including a
R/W bit is H'00) is detected in slave receive mode and FS
= 0 or FSX = 0
[Clearing conditions]
•
When ICDR is written to (transmit mode) or read from
(receive mode)
•
When 0 is written in ADZ after reading ADZ = 1
•
In master mode
If a general call address is detected while FS=1 and
FSX=0, the ADZ flag is set to 1; however, the general call
address is not recognized (AAS flag is not set to 1).
Rev. 2.00 Aug. 20, 2008 Page 611 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
0
ACKB
0
R/W
Acknowledge Bit
Stores acknowledge data.
Transmit mode:
[Setting condition]
When 1 is received as the acknowledge bit when ACKE=1
in transmit mode
[Clearing conditions]
•
When 0 is received as the acknowledge bit when
ACKE=1 in transmit mode
•
When 0 is written to the ACKE bit
Receive mode:
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus line
(returned by the receiving device) is read in transmission
(when TRS = 1). In reception (when TRS = 0), the value
set by internal software is read.
When this bit is written, acknowledge data that is returned
after receiving is rewritten regardless of the TRS value. If
the ICSR register bit is written using bit-manipulation
instructions, the acknowledge data should be re-set since
the acknowledge data setting is rewritten by the ACKB bit
reading value.
Write the ACKE bit to 0 to clear the ACKB flag to 0, before
transmission is ended and a stop condition is issued in
master mode, or before transmission is ended and SDA is
released to issue a stop condition by a master device.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 612 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.8
2
I C Bus Extended Control Register (ICXR)
2
ICXR enables or disables the I C bus interface interrupt generation and continuous receive
operation, and indicates the status of receive/transmit operations.
Bit
Bit Name
Initial
Value
R/W
Description
7
STOPIM
0
R/W
Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the
stop condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation when
the stop condition is detected (STOP = 1 or ESTP = 1)
in slave mode.
1: Disables IRIC flag setting and interrupt generation
when the stop condition is detected.
6
HNDS
0
R/W
Handshake Receive Operation Select
Enables or disables continuous receive operation in
receive mode.
0: Enables continuous receive operation
1: Disables continuous receive operation
When the HNDS bit is cleared to 0, receive operation is
performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level after data has been received successfully while
ICDRF flag is 0; thus disabling the next data to be
transferred. The bus line is released and next receive
operation is enabled by reading the receive data in ICDR.
Rev. 2.00 Aug. 20, 2008 Page 613 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
5
ICDRF
0
R
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) status in receive mode.
0: Indicates that the data has been already read from
ICDR (ICDRR) or ICDR is initialized.
1: Indicates that data has been received successfully and
transferred from ICDRS to ICDRR, and the data is
ready to be read out.
[Setting conditions]
•
When data is received successfully and transferred
from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF = 0
(at the rise of the 9th clock pulse).
(2) When ICDR is read successfully in receive mode after
data was received while ICDRF = 1.
[Clearing conditions]
•
When ICDR (ICDRR) is read.
•
When 0 is written to the ICE bit.
When ICDRF is set due to the condition (2) above, ICDRF
is temporarily cleared to 0 when ICDR (ICDRR) is read;
however, since data is transferred from ICDRS to ICDRR
immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Be sure to read data from ICDR in
receive mode (TRS = 0).
Rev. 2.00 Aug. 20, 2008 Page 614 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
4
ICDRE
0
R
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to ICDR
(ICDRT) or ICDR is initialized.
1: Indicates that data has been transferred from ICDRT to
ICDRS and is being transmitted, or the start condition
has been detected or transmission has been completed,
thus allowing the next data to be written to.
[Setting conditions]
•
When the start condition is detected from the bus line
2
state in I C bus format or serial format.
•
When data is transferred from ICDRT to ICDRS.
1. When data is transmitted completely while ICDRE
= 0 (at the rise of the 9th clock pulse).
2. When data is written to ICDR completely in transmit
mode after data was transmitted while ICDRE = 1.
[Clearing conditions]
•
When data is written to ICDR (ICDRT).
•
When the stop condition is detected in I C bus format
or serial format.
•
When 0 is written to the ICE bit.
2
2
Note that if the ACKE bit is set to 1 in I C bus format thus
enabling acknowledge bit decision, ICDRE is not set when
data is transmitted completely while the acknowledge bit is
1.
When ICDRE is set due to the condition (2) above, ICDRE
is temporarily cleared to 0 when data is written to ICDR
(ICDRT); however, since data is transferred from ICDRT to
ICDRS immediately, ICDRF is set to 1 again. Do not write
data to ICDR when TRS = 0 because the ICDRE flag
value is invalid during the time.
Rev. 2.00 Aug. 20, 2008 Page 615 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Bit
Bit Name
Initial
Value
R/W
Description
3
ALIE
0
R/W
Arbitration Lost Interrupt Enable
Enables or disables IRIC flag setting and interrupt request
when arbitration is lost.
0: Disables interrupt request when arbitration is lost.
1: Enables interrupt request when arbitration is lost.
2
ALSL
0
R/W
Arbitration Lost Condition Select
Selects the condition under which arbitration is lost.
2
0: If the SDA pin state disagrees with the data that I C bus
interface outputs at the rise of SCL and the SCL pin is
driven low by another device.
2
1: If the SDA pin state disagrees with the data that I C bus
interface outputs at the rise of SCL and the SDA line is
driven low by another device in idle state or after the
start condition instruction was executed.
1
FNC1
0
R/W
Function Bit
0
FNC0
0
R/W
These bits cancel some restrictions on usage. For details,
refer to section 18.6, Usage Notes.
00: Restrictions on operation remaining in effect
01: Setting prohibited
10: Setting prohibited
11: Restrictions on operation canceled
Rev. 2.00 Aug. 20, 2008 Page 616 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.3.9
2
I C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 18.7 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7
SMB5E
0
R/W
SMBus Enable
6
SMB4E
0
R/W
5
SMB3E
0
R/W
4
SMB2E
0
R/W
These bits enable/disable to support the SMBus, in
combination with bits FSEL1 and FSEL0. Bits SMB5E,
SMB4E, SMB3E, SMB2E, SMB1E, and SMB0E control
IIC_5, IIC_4, IIC_3, IIC_2, IIC_1, and IIC_0, respectively.
3
SMB1E
0
R/W
0: Disables to support the SMBus
2
SMB0E
00
R/W
1: Enables to support the SMBus
1
FSEL1
0
R/W
Frequency Selection
0
FSEL0
0
R/W
These bits must be specified to match the system clock
frequency in order to support the SMBus. For details of the
setting, see table 18.6.
Rev. 2.00 Aug. 20, 2008 Page 617 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Table 18.6 Output Data Hold Time
Output Data Hold Time (ns)
SMBnE
FSEL1
FSEL0
Min./Max.
φ = 20 MHz
φ = 25 MHz
φ = 34 MHz
0


Min.
100*
80*
59*
Max.
150*
120*
88*
Min.
150*
120*
88*
Max.
250*
200*
147*
Min.
200*
160*
118*
Max.
350
280*
206*
Min.
300
240*
176*
Max.
550
440
324
Min.
500
400
294*
Max.
950
760
559
1
0
0
1
1
0
1
Notes:
*
n = 0 to 5
Since the value is outside the SMBus specification, it should not be set.
Table 18.7 ISCMBCR Setting
System Clock
SMBnE
FSEL1
FSEL0
20 MHz
1
1
0
20 to 34 MHz
1
1
1
n = 0 to 5
Rev. 2.00 Aug. 20, 2008 Page 618 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4
Operation
18.4.1
I C Bus Data Format
2
2
2
The I C bus interface has an I C bus format and a serial format.
2
The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures
18.3 (a) and (b). The first frame following a start condition always consists of 9 bits.
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
18.4.
2
Figure 18.5 shows the I C bus timing.
The symbols used in figures 18.3 to 18.5 are explained in table 18.8.
(a) FS = 0 or FSX = 0
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = from 1)
m
(b) Start condition retransmission FS = 0 or FSX = 0
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
1
7
1
1
n1
1
1
7
1
1
n2
1
m1
1
A/A
P
1
1
m2
Upper row: Transfer bit count (n1, n2 = 1 to 8)
Lower row: Transfer frame count (m1, m2 = from 1)
2
2
Figure 18.3 I C Bus Data Formats (I C Bus Formats)
FS=1 and FSX=1
S
DATA
DATA
P
1
8
n
1
1
m
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = from 1)
2
Figure 18.4 I C Bus Data Formats (Serial Formats)
Rev. 2.00 Aug. 20, 2008 Page 619 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
SDA
SCL
S
1–7
8
9
SLA
R/W
A
1–7
8
DATA
9
A
1–7
DATA
8
9
A/A
P
2
Figure 18.5 I C Bus Timing
2
Table 18.8 I C Bus Data Format Symbols
Symbol
Description
S
Start condition. The master device drives SDA from high to low while SCL is high
SLA
Slave address. The master device selects the slave device.
R/W
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
DATA
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
P
Stop condition. The master device drives SDA from low to high while SCL is high
Rev. 2.00 Aug. 20, 2008 Page 620 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.2
Initialization
Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of
data.
Start initialization
Set MSTP4 = 0 (IIC_0)
MSTP3 = 0 (IIC_1)
MSTP2 = 0 (IIC_2, IIC_3)
MSTP0 = 0 (IIC_4, IIC_5)
(MSTPCRL)
Cancel module stop mode
Set IICE = 1 in STCR
Enable the CPU accessing to the IIC control register and data register
Set ICE = 0 in ICCR
Enable SAR and SARX to be accessed
Set SAR and SARX
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Set ICE = 1 in ICCR
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set ICSR
Set STCR and IICX3
Set ICMR
Set ICXR
Set ICCR
Set acknowledge bit (ACKB)
Set transfer rate (IICX and TCSS)
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
<< Start transmit/receive operation >>
Figure 18.6 Sample Flowchart for IIC Initialization
Note: Be sure to modify the ICMR register after transmit/receive operation has been completed.
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to
BC0 will be modified erroneously, thus causing incorrect operation.
18.4.3
Master Transmit Operation
2
In I C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Rev. 2.00 Aug. 20, 2008 Page 621 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Figure 18.7 shows the sample flowchart for the operations in master transmit mode.
Start
Initialize IIC
[1] Initialization
Read BBSY in ICCR
[2] Test the status of the SCL and SDA lines.
No
BBSY = 0?
Yes
Set MST = 1 and
TRS = 1 in ICCR
[3] Select master transmit mode.
Set BBSY =1 and
SCP = 0 in ICCR
[4] Start condition issuance
Read IRIC in ICCR
[5] Wait for a start condition generation
No
IRIC = 1?
Yes
Write transmit data in ICDR
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing to ICDR, clear IRIC
continuously.)
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
No
ACKB = 0?
[8] Test the acknowledge bit
transferred from the slave device.
Yes
Transmit mode?
No
Master receive mode
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
[9] Set transmit data for the second and
subsequent bytes.
(After writing to ICDR, clear IRIC
immediately.)
Read IRIC in ICCR
[10] Wait for 1 byte to be transmitted.
No
IRIC = 1?
Yes
Read ACKB in ICSR
[11] Determine end of transfer
No
End of transmission?
(ACKB = 1?)
Yes
Clear IRIC in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
[12] Stop condition issuance
End
Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode
Rev. 2.00 Aug. 20, 2008 Page 622 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR (ICDRT) write operations, are described below.
1. Initialize the IIC as described in section 18.4.2, Initialization.
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU.
6. Write the data (slave address + R/W) to ICDR.
2
With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame
data following the start condition indicates the 7-bit slave address and transmit/receive
direction (R/W).
To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear
IRIC continuously so no other interrupt handling routine is executed. If the time for
transmission of one frame of data has passed before the IRIC clearing, the end of transmission
cannot be determined. The master device sequentially sends the transmission clock and the
data written to ICDR. The selected slave device (i.e. the slave device with the matching slave
address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal.
7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has
not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the
transmit operation.
9. Write the transmit data to ICDR.
As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and
the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is
performed in synchronization with the internal clock.
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
11. Read the ACKB bit in ICSR.
Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data
to be transmitted, go to step [9] to continue the next transmission operation. When the slave
device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission.
Rev. 2.00 Aug. 20, 2008 Page 623 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP
in ICCR. This changes SDA from low to high when SCL is high, and generates the stop
condition.
Start condition generation
SCL
(master output)
1
2
3
4
5
6
7
SDA
(master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Slave address
SDA
(slave output)
8
9
Bit 0
R/W
[7]
1
2
Bit 7
Bit 6
Data 1
A
[5]
ICDRE
IRIC
Interrupt
request
Interrupt
request
IRTR
ICDRT
ICDRS
Data 1
Address + R/W
Address + R/W
Data 1
Note: Do not set ICDR
during this period.
User processing
[4] BBSY set to 1 and
[6] ICDR write
SCP cleared to 0
(start condition issuance)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 18.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
Rev. 2.00 Aug. 20, 2008 Page 624 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Stop condition issuance
SCL
(master output)
8
9
SDA
Bit 0
(master output)
Data 1
SDA
(slave output)
[7]
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
9
[10]
Data 2
A
A
ICDRE
IRIC
IRTR
ICDR
Data 2
Data 1
User processing
[9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] IRIC clear
[12] BBSY set to 1 and
SCP cleared to 0
(Stop condition issuance)
Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)
18.4.4
Master Receive Operation
2
In I C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Rev. 2.00 Aug. 20, 2008 Page 625 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 18.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
[1] Select receive mode.
Set HNDS = 1 in ICXR
Clear IRIC in ICCR
Last receive?
Yes
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
No
Read ICDR
Read IRIC in ICCR
No
[3] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock for the receive frame)
IRIC = 1?
Yes
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICCR
No
[4] Clear IRIC.
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
Dummy read to start receiving if the first frame is
the last receive data.
[8] Wait for 1 byte to be received.
IRIC = 1?
Yes
Clear IRIC in ICCR
Set TRS = 1 in ICCR
[9] Clear IRIC.
[10] Read the receive data.
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
[11] Set stop condition issuance.
Generate stop condition.
End
Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
Rev. 2.00 Aug. 20, 2008 Page 626 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
The reception procedure and operations by which the data reception process is provided in 1-byte
units with SCL fixed low at each data reception are described below.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Set the HNDS bit in ICXR to 1.
Clear the IRIC flag to 0 to determine the end of reception.
Go to step [6] to halt reception operation if the first frame is the last receive data.
2. When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. (Data from the SDA pin is
sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.)
3. The master device drives SDA low to return the acknowledge data at the 9th receive clock
pulse. The receive data is transferred to ICDRR from ICDRS at the rise of the 9th clock pulse,
setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt
request is sent to the CPU.
The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data
reading.
4. Clear the IRIC flag to determine the next interrupt.
Go to step [6] to halt reception operation if the next frame is the last receive data.
5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock continuously to receive the next data.
Data can be received continuously by repeating steps [3] to [5].
6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception.
7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock to receive data.
8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the
rise of the 9th receive clock pulse.
9. Clear the IRIC flag to 0.
10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0.
11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
is high, and generates the stop condition.
Rev. 2.00 Aug. 20, 2008 Page 627 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Master receive mode
Master transmit mode
SCL is fixed low until ICDR is read
SCL is fixed low until ICDR is read
SCL
(master output)
9
1
2
3
4
5
6
7
8
SDA
(slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
Bit 7
Bit 6
9
[3]
Data 1
SDA
(master output)
Data 2
A
IRIC
IRTR
ICDRF
ICDRR
Data 1
Undefined value
User processing
[1] TRS cleared to 0
[6] ICDR read
(Data 1)
[4] IRIC clear
[2] ICDR read
(Dummy read)
[1] IRIC clear
Figure 18.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)
SCL is fixed low until ICDR is read
SCL
(master output)
SDA
(slave output)
7
8
Bit 1
Bit 0
Data 2
SDA
(master output)
9
SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[3]
Data 3
A
Stop condition generation
9
[8]
A
IRIC
IRTR
ICDRF
ICDRR
User processing
Data 1
Data 2
[4] IRIC clear
[7] ICDR read
(Data 2)
[6] ACKB set to 1
Data 3
[10] ICDR read
(Data 3)
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
[9] IRIC clear
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
Rev. 2.00 Aug. 20, 2008 Page 628 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Receive Operation Using the Wait Function:
Figures 18.13 and 18.14 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Master receive mode
Set TRS = 0 in ICCR
[1] Select receive mode.
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC in ICCR
Set WAIT = 1 in ICMR
[2] Start receiving. The first read
is a dummy read.
Read ICDR
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
Yes
No
[4] Determine end of reception
IRTR = 1?
Yes
Last receive?
Yes
No
Read ICDR
[5] Read the receive data.
[6] Clear IRIC.
(to end the wait insertion)
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Wait for one clock pulse
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
Set TRS = 1 in ICCR
[10] Read the receive data.
Read ICDR
No
[7] Set acknowledge data for the last reception.
Clear IRIC in ICCR
[11] Clear IRIC.
Read IRIC in ICCR
[12] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
IRIC=1?
Yes
IRTR=1?
Yes
[13] Determine end of reception
No
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Read ICDR
Set BBSY= 0 and SCP= 0
in ICCR
[14] Clear IRIC.
(to end the wait insertion)
[15] Clear wait mode.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data.
[17] Generate stop condition
End
Figure 18.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)
Rev. 2.00 Aug. 20, 2008 Page 629 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
[1] Select receive mode.
Clear IRIC in ICCR
Set WAIT = 0 in ICMR
Read ICDR
[2] Start receiving. The first read
is a dummy read.
Read IRIC in ICCR
No
IRIC = 1?
[3] Wait for a receive wait
(Set IRIC at the fall of the 8 th clock)
Yes
No
Set ACKB = 1 in ICSR
[7] Set acknowledge data for
the last reception.
Set TRS = 1 in ICCR
[9] Set TRS for stop condition issuance
Clear IRIC in ICCR
[14] Clear IRIC.
(to end the wait insertion)
Read IRIC in ICCR
[12] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock)
IRIC = 1?
Yes
Set WAIT = 0 in ICMR
Clear IRIC in ICCR
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
[15] Clear wait mode.
Clear IRIC.
( IRIC should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data
[17] Generate stop condition
End
Figure 18.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1)
The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
18.14.
Rev. 2.00 Aug. 20, 2008 Page 630 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 to set the acknowledge data.
Clear the HNDS bit in ICXR to 0 to cancel the handshake function.
Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1.
2. When ICDR is read (dummy data is read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock.
3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to
1, an interrupt request is sent to the CPU.
(1) At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag clearing.
(2) At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next
data.
4. Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception.
5. If IRTR flag is 1, read ICDR receive data.
6. Clear the IRIC flag. When the flag is set as (1) in step [3], the master device outputs the 9th
clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal.
Data can be received continuously by repeating steps [3] to [6].
7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock
pulse for the next receive data.
9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value
becomes valid when the rising edge of the next 9th clock pulse is input.
10. Read the ICDR receive data.
11. Clear the IRIC flag to 0.
Rev. 2.00 Aug. 20, 2008 Page 631 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
12. The IRIC flag is set to 1 in either of the following cases.
(1) At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
(2) At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received.
13. Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Execute step [12] to read the IRIC flag to detect the end of reception.
15. Clear the WAIT bit in ICMR to cancel the wait mode.
Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0
after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition may not be issued correctly.)
16. Read the last ICDR receive data.
17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
is high, and generates the stop condition.
Rev. 2.00 Aug. 20, 2008 Page 632 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Master transmit mode
SCL
(master output)
SDA
(slave output)
Master receive mode
9
1
2
A
Bit 7
Bit 6
3
Bit 5
4
5
6
7
8
9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
Bit 7
Data 1
[3]
SDA
(master output)
Bit 6
3
4
5
Bit 5
Bit 4
Bit 3
Data 2
[3]
A
IRIC
[4]IRTR=0
IRTR
[4] IRTR=1
ICDR
Data 1
User processing [1] TRS cleared to 0
IRIC clear to 0
[6] IRIC clear
[5] ICDR read [6] IRIC clear
(to end wait insertion)
(Data 1)
[2] ICDR read
(dummy read)
Figure 18.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)
[8] Wait for one clock pulse
Stop condition generation
SCL
(master output)
8
9
SDA
Bit 0
(slave output)
Data 2
[3]
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 3
[3]
A
9
[12]
[12]
A
IRIC
IRTR
[4] IRTR=0
ICDR
Data 1
User processing
[13] IRTR=0
[4] IRTR=1
[13] IRTR=1
Data 2
[6] IRIC clear
(to end wait
insertion)
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
Data 3
[15] WAIT cleared to 0,
IRIC clear
[14] IRIC clear
(to end wait
insertion)
[17] Stop condition issuance
[16] ICDR read
(Data 3)
Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
Rev. 2.00 Aug. 20, 2008 Page 633 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.5
Slave Receive Operation
2
In I C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Rev. 2.00 Aug. 20, 2008 Page 634 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 18.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
Slave receive mode
Initialize IIC
Set MST = 0
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
and HNDS = 1 in ICXR
Clear IRIC in ICCR
ICDRF = 1?
No
[1] Initialization. Select slave receive mode.
[2] Read the receive data remaining unread.
Yes
ReadICDR, clear IRIC
[3] to [7] Wait for one byte to be received (slave address + R/W)
Read IRIC in ICCR
No
IRIC = 1?
Yes
[8] Clear IRIC
Clear IRIC in ICCR
Read AASX, AAS and ADZ in ICSR
Yes
AAS = 1
and ADZ = 1?
General call address processing
No
* Description omitted
Read TRS in ICCR
Yes
TRS = 1?
Slave transmit mode
No
Last reception?
No
Yes
Read ICDR
[10] Read the receive data. The first read is a dummy read.
[5] to [7] Wait for the reception to end.
Read IRIC in ICCR
No
IRIC = 1?
Yes
[8] Clear IRIC
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
[10] Read the receive data.
Read ICDR
[5] to [7] Wait for the reception to end.
or
[11] Detect stop condition
Read IRIC in ICCR
No
[9] Set acknowledge data for the last reception.
IRIC = 1?
Yes
ESTP = 1 or
STOP = 1?
[12] Check STOP
Yes
No
Clear IRIC in ICCR
[8] Clear IRIC
Clear IRIC in ICCR
[12] Clear IRIC
End
Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
Rev. 2.00 Aug. 20, 2008 Page 635 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
The reception procedure and operations using the HNDS bit function by which data reception
process is provided in 1-byte unit with SCL being fixed low at every data reception, are described
below.
1. Initialize the IIC as described in section 18.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the
ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1. The master device then outputs the 7-bit slave address, and transmit/receive direction
(R/W), in synchronization with the transmit clock pulses.
4. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as the acknowledge data.
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, IRTR flag is also set to 1.
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive
clock pulse until data is read from ICDR.
8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0.
9. If the next frame is the last receive frame, set the ACKB bit to 1.
10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the
master device to transfer the next data.
Receive operations can be performed continuously by repeating steps [5] to [10].
11. When the stop condition is detected (SDA is changed from low to high when SCL is high),
the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1.
12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
Rev. 2.00 Aug. 20, 2008 Page 636 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Start condition generation
SCL
(Pin waveform)
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
[7] SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
9
1
2
1
2
3
4
5
6
7
8
9
1
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave address
Bit 7
R/W
Bit 6
Data 1
[6]
A
Interrupt
request
occurrence
IRIC
ICDRF
Address+R/W
ICDRS
ICDRR
Address+R/W
Undefined value
User processing
[2] ICDR read
[8] IRIC clear
[10] ICDR read (dummy read)
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)
[7] SCL is fixed low until ICDR is read
SCL
(master output)
8
9
1
2
3
[7] SCL is fixed low until ICDR is read
4
5
6
7
8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Stop condition generation
9
SCL
(slave output)
SDA
(master output)
Bit 0
Bit 7
[6]
Data (n-1)
SDA
(slave output)
Bit 6
Bit 5
[6]
Data (n)
A
[11]
A
IRIC
ICDRF
ICDRS
ICDRR
User processing
Data (n-1)
Data (n-2)
Data (n)
Data (n)
Data (n-1)
[8] IRIC clear [10] ICDR read (Data (n-1))
[9] Set ACKB=1
[8] IRIC clear
[10] ICDR read
(Data (n))
[12] IRIC clear
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)
Rev. 2.00 Aug. 20, 2008 Page 637 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Continuous Receive Operation:
Figure 18.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Slave receive mode
Set MST = 0
and TRS = 0 in ICCR
[1] Select slave receive mode.
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC in ICCR
ICDRF = 1?
No
[2] Read the receive data remaining unread.
Yes
Read ICDR
Clear IRIC in ICCR
[3] to [7] Wait for one byte to be received (slave address + R/W)
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR
[8] Clear IRIC
Read AASX, AAS and ADZ in ICSR
AAS = 1
and ADZ = 1?
Yes
General call address processing
* Description omitted
No
Read TRS in ICCR
TRS = 1?
Yes
Slave transmit mode
No
(n-2)th-byte
reception?
No
* n: Address + total number of bytes received
[9] Wait for ACKB setting and set acknowledge data
for the last reception
(after the rise of the 9th clock of (n-1)th byte data)
Wait for one frame
Set ACKB = 1 in ICSR
ICDRF = 1?
No
[10] Read the receive data. The first read is a dummy read.
Yes
Read ICDR
[11] Wait for one byte to be received
(Set IRIC at the rise of the 9th clock)
Read IRIC in ICCR
No
IRIC = 1?
ESTP = 1 or
STOP = 1?
Yes
[12] Detect stop condition
No
Clear IRIC in ICCR
ICDRF = 1?
[13] Clear IRIC
No
[14] Read the last receive data
Yes
Read ICDR
Clear IRIC in ICCR
[15] Clear IRIC
End
Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
Rev. 2.00 Aug. 20, 2008 Page 638 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
The reception procedure and operations in slave receive are described below.
1. Initialize the IIC as described in section 18.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits
to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1. The master device then outputs the 7-bit slave address, and transmit/receive direction
(R/W) in synchronization with the transmit clock pulses.
4. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as the acknowledge data.
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, the IRTR flag is also set to 1.
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1.
8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0.
9. If the next read data is the third last receive frame, wait for at least one frame time to set the
ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive
frame.
10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0.
11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to
ICDRR due to ICDR read operation, The IRIC and ICDRF flags are set to 1.
12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the
BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1. In this case, execute step 14 to read the last receive data.
13. Clear the IRIC flag to 0.
Rev. 2.00 Aug. 20, 2008 Page 639 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Receive operations can be performed continuously by repeating steps 9 to 13.
14. Confirm that the ICDRF flag is set to 1, and read ICDR.
15. Clear the IRIC flag.
Start condition issuance
SCL
(master output)
SDA
(master output)
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Slave address
SDA
(slave output)
8
9
1
Bit 7
Bit 0
R/W
[6]
2
3
4
Bit 6
Bit 5
Bit 4
Data 1
A
IRIC
ICDRF
ICDRS
Address+R/W
Data 1
[7]
ICDRR
Address+R/W
User processing
[8] IRIC clear
[10] ICDR read
Figure 18.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)
Rev. 2.00 Aug. 20, 2008 Page 640 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Stop condition detection
SCL
(master output)
8
9
SDA
(master output) Bit 0
Data (n-2)
SDA
(slave output)
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data (n-1)
A
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data (n)
A
[11]
[12]
A
IRIC
ICDRF
ICDRS
Data (n-2)
ICDRR
Data (n-1)
Data (n-2)
[9] Wait for one frame
User processing
[13] IRIC clear
Data (n)
Data (n-1)
[13] IRIC clear [10] ICDR read
[10] ICDR read
(Data (n-1))
(Data (n-2))
[9] Set ACKB = 1
Data (n)
[13] IRIC clear
[14] ICDR read
(Data (n))
[15] IRIC clear
Figure 18.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)
Rev. 2.00 Aug. 20, 2008 Page 641 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.6
Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 18.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode
Clear IRIC in ICCR
[1], [2] If the slave address matches to the address in the first frame
following the start condition detection and the R/W bit is 1
in slave receive mode, the mode changes to slave transmit mode.
[3], [5] Set transmit data for the second and subsequent bytes.
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
[3], [4] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
[4] Determine end of transfer.
End
of transmission
(ACKB = 1)?
No
Yes
Clear IRIC in ICCR
Clear ACKE to 0 in ICCR
(ACKB=0 clear)
Set TRS = 0 in ICCR
Read ICDR
Read IRIC in ICCR
No
[6] Clear IRIC in ICCR
[7] Clear acknowledge bit data
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
IRIC = 1?
Yes
Clear IRIC in ICCR
End
Figure 18.23 Sample Flowchart for Slave Transmit Mode
Rev. 2.00 Aug. 20, 2008 Page 642 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations
in slave transmit mode are described below.
1. Initialize slave receive mode and wait for slave address reception.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
ICDRE flag is set to 1. The slave device drives SCL low from the fall of the 9th transmit clock
until ICDR data is written, to disable the master device to output the next transfer clock.
3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to
0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again.
The slave device sequentially sends the data written into ICDRS in accordance with the clock
output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
register writing to the IRIC flag clearing should be performed continuously. Prevent any other
interrupt processing from being inserted.
4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to
determine whether the transfer operation was performed successfully. When one frame of data
has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock
pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS and the
ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device
drives SCL low from the fall of the 9th transmit clock until data is written to ICDR.
5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is
cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from
the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent
any other interrupt processing from being inserted.
Transmit operations can be performed continuously by repeating steps 4 and 5.
6. Clear the IRIC flag to 0.
7. To end transmission, clear the ACKE bit in the ICCR register to 0, to clear the acknowledge
bit stored in the ACKB bit to 0.
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SCL on the slave side.
Rev. 2.00 Aug. 20, 2008 Page 643 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to
0.
Slave transmit mode
Slave receive mode
SCL
(master output)
8
SDA
(slave output)
9
1
2
A
Bit 7
Bit 6
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 1
[2]
SDA
(master output) R/W
9
1
2
Bit 7
Bit 6
[4]
Data 2
A
IRIC
ICDRE
ICDR
User processing
Data 1
[3] IRIC clear
[3] ICDR write
[3] IRIC clear
Data 2
[5] IRIC clear
[5] ICDR write
Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0)
Rev. 2.00 Aug. 20, 2008 Page 644 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figures 18.25 to 18.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
SDA
7
8
9
7
8
A
1
1
2
2
3
3
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
7
8
9
1
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.25 IRIC Setting Timing and SCL Control (1)
Rev. 2.00 Aug. 20, 2008 Page 645 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
SDA
8
9
1
2
3
8
A
1
2
3
IRIC
User processing
Clear IRIC
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
8
9
1
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.26 IRIC Setting Timing and SCL Control (2)
Rev. 2.00 Aug. 20, 2008 Page 646 of 1198
REJ09B0403-0200
Clear IRIC
Section 18 I2C Bus Interface (IIC)
When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
SDA
7
8
7
8
1
1
2
2
3
3
4
4
IRIC
User processing
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
SDA
7
8
1
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 18.27 IRIC Setting Timing and SCL Control (3)
Rev. 2.00 Aug. 20, 2008 Page 647 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.8
Operation Using the DTC
This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR
flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0,
the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the
acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data
transmission is completed with the acknowledge bit value of 0, and when the ACKE bit is 1, only
the IRIC flag is set if data transmission is completed with the acknowledge bit value of 1.
When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags
to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data
transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is
not initiated, thus allowing an interrupt to be generated if enabled.
The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,
indicating no specific events.
2
The I C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 18.9 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Rev. 2.00 Aug. 20, 2008 Page 648 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Table 18.9 Examples of Operation Using the DTC
Item
Master Transmit
Mode
Slave address + Transmission by
R/W bit
DTC (ICDR write)
transmission/
reception
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read

Processing by
CPU (ICDR read)


Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write


Processing by
DTC (ICDR write)

Last frame
processing
Not necessary
Reception by
CPU (ICDR read)
Not necessary
Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
Not necessary
Automatic clearing Not necessary
on detection of
stop condition
during
transmission of
dummy data (H'FF)
Setting of
number of DTC
transfer data
frames
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
2nd time: Stop
condition issuance
by CPU
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Rev. 2.00 Aug. 20, 2008 Page 649 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.4.9
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 18.28 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
C
SCL or
SDA input
signal
D
Q
Latch
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
System clock
cycle
Sampling
clock
Figure 18.28 Block Diagram of Noise Canceler
18.4.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with clearing ICE bit.
Scope of Initialization: The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Rev. 2.00 Aug. 20, 2008 Page 650 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (other than ICDRE
and ICDRF))
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, and ICSR registers
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the ICE bit clearing.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the ICE bit clearing.
4. Initialize (re-set) the IIC registers.
Rev. 2.00 Aug. 20, 2008 Page 651 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
18.5
Interrupt Source
The IIC interrupt source is IICI. The IIC interrupt sources and their priority order are shown in
table 18.10. Each interrupt source is enabled or disabled by the ICCR interrupt enable bit and
transferred to the interrupt controller independently.
Table 18.10 IIC Interrupt Source
Channel
Bit
Name
Enable
Bit
Interrupt
Flag
DTC Activation Priority
2
IRIC
Possible
2
IRIC
Possible
2
IRIC
Possible
2
IRIC
Possible
2
IRIC
Not possible
2
IRIC
Not possible
Interrupt Source
2
IICI2
IEIC
I C bus interface interrupt
request
3
IICI3
IEIC
I C bus interface interrupt
request
0
IICI0
IEIC
I C bus interface interrupt
request
1
IICI1
IEIC
I C bus interface interrupt
request
4
IICI4
IEIC
I C bus interface interrupt
request
5
IICI5
IEIC
I C bus interface interrupt
request
Rev. 2.00 Aug. 20, 2008 Page 652 of 1198
REJ09B0403-0200
High
Low
Section 18 I2C Bus Interface (IIC)
18.6
Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions*, after issuing the instruction that generates the start
2
condition, read the relevant DR registers of I C bus output pins, check that SCL and SDA are
both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then
issue the instruction that generates the stop condition. Note that SCL may not yet have gone
low when BBSY is cleared to 0.
2
Note: * An illegal procedure in the I C bus specification.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 18.11 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 18.11 I C Bus Timing (SCL and SDA Outputs)
Item
Symbol Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28 tcyc to 512 tcyc
ns
See figure
SCL output high pulse width
tSCLHO
0.5 tSCLO
ns
SCL output low pulse width
tSCLLO
0.5 tSCLO
ns
31.32
(reference)
SDA output bus free time
tBUFO
0.5 tSCLO – 1 tcyc
ns
Start condition output hold time
tSTAHO
0.5 tSCLO – 1 tcyc
ns
Retransmission start condition output
setup time
tSTASO
1 tSCLO
ns
Stop condition output setup time
tSTOSO
0.5 tSCLO + 2 tcyc
ns
Data output setup time (master)
tSDASO
1 tSCLLO – 3 tcyc
ns
Data output setup time (slave)
Data output hold time
Note:
*
1 tSCLLO – (6 tcyc or 12 tcyc*)
tSDAHO
3 tcyc
ns
6 tcyc when IICXn is 0, 12 tcyc when IICXn is 1 (n = 0 to 5).
Rev. 2.00 Aug. 20, 2008 Page 653 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in section 31, Electrical
2
Characteristics. Note that the I C bus interface AC timing specification will not be met with a
system clock frequency of less than 5 MHz.
2
5. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2
speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
2
the time determined by the input clock of the I C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 18.12.
Table 18.12 Permissible SCL Rise Time (tsr) Values
Time Indication [ns]
TCSS IICXn
tcyc Indication
0
7.5 tcyc
0
1
1
0
1
1
17.5 tcyc
37.5 tcyc
2
I C Bus Specification
(Max.)
φ = 20 MHz
φ = 25 MHz
φ = 34 MHz
Standard
mode
1000
375
300
221
High-speed
mode
300
300
300
221
Standard
mode
1000
875
700
515
High-speed
mode
300
300
300
300
Standard
mode
1000
1000
1000
1000
High-speed
mode
300
300
300
300
Note: n = 0 to 5
Rev. 2.00 Aug. 20, 2008 Page 654 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
2
table 18.11. However, because of the rise and fall times, the I C bus interface specifications
may not be satisfied at the maximum transfer rate. Table 18.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
2
tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
2
permits this output timing for use as slave devices connected to the I C bus.
2
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
2
whose input timing permits this output timing for use as slave devices connected to the I C
bus.
Rev. 2.00 Aug. 20, 2008 Page 655 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
Table 18.13 I C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
2
tSr/tSf
Influence
(Max.)
I C Bus
Specification (Min.)
φ = 20 MHz
φ = 25 MHz
φ = 34 MHz
Item
tcyc
Indication


Standard mode


φ/200
φ/224
φ/224


High-speed mode


φ/48
φ/56
φ/80
tSCLHO
0.5 tSCLO (–tSr)
Standard mode
–1000
4000
4000
3480
3706
High-speed mode
–300
600
900
820
876
tSCLLO
0.5 tSCLO (–tSf)
Standard mode
–250
4700
4750
4230
tBUFO
0.5 tSCLO –1 tcyc
( –tSr)
1
High-speed mode
–250
1300
950*
Standard mode
–1000
4700
3950*1
High-speed mode
–300
1300
850*
1
870*
1
3440*1
780*
1
4456
926*
1
3676*1
847*1
0.5 tSCLO –1 tcyc
(–tSf)
Standard mode
–250
4000
4700
4190
4426
High-speed mode
–250
600
900
830
897
tSTASO
1 tSCLO (–tSr)
Standard mode
–1000
4700
9000
7960
8412
High-speed mode
–300
600
2100
1940
2053
tSTOSO
0.5 tSCLO + 2 tcyc
(–tSr)
Standard mode
–1000
4000
4100
3560
3765
High-speed mode
–300
600
1000
900
935
tSTAHO
3
tSDASO
(master)
1 tSCLLO* –3 tcyc
(–tSr)
Standard mode
–1000
250
3600
3110
3368
High-speed mode
–300
100
500
450
538
tSDASO
(slave)
3
1 tSCLL* –12
2
tcyc*
(–tSr)
Standard mode
–1000
250
3100
3220
3347
High-speed mode
–300
100
400
520
64
tSDAHO
3 tcyc
Standard mode
0
0
150
120
88
High-speed mode
0
0
150
120
88
2
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the bits TCSS,
IICX3 to IICX0 and CKS2 to CKS0. Depending on the frequency it may not be possible
2
to achieve the maximum transfer rate; therefore, whether or not the I C bus interface
specifications are met must be determined in accordance with the actual setting
conditions.
2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is
(– 6tcyc) (n = 0 to 5).
2
3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
Rev. 2.00 Aug. 20, 2008 Page 656 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
7. Notes on ICDR register read at end of master reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 18.29 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Stop condition
Start condition
(a)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
ICDR read
disabled period
Execution of instruction
for issuing stop condition
(write 0 to BBSY and SCP)
Confirmation of stop
condition issuance
(read BBSY = 0)
Start condition
issuance
Figure 18.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 2.00 Aug. 20, 2008 Page 657 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
8. Notes on start condition issuance for retransmission
Figure 18.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
No
IRIC = 1?
[1] Wait for end of 1-byte transfer
[1]
Yes
[2] Determine whether SCL is low
Clear IRIC in ICCR
[3] Issue start condition instruction for retransmission
Read SCL pin
No
SCL = Low?
[4] Determine whether start condition is generated or not
[2]
Yes
[5] Set transmit data (slave address + R/W)
Set BBSY = 1,
SCP = 0 (ICCR)
[3]
No
IRIC = 1?
[4]
Note: Program so that processing from [3] to [5]
is executed continuously.
Yes
Write transmit data to ICDR
[5]
Start condition generation
(retransmission)
SCL
9
SDA
ACK
Bit 7
IRIC
[5] ICDR write (transmit data)
[4] IRIC determination
[3] (Retransmission) Start condition instruction issuance
[2] Determination of SCL = Low
[1] IRIC determination
Figure 18.30 Flowchart for Start Condition Issuance Instruction
for Retransmission and Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Rev. 2.00 Aug. 20, 2008 Page 658 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
2
9. Note on when I C bus interface stop condition instruction is issued
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low.
SCL
9th clock
VIH
Secures a high period
SCL is detected as low
because the rise of the
waveform is delayed
SDA
Stop condition generation
IRIC
[1] SCL = low determination
[2] Stop condition instruction issuance
Figure 18.31 Stop Condition Issuance Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
10. Note on IRIC flag clear when the wait function is used
2
When the wait function is used in I C bus interface master mode and in a situation where the
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
Rev. 2.00 Aug. 20, 2008 Page 659 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Secures a high period
SCL
VIH
SCL = low detected
SDA
IRIC
[1] SCL = low determination
[2] IRIC clear
Figure 18.32 IRIC Flag Clearing Timing When WAIT = 1
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
11. Note on ICDR register read and ICCR register access in slave transmit mode
2
In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 18.33. However, such read and write operations source no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
 Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
 Monitor the BC2 to BC0 counter in ICMR; when the count is B'000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
Rev. 2.00 Aug. 20, 2008 Page 660 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Waveform at problem occurrence
SDA
R/W
A
SCL
8
9
TRS bit
Bit 7
Address reception
Data transmission
ICDR read and ICCR read/write are disabled
ICDR write
(6 system clock period)
The rise of the 9th clock is detected
Figure 18.33 ICDR Register Read and ICCR Register Access Timing
in Slave Transmit Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
12. Note on TRS bit setting in slave mode
2
In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 18.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 18.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 18.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
Rev. 2.00 Aug. 20, 2008 Page 661 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
Restart condition
(a)
(b)
A
SDA
SCL
TRS
8
9
1
Data
transmission
2
3
4
5
6
7
8
9
Address reception
TRS bit setting is suspended in this period
ICDR dummy read
TRS bit setting
The rise of the 9th clock is detected
The rise of the 9th clock is detected
Figure 18.34 TRS Bit Set Timing in Slave Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
13. Note on ICDR read in transmit mode and ICDR write in receive mode
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive
mode or write to the ICDR after setting transmit mode.
Rev. 2.00 Aug. 20, 2008 Page 662 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
14. Note on ACKE and TRS bits in slave mode
2
In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition and address are transmitted from the
master device in slave transmit mode (TRS = 1), the ICDRE flag is set, and 1 is received as the
acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source
even when the address does not match.
2
To use the I C bus interface module in slave mode, be sure to follow the procedures below.
 When having received 1 as the acknowledge bit value for the last transmit data at the end
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
 Set receive mode (TRS = 0) before the next start condition is input in slave mode.
Complete transmit operation by the procedure shown in figure 18.23, in order to switch
from slave transmit mode to slave receive mode.
15. Notes on Arbitration Lost in Master Mode Operation
2
The I C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
2
register, the I C bus interface erroneously recognizes that the address call has occurred. (See
figure 18.35.)
2
In multi-master mode, a bus conflict could happen. When the I C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Rev. 2.00 Aug. 20, 2008 Page 663 of 1198
REJ09B0403-0200
Section 18 I2C Bus Interface (IIC)
• Arbitration is lost
• The AL flag in ICSR is set to 1
I2C bus interface
(Master transmit mode)
S
SLA
R/W
A
DATA1
Transmit data match
Transmit timing match
Other device
(Master transmit mode)
S
SLA
R/W
A
Transmit data does not match
DATA2
A
DATA3
A
Data contention
I2C bus interface
(Slave receive mode)
S
SLA
R/W
A
• Receive address is ignored
SLA
R/W
A
DATA4
A
• Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device.
Figure 18.35 Diagram of Erroneous Operation when Arbitration Lost
2
Though it is prohibited in the normal I C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode.
When the MST bit is set to 1 during data transmission or reception in slave mode, the
arbitration decision circuit is enabled and arbitration is lost if conditions are satisfied. In this
case, the transmit/receive data which is not an address may be erroneously recognized as an
address.
In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may
occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order
below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Note: Above restrictions can be released by setting the bits FNC1 and FNC2 in ICXR to B'11.
Rev. 2.00 Aug. 20, 2008 Page 664 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Section 19 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC includes three register sets, each of which comprises data and status registers, control
register, the fast Gate A20 logic circuit, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC
module supports I/O read and I/O write cycle transfers. It is also provided with power-down
functions that can control the PCI clock and shut down the LPC interface.
19.1
Features
• Supports LPC interface I/O read and I/O write cycles
 Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
 Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Three register sets comprising data and status registers
 The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
 I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 3.
 A fast Gate A20 function is provided for channel 1.
 For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to
the basic register set.
• Supports SCIF
 The LPC interface is connected to the SCIF, allowing direct control of the SCIF by the
LPC host.
Rev. 2.00 Aug. 20, 2008 Page 665 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
• Supports SERIRQ
 Host interrupt requests are transferred serially on a single signal line (SERIRQ).
 On channel 1, HIRQ1 and HIRQ12 can be generated.
 On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
 In the SCIF, SMI, and HIRQ1 to HIRQ15 can be generated.
 Operation can be switched between quiet mode and continuous mode.
 The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
• Power-down modes and interrupts
 The LPC module can be shut down by inputting the LPCPD signal.
 Three pins, PME, LSMI, and LSCI, are provided for general input/output.
• Supports version 1.5 of the Intelligent Platform Management Interface (IPMI) specifications
 Channel 3 supports the SMIC interface, KCS interface, and BT interface.
Rev. 2.00 Aug. 20, 2008 Page 666 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Figure 19.1 shows a block diagram of the LPC.
Module data bus
BTDTR
FIFO
(IN)
TWR0MW
IDR3
Parallel → serial conversion
SERIRQ
IDR2
TWR1 to
TWR15
IDR1
SIRQCR0 to 5
CLKRUN
HISEL
Cycle detection
Serial → parallel conversion
LPCPD
Control logic
LFRAME
Address match
LAD0 to
LAD3
LRESET
LCLK
LSCIE
LSCIB
LSCI input
LADR12
LSCI
LADR1
LSMIE
LSMIB
LSMI input
LADR2
LADR3
Serial ← parallel conversion
LSMI
PMEE
PMEB
PME input
PME
SYNC output
ODR3
BTDTR
FIFO
(OUT)
TWR0SW
TWR1 to
TWR15
ODR2
HICR0 to HICR5
ODR1
GA20
STR3
STR2
STR1
Internal interrupt
control
[Legend]
HICR0 to HICR5:
LADR12H, LADR12L:
LADR3H, LADR3L:
IDR1 to IDR3:
ODR1 to ODR3:
STR1 to STR3:
Host interface control registers 0 to 5
LPC channel 1, 2 address registers 12H and 12L
LPC channel 3 address registers 3H and 3L
Input data registers 1 to 3
Output data registers 1 to 3
Status registers 1 to 3
OBEI
IBFI1
IBFI2
IBFI3
ERRI
TWR0MW:
TWR0SW:
TWR1 to TWR15:
SIRQCR0 to SIRQCR5:
HISEL:
Bidirectional data register 0MW
Bidirectional data register 0SW
Bidirectional data registers 1 to 15
SERIRQ control registers 0 to 5
Host interface select register
Figure 19.1 Block Diagram of LPC
Rev. 2.00 Aug. 20, 2008 Page 667 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.2
Input/Output Pins
Table 19.1 lists the LPC pin configuration.
Table 19.1 Pin Configuration
Name
Abbreviation
Port
I/O
Function
LPC address/
data 3 to 0
LAD3 to LAD0 PE to PE0 I/O
LPC frame
LFRAME
PE4
Input*
1
Transfer cycle start and forced
termination signal
LPC reset
LRESET
PE5
Input*
1
LPC interface reset signal
LPC clock
LCLK
PE6
Input
1
Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
33-MHz PCI clock signal
Serialized
interrupt request
SERIRQ
PE7
I/O*
LSCI general
output
LSCI
PD0
Output* *
LSMI general
output
LSMI
PD1
Output* *
PME general
output
PME
PD2
Output* *
GATE A20
GA20
PD3
Output* *
LPC clock run
CLKRUN
PD4
I/O* *
LPC power-down
LPCPD
PD5
Input*
1,
Serialized host interrupt request
signal (SMI, HIRQ1 to HIRQ15) in
synchronization with LCLK
2
1
1,
2
General output
1,
2
General output
1,
2
General output
1,
2
Gate A20 control signal output
LCLK restart request signal when
serial host interrupt is requested
LPC module shutdown signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
Rev. 2.00 Aug. 20, 2008 Page 668 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3
Register Descriptions
The LPC has the following registers.
• Host interface control register 0 (HICR0)
• Host interface control register 1 (HICR1)
• Host interface control register 2 (HICR2)
• Host interface control register 3 (HICR3)
• Host interface control register 4 (HICR4)
• Host interface control register 5 (HICR5)
• Pin function control register (PINFNCR)
• LPC channel 1, 2 address register H, L (LADR12H, LADR12L)
• LPC channel 3 address register H, L (LADR3H, LADR3L)
• Input data register 1 (IDR1)
• Input data register 2 (IDR2)
• Input data register 3 (IDR3)
• Output data register 1 (ODR1)
• Output data register 2 (ODR2)
• Output data register 3 (ODR3)
• Status register 1 (STR1)
• Status register 2 (STR2)
• Status register 3 (STR3)
• Bidirectional data registers 0 to 15 (TWR0 to TWR15)
• SERIRQ control register 0 (SIRQCR0)
• SERIRQ control register 1 (SIRQCR1)
• SERIRQ control register 2 (SIRQCR2)
• SERIRQ control register 3 (SIRQCR3)
• SERIRQ control register 4 (SIRQCR4)
• SERIRQ control register 5 (SIRQCR5)
• Host interface select register (HISEL)
• SCIF address register H, L (SCIFADRH, SCIFADRL)
Rev. 2.00 Aug. 20, 2008 Page 669 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
The following registers are necessary for SMIC mode
• SMIC flag register (SMICFLG)
• SMIC control/status register (SMICCSR)
• SMIC data register (SMICDTR)
• SMIC interrupt register 0 (SMICIR0)
• SMIC interrupt register 1 (SMICIR1)
The following registers are necessary for BT mode
• BT status register 0 (BTSR0)
• BT status register 1 (BTSR1)
• BT control/status register 0 (BTCSR0)
• BT control/status register 1 (BTCSR1)
• BT control register (BTCR)
• BT data buffer (BTDTR)
• BT interrupt mask register (BTIMSR)
• FIFO valid size register 0 (BTFVSR0)
• FIFO valid size register 1 (BTFVSR1)
Rev. 2.00 Aug. 20, 2008 Page 670 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.1
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
R/W
Bit
Bit Name
Initial
Value
7
LPC3E
0
R/W

LPC Enable 3 to 1
6
LPC2E
0
R/W

5
LPC1E
0
R/W

Enable or disable the LPC interface function. When
the LPC interface is enabled (one of the three bits is
set to 1), processing for data transfer between the
slave (this LSI) and the host is performed using pins
LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
Slave Host Description
•
LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, TWR0 to TWR15, SMIC, KCS, or BT
1: LPC channel 3 operation is enabled
•
LPC2E
0: LPC channel 2 operation is disabled
No address (LADR2) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
•
LPC1E
0: LPC channel 1 operation is disabled
No address (LADR1) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled
Rev. 2.00 Aug. 20, 2008 Page 671 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
4
FGA20E
0
R/W
Slave Host Description
R/W

Fast Gate A20 Function Enable
Enables or disables the fast Gate A20 function. The
PD3DDR bit should be cleared to 0 when the LPC is
used. With the fast Gate A20 disabled, the normal
Gate A20 can be implemented by firmware controlling
PD3 output.
0: Fast Gate A20 function disabled
General I/O function of pin PD3 is enabled
The internal state of GA20 output is initialized to 1
1: Fast Gate A20 function enabled
GA20 pin output is open-drain (external pull-up
resistor (Vcc) required)
3
SDWNE
0
R/W

LPC Software Shutdown Enable
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of initialization
by an LPC reset and an LPC shutdown, see section
19.4.6, LPC Interface Shutdown Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
•
Writing 0
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown release (rising edge of
LPCPD signal)
1: LPC hardware shutdown state setting enabled
Hardware shutdown state when LPCPD signal is
low level
[Setting condition]
Writing 1 after reading SDWNE = 0
Rev. 2.00 Aug. 20, 2008 Page 672 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
2
PMEE
0
R/W
Slave Host Description
R/W

PME Output Enable
Controls PME output in combination with the PMEB bit
in HICR1. PME pin output is open-drain, and an
external pull-up resistor (Vcc) is needed. The PD2DDR
bit should be cleared to 0 when the LPC is used.
1
LSMIE
0
R/W

PMEE
PMEB
0
X
: PME output disabled; general I/O
function of pin PD2 is enabled
1
0
: PME output enabled, PME pin
output goes to 0 level
1
1
: PME output enabled, PME pin
output is high-impedance
LSMI output Enable
Controls LSMI output in combination with the LSMIB
bit in HICR1. LSMI pin output is open-drain, and an
external pull-up resistor (Vcc) is needed. The PD1DDR
bit should be cleared to 0 when the LPC is used.
LSMIE
LSMIB
0
X
: LSMI output disabled; general I/O
function of pin PD1 is enabled
1
0
: LSMI output enabled, LSMI pin
output goes to 0 level
1
1
: LSMI output enabled, LSMI pin
output is Hi-Z
Rev. 2.00 Aug. 20, 2008 Page 673 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
0
LSCIE
0
R/W
Slave Host Description
R/W

LSCI output Enable
Controls LSCI output in combination with the LSCIB bit
in HICR1. LSCI pin output is open-drain, and an
external pull-up resistor (Vcc) is needed. The PD0DDR
bit should be cleared to 0 when the LPC is used.
[Legend]
X:
Don't care
Rev. 2.00 Aug. 20, 2008 Page 674 of 1198
REJ09B0403-0200
LSCIE
LSCIB
0
X
: LSCI output disabled; general I/O
function of pin PD0 is enabled
1
0
: LSCI output enabled, LSCI pin
output goes to 0 level
1
1
: LSCI output enabled, LSCI pin
output is high-impedance
Section 19 LPC Interface (LPC)
• HICR1
Bit
Bit Name
Initial
Value
7
LPCBSY
0
R/W
Slave Host Description
R

LPC Busy
Indicates that the LPC interface is processing a
transfer cycle.
0: LPC interface is in transfer cycle wait state
•
Bus idle, or transfer cycle not subject to processing
is in progress
•
Cycle type or address indeterminate during transfer
cycle
[Clearing conditions]
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown or LPC software
shutdown
•
Forced termination (abort) of transfer cycle subject
to processing
•
Normal termination of transfer cycle subject to
processing
1: LPC interface is performing transfer cycle
processing
[Setting condition]
Match of cycle type and address
Rev. 2.00 Aug. 20, 2008 Page 675 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
6
CLKREQ
0
R/W
Slave Host Description
R

LCLK Request
Indicates that the LPC interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown or LPC software shutdown
•
SERIRQ is set to continuous mode
•
There are no further interrupts for transfer to the
host in quiet mode
1: LCLK restart request issued
[Setting condition]
In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped
5
IRQBSY
0
R

SERIRQ Busy
Indicates that the LPC interface's SERIRQ is engaged
in transfer processing.
0: SERIRQ transfer frame wait state
[Clearing conditions]
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown or LPC software shutdown
•
End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress
[Setting condition]
Start of SERIRQ transfer frame
Rev. 2.00 Aug. 20, 2008 Page 676 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
4
LRSTB
0
R/W
Slave Host Description
R/W

LPC Software Reset Bit
Resets the LPC interface. For the scope of initialization
by an LPC reset, see section 19.4.6, LPC Interface
Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
•
Writing 0
•
LPC hardware reset
1: LPC software reset state
[Setting condition]
Writing 1 after reading LRSTB = 0
3
SDWNB
0
R/W

LPC Software Shutdown Bit
Controls LPC interface shutdown. For details of the
LPC shutdown function, and the scope of initialization
by an LPC reset and an LPC shutdown, see section
19.4.6, LPC Interface Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
•
Writing 0
•
LPC hardware reset or LPC software reset
•
LPC hardware shutdown
•
LPC hardware shutdown release
(falling edge of LPCPD signal when SDWNE = 1)
(rising edge of LPCPD signal when SDWNE = 0)
1: LPC software shutdown state
[Setting condition]
Writing 1 after reading SDWNB = 0
2
PMEB
0
R/W

PME Output Bit
Controls PME output in combination with the PMEE
bit. For details, refer to description on the PMEE bit in
HICR0.
Rev. 2.00 Aug. 20, 2008 Page 677 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
1
LSMIB
0
R/W
Slave Host Description
R/W

LSMI Output Bit
Controls LSMI output in combination with the LSMIE
bit. For details, refer to description on the LSMIE bit in
HICR0.
0
LSCIB
0
R/W

LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit. For details, refer to description on the LSCIE bit in
HICR0.
Rev. 2.00 Aug. 20, 2008 Page 678 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.2
Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the
LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits
are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless
of the LPC interface operating state or the operating state of the functions that use pin
multiplexing.
• HICR2
R/W
Bit
Bit Name
Initial
Value
7
GA20
Undefined R
6
LRST
0
Slave Host Description

R/(W)* 
GA20 Pin Monitor
LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
5
SDWN
0
R/(W)* 
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
•
Writing 0 after reading SDWN = 1
•
LPC hardware reset
•
LPC software reset (LRSTB = 1)
(LRESET pin falling edge detection)
1: [Setting condition]
LPCPD pin falling edge detection
Rev. 2.00 Aug. 20, 2008 Page 679 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
4
ABRT
0
R/W
Slave
Host Description
R/(W)* 
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
•
Writing 0 after reading ABRT = 1
•
LPC hardware reset
•
LPC software reset (LRSTB = 1)
•
LPC hardware shutdown
(LRESET pin falling edge detection)
(SDWNE = 1 and LPCPD pin falling edge
detection)
•
LPC software shutdown (SDWNB = 1)
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
3
IBFIE3
0
R/W

IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register (IDR3) and TWR receive
complete interrupt requests and SMIC/BT mode
interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive complete
interrupt requests and SMIC/BT mode
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests and SMIC/BT
mode interrupt requests enabled
Rev. 2.00 Aug. 20, 2008 Page 680 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
2
IBFIE2
0
R/W
Slave Host Description
R/W

IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled
1
IBFIE1
0
R/W

IDR1 Receive Complete interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled
0
ERRIE
0
R/W

Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note:
*
Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
R/W
Bit
Bit Name Initial Value Slave Host Description
7
LFRAME Undefined
R

LFRAME Pin Monitor
6
CLKRUN Undefined
R

CLKRUN Pin Monitor
5
SERIRQ
Undefined
R

SERIRQ Pin Monitor
4
LRESET
Undefined
R

LRESET Pin Monitor
3
LPCPD
Undefined
R

LPCPD Pin Monitor
2
PME
Undefined
R

PME Pin Monitor
1
LSMI
Undefined
R

LSMI Pin Monitor
0
LSCI
Undefined
R

LSCI Pin Monitor
Rev. 2.00 Aug. 20, 2008 Page 681 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.3
Host Interface Control Register 4 (HICR4)
HICR4 controls the operation of the KCS, SMIC, and BT interface functions on channel 3.
Initial
Value
Bit
Bit Name
7
LADR12SEL 0
R/W
Slave Host Description
R/W

Switches the channel accessed via LADR12H and
LADR12L.
0: LADR1 is selected
1: LADR2 is selected
6 to 4

All 0
R/W

Reserved
The initial value should not be changed.
3
SWENBL
0
R/W

In BT mode, H'5 (short wait) or H'6 (long wait) is
returned to the host in the synchronized return
cycle from slave, thus can make the host wait.
0: Short wait is issued
1: Long wait is issued
2
KCSENBL
0
R/W

Enables or disables the use of the KCS interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: KCS interface operation is disabled
No address (LADR3) matches for IDR3, ODR3,
or STR3 in KCS mode
1: KCS interface operation is enabled
Rev. 2.00 Aug. 20, 2008 Page 682 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name
Initial Value Slave Host Description
1
SMICENBL
0

R/W
Enables or disables the use of the SMIC interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: SMIC interface operation is disabled
No address (LADR3) matches for SMICFLG,
SSMICCSR, or SMICDTR
1: SMIC interface operation is enabled
0
BTENBL
0

R/W
Enables or disables the use of the BT interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: BT interface operation is disabled
No address (LADR3) matches for BTIMSR,
BTCR, or BTDTR
1: BT interface operation is enabled
19.3.4
Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
R/W
Initial
Value
Slave Host Description
7 to 2 
All 0
R/W

Reserved
The initial value bit should not be changed.
1
SCIFE
0
R/W

0

0
R/W

SCIF Enable
Enables or disables access from the LPC host of
the SCIF.
0: Disables access to the SCIF from the LPC host
1: Enables access to the SCIF from the LPC host
Reserved
The initial value should not be changed.
Bit
Bit Name
Rev. 2.00 Aug. 20, 2008 Page 683 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.5
Pin Function Control Register (PINFNCR)
PINFNCR selects whether the pins of the associated port are used for the LPC function or general
I/O.
R/W
Initial
Value
Slave Host Description
7 to 3 
All 0
R/W

Reserved
The initial value bit should not be changed.
2
SERIRQOFF
0
R/W

0: SERIRQ pin
1: General I/O port
1
LPCPDOFF
0
R/W

0
CLKRUNOFF 0
R/W

0: LPCPD pin
1: General I/O port
0: CLKRUN pin
1: General I/O port
Bit
Bit Name
19.3.6
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 19.2 shows the initial value of each register. Table 19.3 shows the host register selection in
address match determination. Table 19.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 19.2 LADR1, LADR2 Initial Values
Register Name
Initial Value
Description
LADR1
H'0060
I/O address of channel 1
LADR2
H'0062
I/O address of channel 2
Rev. 2.00 Aug. 20, 2008 Page 684 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Table 19.3 Host Register Selection
I/O Address
Bits 15 to 3
Bit 2 Bit 1
Transfer
Cycle
Bit 0
Host Register Selection
LADR1 (bits 15 to 3) 0
LADR1 (bit 1)
LADR1 (bit 0) I/O write
IDR1 write (data),
C/D1 ← 0
LADR1 (bits 15 to 3) 1
LADR1 (bit 1)
LADR1 (bit 0) I/O write
IDR1 write (command),
C/D1 ← 1
LADR1 (bits 15 to 3) 0
LADR1 (bit 1)
LADR1 (bit 0) I/O read
ORD1 read
LADR1 (bits 15 to 3) 1
LADR1 (bit 1)
LADR1 (bit 0) I/O read
STR1 read
LADR2 (bits 15 to 3) 0
LADR2 (bit 1)
LADR2 (bit 0) I/O write
IDR2 write (data),
C/D2 ← 0
LADR2 (bits 15 to 3) 1
LADR2 (bit 1)
LADR2 (bit 0) I/O write
IDR2 write (command),
C/D2 ← 1
LADR2 (bits 15 to 3) 0
LADR2 (bit 1)
LADR2 (bit 0) I/O read
ODR2 read
LADR2 (bits 15 to 3) 1
LADR2 (bit 1)
LADR2 (bit 0) I/O read
STR2 read
Table 19.4 Slave Selection Internal Registers
Slave (R/W) Bus Width (B/W) LADR12SEL
LADR12
Internal Register
R/W
B
0
LADR12H
LADR1H
R/W
B
1
LADR12H
R/W
B
0
LADR12L
LADR1L
R/W
B
1
LADR12L
LADR2L
R/W
W
0
LADR12H
LADR12L
LADR1H
LADR1L
R/W
W
1
LADR12H
LADR12L
LADR2H
LADR2L
LADR2H
Rev. 2.00 Aug. 20, 2008 Page 685 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.7
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
R/W
Bit
Bit Name Initial Value Slave Host
7
Bit 15
6
5
Bit 14
Bit 13
4
3
Bit 12
Bit 11
2
1
Bit 10
Bit 9
0
Bit 8
All 0

R/W
Description
Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
• LADR3L
R/W
Bit
Bit Name
Initial
Value
7
Bit 7
All 0
6
5
Bit 6
Bit 5
4
3
Bit 4
Bit 3
2

0
R/W

1
Bit 1
0
R/W

0
TWRE
0
R/W

Slave Host
R/W

Description
Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
Reserved
The initial value should not be changed.
Channel 3 Address Bit 1
The host address of LPC channel 3 is set.
Bidirectional data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
TWR-related address (LADR3) match does not
occur.
1: TWR operation is enabled
Rev. 2.00 Aug. 20, 2008 Page 686 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3,
ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address
match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of
bits 3 to 0 are ignored.
Register selection according to the bits ignored in address match determination is as shown in the
following table.
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register
Selection
Bits 15 to5
Bit 4
Bit 3
0
Bit 1
0
I/O write
IDR3 write, C/D3 ← 0
Bits 15 to5
Bit 4
Bit 3
1
Bit 1
0
I/O write
IDR3 write, C/D3 ← 1
Bits 15 to5
Bit 4
Bit 3
0
Bit 1
0
I/O read
ODR3 read
Bits 15 to5
Bit 4
Bit 3
1
Bit 1
0
I/O read
STR3 read
Bits 15 to5
Bit 4
0
0
0
0
I/O write
TWR0MW write
Bits 15 to5
Bit 4
0
0
0
1
I/O write
TWR1 to TWR15
write
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
Bits 15 to5
Bit 4
0
0
0
0
I/O read
TWR0SW read
Bits 15 to5
Bit 4
0
0
0
1
I/O read
TWR1 to TWR15
read
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
Rev. 2.00 Aug. 20, 2008 Page 687 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
• KCS mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
0
0
1
0
I/O write
IDR3 write, C/D3 ← 0
Bits 15 to5
Bit 4
0
0
1
1
I/O write
IDR3 write, C/D3 ← 1
Bits 15 to5
Bit 4
0
0
1
0
I/O read
ODR3 read
Bits 15 to5
Bit 4
0
0
1
1
I/O read
STR3 read
• BT mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
0
1
0
0
I/O write
BTCR write
Bits 15 to5
Bit 4
0
1
0
1
I/O write
BTDTR write
Bits 15 to5
Bit 4
0
1
1
0
I/O write
BTIMSR write
Bits 15 to5
Bit 4
0
1
0
0
I/O read
BTCR read
Bits 15 to5
Bit 4
0
1
0
1
I/O read
BTDTR read
Bits 15 to5
Bit 4
0
1
1
0
I/O read
BTIMSR read
• SMIC mode
I/O Address
Bits 15 to5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transfer
Cycle
Host Register Selection
Bits 15 to5
Bit 4
1
0
0
1
I/O write
SMICDTR write
Bits 15 to5
Bit 4
1
0
1
0
I/O write
SMICCSR write
Bits 15 to5
Bit 4
1
0
1
1
I/O write
SMICFLG write
Bits 15 to5
Bit 4
1
0
0
1
I/O read
SMICDTR read
Bits 15 to5
Bit 4
1
0
1
0
I/O read
SMICCSR read
Bits 15 to5
Bit 4
1
0
1
1
I/O read
SMICFLG read
Rev. 2.00 Aug. 20, 2008 Page 688 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.8
Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit writeonly registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on IDR1 and IDR2 selection, see
section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on IDR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers are undefined.
19.3.9
Output Data Registers 0 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor (this LSI), and 8-bit
read-only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on ODR1 and ODR2 selection, see
section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on ODR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to
the host.
The initial values of the ODR registers are undefined.
Rev. 2.00 Aug. 20, 2008 Page 689 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register to the host processor, and a read-only register to the slave processor, while
TWR0SW is a write-only register to the slave processor and a read-only register to the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host.
The initial values of TWR0 to TWR15 are undefined.
Rev. 2.00 Aug. 20, 2008 Page 690 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.11 Status Registers 1 to 3 (STR1 to STR3)
The STR registers are 8-bit registers that indicate status information during LPC interface
processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the
slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to
bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0. The functions for
bits 7 to 4 in STR3 differ according to the settings of bit SELSTR3 in HISEL and the TWRE bit in
LADR3L. For details, see section 19.3.18, Host Interface Select Register (HISEL). The registers
selected from the host processor according to the I/O address are described in the following
sections. For information on STR1 and STR2 selection, see section 19.3.6, LPC Channel 1, 2
Address Register H, L (LADR12H, LADR12L), and information on STR3 selection, see section
19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle,
the data in the selected register is transferred to the host processor.
The STR registers are initialized to H'00 by a reset or in hardware standby mode.
• STR1
R/W
Bit
Bit Name Initial Value Slave Host Description
7
DBU17
6
DBU16
5
DBU15
4
DBU14
3
C/D1
All 0
R/W
R
Defined by User
The user can use these bits as necessary.
0
R
R
Command/Data
When the host processor writes to an IDR1 register,
bit 2 of the I/O address (when CH1OFFSEL1 = 0) or
bit 0 of the I/O address (when CH1OFFSEL1 = 1) is
written to this bit to indicate whether IDR1 contains
data or a command.
0: Content of input data register (IDR1) is data
1: Content of input data register (IDR1) is a
command
2
DBU12
0
R/W
R
Defined by User
The user can use this bit as necessary.
Rev. 2.00 Aug. 20, 2008 Page 691 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IBF1
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR1. This bit is an internal interrupt source to the
slave processor (this LSI).
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 19.7.
0: There is not receive data in IDR1
[Clearing condition]
When the slave processor reads IDR
1: There is receive data in IDR1
[Setting condition]
When the host processor writes to IDR using I/O
write cycle
0
OBF1
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR1.
0: There is not transmit data in ODR1
[Clearing condition]
When the host processor reads ODR1 using I/O
read cycle, or the slave processor writes 0 to the
OBF1 bit
1: There is transmit data in ODR1
[Setting condition]
When the slave processor writes to ODR1
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 692 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
•
STR2
R/W
Bit
Bit Name Initial Value Slave Host Description
7
DBU27
0
R/W
R
Defined by User
6
DBU26
0
R/W
R
The user can use these bits as necessary.
5
DBU25
0
R/W
R
4
DBU24
0
R/W
R
3
C/D2
0
R
R
Command/Data
When the host writes to IDR2, bit 2 of the I/O
address (when CH2OFFSEL1 = 0) or bit 0 of the I/O
address (when CH2OFFSEL1 = 1) is written to this
bit to indicate whether IDR2 contains data or a
command.
0: Content of input data register (IDR2) is a data
1: Content of input data register (IDR2) is a
command
2
DBU22
0
R/W
R
Defined by User
The user can use this bit as necessary.
1
IBF2
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR2.
This bit is an internal interrupt source to the slave
(this LSI).
0: There is not receive data in IDR2
[Clearing condition]
When the slave reads IDR2
1: There is receive data in IDR2
[Setting condition]
When the host writes to IDR2 in an I/O write cycle
Rev. 2.00 Aug. 20, 2008 Page 693 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
0
OBF2
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR2.
0: There is not transmit data in ODR2
[Clearing conditions]
•
•
When the host reads ODR2 in an I/O read
cycle
When the slave writes 0 to bit OBF2
1: There is transmit data in ODR2
[Setting condition]
•
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 694 of 1198
REJ09B0403-0200
When the slave writes to ODR2
Section 19 LPC Interface (LPC)
• STR3 (TWRE = 1 or SELSTR3 = 0)
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IBF3B
0
R
R
Bidirectional Data Register Input Buffer Full Flag
This is an internal interrupt source to the slave (this
LSI).
0: [Clearing condition]
When the slave reads TWR15
1: [Setting condition]
When the host writes to TWR15 in I/O write cycle
6
OBF3B
0
R/(W)* R
Bidirectional Data Register Output Buffer Full Flag
0: [Clearing conditions]
•
When the host reads TWR15 in I/O read cycle
•
When the slave writes 0 to the OBF3B bit
1: [Setting condition]
When the slave writes to TWR15
5
MWMF
0
R
R
Master Write Mode Flag
0: [Clearing condition]
When the slave reads TWR15
1: [Setting condition]
When the host writes to TWR0 in I/O write cycle
while SWMF = 0
4
SWMF
0
R/(W)* R
Slave Write Mode Flag
In the event of simultaneous writes by the master
and the slave, the master write has priority.
0: [Clearing conditions]
•
When the host reads TWR15 in I/O read cycle
•
When the slave writes 0 to the SWMF bit
1: [Setting condition]
When the slave writes to TWR0 while MWMF = 0
Rev. 2.00 Aug. 20, 2008 Page 695 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave
Host Description
3
C/D3
R
0
R
Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
2
DBU32
0
R/W
R
Defined by User
The user can use this bit as necessary.
1
IBF3A
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host writes to IDR3 in an I/O write cycle
0
OBF3A
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not transmit data in ODR3
[Clearing conditions]
•
When the host reads ODR3 in an I/O
read cycle
•
When the slave writes 0 to bit OBF3A
1: There is transmit data in ODR3
[Setting condition]
•
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 696 of 1198
REJ09B0403-0200
When the slave writes to ODR3
Section 19 LPC Interface (LPC)
• STR3 (TWRE = 0 and SELSTR3 = 1)
R/W
Bit
Bit Name Initial Value Slave Host Description
7
DBU37
0
R/W
R
Defined by User
6
DBU36
0
R/W
R
The user can use these bits as necessary.
5
DBU35
0
R/W
R
4
DBU34
0
R/W
R
3
C/D3
0
R
R
Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
2
DBU32
0
R/W
R
Defined by User
The user can use this bit as necessary.
1
IBF3A
0
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This bit is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host writes to IDR3 in an I/O write cycle
Rev. 2.00 Aug. 20, 2008 Page 697 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
0
OBF3A
0
R/(W)* R
Output Data Register Full
Indicates whether or not there is transmit data in
ODR3.
0: There is not receive data in ODR3
[Clearing conditions]
• When the host reads ODR3 in an I/O read
cycle
• When the slave writes 0 to bit OBF3A
1: There is receive data in ODR3
[Setting condition]
• When the slave writes to ODR3
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 698 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.12
SERIRQ Control Register 0 (SIRQCR0)
SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
R/W
Bit
Bit Name Initial Value Slave Host Description
7
Q/C
0
R

Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
•
LPC hardware reset, LPC software reset
•
Specification by SERIRQ transfer cycle stop
frame
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
6
SELREQ 0
R/W

Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all
interrupt requests are cleared
1: Start frame initiation is requested when one or
more interrupt requests are cleared
5
IEDIR2
0
R/W

Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable and corresponding OBF bits are both set to
1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
Rev. 2.00 Aug. 20, 2008 Page 699 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
4
SMIE3B
0
R/W

Host SMI Interrupt Enable 3B
Enables or disables an SMI interrupt request when
OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and
SMIE3B is disabled
[Clearing conditions]
•
Writing 0 to SMIE3B
•
LPC hardware reset, LPC software reset
•
Clearing OBF3B to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting OBF3B to 1
is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3B = 0
3
SMIE3A
0
R/W

Host SMI Interrupt Enable 3A
Enables or disables an SMI interrupt request when
OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and
SMIE3A is disabled
[Clearing conditions]
•
Writing 0 to SMIE3A
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3A = 0
Rev. 2.00 Aug. 20, 2008 Page 700 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
2
SMIE2
0
R/W

Host SMI Interrupt Enable 2
Enables or disables an SMI interrupt request when
OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
•
Writing 0 to SMIE2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
Host SMI interrupt request by setting OBF2 to 1
is enabled
[When IEDIR2 = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE2 = 0
1
IRQ12E1 0
R/W

Host IRQ12 Interrupt Enable 1
Enables or disables an HIRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ12 interrupt request by OBF1 and IRQ12E1
is disabled
[Clearing conditions]
•
Writing 0 to IRQ12E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ12 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
Writing 1 after reading IRQ12E1 = 0
Rev. 2.00 Aug. 20, 2008 Page 701 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
0
IRQ1E1
0
R/W

Host IRQ1 Interrupt Enable 1
Enables or disables a host HIRQ1 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ1E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
Writing 1 after reading IRQ1E1 = 0
Rev. 2.00 Aug. 20, 2008 Page 702 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.13 SERIRQ Control Register 1 (SIRQCR1)
SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IRQ11E3 0
R/W

Host IRQ11 Interrupt Enable 3
Enables or disables an HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
IRQE11E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ11E3 = 0
6
IRQ10E3 0
R/W

Host IRQ10 Interrupt Enable 3
Enables or disables an HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
IRQE10E3 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ10E3 = 0
Rev. 2.00 Aug. 20, 2008 Page 703 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
5
IRQ9E3
0
R/W

Host IRQ9 Interrupt Enable 3
Enables or disables an HIRQ9 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ9 interrupt request by OBF3A and IRQE9E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ9 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ9 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ9E3 = 0
4
IRQ6E3
0
R/W

Host IRQ6 Interrupt Enable 3
Enables or disables an HIRQ6 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ6 interrupt request by OBF3A and IRQE6E3
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E3
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ6 interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR3 = 1]
HIRQ6 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ6E3 = 0
Rev. 2.00 Aug. 20, 2008 Page 704 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
3
IRQ11E2 0
R/W

Host IRQ11 Interrupt Enable 2
Enables or disables an HIRQ11 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ11 interrupt request by OBF2 and
IRQE11E2 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ11 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ11E2 = 0
2
IRQ10E2 0
R/W

Host IRQ10 Interrupt Enable 2
Enables or disables an HIRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ10 interrupt request by OBF2 and
IRQE10E2 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ10 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ10E2 = 0
Rev. 2.00 Aug. 20, 2008 Page 705 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
1
IRQ9E2
0
R/W

Host IRQ9 Interrupt Enable 2
Enables or disables an HIRQ9 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ9 interrupt request by OBF2 and IRQE9E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ9 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ9E2 = 0
0
IRQ6E2
0
R/W

Host IRQ6 Interrupt Enable 2
Enables or disables an HIRQ6 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ6 interrupt request by OBF2 and IRQE6E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ6 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ6E2 = 0
Rev. 2.00 Aug. 20, 2008 Page 706 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.14 SERIRQ Control Register 2 (SIRQCR2)
SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host
interrupt request outputs.
R/W
Bit
Bit Name Initial Value Slave Host Description
7
IEDIR3
0
R/W

Interrupt Enable Direct Mode 3
Selects whether an SERIRQ interrupt generation of
LPC channel 3 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the
enable bit.
0: A host interrupt is generated when both the
enable bit and the corresponding OBF flag are
set
1: A host interrupt is generated when the enable bit
is set
6 to 0 
All 0
R/W

Reserved
The initial value should not be changed.
Rev. 2.00 Aug. 20, 2008 Page 707 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.15 SERIRQ Control Register 3 (SIRQCR3)
SIRQCR3 selects the SERIRQ interrupt requests of the SCIF.
R/W
Initial
Value
Slave Host Description
7 to 4 
All 0
R/W

3
SCSIRQ3
0
R/W

SCIF SERIRQ Interrupt Select
2
SCSIRQ2
0
R/W

1
SCSIRQ1
0
R/W

These bits select the SCIF interrupt request to the
host.
0
SCSIRQ0
0
R/W

0000: No interrupt request to the host
Bit
Bit Name
Reserved
The initial value should not be changed.
0001: HIRQ1
0010: SMI
0011: HIRQ3
0100: HIRQ4
0101: HIRQ5
0110: HIRQ6
0111: HIRQ7
1000: HIRQ8
1001: HIRQ9
1010: HIRQ10
1011: HIRQ11
1100: HIRQ12
1101: HIRQ13
1110: HIRQ14
1111: HIRQ15
Rev. 2.00 Aug. 20, 2008 Page 708 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.16 SERIRQ Control Register 4 (SIRQCR4)
SIRQCR4 controls LPC interrupt requests to the host.
Bit
Bit Name
Initial
Value
7
IRQ15E
0
R/W
Slave Host Description
R/W

Host IRQ15 Interrupt Enable
0: Disables HIRQ15 interrupt request by IRQ15E
1: Enables HIRQ15 interrupt request
6
IRQ14E
0
R/W

Host IRQ14 Interrupt Enable
0: Disables HIRQ14 interrupt request by IRQ14E
1: Enables HIRQ14 interrupt request
5
IRQ13E
0
R/W

Host IRQ13 Interrupt Enable
0: Disables HIRQ13 interrupt request by IRQ13E
1: Enables HIRQ13 interrupt request
4
IRQ8E
0
R/W

Host IRQ8 Interrupt Enable
0: Disables HIRQ8 interrupt request by IRQ8E
1: Enables HIRQ8 interrupt request
3
IRQ7E
0
R/W

Host IRQ7 Interrupt Enable
0: Disables HIRQ7 interrupt request by IRQ7E
1: Enables HIRQ7 interrupt request
2
IRQ5E
0
R/W

Host IRQ5 Interrupt Enable
0: Disables HIRQ5 interrupt request by IRQ5E
1: Enables HIRQ5 interrupt request
1
IRQ4E
1
R/W

Host IRQ4 Interrupt Enable
0: Disables HIRQ4 interrupt request by IRQ4E
1: Enables HIRQ4 interrupt request
0
IRQ3E
1
R/W

Host IRQ3 Interrupt Enable
0: Disables HIRQ3 interrupt request by IRQ3E
1: Enables HIRQ3 interrupt request
Rev. 2.00 Aug. 20, 2008 Page 709 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.17 SERIRQ Control Register 5 (SIRQCR5)
SIRQCR5 selects the output of the host interrupt request signal of each frame.
R/W
Bit
Bit Name
Initial
Value
7
SELIRQ15
0
R/W

SERIRQ Output Select
6
SELIRQ14
0
R/W

5
SELIRQ13
0
R/W

4
SELIRQ8
0
R/W

These bits select the state of the output on the pin for
LPC host interrupt requests (HIRQ15, HIRQ14,
HIRQ13, HIRQ8, HIRQ7, HIRQ5, HIRQ4, and
HIRQ3).
3
SELIRQ7
0
R/W

0: [When host interrupt request is cleared]
2
SELIRQ5
0
R/W

SERIRQ pin output is in the Hi-Z state
1
SELIRQ4
0
R/W

[When host interrupt request is set]
0
SELIRQ3
0
R/W

SERIRQ pin output is low
Slave Host Description
1: [When host interrupt request is cleared]
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.
Rev. 2.00 Aug. 20, 2008 Page 710 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.18 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt
request signal of each frame.
Bit
Bit Name
Initial
Value
7
SELSTR3
0
R/W
Slave Host Description
R/W

Status Register 3 Selection
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. For
details of STR3, see section 19.3.11, Status
Registers 1 to 3 (STR1 to STR3).
0: Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are readable/writable bits
which user can use as necessary
6
SELIRQ11
0
R/W

Host IRQ Interrupt Select
5
SELIRQ10
0
R/W

4
SELIRQ9
0
R/W

These bits select the state of the output on the
SERIRQ pin.
3
SELIRQ6
0
R/W

0: [When host interrupt request is cleared]
2
SELSMI
0
R/W

SERIRQ pin output is in the Hi-Z state
1
SELIRQ12
1
R/W

[When host interrupt request is set]
0
SELIRQ1
1
R/W

SERIRQ pin output is low
1: [When host interrupt request is cleared]
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.
Rev. 2.00 Aug. 20, 2008 Page 711 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.19 SCIF Address Register (SCIFADRH, SCIFADRL)
SCIFADR sets the host address for the SCIF. Do not change the contents of SCIFADR while the
SCIF is operating (i.e. while SCIFE is set to 1).
• SCIFADRH
R/W
Bit
Bit Name
Initial
Value
7

0
R/W

SCIF Address 15 to 8
6

0
R/W

These bits set the host address for the SCIF.
5

0
R/W

4

0
R/W

3

0
R/W

2

0
R/W

1

1
R/W

0

1
R/W

Slave Host Description
• SCIFADRL
R/W
Bit
Bit Name
Initial
Value
Slave Host Description
7

1
R/W

SCIF Address 7 to 0
6

1
R/W

These bits set the host address for the SCIF.
5

1
R/W

4

1
R/W

3

1
R/W

2

0
R/W

1

0
R/W

0

0
R/W

Note: When the SCIF is in use, SCIFADR must be set to an address that is different from those
for LPC channels 1, 2, and 3.
Rev. 2.00 Aug. 20, 2008 Page 712 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.20 SMIC Flag Register (SMICFLG)
SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that
indicate whether or not the system is ready to data transfer and those that are used for handshake
of the transfer cycles.
R/W
Bit Bit Name
Initial Value Slave Host Description
7
0
RX_DATA_RDY
R/W
R
Read Transfer Ready
Indicates whether or not the slave is ready for
the host read transfer.
0: Slave waits for ready status
1: Slave is ready for the host read transfer
6
TX_DATA_RDY
0
R/W
R
Write Transfer Ready
Indicates whether or not the slave is ready for
the host next write transfer.
0: The slave waits for ready status
1: The slave is ready for the host write
transfer.
5

0
R/W
R
Reserved
4
SMI
0
R/W
R
SMI Flag
The initial value should not be changed.
This bit indicates that the SMI is asserted.
0: Indicates waiting for SMI assertion
1: Indicates SMI assertion
3
SEVT_ATN
0
R/W
R
Event Flag
When the slave detects an event for the host,
this bit is set.
0: Indicates waiting for event detection
1: Indicates event detection
2
SMS_ATN
0
R/W
R
SMS Flag
When there is a message to be transmitted
from the slave to the host, this bit is set.
0: There is not a message
1: There is a message
Rev. 2.00 Aug. 20, 2008 Page 713 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
1

0
R/W
R
Reserved
The initial value should not be changed.
0
BUSY
0
R/(W)* W
SMIC Busy
This bit indicates that the slave is now transferring
data. This bit can be cleared only by the slave and
set only by the host.
The rising edge of this bit is a source of internal
interrupt to the slave.
0: Transfer cycle wait state
[Clearing conditions]
After the slave reads BUSY = 1, writes 0 to this bit.
1: Transfer cycle in progress
[Setting condition]
When the host writes 1 to this bit.
Note: Only 0 can be written to clear the flag.
19.3.21 SMIC Control Status Register (SMICCSR)
SMICCSR is one of the registers used to implement SMIC mode. This is an 8-bit
readable/writable register that stores a control code issued from the host and a status code that is
returned from the slave.
The control code is written to this register accompanied by the transfer between the host and slave.
The status code is returned to this register to indicate that the slave has recognized the control
code, and a specified transfer cycle has been completed.
19.3.22 SMIC Data Register (SMICDTR)
SMICDTR is one of the registers used to implement SMIC mode. This is an 8-bit register that is
accessible (readable/writable) from both the slave processor (this LSI) and host processor. This is
used for data transfer between the host and slave.
Rev. 2.00 Aug. 20, 2008 Page 714 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.23 SMIC Interrupt Register 0 (SMICIR0)
SMICIR0 is one of the registers used to implement SMIC mode. This register includes the bits that
indicate the source of interrupt to the slave.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
All 0
R/W

Reserved
The initial value should not be changed.
4
HDTWI
0
R/(W)* 
Transfer Data Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the transfer data to SMICDTR.
When the IBFIE3 bit and HDTWIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data transmission wait state
[Clearing condition]
After the slave reads HDTWI = 1, writes 0 to this bit.
1: Transfer data transmission end
[Setting condition]
The transfer cycle is write transfer and the host
writes the transfer data to SMICDTR.
3
HDTRI
0
R/(W)* 
Transfer Data Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the transfer data from SMICDTR.
When the IBFIE3 bit and HDTRIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data receive wait state
[Clearing condition]
After the slave reads HDTRI = 1, writes 0 to this bit.
1: Transfer data receive end
[Setting condition]
The transfer cycle is read transfer and the host
reads the transfer data from SMICDTR.
Rev. 2.00 Aug. 20, 2008 Page 715 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
2
STARI
0
R/(W)* 
Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
1
CTLWI
0
R/(W)* 
Control Code Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the control code to SMICCSR.
When the IBFIE3 bit and CTLWIE bit are set to1, the
IBFI3 interrupt is requested to the slave.
0: Control code transmission wait state
[Clearing condition]
After the slave reads CTLWI = 1, writes 0 to this bit.
1: Control code transmission end
[Setting condition]
When the host writes the status code to SMICCSR.
0
BUSYI
0
R/(W)* 
Transfer Start Interrupt
This is a status flag that indicates that the host starts
transferring. When the IBFIE3 bit and BUSYIE bit
are set to 1, the IBFI3 interrupt is requested to the
slave.
0: Transfer start wait state
[Clearing condition]
After the slave reads BUSYI = 1, writes 0 to this bit.
1: Transfer start
[Setting condition]
When the rising edge of the BUSY bit in SMICFLG is
detected.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 716 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.24 SMIC Interrupt Register 1 (SMICIR1)
SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that
enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit
in HICR2 to 1.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
4
All 0
HDTWIE 0
R/W

Reserved
The initial value should not be changed.
R/W

Transfer Data Transmission End Interrupt Enable
Enables or disables HDTWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data transmission end interrupt
1: Enables transfer data transmission end interrupt
3
HDTRIE
0
R/W

Transfer Data Receive End Interrupt Enable
Enables or disables HDTRI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data receive end interrupt
1: Enables transfer data receive end interrupt
2
STARIE
0
R/W

Status Code Receive End Interrupt Enable
Enables or disables STARI interrupt that is IBFI3
interrupt source to the slave.
0: Disables status code receive end interrupt
1: Enables status code receive end interrupt
1
CTLWIE
0
R/W

Control Code Transmission End Interrupt Enable
Enables or disables CTLWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables control code transmission end interrupt
1: Enables control code transmission end interrupt
0
BUSYIE
0
R/W

Transfer Start Interrupt Enable
Enables or disables BUSYI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer start interrupt
1: Enables transfer start interrupt
Rev. 2.00 Aug. 20, 2008 Page 717 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.25 BT Status Register 0 (BTSR0)
BTSR0 is one of the registers used to implement BT mode. This register includes flags that control
interrupts to the slave (this LSI).
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 5 
All 0
R/W

Reserved
The initial value should not be changed.
4
FRDI
0
R/(W)* 
FIFO Read Request Interrupt
This status flag indicates that host writes the data to
BTDTR buffer with FIFO full state at the host write
transfer. When the IBFIE3 bit and FRDIE bit are set
to 1, IBFI3 interrupt is requested to the slave. The
slave must clear the flag after creating an unused
area by reading the data in FIFO.
0: FIFO read is not requested
[Clearing condition]
After the slave reads FRDI = 1, writes 0 to this bit.
1: FIFO read is requested
[Setting condition]
After the host processor transfers data, the host
writes the data with FIFO Full state.
3
HRDI
0
R/(W)* 
BT Host Read Interrupt
This status flag indicates that the host reads 1 byte
from BTDTR buffer. When the IBFIE3 bit and HRDIE
bit are set to 1, IBFI3 interrupt is requested to the
slave.
0: Host BTDTR read wait state
[Clearing condition]
After the slave reads HRDI = 1, writes 0 to this bit.
1: The host reads from BTDTR
[Setting condition]
The host reads one byte from BTDTR.
Rev. 2.00 Aug. 20, 2008 Page 718 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
2
HWRI
0
R/(W)* 
BT Host Write Interrupt
This status flag indicates that the host writes 1byte
to BTDTR buffer. When the IBFIE3 bit and HWRIE
bit are set to 1, IBFI3 interrupt is requested to the
slave.
0: Host BTDTR write wait state
[Clearing condition]
After the slave reads HWRI = 1, writes 0 to this bit.
1: The host writes to BTDTR
[Setting condition]
The host writes one byte to BTDTR.
1
HBTWI
0
R/(W)* 
BTDTR Host Write Start Interrupt
This status flag indicates that the host writes the first
byte of valid data to BTDTR buffer. When the IBFIE3
bit and HBTWIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: BTDTR host write start wait state
[Clearing condition]
After the slave reads HBTWI = 1 and writes 0 to this
bit.
1: BTDTR host write start
[Setting condition]
The host starts writing valid data to BTDTR.
Rev. 2.00 Aug. 20, 2008 Page 719 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
R/W
Bit
Bit Name Initial Value Slave Host Description
0
HBTRI
0
R/(W)* 
BTDTR Host Read End Interrupt
This status flag indicates that the host reads all valid
data from BTDTR buffer. When the BFIE3 bit and
HBTRIE bit are set to 1, IBFI3 interrupt is requested
to the slave.
0: BTDTR host read end wait state
[Clearing condition]
After the slave reads HBTRI = 1 and writes 0 to this
bit.
1: BTDTR host read end
[Setting condition]
When the host finished reading the valid data from
BTDTR.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 720 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.26 BT Status Register 1 (BTSR1)
BTSR1 is one of the registers used to implement the BT mode. This register includes a flag that
controls an interrupt to the slave (this LSI).
R/W
Bit
Bit Name Initial Value Slave Host Description
7

0
R/W

Reserved
The initial value should not be changed.
6
HRSTI
0
R/(W)* 
BT Reset Interrupt
This status flag indicates that the BMC_HWRST bit
in BTIMSR is set to 1 by the host. When the IBFIE3
bit and HRSTIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads HRSTI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the rising edge of
BMC_HWRST.
5
IRQCRI
0
R/(W)* 
B2H_IRQ Clear Interrupt
This status flag indicates that the B2H_IRQ bit in
BTIMSR is cleared by the host. When the IBFIE3 bit
and IRQCRIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads IRQCRI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the falling edge of
B2H_IRQ.
Rev. 2.00 Aug. 20, 2008 Page 721 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
4
BEVTI
0
R/W
Slave
Host Description
R/(W)*

BEVT_ATN Clear Interrupt
This status flag indicates that the BEVT_ATN bit in
BTCR is cleared by the host. When the IBFIE3 bit
and BEVTIE bit are set to 1, IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
When the slave reads BEVTI = 1 and writes 0 to
this bit.
1: [Setting condition]
When the slave detects the falling edge of
BEVT_ATN.
3
B2HI
0
R/(W)*

Read End Interrupt
This status flag indicates that the host has finished
reading all data from the BTDTR buffer. When the
IBFIE3 bit and B2HIE bit are set to 1, the IBFI3
interrupt is requested to the slave.
0: [Clearing condition]
When the slave reads B2HI = 1 and writes 0 to
this bit.
1: [Setting conditions]
When the slave detects the falling edge of
B2H_ATN.
2
H2BI
0
R/(W)*

Write End Interrupt
This status flag indicates that the host has finished
writing all data to the BTDTR buffer. When the
IBFIE3 bit and H2BIE bit are set to 1, the IBFI3
interrupt is requested to the slave.
0: [Clearing condition]
After the slave reads H2BI = 1, writes 0 to this bit.
1: [Setting condition]
When the slave detects the falling edge of
H2B_ATN.
Rev. 2.00 Aug. 20, 2008 Page 722 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
1
CRRPI
0
R/W
Slave
Host Description
R/(W)* 
Read Pointer Clear Interrupt
This status flag indicates that the CLR_RD_PTR bit
in BTCR is set to 1 by the host. When the IBFIE3 bit
and CRRPIE bit are set to 1, the IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
After the slave reads CRRPI = 1, writes 0 to this
bit.
1: [Setting condition]
When the slave detects the rising edge of
CLR_RD_PTR.
0
CRWPI
0
R/(W)* 
Write Pointer Clear Interrupt
This status flag indicates that the CLR_WR_PTR bit
in BTCR is set to 1 by the host. When the IBFIE3 bit
and CRWPIE bit are set to 1, the IBFI3 interrupt is
requested to the slave.
0: [Clearing condition]
After the slave reads CRWPI = 1, writes 0 to this
bit.
1: [Setting condition]
When the slave detects the rising edge of
CLR_WR_PTR.
Note:
*
Only 0 can be written to clear the flag.
Rev. 2.00 Aug. 20, 2008 Page 723 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.27 BT Control Status Register 0 (BTCSR0)
BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains
the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this
LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1.
Bit
Bit Name
Initial
Value
7

0
R/W
Slave Host Description
R/W

Reserved
The initial value should not be changed.
6
FSEL1
0
R/W

These bits select either FIFO during BT transfer
5
FSEL0
0
R/W

FSEL1 FSEL0
0
X
:FIFO disabled
1
X
:FIFO enabled
The FIFO size: 64 bytes (for host write transfer),
additional 64 bytes (for host read transfer).
4
FRDIE
0
R/W

FIFO Read Request Interrupt Enable
Enables or disables the FRDI interrupt which is an
IBFI3 interrupt source to the slave.
0: FIFO read request interrupt is disabled.
1: FIFO read request interrupt is enabled.
3
HRDIE
0
R/W

BT Host Read Interrupt Enable
Enables or disables the HRDI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HRDIE bit must not be set to 1.
0: BT host read interrupt is disabled.
1: BT host read interrupt is enabled.
2
HWRIE
0
R/W

BT Host Write Interrupt Enable
Enables or disables the HWRI interrupt which is an
IBFI3 interrupt source to the slave.
When using FIFO, the HWRIE bit must not be set to
1.
0: BT host write interrupt is disabled.
1: BT host write interrupt is enabled.
Rev. 2.00 Aug. 20, 2008 Page 724 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
1
HBTWIE
0
R/W
Slave Host Description
R/W

BTDTR Host Write Start Interrupt Enable
Enables or disables the HBTWI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host write start interrupt is disabled.
1: BTDTR host write start interrupt is enabled.
0
HBTRIE
0
R/W

BTDTR Host Read End Interrupt Enable
Enables or disables the HBTRI interrupt which is an
IBFI3 interrupt source to the slave.
0: BTDTR host read end interrupt is disabled.
1: BTDTR host read end interrupt is enabled.
Note:
X Don't care.
19.3.28 BT Control Status Register 1 (BTCSR1)
BTCSR1 is one of the registers used to implement the BT mode. The BTCSR1 register contains
the bits used to enable or disable interrupts to the slave (this LSI). The IBFI3 interrupt is enabled
by setting the IBFIE3 bit in HICR2 to 1.
Initial
Value
Bit
Bit Name
7
RSTRENBL 0
R/W
Slave Host
R/W

Description
Slave Reset Read Enable
The host reads 0 from the BMC_HWRST bit in
BTIMSR. When this bit is set to 1, the host can read
1 from the BMC_HWRST bit.
0: Host always reads 0 from BMC_HWRST
1: Host can reads 0 from BMC_HWRST
6
HRSTIE
0
R/W

BT Reset Interrupt Enable
Enables or disables the HRSTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BT reset interrupt is disabled.
1: BT reset interrupt is enabled.
Rev. 2.00 Aug. 20, 2008 Page 725 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value
5
IRQCRIE
0
R/W
Slave Host
R/W

Description
B2H_IRQ Clear Interrupt Enable
Enables or disables the IRQCRI interrupt which is an
IBFI3 interrupt source to the slave.
0: B2H_IRQ clear interrupt is disabled.
1: B2H_IRQ clear interrupt is enabled.
4
BEVTIE
0
R/W

BEVT_ATN Clear Interrupt Enable
Enables or disables the BEVTI interrupt which is an
IBFI3 interrupt source to the slave.
0: BEVT_ATN clear interrupt is disabled.
1: BEVT_ATN clear interrupt is enabled.
3
B2HIE
0
R/W

Read End Interrupt Enable
Enables or disables the B2HI interrupt which is an
IBFI3 interrupt source to the slave.
0: Read end interrupt is disabled.
1: Read end interrupt is enabled.
2
H2BIE
0
R/W

Write End Interrupt Enable
Enables or disables the H2BI interrupt which is an
IBFI3 interrupt source to the slave.
0: Write end interrupt is disabled.
1: Write end interrupt is enabled.
1
CRRPIE
0
R/W

Read Pointer Clear Interrupt Enable
Enables or disables the CRRPI interrupt which is an
IBFI3 interrupt source to the slave.
0: Read pointer clear interrupt is disabled.
1: Read pointer clear interrupt is enabled.
0
CRWPIE
0
R/W

Write Pointer Clear Interrupt Enable
Enables or disables the CRWPI interrupt which is an
IBFI3 interrupt source to the slave.
0: Write pointer clear interrupt is disabled.
1: Write pointer clear interrupt is enabled.
Rev. 2.00 Aug. 20, 2008 Page 726 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.29 BT Control Register (BTCR)
BTCR is one of the registers used to implement BT mode. The BTCR register contains bits used
in transfer cycle handshaking, and those indicating the completion of data transfer to the buffer.
Bit
Bit Name
R/W
Initial
Value Slave Host
7
B_BUSY
1
R/W
R
Description
BT Write Transfer Busy Flag
Read-only bit from the host. Indicates that the BTDTR
buffer is being used for BT write transfer (write transfer
is in progress.)
0: Indicates waiting for BT write transfer
1: Indicates that the BTDTR buffer is being used
6
H_BUSY
0
R
(W)*
3
BT Read Transfer Busy Flag
This is a set/clear bit from the host. Indicates that the
BTDTR buffer is being used for BT read transfer (read
transfer is in progress.)
0: Indicates waiting for BT read transfer
[Clearing condition]
When the host writes a 1 while H_BUSY is set to 1.
1: Indicates that the BTDTR buffer is being used
[Setting condition]
When the host writes a 1 while H_BUSY is set to 0.
5
OEM0
0
R/W
R/(W)*
4
User defined bit
This bit is defined by the user, and validated only when
set to 1 by a 0 written from the host.
0: [Clearing condition]
When the slave writes a 0 after a 1 has been read
from OEM0.
1: [Setting condition]
When the slave writes a 1, after a 0 has been read
from OEM0, or when the host writes a 0.
Rev. 2.00 Aug. 20, 2008 Page 727 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
4
Bit Name
Initial
Value
BEVT_ATN 0
R/W
Slave
R/(W)*
Host
1
R/(W)*
Description
5
Event Interrupt
Sets when the slave detects an event to the host.
Setting the B2H_IRQ_EN bit in the BTIMSR
register enables the BEVT_ATN bit to be used as
an interrupt source to the host.
0: No event interrupt request is available
[Clearing condition]
When the host writes a 1 to the bit.
1: An event interrupt request is available
[Setting condition]
When the slave writes a 1 after a 0 has been read
from BEVT_ATN.
3
B2H_ATN
0
R/(W)*
1
R/(W)*
5
Slave Buffer Write End Indication Flag
This status flag indicates that the slave has
finished writing all data to the BTDTR buffer.
Setting the B2H_IRQ_EN bit in the BTIMSR
register enables the B2H_ATN bit to be used as
an interrupt source to the host.
0: Host has completed reading the BTDTR buffer
[Clearing condition]
When the host writes a 1
1: Slave has completed writing to the BTDTR
buffer
[Setting condition]
When the slave writes a 1 after a 0 has been read
from B2N_ATN.
2
H2B_ATN
0
R/(W)*
2
R/(W)*
1
Host Buffer Write End Indication Flag
This status flag indicates that the host has finished
writing all data to the BTDTR buffer.
0: Slave has completed reading the BTDTR buffer
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from H2B_ATN.
1: Host has completed writing to the BTDTR buffer
[Setting condition]
When the host writes a 1
Rev. 2.00 Aug. 20, 2008 Page 728 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Bit
1
Bit Name
CLR_RD_
PTR
Initial
Value
0
R/W
Slave
Host Description
2
1
R/(W)* (W)* Read Pointer Clear
This bit is used by the host to clear the read pointer
during read transfer. A host read operation always
yields 0 on readout.
0: Read pointer clear wait
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from CLR_RD_PTR.
1: Read pointer clear
[Setting condition]
When the host writes a 1.
0
CLR_WR_
PTR
0
2
1
R/(W)* (W)* Write Pointer Clear
This bit is used by the host to clear the write pointer
during write transfer. A host read operation always
yields 0 on readout.
0: Write pointer clear wait
[Clearing condition]
When the slave writes a 0 after a 1 has been read
from CLR_WR_PTR.
1: Write pointer clear
[Setting condition]
When the host writes a 1.
Notes: 1.
2.
3.
4.
5.
Only 1 can be written to set this flag.
Only 0 can be written to clear this flag.
Only 1 can be written to toggle this flag.
Only 0 can be written to set this flag.
Only 1 can be written to clear this flag.
Rev. 2.00 Aug. 20, 2008 Page 729 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.30 BT Data Buffer (BTDTR)
BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer
FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR,
enable FIFO by means of the bits FSEL0 and FSEL1.
Bit
Bit Name
Initial
Value
R/W
Slave Host Description
7 to 0 bit7 to bit0 Undefined R/W
R/W
The data written by the host is stored in FIFO (64
bytes) for host write transfer and read out by the
slave in order of host writing. The data written by the
slave is stored in FIFO (64 bytes) for host read
transfer and read out by the host in order of slave
writing.
19.3.31 BT Interrupt Mask Register (BTIMSR)
BTIMSR is one of the registers used to implement BT mode. The BTIMSR register contains the
bits used to control the interrupts to the host.
Bit
7
Bit Name
BMC_
HWRST
Initial
Value
0
R/W
Slave
R/(W)*
Host
2
Description
1
R/(W)* Slave Reset
Performs a reset from the host to the slave. The
host can only write a 1. Writing a 0 to this bit is
invalid. The host will always return a 0 on read
out. Setting the RSTRENBL bit enables a 1 to be
read from the host.
0: The reset is cancelled
[Clearing condition]
When the slave writes a 0, after a 1 has been
read from BMC_HWRST.
1: The reset is in progress.
[Setting condition]
When the host writes a 1.
6

0
R/W
R/W
5

0
R/W
R/W
Rev. 2.00 Aug. 20, 2008 Page 730 of 1198
REJ09B0403-0200
Reserved
Section 19 LPC Interface (LPC)
Bit
Bit Name
Initial
Value Slave
R/W
Host
Description
4
4
OEM3
0
R/W
R/(W)* User defined bit
3
OEM2
0
R/W
2
OEM1
0
R/W
R/(W)* These bits are defined by the user and are valid
4
R/(W)* only when set to 1 by a 0 written from the host.
4
0: [Clearing condition]
When the slave writes a 0, after a 1 has been
read from OEM.
1: [Setting condition]
When the slave writes a 1, after a 0 has been
read from OEM, or when the host writes a 0.
1
B2H_IRQ
0
R/(W)*
1
3
R/(W)* BMC to HOST interrupt
Informs the host that an interrupt has been
requested when the BEVT_ATN or B2H_ATN bit
has been set. The SERIRQ is not issued. To
generate the SERIRQ, it should be issued by the
program.
0: B2H_IRQ interrupt is not requested
[Clearing condition]
When the host writes a 1.
1: B2H_IRQ interrupt is requested
[Setting condition]
When the slave writes a 1, after a 0 has been read
from B2H_IRQ
0
B2H_IRQ_EN 0
R
R/W
BMC to HOST interrupt enable
Enables or disables the B2H_IRQ interrupt which
is an interrupt source from the slave to the host.
0: B2H_IRQ interrupt is disabled
[Clearing condition]
When a 0 is written by the host.
1: B2H_IRQ interrupt is enabled
[Setting condition]
When a 1 is written by the host.
Notes: 1. Only 1 can be written to set this flag.
2. Only 0 can be written to clear this flag.
3. Only 1 can be written to clear this flag.
4. Only 0 can be written to set this flag.
Rev. 2.00 Aug. 20, 2008 Page 731 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0)
BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data
size in the FIFO for host write transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 0 N7 to N0 All 0

R
These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the slave can
read) for host write transfer. When data is written
from the host, the value in BTFVSR0 is incremented
by the number of bytes that have been written to.
Further, when data is read from the slave, the value
is decremented by only the number of bytes that
have been read.
19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1)
BTFVSR1 is one of the registers used to implement BT mode. BTFVSR1 indicates a valid data
size in the FIFO for host read transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 0 N7 to N0 All 0
R
Rev. 2.00 Aug. 20, 2008 Page 732 of 1198
REJ09B0403-0200

These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the host can read)
for host read transfer. When data is written from the
slave, the value in BTFVSR1 is incremented by the
number of bytes that have been written to. Further,
when data is read from the host, the value is
decremented by only the number of bytes that have
been read.
Section 19 LPC Interface (LPC)
19.4
Operation
19.4.1
LPC interface Activation
The LPC interface is activated by setting any one of bits LPC3E to LPC1E in HICR0 and bit
SICIE bit in HICR5 to 1. When the LPC interface is activated, the related I/O port pins (PE7 to
PE0, PD5 and PD4) function as dedicated LPC interface input/output pins. In addition, setting the
FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O port pins (PD3 to PD0) to the
LPC interface's input/output pins.
Use the following procedure to activate the LPC interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. When using channels 1 and 2, set LADR1 and LADR2 to determine the I/O address.
3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data
registers are to be used.
4. When using the SCIF module, set SCIFAR to determine the I/O address.
5. Set the enable bit (LPC3E to LPC1E) for the channel to be used. Also set SCIFE if the SCIF is
to be used.
6. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
used.
7. Set the selection bits for other functions (SDWNE, IEDIR).
8. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, and OBEI). Read IDR
or TWR15 to clear IBF.
9. Set receive complete interrupt enable bits (IBFIE3 to IBFIE1, and ERRIE) as necessary.
19.4.2
LPC I/O Cycles
There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O
write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O
read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this
LSI supports I/O read and I/O write.
Rev. 2.00 Aug. 20, 2008 Page 733 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle, but the LPC interface of this
LSI always returns B'0000 (except for the BT interface).
If the received address matches the host address for an LPC register, the LPC interface enters the
busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag
changes are made at this timing, so in the event of a transfer cycle forced termination (abort),
registers and flags are not changed.
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 19.2 and 19.3.
Table 19.5 LPC I/O Cycle
I/O Read Cycle
I/O Write Cycle
State
Count
Contents
Drive
Source
Value
(3 to 0)
Contents
Drive
Source
Value
(3 to 0)
1
Start
Host
0000
Start
Host
0000
2
Cycle type/direction
Host
0000
Cycle type/direction
Host
0010
3
Address 1
Host
Bits 15 to 12
Address 1
Host
Bits 15 to 12
4
Address 2
Host
Bits 11 to 8
Address 2
Host
Bits 11 to 8
5
Address 3
Host
Bits 7 to 4
Address 3
Host
Bits 7 to 4
6
Address 4
Host
Bits 3 to 0
Address 4
Host
Bits 3 to 0
7
Turnaround (recovery) Host
1111
Data 1
Host
Bits 3 to 0
8
Turnaround
None
ZZZZ
Data 2
Host
Bits 7 to 4
9
Synchronization
Slave
0000
Turnaround (recovery) Host
1111
10
Data 1
Slave
Bits 3 to 0
Turnaround
None
ZZZZ
11
Data 2
Slave
Bits 7 to 4
Synchronization
Slave
0000
12
Turnaround (recovery) Slave
1111
Turnaround (recovery) Slave
1111
13
Turnaround
ZZZZ
Turnaround
ZZZZ
None
Rev. 2.00 Aug. 20, 2008 Page 734 of 1198
REJ09B0403-0200
None
Section 19 LPC Interface (LPC)
LCLK
LFRAME
LAD3 to
LAD0
Start
ADDR
TAR
Sync
Data
TAR
Start
Cycle type,
direction,
and size
Number of clocks
1
1
4
2
1
2
2
1
Figure 19.2 Typical LFRAME Timing
LCLK
LFRAME
LAD3 to LAD0
Start
ADDR
Cycle type,
direction,
and size
TAR
Sync
Slave must stop driving
Master will
drive high
Too many Syncs
cause timeout
Figure 19.3 Abort Mechanism
19.4.3
SMIC Mode Transfer Flow
Figure 19.4 shows the write transfer flow and figure 19.5 shows the read transfer flow in SMIC
mode.
Rev. 2.00 Aug. 20, 2008 Page 735 of 1198
REJ09B0403-0200
Section 19 LPC Interface (LPC)
Slave
Host
Wait for BUSY = 0
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Bit that indicates slave is ready for write transfer.
Issues when slave is ready for the next write transfer.
Wait for
TX_DATA_RDY = 1
Host confirms the TX_DATA_RDY bit in SMICFLG.
The confirmation is unnecessary when Write Start control is issued.
A
Write control code
Host writes the Write control code in SMICCSR.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Slave waits for the BUSY bit in SMICFLG is set.
Generate slave
interrupt
Write transfer data
Slave confirms that valid data is written to SMICDTR
by host.
The HDTWI bit in SMICIR0 is set.
Host writes transfer data in SMICDTR.
Generate slave
interrupt
BUSY = 1
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Generate slave
interrupt
Slave clears the TX_DATA_RDY bit in SMICFLG.
TX_DATA_RDY = 0
Slave reads the control code in SMICCSR.
Read control code
Slave reads t