FINAL Am29F016 16-Megabit (2,097,152 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory DISTINCTIVE CHARACTERISTICS ■ 5.0 Volt ± 10% for read and write operations — Minimizes system level power requirements ■ Compatible with JEDEC-standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ 48-pin TSOP ■ 44-pin SO ■ Minimum 100,000 write/erase cycles guaranteed ■ High performance — 70 ns maximum access time ■ Sector erase architecture — Uniform sectors of 64 Kbytes each — Any combination of sectors can be erased. Also supports full chip erase ■ Group sector protection — Hardware method that disables any combination of sector groups from write or erase operations (a sector group consists of 4 adjacent sectors of 64 Kbytes each) ■ Embedded Program Algorithms — Automatically programs and verifies data at specified address ■ Data Polling and Toggle Bit feature for detection of program or erase cycle completion ■ Ready/Busy output (RY/BY) — Hardware method for detection of program or erase cycle completion ■ Erase Suspend/Resume — Supports reading or programming data to a sector not being erased ■ Low power consumption — 25 mA typical active read current — 30 mA typical program/erase current ■ Enhanced power management for standby mode — <1 µA typical standby current — Standard access time from standby mode ■ Hardware RESET pin — Resets internal state machine to the read mode ■ Embedded Erase Algorithms — Automatically pre-programs and erases the chip or any sector GENERAL DESCRIPTION The Am29F016 is a 16 Mbit, 5.0 Volt-only Flash memory organized as 2 Megabytes of 8 bits each. The 2 Mbytes of data is divided into 32 sectors of 64 Kbytes for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F016 is offered in 48-pin TSOP and 44-pin SO packages. This device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. 12.0 Volt V PP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard Am29F016 offers access times of 70 ns, 90 ns, 120 ns, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The Am29F016 is entirely command set compatible with the JEDEC single-power supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 Volt Flash or EPROM devices. The Am29F016 is programmed by executing the program command sequence. This will invoke the EmbedPublication# 18805 Rev: D Amendment/0 Issue Date: April 1997 ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within one second. The Am29F016 is erased when shipped from the factory. The Am29F016 device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. A sector group consists of four adjacent sectors grouped in the following pattern: sectors 0–3, 4–7, 8–11, 12–15, 16–19, 20–23, 24–27, and 28–31. h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t effectiveness. The Am29F016 memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. Flexible Sector-Erase Architecture ■ Thirty two 64 Kbyte sectors ■ Eight sector groups each of which consists of 4 adjacent sectors in the following pattern: sectors 0–3, 4–7, 8–11, 12–15, 16–19, 20–23, 24–27, and 28–31. ■ Individual-sector or multiple-sector erase capability ■ Sector group protection is user-definable SA31 SA30 SA29 SA28 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte AMD has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from, or program data to, a sector that was not being erased. Thus, true background erase can be achieved. The device features single 5.0 Volt power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the RY/BY pin, Data Polling of DQ7, or by the Toggle Bit I (DQ6).Once the end of a program or erase cycle has been completed, the device automatically resets to the readmode. The Am29F016 also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm will be terminated. The internal state machine will then be reset into the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device will be automatically reset to the read mode. This will enable the system’s microprocessor to read the boot-up firmware from the Flash memory. 32 Sectors Total SA3 SA2 SA1 SA0 AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the 2 Am29F016 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh 000000h Sector Group 7 Sector Group 0 18805D-1 PRODUCT SELECTOR GUIDE Family Part No. VCC = 5.0 Volt ± 5% Ordering Part No: -75 VCC = 5.0 Volt ± 10% -90 -120 -150 Max Access Time (ns) 70 90 120 150 CE (E) Access (ns) 70 90 120 150 OE (G) Access (ns) 40 40 50 75 BLOCK DIAGRAM DQ0–DQ7 Sector Switches VCC VSS Erase Voltage Generator RY/BY RESET WE Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE OE VCC Detector Address Latch STB Timer A0–A20 STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 18805D-2 Am29F016 3 CONNECTION DIAGRAMS SO NC 1 44 VCC RESET 2 43 CE A11 3 42 A12 A10 4 41 A13 A9 5 40 A14 A8 6 39 A15 A7 7 38 A16 A6 8 37 A17 A5 9 36 A18 A4 10 35 A19 NC 11 34 NC NC 12 33 A3 13 32 A20 A2 14 31 NC A1 15 30 WE A0 16 29 OE DQ0 17 28 RY/BY DQ1 18 27 DQ7 DQ2 19 26 DQ6 DQ3 20 25 DQ5 VSS 21 24 DQ4 VSS 22 23 VCC NC 18805D-3A 4 Am29F016 CONNECTION DIAGRAMS NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE VCC NC RESET A11 A10 A9 A8 A7 A6 A5 A4 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NC A20 NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard TSOP 18805D-3 NC NC A20 NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE VCC NC RESET A11 A10 A9 A8 A7 A6 A5 A4 NC NC Reverse TSOP 18805D-4 Am29F016 5 PIN CONFIGURATION A0–A20 = 21 Addresses CE = Chip Enable LOGIC SYMBOL 21 A0–A20 DQ0–DQ7 = 8 Data Inputs/Outputs DQ0–DQ7 NC = Pin Not Connected Internally OE = Output Enable RESET = Hardware Reset Pin, Active Low RY/BY = Ready/BUSY Output OE (G) VCC = +5.0 Volt Single-Power Supply (±10% for -90, -120, -150) or (±5% for -95) WE (W) VSS = Device Ground WE = Write Enable 6 8 CE (E) RESET RY/BY 18805D-5 Am29F016 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM29F016 -75 E I B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F016 16 Megabit (2M x 8-Bit) CMOS Flash Memory 5.0 Volt-only Program and Erase Valid Combinations AM29F016-75 EC, EI, FC, FI, SC, SI AM29F016-90 AM29F016-120 AM29F016-150 EC, ECB, EI, EIB, FC, FCB, FI, FIB, SC, SCB, SI, SIB Am29F016 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 7 Table 1. Am29F016 User Bus Operations CE OE WE A0 A1 A6 A9 DQ0–DQ7 RESET Autoselect, AMD Manuf. Code (1) L L H L L L VID Code H Autoselect Device Code (1) L L H H L L VID Code H Read L L X A0 A1 A6 A9 DOUT H Standby H X X X X X X HIGH Z H Output Disable L H H X X X X HIGH Z H Write L H L A0 A1 A6 A9 DIN H Enable Sector Group Protect (2) L VID L X X X VID X H Verify Sector Group Protect (2) L L H L H L VID Code H Temporary Sector Group Unprotect X X X X X X X X VID Hardware Reset/Standby X X X X X X X HIGH Z L Operation Legend: L = logic 0, H = logic 1, X = Don’t Care. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5. 2. Refer to the section on Sector Group Protection. Read Mode The Am29F016 has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if the device is selected. reduced to less than 1 µA. A TTL standby mode is achieved with CE and RESET pins held at VIH. Under this condition the current is typically reduced to 200 µA. The device can be read with standard access time (tCE) from either of these standby modes. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC–tOE time). When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = don’t care). Under this condition the current is typically reduced to less than 1 µA. A TTL standby mode is achieved with RESET pin held at VIL (CE = don’t care). Under this condition the current is typically reduced to less than 200 µA. Once the RESET pin is taken high, the device requires 50 ns of wake up time before outputs are valid for read access. Standby Mode There are two ways to implement the standby mode on the Am29F016 device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current is typically 8 In the standby mode the outputs are in the high impedance state, independent of the OE input. Output Disable With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Am29F016 Autoselect sequence is illustrated in Table 5 (see Autoselect Command Sequence). The autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. Byte 0 (A0 = VIL) represents the manufacturer’s code (AMD = 01H) and byte 1 (A0 = VIH) the device identifier code for Am29F016 = ADH. These two bytes are given in the table below. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL (see Table 2). To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don’t cares except A0, A1, and A6 (seeTable 2). The autoselect mode also facilitates the determination of sector group protection in the system. By performing a read operation at the address location XX02H with the higher order address bits A18, A19, and A20 set to the desired sector group address, the device will return 01H for a protected sector group and 00H for a non-protected sector group. The manufacturer and device codes may also be read via the command register, for instances when the Am29F016 is erased or programmed in a system without access to high voltage on the A9 pin. The command Table 2. Am29F016 Sector Protection Verify Autoselect Codes Type A18 to A20 A6 A1 A0 Code DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 (HEX) Manufacturer Code–AMD X X X VIL VIL VIL 01H 0 0 0 0 0 0 0 1 Am29F016 Device X X X VIL VIL VIH ADH 1 0 1 0 1 1 0 1 Sector Group Protection Sector Group Address VIL VIH VIL 01H* 0 0 0 0 0 0 0 1 * Outputs 01H at protected sector addresses Am29F016 9 Table 3. 10 Sector Address Table A20 A19 A18 A17 A16 Address Range SA0 0 0 0 0 0 000000h-00FFFFh SA1 0 0 0 0 1 010000h-01FFFFh SA2 0 0 0 1 0 020000h-02FFFFh SA3 0 0 0 1 1 030000h-03FFFFh SA4 0 0 1 0 0 040000h-04FFFFh SA5 0 0 1 0 1 050000h-05FFFFh SA6 0 0 1 1 0 060000h-06FFFFh SA7 0 0 1 1 1 070000h-07FFFFh SA8 0 1 0 0 0 080000h-08FFFFh SA9 0 1 0 0 1 090000h-09FFFFh SA10 0 1 0 1 0 0A0000h-0AFFFFh SA11 0 1 0 1 1 0B0000h-0BFFFFh SA12 0 1 1 0 0 0C0000h-0CFFFFh SA13 0 1 1 0 1 0D0000h-0DFFFFh SA14 0 1 1 1 0 0E0000h-0EFFFFh SA15 0 1 1 1 1 0F0000h-0FFFFFh SA16 1 0 0 0 0 100000h-10FFFFh SA17 1 0 0 0 1 110000h-11FFFFh SA18 1 0 0 1 0 120000h-12FFFFh SA19 1 0 0 1 1 130000h-13FFFFh SA20 1 0 1 0 0 140000h-14FFFFh SA21 1 0 1 0 1 150000h-15FFFFh SA22 1 0 1 1 0 160000h-16FFFFh SA23 1 0 1 1 1 170000h-17FFFFh SA24 1 1 0 0 0 180000h-18FFFFh SA25 1 1 0 0 1 190000h-19FFFFh SA26 1 1 0 1 0 1A0000h-1AFFFFh SA27 1 1 0 1 1 1B0000h-1BFFFFh SA28 1 1 1 0 0 1C0000h-1CFFFFh SA29 1 1 1 0 1 1D0000h-1DFFFFh SA30 1 1 1 1 0 1E0000h-1EFFFFh SA31 1 1 1 1 1 1F0000h-1FFFFFh Am29F016 Table 4. Sector Group Addresses A20 A19 A18 Sectors SGA0 0 0 0 SA0–SA3 SGA1 0 0 1 SA4–SA7 SGA2 0 1 0 SA8–SA11 SGA3 0 1 1 SA12–SA15 SGA4 1 0 0 SA16–SA19 SGA5 1 0 1 SA20–SA23 SGA6 1 1 0 SA24–SA27 SGA7 1 1 1 SA28–SA31 Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The Am29F016 features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0–3, 4–7, 8–11, 12–15, 16–19, 20–23, 24–27, and 28–31 (see Table 4). The sector group protect feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. Alternatively, AMD may program and protect sector groups in the factory prior to shipping the device (AMD’s ExpressFlash™ Service). It is possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order address bits A18, A19, and A20 is the desired sector group address, will produce a logical “1” at DQ0 for a protected sector group. See Table 2 for Autoselect codes. Temporary Sector Group Unprotect This feature allows temporary unprotection of previously protected sector groups of the Am29F016 device in order to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET pin to high voltage (12V). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 15 and 16. Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read mode. Am29F016 11 Table 5. Am29F016 Command Definitions Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Addr Reset/Read 1 XXXXH F0H Reset/Read 3 5555H AAH 2AAAH 55H 5555H F0H RA RD Autoselect 3 5555H AAH 2AAAH 55H 5555H 90H Byte Program 4 5555H AAH 2AAAH 55H 5555H A0H PA Data Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 30H Erase Suspend 1 XXXXH B0H Erase Resume 1 XXXXH 30H Command Sequence Read/Reset Data SA Data Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA= Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select any sector. 3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 4. Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode. 5. Address bits A15, A14, A13, A12 and A11 = X, X = don’t care. Read/Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an autoselect command operation to supplement traditional PROM programming 12 methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacturer code of 01H. A read cycle from address XX01H returns the device code ADH (see Table 2). All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Furthermore, the write protect status of sectors can be read in this mode. Scanning the sector group addresses (A18, A19, and A20) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. To terminate the operation, it is necessary to write the read/reset command sequence into the register. Byte Programming The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming using the Embedded Program Algo- Am29F016 rithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. This automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see Table 6, Write Operation Status). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. Figure 1 illustrates the Embedded Programming Algor ithm using typic al command s tr ings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read mode. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (30H) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this period will reset the device to the read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete.(Refer to the Write Operation Status section for DQ3, Sector Erase Timer, operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 31). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7, Data Polling, is “1” (see Write Operation Status section) at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. Erase Suspend The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Am29F016 13 Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. pended. Successively reading from the erase-susp e n d e d s e c t o r w h i l e t h e d ev i c e i s i n t h e erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2). Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are “don’t-cares” when writing the Erase Suspend or Erase Resume command. After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-susp e n d e d s e c t o r w h i l e t h e d ev i c e i s i n t h e erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended program operation is detected by the RY/BY output pin, Data Polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from the byte program address while DQ6 can be read from any address. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin and the DQ7 bit will be at logic ‘1’, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-sus- 14 To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Am29F016 Write Operation Status Table 6. Write Operation Status Status Byte Program in Embedded Program Algorithm Embedded Program Algorithm Erase Suspended Read (Erase Suspended Sector) In Progress Erase Suspended Mode Erase Suspended Read (Non-Erase Suspended Sector) Erase Suspended Read (Non-Erase Suspended Sector) Byte Program in Embedded Program Algorithm Exceeded Time Limits Program/Erase Program in Embedded Program Algorithm Erase Suspended Mode Erase Suspended Read (non-Erase Suspended Sector) DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 1 Data Data Data Data DQ7 Toggle (Note 2) 0 1 DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 1 N/A Toggle (Note 1) Data 1 (Note 3) Notes: 1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle. 2. Performing successive read operations from any address will cause DQ6 to toggle. 3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic ‘1’ at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. DQ7 Data Polling The Am29F016 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 3. Data Polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase Suspend Mode. During Program in Erase Suspend, Data Polling will perform the same as in regular program execution outside of the suspend mode. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector addresses within any of the sectors being erased and not a sector that is within a protected sector group. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0–DQ6 may be still invalid. The valid data on DQ0–DQ7 can be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out (see Table 6). See Figure 11 for the Data Polling timing specifications and diagrams. Am29F016 15 DQ6 Toggle Bit I The Am29F016 also features the “Toggle Bit I” as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 12 for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 1. The DQ5 failure condition will also appear if a user tries to program a “1” to a location that is previously programmed to “0”. In this case the device locks out and never completes the Embedded Program Algorithm. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device. DQ3 If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 6: Write Operation Status. DQ2 Toggle Bit II This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspend sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic ‘1’ at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard Program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: Mode Program Erase Erase Suspend Read (1) (Erase-Suspended Sector) Erase Suspend Program DQ7 DQ6 DQ2 DQ7 toggles 1 0 toggles toggles 1 1 toggles DQ7 (2) toggles 1 (2) Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended. Sector Erase Timer 2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector. After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence. For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while DQ6 does not). See also Table 6 and Figure 17. 16 Am29F016 Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from the erasing sector. RY/BY Ready/Busy The Am29F016 provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the Am29F016 is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to Figure 13 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. RESET Hardware Reset The Am29F016 device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 µs after the RESET pin is driven low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the RESET pin is taken high, the device requires 500 ns of wake up time until outputs are valid for read access. The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s microprocessor to read the boot-up firmware from the Flash memory. Data Protection The Am29F016 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for V CC less than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = V IL and OE = V IH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Am29F016 17 EMBEDDED ALGORITHMS Start Write Program Command Sequence (see below) Data Poll Device Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data 18805D-6 Figure 1. Embedded Programming Algorithm 18 Am29F016 EMBEDDED ALGORITHMS Start Write Erase Command Sequence (see below) Data Polling or Toggle Bit I Successfully Completed Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H Sector Address/30H Additional sector erase commands are optional Sector Address/30H 18805C-7 To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Figure 2. Embedded Erase Algorithm Am29F016 19 Start VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any non-protected sector group address during chip erase Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No No DQ5 = 1 ? Yes Yes Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No Pass Fail 18805D-8 DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 3. Data Polling Algorithm 20 ns 20 ns +0.8 V –0.5 V –2.0 V 20 ns Figure 5. Maximum Negative Overshoot Waveform 20 Am29F016 18805D-10 Start Read Byte (DQ0–DQ7) Addr = Don’t Care No DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Yes Read Byte (DQ0–DQ7) Addr = Don’t Care No DQ6 = Toggle ? Yes Pass Fail DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”. 18805D-9 Figure 4. Toggle Bit I Algorithm 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns 18805D-11 Figure 6. Maximum Positive Overshoot Waveform Am29F016 21 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C vice to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Commercial (C) Devices Voltage with Respect to Ground All pins except A9 (Note 1). . . . . . . . .–2.0 V to +7.0 V Industrial (I) Devices VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V A9, OE, RESET (Note 2) . . . . . . . . .–2.0 V to +13.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. Case Temperature (TC). . . . . . . . . . . . . .0°C to +70°C Case Temperature (TC). . . . . . . . . . . .–40°C to +85°C VCC Supply Voltages VCC for Am29F016-75 . . . . . . . . . +4.75 V to +5.25 V VCC for Am29F016-90, 120, 150. . +4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9, OE, RESET pins is –0.5 V. During voltage transitions, A9, OE, RESET pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the de- 22 Am29F016 DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description Min Max Unit ±1.0 µA 50 µA ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 Volt ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH 40 mA ICC2 VCC Active Current (Notes 2, 3) CE = VIL, OE = VIH 60 mA ICC3 VCC Standby Current VCC = VCC Max, CE = VIH, RESET = VIH 1.0 mA ICC4 VCC Standby Current (Reset) VCC = VCC Max, RESET = VIL 1.0 mA VIL Input Low Level –0.5 0.8 V VIH Input High Level 2.0 VCC + 0.5 V VID Voltage for Autoselect and Sector VCC = 5.0 Volt Protect 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Level IOH = –2.5 mA VCC = VCC Min VLKO Low VCC Lock-out Voltage 2.4 3.2 V 4.2 V Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested. Am29F016 23 DC CHARACTERISTICS (continued) CMOS Compatible Parameter Symbol Parameter Description Test Description Min Typ Max Unit ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 Volt 50 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH 25 40 mA ICC2 VCC Active Current (Notes 2, 3) CE = VIL, OE = VIH 30 40 mA ICC3 VCC Standby Current VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V 1 5 µA ICC4 VCC Standby Current (Reset) VCC = VCC Max, RESET = VSS ± 0.3 V 1 5 µA VIL Input Low Level –0.5 0.8 V VIH Input High Level 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Sector Protect VCC = 5.0 Volt 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage VOH2 VLKO IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V IOH = –100 µA, VCC = VCC Min VCC – 0.4 V Low VCC Lock-out Voltage 3.2 4.2 Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested. 24 Am29F016 V AC CHARACTERISTICS Read-only Operations Characteristics Parameter Symbol Speed Options (Notes 1 and 2) JEDEC Standard Parameter Description tAVAV tRC Read Cycle Time 4 tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE tEHQZ -75 -90 -120 -150 Unit Min 70 90 120 150 ns CE = VIL OE = VIL Max 70 90 120 150 ns OE = VIL Max 70 90 120 150 ns Output Enable to Output Delay Max 40 40 50 55 ns tDF Chip Enable to Output High Z (Notes 3, 4) Max 20 20 30 35 ns tGHQZ tDF Output Enable to Output High Z (Notes 3, 4) Max 20 20 30 35 ns tAXQX tOH Output Hold Time From Addresses CE or OE Whichever Occurs First Min 0 0 0 0 ns tReady RESET Pin Low to Read Mode 4 Max 20 20 20 20 µs Notes: 1. Test Conditions (for -75): Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level: 1.5 V input and output Test Setup 2. Test Conditions (for all others): Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level: 0.8 V and 2.0 V input and output 3. Output driver disable time. 4. Not 100% tested. 5.0 Volt IN3064 or Equivalent Device Under Test 2.7 kΩ 6.2 kΩ CL Diodes = IN3064 or Equivalent Note: CL (for -75) = 30 pF including jig capacitance CL (for all others) = 100 pF including jig capacitance 18805D-11 Figure 7. Test Conditions Am29F016 25 AC CHARACTERISTICS Write/Erase/Program Operations Parameter Symbol JEDEC Speed Options (Notes 1 and 2) Standard Parameter Description -75 -90 -120 -150 Unit tAVAV tWC Write Cycle Time Min 70 90 120 150 ns tAVWL tAS Address Setup Time Min 0 0 0 0 ns tWLAX tAH Address Hold Time Min 40 45 50 50 ns tDVWH tDS Data Setup Time Min 40 45 50 50 ns tWHDX tDH Data Hold Time Min 0 0 0 0 ns Read 2 Min 0 0 0 0 ns tOEH Output Enable Hold Time Toggle Bit I and Data Polling 2 Min 10 10 10 10 ns Min 0 0 0 0 ns Read Recover Time Before Write tGHWL tGHWL tELWL tCS CE Setup Time Min 0 0 0 0 ns tWHEH tCH CE Hold Time Min 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 40 45 50 50 ns tWHWL tWPH Write Pulse Width High Min 20 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation Typ 7 7 7 7 µs Typ 1 1 1 1 sec tWHWH2 tWHWH2 Sector Erase Operation 1 Max 8 8 8 8 sec tVCS VCC Set Up Time 2 Min 50 50 50 50 µs tVIDR Rise Time to VID (Notes 2, 3) Min 500 500 500 500 ns tVLHT Voltage Transition Time (Notes 2, 3) Min 4 4 4 4 µs tOESP OE Setup Time to WE Active (Notes 2, 3) Min 4 4 4 4 µs tRP RESET Pulse Width Min 500 500 500 500 ns tBUSY Program/Erase Valid to RY/BY Delay Min 40 40 50 60 ns (OE high to WE low) Notes: 1. This does not include the preprogramming time. 2. Not 100% tested. 3. These timings are for Temporary Sector Group Unprotect operation. 26 Am29F016 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST WAVEFORM tRC Addresses Stable Addresses tACC CE (tDF) tOE OE tOEH WE (tCE) (tOH) Outputs High Z High Z Output Valid 18805D-12 Figure 8. AC Waveforms for Read Operations Am29F016 27 SWITCHING WAVEFORMS Data Polling 3rd Bus Cycle Addresses 5555H PA tWC tAS PA tAH tRC CE tGHWL OE tWHWH1 tWP WE tWPH tCS tDH Data PD A0H tDF tOE DQ7 DOUT tDS tOH 5.0 Volt tCE Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 18805D-13 Figure 9. Program Operation Timings tAH 5555H Addresses 2AAAH 5555H 5555H 2AAAH 80H AAH 55H SA tAS CE tGHWL OE tWP WE tWPH tCS tDH Data AAH 55H 10H/30H tDS VCC tVCS Note: SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase. 18805D-14 Figure 10. 28 AC Waveforms Chip/Sector Erase Operations Am29F016 SWITCHING WAVEFORMS tCH CE tDF tOE OE tOEH tCE WE tOH * DQ7 DQ7 = Valid Data DQ7 High Z tWHWH 1 or 2 DQ0–DQ6 DQ0–DQ6 = Invalid DQ0–DQ7 Valid Data *DQ7 = Valid Data (The device has completed the Embedded operation). 18805D-15 Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations CE tOEH WE OE * Data (DQ0–DQ7) DQ6 = Toggle DQ6 = Stop Toggling DQ6 = Toggle DQ0–DQ7 Valid tOE *DQ6 stops toggling (The device has completed the Embedded operation). 18805D-16 Figure 12. AC Waveforms for Toggle Bit I During Embedded Algorithm Operations Am29F016 29 CE The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY 18805D-17 Figure 13. RY/BY Timing Diagram During Program/Erase Operations RESET tRP tReady 18805D-18 Figure 14. RESET Timing Diagram Start RESET = VID (Note 1) Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotect Completed (Note 2) 18805D-21 Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again. Figure 15. 30 Temporary Sector Group Unprotect Algorithm Am29F016 12V RESET 0 or 5V 0V or 5 V tVIDR CE WE Program or Erase Command Sequence RY/BY 18805D-22 Figure 16. Temporary Sector Group Unprotect Timing Diagram Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note: DQ2 is read from the erase-suspended sector. 18805D-23 Figure 17. DQ2 vs. DQ6 Am29F016 31 AC CHARACTERISTICS Write/Erase/Program Operations Alternate CE Controlled Writes Parameter Symbol JEDEC Speed Options (Notes 1 and 2) Standard Parameter Description -75 -90 -120 -150 Unit tAVAV tWC Write Cycle Time Min 70 90 120 150 ns tAVEL tAS Address Setup Time Min 0 0 0 0 ns tELAX tAH Address Hold Time Min 40 45 50 50 ns tDVEH tDS Data Setup Time Min 40 45 50 50 ns tEHDX tDH Address Hold Time Min 0 0 0 0 ns tOES Output Enable Setup Time (Note 2) Min 0 0 0 0 ns Read (Note 2) Min 0 0 0 0 ns tOEH Output Enable Hold Time Toggle Bit I and Data Polling (Note 2) Min 10 10 10 10 ns tGHEL tGHEL Read Recover Time Before Write Min 0 0 0 0 ns tWLEL tWS CE Setup Time Min 0 0 0 0 ns tEHWH tWH CE Hold Time Min 0 0 0 0 ns tELEH tCP Write Pulse Width Min 40 45 50 50 ns tEHEL tCPH Write Pulse Width High Min 20 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation Typ 7 7 7 7 µs Typ 1 1 1 1 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Max 8 8 8 8 sec Notes: 1. This does not include the preprogramming time. 2. Not 100% tested. 32 Am29F016 Data Polling Addresses 5555H PA tWC tAS PA tAH WE tGHEL OE tCP tWHWH1 CE tWS tCPH tDH Data PD A0H DQ7 DOUT tDS 5.0 Volt Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 18805D-24 Figure 18. Alternate CE Controlled Program Operation Timing Am29F016 33 ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min Typ Max Unit Comments 1 (Note 1) 8 sec Excludes 00H programming prior to erasure Chip Erase Time 32 256 sec Excludes 00H programming prior to erasure Byte Programming Time 7 300 (Note 3) µs Excludes system-level overhead sec Excludes system-level overhead Sector Erase Time Chip Programming Time 14.4 (Note 1) 43.2 (Notes 2, 3) Notes: 1. 25°C, 5 V VCC, 100,000 cycles. 2. Although Embedded Algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 3. Under worst case condition of 90°C, 4.5 V VCC, 100,000 cycles. LATCHUP CHARACTERISTIC Input Voltage with respect to VSS on I/O pins VCC Current Min Max –1.0 V VCC + 1.0 V –100 mA +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Max Unit 6 7.5 pF Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF CIN Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 34 Min Am29F016 PHYSICAL DIMENSIONS TS 048 48-Pin Standard Thin Small Outline Package 0.95 1.05 Pin 1 I.D. 1 48 11.90 12.10 0.50 BSC 24 25 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.25MM (0.0098") BSC 16-038-TS48-2 TS 048 DA101 8-8-94 ae 0.50 0.70 Am29F016 35 PHYSICAL DIMENSIONS TSR048 48-Pin Reversed Thin Small Outline Package 0.95 1.05 Pin 1 I.D. 1 48 11.90 12.10 0.50 BSC 24 25 0.05 0.15 18.30 18.50 19.80 20.20 SEATING PLANE 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.25MM (0.0098") BSC 16-038-TS48 TSR048 DA104 8-8-94 ae 0.50 0.70 Trademarks Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies 36 Am29F016