PRELIMINARY DATASHEET ISD2360 Digital ChipCorder with Embedded Flash 3-Channel Audio Playback -1Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET TABLE OF CONTENTS 1 GENERAL DESCRIPTION .............................................................................................................. 4 2 FEATURES ...................................................................................................................................... 4 3 BLOCK DIAGRAM ........................................................................................................................... 6 4 PINOUT CONFIGURATION ............................................................................................................ 7 5 PIN DESCRIPTION – QFN32 .......................................................................................................... 8 6 DEVICE OPERATION .................................................................................................................... 10 6.1 6.2 6.3 6.4 7 AUDIO STORAGE..................................................................................................................................... 10 DEVICE CONFIGURATION ........................................................................................................................ 10 GPIO CONFIGURATION........................................................................................................................... 10 OSCILLATOR AND SAMPLE RATES .......................................................................................................... 11 MEMORY FORMAT ....................................................................................................................... 11 7.1.1 Voice Prompts ................................................................................................................................ 12 7.1.2 Voice Macros ................................................................................................................................. 12 7.1.3 User Data ....................................................................................................................................... 13 7.2 MEMORY CONTENTS PROTECTION ......................................................................................................... 13 8 SPI INTERFACE ............................................................................................................................ 14 9 SIGNAL PATH................................................................................................................................ 16 10 GPIO VOICE MACRO TRIGGERS ............................................................................................ 17 10.1 ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER ........................................................................ 17 10.2 VOICE MACRO EXAMPLES ...................................................................................................................... 17 10.2.1 POI/PU/WAKEUP Voice Macros .................................................................................................. 17 10.2.2 Example: Cycle through a sequence of messages. ......................................................................... 18 10.2.3 Example: Looping short sounds. Interrupt to stop playback. ........................................................ 19 10.2.4 Example: Uninterruptable Trigger, smooth audio. ........................................................................ 19 10.2.5 Example: Continuous Play until re-trigger. ................................................................................... 20 10.2.6 Example: Level Hold Trigger. ....................................................................................................... 21 11 CHANNEL SELECTION AND EXECUTION CONTROL............................................................ 21 11.1 SELECT CHANNEL FOR THE PLYABCK AND MIXING .............................................................................. 21 11.2 EXECUTION CONTROL ............................................................................................................................ 21 11.2.1 Conditional Branch and Unconditional Jump ............................................................................... 22 11.2.2 Execution Delay / Pause ................................................................................................................ 22 12 ELECTRICAL CHARACTERISTICS .......................................................................................... 23 12.1 OPERATING CONDITIONS ........................................................................................................................ 23 12.2 AC PARAMETERS ................................................................................................................................... 23 12.2.1 Internal Oscillator ......................................................................................................................... 23 12.2.2 Speaker Outputs ............................................................................................................................. 23 12.3 DC PARAMETERS ................................................................................................................................... 24 -2Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 12.4 13 13.1 13.2 14 14.1 SPI TIMING ............................................................................................................................................. 25 APPLICATION DIAGRAM .......................................................................................................... 26 SPI MODE APPLICATION ........................................................................................................................ 26 STANDALONE APPLICATION ................................................................................................................... 27 PACKAGE SPECIFICATION ...................................................................................................... 28 16 LEAD 300-MIL SOP .......................................................................................................................... 29 15 ORDERING INFORMATION ...................................................................................................... 30 16 REVISION HISTORY.................................................................................................................. 31 -3Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 1 GENERAL DESCRIPTION ® The ISD2360 is a 3-channel digital ChipCorder providing single-chip storage and playback of high quality audio. The device features digital de-compression, comprehensive memory management, flash storage, integrated audio signal path with up to 3 channel concurrent playback and Class D speaker driver capable of delivering power of 0.95W. This family utilizes flash memory to provide non-volatile audio playback with duration up to 64 seconds (based on 8kHz/4bit ADPCM compression) for a singlechip audio playback solution. The ISD2360 can be controlled and programmed through an SPI serial interface or operated standalone by triggers applied to the device‟s six GPIO pins. The ISD2360 requires no external clock sources or components except a speaker to deliver quality audio prompts or sound effects to enhance user interfaces. In addition the part can provide non-volatile flash storage in 1Kbyte sectors eliminating the need for additional serial EEPROM/Flash devices. Compared to previous ChipCorder series, this device provides higher sampling frequencies, improved SNR, lower power, fast programming time and integrated program verification. 2 FEATURES Duration o ISD2360 – 64 seconds based on 8kHz/4bit ADPCM in 2Mbit of flash storage (256KB) Audio Management o Store pre-recorded audio (Voice Prompts) using high quality digital compression o Use simple index based command for playback – no address needed. o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration of the device and playback Voice Prompts sequences. Path and playback Control o Up to 3 channel audio streaming can be mixed and played back concurrently o Each channel has independent counter which enables user micro-management on VM execution o Mask Jump allows branch execution depending on internal register or external GPIO pin status Control o Serial SPI interface for microprocessor control and programming. o Stand-alone control where customized Voice Macro scripts are assigned to GPIO trigger pins. Sample Rate o 7 sampling frequencies 4, 5.3, 6.4, 8, 12.8, 16 and 32 kHz are available. o Each Voice Prompt can have optimal sample rate. Compression Algorithms o µ-Law: 6, 7 or 8 bits per sample o Differential µ-Law: 6, 7 or 8 bits per sample o PCM: 8, 10 or 12 bits per sample o Enhanced ADPCM: 2, 3, 4 or 5 bits per sample o Variable-bit-rate optimized compression. This allows best possible compression given a metric of SNR and background noise levels. Oscillator o Internal oscillator with internal reference: factory trimmed to ±1% deviation at room temperature. -4Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Output o PWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer. o Delivers 400mW at 3V supply. I/Os o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data o 6 general purpose I/O pins multiplexed with SPI interface. Flash Storage o 2Mbit of storage for combined audio/data. o Fast programming time (20µs/byte) o Erase sector size 1Kbyte, sector erase time 2ms. o Integrated memory checksum calculation for fast verification. o Endurance >100K cycles. Retention > 10 years Operating Voltage: 2.4-5.5V Package: o Green, QFN32 Temperature Options: o Industrial: -40C to 85C -5Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET BLOCK DIAGRAM SP+ Digital Signal Path Digital Filters Digital Mixing Resampling Volume Control PWM Control SP- MOSI/GPIO(0) SCLK/GPIO(1) MISO/GPIO(2) INTB/GPIO(3) RDY/BSYB/GPIO(4) GPIO(5) SPI Interface GPIO Interface Memory management and Command Interpreter Ch1 De-Compression Memory management and Command Interpreter Ch2 De-Compression Memory management and Command Interpreter Ch3 De-Compression Internal Flash Memory SSB VSSDPWM VSSD Power Conditioning VCCDPWM Flash Memory Controller VCCD 3 Figure 3-1 ISD2360 Block Diagram -6Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 4 PINOUT CONFIGURATION Figure 4-1 ISD2360 32-Lead QFN Pin Configuration. Figure 4-2 ISD2360 16-Lead SOP Pin Configuration. -7Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 5 PIN DESCRIPTION – QFN32 Pin Number Pin Name I/O Function 1 NC This pin should be left unconnected. 2 NC This pin should be left unconnected. 3 MOSI / GPIO0 4 VSSD Digital Ground. 5 NC This pin should be left unconnected. 6 NC This pin should be left unconnected. 7 NC This pin should be left unconnected. 8 NC This pin should be left unconnected. 9 NC This pin should be left unconnected. 10 VCCD_PWM I Digital Power for the PWM Driver. 11 SPK+ O PWM driver positive output. This SPK+ output, together with SPK- pin, provide a differential output to drive 8Ω speaker or buzzer. During power down this pin is in tri-state. 12 VSSD_PWM I Digital Ground for the PWM Driver. 13 VSSD_PWM I Digital Ground for the PWM Driver. 14 SPK- O PWM driver negative output. This SPK- output, together with SPK+ pin, provides a differential output to drive 8Ω speaker or buzzer. During power down this pin is tri-state. 15 VCCD_PWM I Digital Power for the PWM Driver. 16 NC This pin should be left unconnected. 17 NC This pin should be left unconnected. 18 NC This pin should be left unconnected. 19 NC This pin should be left unconnected. 20 NC This pin should be left unconnected. 21 INTB / GPIO3 O Active low interrupt request pin. This pin is an open-drain output. Can be configured as a general purpose I/O pin. 22 RDY/BSYB / GPIO4 O An output pin to report the status of data transfer on the SPI interface. “High” indicates that ISD2360 is ready to accept new SPI commands or data. Can be configured as a general purpose I/O pin. 23 NC I Master-Out-Slave-In. Serial input to the ISD2360 from the host. Can be configured as a general purpose I/O pin. This pin should be left unconnected. -8Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Pin Number Pin Name I/O Function 24 NC This pin should be left unconnected. 25 NC This pin should be left unconnected. 26 VCCD 27 GPIO5 28 NC 29 MISO / GPIO2 O Master-In-Slave-Out. Serial output from the ISD2360 to the host. This pin is in tri-state when SSB=1. Can be configured as a general purpose I/O pin. 30 SCLK / GPI1 I Serial Clock input to the ISD2360 from the host. Can be configured as a general purpose input pin. 31 SSB I Slave Select input to the ISD2360 from the host. When SSB is low device is selected and responds to commands on the SPI interface. When asserted, GPIO0/1/2 automatically configure to MOSI/SCLK and MISO respectively. SSB has an internal pull-up to Vccd. 32 NC I I/O Digital Power. General purpose I/O pin This pin should be left unconnected. This pin should be left unconnected. -9Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 6 DEVICE OPERATION Playback of audio stored on the ISD2360 can be accomplished by either sending SPI commands via the serial interface or triggered by signal edges applied to GPIO pins. The device is programmed via the SPI interface either in-system or utilizing commercially available gang programmers. 6.1 AUDIO STORAGE The audio compression and customization of the ISD2360 is rapidly achieved with the supplied ISD2360VPE or Voice Prompt Editor. This software tool allows the developer to take audio clips in standard wave file format and re-sample and compress them for download to the ISD2360. Audio is stored in the ISD2360 as series of Voice Prompts: these units of audio can be of any length – the compression and sample rate of each Voice Prompt can be individually selected. A powerful feature of the ISD2360 is presence of a scripting ability Voice Macros. A Voice Macro can contain commands to play individual Voice Prompts and configure the ISD2360. A Voice Macro can be associated with a GPIO pin such that it is triggered by a transition on that pin. In this way stand-alone systems can be developed without the need for micro-controller interaction. Voice Macros can also be executed via the SPI command interface. Both Voice Prompts and Voice Macros are addressed via a simple sequential index address, no absolute memory address is required, thus audio source material or voice macro function can be updated (or changed for multi-language implementation) without the need to update microcontroller code. 6.2 DEVICE CONFIGURATION The ISD2360 is configured by writing to a set of configuration registers. This can be accomplished either by sending configuration via the serial SPI interface or executing Voice Macros containing configuration commands. Most configuration registers are reset to their default values when the device is powered down to ensure lowest possible standby current. Exceptions to this are registers that control the configuration of GPIO pins and Jump registers that contain the Voice Macro index to execute for GPIO triggers. Configuration registers may be initialized automatically in customizable Voice Macros that are executed on a power-on reset or power-up condition. 6.3 GPIO CONFIGURATION The six GPIO pins of the ISD2360 can be configured for a variety of purposes. Each pin can be configured to trigger a Voice Macro function. Each pin also has an alternate function allowing the pins to be configured as SPI, interrupt or oscillator reference pins. PS PE Logic DOUT PIN OE DIN Figure 6-1 GPIO Structure - 10 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET The structure of the GPIO pads is shown in Figure 6-1. Configuration registers allow the user to control pull-up and pull down resistors, enable the pin as an output or set the output value. See ISD2360 Design Guide for details on the configuration options. 6.4 OSCILLATOR AND SAMPLE RATES The ISD2360 has an internal oscillator trimmed at manufacturing that requires no external components to operate. This oscillator provides an internal clock source that operates the ISD2360 at a maximum audio sample rate of 32kHz. The sample rates available for audio storage at this maximum sample rate are shown in Table 6-1. The sample rate is selected during compression using the ISD2360 Voice Prompt Editor software. Table 6-1 Available Sample Rates. SR[2:0] 7 Ratio to Sample Rate 0 8 4 1 6 5.44 2 5 6.4 3 4 8 4 2.5 12.8 5 2 16 6 1 32 (kHz) MEMORY FORMAT The memory of the ISD2360 consists of byte addressable flash memory that is erasable in 1Kbyte sectors. Erased memory has a value of 0xFF. Writing to the memory allows host to change bits from erased „1‟ state to programmed „0‟ state. The memory of the ISD2360 is organized into four distinct regions as shown in Figure 7-1. The four regions are: 1. Configuration and Index Table: The first region of memory contains configuration data for the device and the index table that points to the Voice Prompt and Voice Macro data. The ISD2360VPE creates this section for download to the device. 2. Voice Macros: This section contains the script code of all the projects Voice Macros. 3. Voice Prompts: This section contains the compressed audio data for all Voice Prompts. 4. User Data: An optional section containing memory sectors allocated by the developer for generic use by the host controller. - 11 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Byte Sector Address Address 0 0 400h 1 800h 2 C00h 3 1800h 6 1FC00h 7F 20000h 80 Configuration and Index Table Voice Prompts Voice Macros PMP User Data Figure 7-1 ISD2360 Memory Organization 7.1.1 Voice Prompts Voice prompts are pre-recorded audio of any length, from short words, phrases or sound effects to long passages of music. These Voice Prompts can be played back in any order as determined by the application. A Voice Prompt consists of two components: 1. An index entry in the Index Table pointing to the pre-recorded audio. 2. Compressed pre-recorded audio data. A Voice Prompt is addressed using its index number to locate and play the pre-recorded audio. This address free approach allows users to easily manage the pre-recorded audio without the need to update the code on the host controller. In addition, the users can store a multitude of pre-recorded audio without the overhead of maintaining a complicated lookup table. To assist customers in creating the Voice Prompts, ISD2360 Voice Prompt Editor and writer are available for development purposes. 7.1.2 Voice Macros Voice Macros are a script that allows users to customize their own play patterns such as play Voice Prompts, insert silence, power-down the device and configure the signal path, including volume control. Voice Macros are executed using a single SPI command and are accessed using the same index structure as Voice Prompts. This means that a Voice Macro (or Voice Prompt) can be updated on the ISD2360 without the need to update code on the host microcontroller since absolute addresses are not needed. The following locations have been reserved for special Voice Macros: Index 0: Power-On Initialization (POI) - 12 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Index 1: Power-Up (PU) Index 2: GPIO-Wakeup (WAKEUP) These Voice Macros allow the users to customize the ISD2360 power-on, power-up and GPIO wake-up procedures and are executed automatically when utilized. If these Voice Macros are not used device will perform default operations on these events. An example to illustrate the usage of the PU Voice Macro is: WR_CFG(VOLC, 0x0C) ; Set VOLC to 0x0C WR_CFG(REG2, 0x44) ; Set REG2 to 0x44 WR_CFG (REG_GPIO_AF1 ,0xFF) ; Set REG_GPIO_AF1 to 0xFF WR_CFG (REG_GPIO_AF0 ,0x10) ; Set REG_GPIO_AF0 to 0x10 FINISH ; Exit Voice Macro The above PU Voice Macro will perform the following: Choose Volume Control for -3dB level. Configure and power up the signal path to decode compressed audio to speaker driver. Set up all GPIOs except GPIO4 for Falling edge trigger and set GPIO4 for both falling and rising edge trigger. The following is the complete list of the command available for use in Voice Macros: WR_CFG_REG(reg n) – Set configuration register reg to value n. PWR_DN – Power down the ISD2360. PLAY_VP(i) – Play Voice Prompt index i. PLAY_VP@(Rn) – Indirect Play Voice Prompt of index in register Rn PLAY_VP_LP(i,cnt) – Loop Play Voice Prompt index i, cnt times. PLAY_VP_LP@(Rn,cnt) – Indirect Loop Play Voice Prompt index in Rn, cnt times. EXE_VM(i) – Execute Voice Macro index i. EXE_VM@(Rn) – Indirect Execute Voice Macro index in register Rn PLAY_SIL(n) – Play silence for n units. A unit is 32ms at master sampling rate of 32 kHz. WAIT_INT – Wait until current play command finishes before executing next macro instruction. FINISH – Finish the voice macro and exit. These commands are equivalent to the commands available via the SPI interface and are described in Section 錯誤! 找不到參照來源。. 7.1.3 User Data User Data consists of 1KByte multiples of erasable sectors allocated by the user. This can be used as generic non-volatile storage by the host application. The developer has the freedom not to allocate or reserve any memory sectors. A software tool, the ISD2360 Voice Prompt Editor is available to assist customers in allocating such memory. 7.2 MEMORY CONTENTS PROTECTION - 13 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Under certain circumstances, it is desirable to protect portions of the internal memory from write/erase or interrogation (read). The ISD2360 provides a method to achieve this by setting a protection memory pointer (PMP) that allows the users to protect memory for an address range from the beginning of memory to this sector containing the PMP pointer. The type of protection is set by three bits in the memory header byte. Memory protection is activated on power-up of the chip. Therefore, each time the user changes the setting of memory protection, the new setting will not be effective until the chip is reset. 8 SPI INTERFACE This is a standard four-wire serial interface used for communication between ISD2360 and the host. It consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master Out Slave In MOSI), and a data output (Master In Slave Out - MISO). In addition, for some transactions requiring data flow control, a RDY/BSYB signal (pin) is available. The ISD2360 supports SPI mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data is sampled at SCLK rising edge. A SPI transaction begins on the falling edge of SSB and its waveform is illustrated below: SSB SCLK MISO MOSI Z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 X S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 X C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X Figure 8-1 SPI Data Transaction. A transaction begins with sending a command byte (C7-C0) with the most significant bit (MSB – C7) sent in first. During the byte transmission, the status (S7-S0) of the device is sent out via the MISO pin. After the byte transmission, depending upon the command sent, one or more bytes of data will be sent via the MISO pin. RDY/BSYB pin is used to handshake data into or out of the device. Upon completion of a byte transmission, RDY/BSYB pin could change its state after the rising edge of the SCLK if the built-in 32byte data buffer is either full or empty. At this point, SCLK must remain high until RDY/BSYB pin returns to high, indicating that the ISD2360 is ready for the next data transmission. See 如下 for timing diagram. - 14 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET TR / B SSB SCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RDY/BSYB =1 MISO MOSI Z =1 X PD RDY INT FULL X VG BUF BSY FUL X C7 C2 C6 C5 C4 C3 C1 CMD BSY C0 PD RDY INT FULL X VG BUF CMD BSY FUL BSY D7 D2 D6 D5 D4 D3 D1 D0 X Figure 8-2 RDY/BSYB Timing for SPI Writing Transactions. If the SCLK does not remain high, RDY bit of the status register will be set to zero and be reported via the MISO pin so the host can take the necessary actions (i.e., terminate SPI transmission and retransmit the data when the RDY/BSYB pin returns to high). For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from the ISD2360 device, MISO is used to read the data; therefore, the host must monitor the status via the RDY/BSYB pin and take the necessary actions. The INT pin will go low to indicate (1) data overrun/overflow when sending data to the ISD2360; or (2) invalid data from ISD2360. See Figure 8-3 for the timing diagram. To avoid RDY/BSYB polling for digital operations the following conditions must be met: Ensure device is idle (CMD_BSY=0 in status) before operation. Digital Write: Send 32 bytes of data or less in a digital write transaction or ensure that there is a 24µs period between each byte sent where SCLK is held high. Digital Read: Ensure a 2µs period between last address byte of digital read command and first data byte where SCLK is held high. - 15 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET TR / B SSB SCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RDY/BSYB =1 MISO MOSI Z =0 X PD RDY INT FULL X VG BUF CMD PD RDY INT FULL X BSY FUL BSY VG BUF CMD BSY FUL BSY X C7 C2 D2 C6 C5 C4 C3 C1 C0 D7 D6 D5 D4 D3 D1 D0 X INT Fi gure 8-3 SPI Transaction Ignoring RDY/BSYB 9 SIGNAL PATH The signal path performs filtering, sample rate conversion, volume control and decompression. A block diagram of the signal path is shown in Figure 9-1. The PWM driver output pins SPK- and SPK+ provide a differential output to drive an 8Ω speaker or buzzer. During power down these pins are in tristate. Pre-compressed audio transfers from memory or SPI interface through the de-compressor block to PWM driver or SPI out. The audio level is adjustable via VOLC before going out on to the PWM driver path. The possible path combinations are: MEMORY → DECOMPRESS → SPKR (Playback to speaker) MEMORY → DECOMPRESS → SPI_OUT (SPI playback) SPI_IN → DECOMPRESS → SPKR (SPI decode to speaker) For example to playback audio to speaker, enable decompression and PWM (write 0x44 to register 0x02) then send a PLAY_VP command to play audio. - 16 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Figure 9-1 ISD2360 Signal Path 10 GPIO VOICE MACRO TRIGGERS The ISD2360 Voice Macro capability and GPIO flexibility allows the user to configure the device to operate independently of the SPI interface or host micro-controller. GPIO triggering utilizes the Jump registers R0 through R6. When a GPIO trigger event occurs the ISD2360 executes the Voice Macro whose index is stored in the corresponding Jump register: that is GPIO0 will execute the VM whose index is stored in R0, GPIO1 in R1 etc. The initial values of the R0R6 registers can be set up in the POI Voice macro which is executed when a power-on reset condition is detected. When the ISD2360 responds to a trigger event, if a Voice Macro is currently being executed, that Voice Macro is first stopped before execution of new Voice Macro. 10.1 ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER For each GPIO pins, Register 0x14 and 0x15 can assign the playback channel for that GPIO. So once triggered, the playback audio streaming will be routed to that channel. 10.2 VOICE M ACRO EXAMPLES Below are some useful examples demonstrating the features Voice trigger macros. The example project can be found in the ISD2360VPE distribution as the ISD2360example project. 10.2.1 POI/PU/WAKEUP Voice Macros These special purpose Voice Macros allow the user to configure the ISD2360 for subsequent trigger events. The POI macro is executed when the chip receives an internal power-on reset condition or the SPI SW_RESET command is sent. The POI Voice macro is used to configure the ISD2360 for subsequent trigger events, for example: a. CFG(REG2, 0x44) ; Configure signal path to playback b. CFG(VOLC, 0x00) ; Set Volume to 0dB c. CFG(R5, 0x03) ; Set Jump register R5 to 0x03, GPIO5 to trigger VM#3 d. CFG(R4, 0x07) ; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7 e. CFG(R3, 0x09) ; Set Jump register R3 to 0x09, GPIO3 to trigger VM#9 f. CFG(R2, 0x0a) ; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A - 17 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET g. CFG(R1, 0x0c) ; Set Jump register R1 to 0x0c, GPIO1 to trigger VM#C h. CFG(R0, 0x0e) ; Set Jump register R0 to 0x0e, GPIO0 to trigger VM#E i. PLAY_VP(FastBeep) ; Play Voice Prompt FastBeep j. CFG(REG_GPIO_AF1, 0xff) ; Set up GPIOs to trigger off falling edges k. CFG(REG_GPIO_AF0, 0x00) l. PD ; Power Down This POI macro will initialize the GPIO configuration such that all GPIO triggers are enabled for falling edges and performs initialization of the jump registers to point to appropriate Voice Macros. It also configures the play path and plays a beep. At the end of the macro the chip powers down. The GPIO_WAKEUP is executed whenever the device is triggered from a power down state. a. CFG(REG2, 0x44) ; Configure signal path to playback b. CFG(VOLC, 0x00) ; Set Volume to 0dB c. CFG(R4, 0x07) ; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7 d. CFG(R2, 0x0a) ; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A e. Finish ; Exit Voice Macro, stay powered up. This GPIO_WAKEUP macro sets up the play path as settings in these registers are reset during power down. It also resets jump registers R4 and R2 to default conditions. 10.2.2 Example: Cycle through a sequence of messages. In this example a high-to-low transition on GPIO5 will initially trigger VM#3 as defined in the POI initialization macro. In VM#3 the Voice Prompt “One” is played and jump register R5 set to VM#4. Thus the next high-to-low transition on GPIO5 will trigger VM#4 and play Voice Prompt “Two”. Similarly next trigger will play “Three” then “Four” and back to “One”. Notice the difference in VM#4 where a WAIT_INTERRUPT command has been inserted before the setting of the jump register. If the GPIO5/SW6 button is pushed rapidly, so that play is interrupted, “Two” will continue to be repeated. Other Voice Macros, because the jump register is changed first, will always progress to the next step in sequence. VM#3: R5_Count_One (GPIO5) a. CFG(R5, 0x04) ; Configure GPIO5 to play VM#4 on next trigger b. Play(One) ; Play voice prompt “One” c. PD ; Power Down VM#4:Two a. Play(Two) ; Play voice prompt “Two” b. Wait Interrupt ; Wait until Play finishes c. CFG(R5, 0x05) ; Configure GPIO5 to play VM#5 on next trigger d. PD ; Power Down VM#5: Three a. CFG(R5, 0x06) ; Configure GPIO5 to play VM#6 on next trigger b. Play(Three) ; Play voice prompt “Three” c. PD ; Power Down VM#6: Four a. CFG(R5, 0x03) ; Configure GPIO5 to play VM# 3 on next trigger b. Play(Four) ; Play voice prompt “Four “ c. PD ; Power Down - 18 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 10.2.3 Example: Looping short sounds. Interrupt to stop playback. This example demonstrates how to loop short sound samples and use a trigger interrupt to stop playback. A trigger on GPIO4 will play a series of Voice Prompts until it is interrupted by another trigger to stop playback. VM#7 was associated with the GPIO4 trigger in the POI routine. The first action of this VM is to change the trigger VM to VM#8, thus if GPIO4 is re-triggered while the Voice Macro is running it will execute the power down voice macro rather than start the play sequence again. The next command sets the LRMP bit of REG1, under normal operation the compressor ramps signal level to zero after a sound sample is played to prevent a DC voltage appearing on the output. The LRMP bit prevents this from happening while a sample is looping allowing continuous audio. To loop a sound sample, the audio should be edited such that the last sample loops smoothly to the first. To do this, create the sample in a sound editor at the sample rate desired for storage then find the first sample that returns to the initial condition and cut back audio to one before this sample. Note that tones require different lengths to fulfill these conditions at a given sample rate and thus loop numbers vary to produce the same length of output audio. At the end of the VM REG1 is reset and the trigger is re-enabled back to VM#7 before powering down. VM#7: R4_PlayLoop (GPIO4) a. CFG(R4, 0x08) b. CFG(REG1, 0x20) c. LOOP_VP(Do,20) d. LOOP_VP(Re,250) e. LOOP_VP(Mi,5) f. LOOP_VP(Fa,33) g. LOOP_VP(So,10) h. LOOP_VP(La,10) i. LOOP_VP(Si,7) j. Silence (128 ms) k. CFG(REG1, 0x00) l. CFG(R4, 0x07) m. PD VM#8: PD_R4 a. CFG(REG1, 0x00) b. CFG(R4, 0x07) c. PD ; Configure GPIO4 to execute VM# 8 on next trigger. ; Configure LRMP bit in REG1 ; LOOP “Do” 20 times. ; LOOP “Re” 250 times. ; LOOP “Mi” 5 times. ; LOOP “Fa” 33 times. ; LOOP “So” 10 times ; LOOP “La” 10 times ; LOOP “Si” 7 times. ; Insert 128ms of silence ; Reset REG1 ; Configure GPIO4 to execute VM#7 on next trigger. ; Power Down ; Configure Register one to its default value 00 ; Configure GPIO4 to execute VM#7 on next trigger. ; Power Down 10.2.4 Example: Uninterruptable Trigger, smooth audio. In this example a single trigger on GPIO3 will sequence through several messages until all messages are played the playback cannot be interrupted by any other trigger. The example also demonstrates how to use begin and end segments to create smooth playback. Each “note” consists of concatenating three voice prompts, for instance “So_begin” “So” and “So_end”. The begin and end prompts ramp the audio smoothly to avoid sudden transients in sound level. The middle, full amplitude, section is created by looping a short sample. At the beginning of the Voice Macro, all triggers are disabled so that Voice Macro cannot be interrupted from any source. The NRMP bit of REG1 is set so that concatenation of audio occurs without any ramp down between prompts. At the end of the macro, interrupts are re-enabled and device is powered down. - 19 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET VM#9: R3_Non-Int_Smooth (GPIO3) a. CFG(REG_GPIO_AF1, 0x00) b. CFG(REG1, 0x04) c. PLAY_VP(So_begin) d. LOOP_VP(So,10) e. PLAY_VP(So_end) f. PLAY_VP(Fa_begin) g. LOOP_VP(Fa,33) h. PLAY_VP(Fa_end) i. PLAY_VP(Mi_begin) j. LOOP_VP(Mi,5) k. PLAY_VP(Mi_end) l. PLAY_VP(Re_begin) m. LOOP_VP(Re,250) n. PLAY_VP(Re_end) o. PLAY_VP(Do_begin) p. LOOP_VP(Do,20) q. PLAY_VP(Do_end) r. Wait Interrupt s. CFG(REG1, 0x00) t. CFG(REG_GPIO_AF1, 0x3f) u. PD ; Disable all triggers. ; Set NRMP bit ; Play “So_begin” ; Loop “So” 10 times. ; Play “So_end” ; Wait for audio to finish ; Reset NRMP bit ; Re-enable interrupts ; Power down device. 10.2.5 Example: Continuous Play until re-trigger. In this example a single trigger on GPIO2 will sequence through several messages with pause in between each message. Messages are played in a loop indefinitely until another trigger occurs on GPIO2 to stop playback. VM0#A: R2_Loop_VM (GPIO2) a. CFG(R2, 0x0b) ; Set Trigger to VM#B (PD_R2) b. PLAY_VP(One) ; Play “One” c. Silence (256 ms) ; pause 256ms d. PLAY_VP(two) ; Play “Two” e. Silence (256 ms) f. PLAY_VP(three) g. Silence (736 ms) h. PLAY_VP(four) i. Silence (256 ms) j. EXE_VM(0xA) ; Execute VM#A (repeat) k. Finish VM0#B: PD_R2 a. CFG(R2, 0x0a) ; Reset Trigger to VM#A b. PD ; Power Down. - 20 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 10.2.6 Example: Level Hold Trigger. In this example holding GPIO1 will play several messages. Releasing GPIO1 will stop the playback. No other triggers will affect operation. VM#C: R1_Level_Hold (GPIO1) a. CFG(REG_GPIO_AF0, 0x02) ; Enable rising edge trigger for GPIO2 b. CFG(REG_GPIO_AF1, 0x02) ; Disable all triggers except GPIO2 c. CFG(R1, 0x0d) ; Set Trigger to VM#D (PD_R1) d. CFG(REG1, 0x20) e. LOOP_VP(Re,200) f. Silence (32 ms) g. LOOP_VP(Mi,4) h. Silence (32 ms) i. LOOP_VP(Fa,20) j. Silence (32 ms) k. CFG(REG1, 0x00) l. PLAY_VP(applause) m. PD VM#D: PD_R1 a. CFG(REG_GPIO_AF0, 0x00) ; Disable rising edge trigger b. CFG(REG_GPIO_AF1, 0x3f) ; Re-enable all triggers. c. CFG(REG1, 0x00) ; Ensure REG1 reset d. CFG(R1, 0x0c) ; Set trigger to VM#C e. PD ; Power Down. 11 CHANNEL SELECTION AND EXECUTION CONTROL 11.1 SELECT CHANNEL FOR THE PLYABCK AND MIXING For any play command such as PLAY_VM or PLAY_VP, etc, the playback occurs in either one channel or all three channels. In other words, user can either specify one single active channel for next playback operation, or make the next play operation happen in all three channels. Channel selection can be achieved by configuring register 0x0C. To mix two different sound effects from two channels, e.g. channel #0 and channel #1, user can first configure channel #0 as the active channel by writing 0bxxxxxx00 into register 0x0C, then send a play command to play the first sound effect; then configure channel #1 as the active channel by writing 0bxxxxxx01 into register 0x0C, then send another play command to play the second sound effect. This way sound effect mixing can be achieved. By Default, play operations will always happen in channel #0. 11.2 EXECUTION CONTROL - 21 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET The ISD2360 implemented several commands which allow user add fine control in a VM script execution. 11.2.1 Conditional Branch and Unconditional Jump The ISD2360 can do mask branch which judges device‟s current pin status and its internal status register value against the value in mask register, to decide if jump to a memory address (and start execution from there) or continue executing the next script command inside the current VM. This gives the possibility of multi-tasking, i.e. let the ISD2360 do something during the play. The ISD2360 can also do an absolute jump, which jumps to a memory address and start execution from there. The new start address should be a valid command entry address; otherwise it will cause unknown behavior. The scope for the mask jump and absolute jump is global, i.e. the full range of the flash size. 11.2.2 Execution Delay / Pause The ISD2360 has time counter for each channel. So it allows customer add delay during a VM execution. This adds the convenience for certain operations such as GPIO driving with time control. - 22 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 12 ELECTRICAL CHARACTERISTICS 12.1 OPERATING CONDITIONS OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS) CONDITIONS VALUES Operating temperature range (Case temperature) Supply voltage (VDD) Ground voltage (VSS) Input voltage (VDD) -40°C to +85°C [1] +2.4V to +5.5V [2] 0V [1] 0V to 5.5V (VSS –0.3V) to (VDD +0.3V) Voltage applied to any pins NOTES: 12.2 [1] VDD = VCCD = VCCPWM [2] VSS = VSSD = VSSPWM AC PARAMETERS 12.2.1 Internal Oscillator PARAMETER SYMBOL Sample rate with Internal Oscillator MIN TYP MAX UNITS CONDITIONS -1% 32kHz +1% kHz Vdd = 3V. At room temperature 12.2.2 Speaker Outputs PARAMETER SYMBOL SNR, Memory to SPK+/SPK- SNRMEM_SPK Output Power POUT_SPK VCC=5.0 THD, Memory to SPK+/SPK- THD % Minimum Load Impedance RL(SPK) Notes: MIN [1] TYP MAX 60 0.95 UNITS dB Load 150Ω W Load 8Ω [2] Load 8Ω [2] <1% 4 8 CONDITIONS [2][3] Ω [1] Conditions Vcc=3V, TA=25°C unless otherwise stated. Based on 12-bit PCM. [3] All measurements are C-message weighted. [2] - 23 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 12.3 DC PARAMETERS MIN TYP [1] PARAMETER SYMBOL Supply Voltage VDD 2.4 5.5 V Input Low Voltage VIL VSS-0.3 0.3xVDD V Input High Voltage VIH 0.7xVDD VDD V Output Low Voltage VOL VSS-0.3 0.3xVDD V IOL = 1mA Output High Voltage VOH 0.7xVDD VDD V IOH = -1mA Pull-up Resistance RPU 50 kΩ Pull-down Resistance RPD 10 kΩ INTB Output Low Voltage VOH1 0.4 Playback Current IDD_Playback 3 Standby Current ISB <1 Input Leakage Current IIL Notes: [1] [2] MAX UNITS CONDITIONS V [2] mA No Load 10 µA VDD= 3.6V 1 µA Force VDD Conditions VDD=3V, TA=25°C unless otherwise stated To calculate total current, add load dissipation into application specific load. - 24 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 12.4 SPI TIMING TSSBHI SSB TSSBS TSSBH TSCK TRISE TFALL SCLK TSCKH TSCKL MOSI TMOS TMOH TZMID TMIZD MISO TMID TCRBD TRBCD RDY/BSYB Figure 12-1 SPI Timing SYMBOL DESCRIPTION MIN TSCK SCLK Cycle Time 60 TSCKH SCLK High Pulse Width TSCKL MAX UNIT --- --- ns 25 --- --- ns SCLK Low Pulse Width 25 --- --- ns TRISE Rise Time for All Digital Signals --- --- 10 ns TFALL Fall Time for All Digital Signals --- --- 10 ns TSSBS SSB Falling Edge to 1 SCLK Falling Edge Setup Time 30 --- --- ns TSSBH Last SCLK Rising Edge to SSB Rising Edge Hold Time 30ns --- 50us --- TSSBHI SSB High Time between SSB Lows 20 --- --- ns TMOS MOSI to SCLK Rising Edge Setup Time 15 --- --- ns TMOH SCLK Rising Edge to MOSI Hold Time 15 --- --- ns TZMID Delay Time from SSB Falling Edge to MISO Active -- -- 12 ns TMIZD Delay Time from SSB Rising Edge to MISO Tri-state -- -- 12 ns TMID Delay Time from SCLK Falling Edge to MISO --- --- 12 ns TCRBD Delay Time: SCLK Rising Edge to RDY/BSYB Falling Edge -- -- 12 ns TRBCD Delay Time: RDY/BSYB Rising Edge to SCLK Falling Edge 0 -- -- ns st TYP - 25 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 13 APPLICATION DIAGRAM 13.1 SPI MODE APPLICATION The following applications example is for reference only. It makes no representation or warranty that such applications shall be suitable for the use specified. Each design has to be optimized in its own system for the best performance on voice quality, current consumption, functionality etc. V CCD V CCD 26 0.1 µF V SSD ISD 2360 QFN - 32 VCCD 10 V CCD _ PWM 15 V CCD _ PWM V SSD _ PWM SPK + 29 MISO / GPIO 2 30 VCCD SPI Interface SCLK / GPI 1 31 SSB 3 10 K 21 MOSI / GPIO 0 22 INTB / GPIO 3 RDY /BSYB / GPIO 4 Data flow control 4 12 10 µF 0 .1 µF 11 SPK - 14 GPIO 5 27 Figure 13-1 ISD2360 Application Diagram Example for programming with a Microcontroller SPI Mode - 26 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 13.2 STANDALONE APPLICATION The following applications example is for reference only. It makes no representation or warranty that such applications shall be suitable for the use specified. Each design has to be optimized in its own system for the best performance on voice quality, current consumption, functionality etc. VCCD SWI 29 26 MISO/GPIO2 VCCD 4.7µF SW2 30 4 SCLK /GPIO1 VSSD V CCD 31 NC SW3 3 1 VCCD_PWM SSB ISD2360 VCCD_PWM QFN-32 VSSDPWM _ 10 15 12 10 µF 10 3 MOSI/GPIO0 SW4 21 SPK+ INTB/GPIO3 SW5 11 14 22 SPKRDY/BSYB/GPIO4 SW6 27 GPIO5/XCLK Figure 135-2 ISD2360 Application Diagram Stand-Alone Mode - 27 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 14 PACKAGE SPECIFICATION QFN 32L 5X5 MM^2, Thickness 0.8 MM(Max) ,Pitch 0.5 MM (Saw Type) (GR)EP Size 3.2X3.2MM - 28 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 14.1 16 LEAD 300-MIL SOP - 29 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 15 ORDERING INFORMATION I2360 x Y I x Blank: None R: Tape and Reel Temperature I: Industrial -40C to 85C Duration 60: 64 Seconds * Based on 8kHz/4bit ADPCM Lead-Free Y: green Package Type Y: 32L-QFN S: 16L-SOP - 30 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET 16 REVISION HISTORY Version Date Description 0.1 July 01, 2011 Initial draft. 0.2 Nov 22, 2011 Package update, Application Diagram update 0.3 Mar 21, 2022 Update package and ordering information - 31 Publication Release Date: 4/21/2012 Revision 0.3 PRELIMINARY DATASHEET Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if Nuvoton has been advised of the possibility of such damages. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD ® ChipCorder® product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change without notice. Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder ® and ISD® are trademarks of Nuvoton Electronics Corporation. All other trademarks are properties of their respective owners. Headquarters Nuvoton Technology Corporation America Nuvoton Technology (Shanghai) Ltd. No. 4, Creation Rd. III 2727 North First Street, San Jose, Science-Based Industrial Park, CA 95134, U.S.A. Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 886-3-5770066 FAX: 1-408-5441797 FAX: 886-3-5665577 http:www.nuvoton-usa.com/ http:www.nuvoton.com.tw/ 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office Nuvoton Technology Corporation Japan Nuvoton Technology (H.K.) Ltd. 9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 32 Publication Release Date: 4/21/2012 Revision 0.3