Vicor BCM4414BD1E13A2C10 Isolated, fixed-ratio dc-dc converter Datasheet

BCM® in a VIA Package
Bus Converter
BCM4414xD1E13A2yzz
Isolated, Fixed-Ratio DC-DC Converter
Features & Benefits
Product Ratings
• Up to 125A continuous low voltage side current
• Fixed transformation ratio(K) of 1/32
• Up to 711 W/in3 power density
• 97.1% peak efficiency
VHI = 384V (260 – 410V)
ILO = up to 125A
VLO = 12V (8.1 – 12.8V)
(no load)
K = 1/32
Product Description
• Built-in EMI filtering and In-rush limiting circuit
The BCM in a VIA package is a high efficiency Bus Converter,
operating from a 260 to 410VDC high voltage bus to deliver an
isolated 8.1 to 12.8VDC unregulated, low voltage.
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 4414 package
This unique ultra-low profile module incorporates DC-DC
conversion, integrated filtering and PMBus™ commands and
controls in a chassis or PCB mount form factor.
• High MTBF
• Thermally enhanced VIA™ package
The BCM offers low noise, fast transient response and industry
leading efficiency and power density. A low voltage side referenced
PMBus™ compatible telemetry and control interface provides
access to the BCM’s internal controller configuration, fault
monitoring, and other telemetry functions.
• PMBus™ management interface
• Suitable for hot-swap applications
Typical Applications
Leveraging the thermal and density benefits of Vicor’s VIA
packaging technology, the BCM module offers flexible thermal
management options with very low top and bottom side thermal
impedances.
• 380VDC Power Distribution
• Information and Communication
Technology (ICT) Equipment
When combined with downstream Vicor DC-DC conversion
components and regulators, the BCM allows the Power Design
Engineer to employ a simple, low-profile design which will
differentiate the end system without compromising on cost or
performance metrics.
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Energy Systems
• Transportation
• Green Buildings and Microgrids
Size:
4.35 x 1.40 x 0.37 in
110.55 x 35.54 x 9.40mm
Part Ordering Information
Product
Function
Package
Length
Package
Width
Package
Type
Max
High
Side
Voltage
BCM
44
14
x
D1
BCM =
Bus Converter
Module
Length in
Inches x 10
Width in
Inches x 10
B = Board VIA
V = Chassis VIA
[1]
High Side
Max
Voltage
Low
Range
Side
Ratio
Voltage
E
13
Max
Low
Side
Current
Product Grade
(Case Temperature)
Option Field
A2
y
zz
C = -20 to 100°C[1]
T = -40 to 100°C[1]
02 = Chassis/PMBus
06 = Short Pin/PMBus
10 = Long Pin/PMBus
Internal Reference
High Temperature Current Derating may apply; See Figure 1, specified thermal operating area.
BCM® in a VIA Package
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Typical Application
Host µC
PMBus
V
EXT
+
–
SGND
BCA_SGND
BCM in a VIA Package
BCA_SGND
EXT_BIAS
SCL
SDA
SGND
}
3
BCA_SGND
ADDR
FUSE
V
HI
C
+HI
+LO
–HI
–LO
Non-Isolated
Point of Load
Regulators
HI
HV
SOURCE_RTN
LOAD
LV
ISOLATION BOUNDRY
BCM4414xD1E13A2yzz at point of load
Host µC
PMBus
V
EXT
+
SGND
–
BCA_SGND
BCA_SGND
BCM in a VIA Package
EXT_BIAS
SCL
SDA
SGND
}
3
BCA_SGND
ADDR
FUSE
V
HI
C
+HI
+LO
–HI
–LO
LOAD
HI
HV
SOURCE_RTN
LV
ISOLATION BOUNDRY
BCM4414xD1E13A2yzz direct to load
BCM® in a VIA Package
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Pin Configuration
1
+HI
10
TOP VIEW
3
12
–LO
–LO
+LO
5
6
7
8
9
PMBus™
+LO
–LO
–LO
2
11
13
4
2
11
13
4
–HI
EXT BIAS
SCL
SDA
SGND
ADDR
BCM in a 4414 VIA Package - Chassis (Lug) Mount
–HI
TOP VIEW
–LO
–LO
+LO
9
8
7
6
5
PMBus™
+HI
1
–LO
–LO
10
12
ADDR
SGND
SDA
SCL
EXT BIAS
+LO
3
BCM in a 4414 VIA Package - Board (PCB) Mount
Note: The dot on the VIA housing indicates the location of the signal pin 9.
Pin Descriptions
Pin Number
Signal Name
Type
1
+HI
HIGH SIDE POWER
2
–HI
3, 4
+LO
5
EXT BIAS
INPUT
5V supply input
6
SCL
INPUT
I2C Clock, PMBus™ Compatible
7
SDA
INPUT/OUTPUT
I2C Data, PMBus™ Compatible
8
SGND
LOW SIDE
SIGNAL RETURN
Signal Ground
9
ADDR
INPUT
10, 11, 12, 13
–LO
LOW SIDE
POWER RETURN
HIGH SIDE POWER
RETURN
LOW SIDE
POWER
Function
Positive transformer power terminal on high voltage side
Negative transformer power terminal on high voltage side
Positive transformer power terminal on low voltage side
Address assignment - Resistor based
Negative transformer power terminal on low voltage side
Note: All signal pins (5, 6, 7, 8, 9) are referenced to low voltage side and isolated from the high voltage side.
BCM® in a VIA Package
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Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
+HI to –HI
Min
Max
Unit
-1
480
V
N/A
V/µs
15
V
HI_DC or LO_DC slew rate
+LO to –LO
-1
-0.3
EXT BIAS to SGND
10
V
0.15
A
SCL to SGND
-0.3
5.5
V
SDA to SGND
-0.3
5.5
V
ADDR to SGND
-0.3
3.6
V
Dielectric Withstand*
See note below
High Voltage Side to Case
Basic Insulation
2121
VDC
High Voltage Side to
Low Voltage Side
Reinforced Insulation (4242VDC)
2121
VDC
Low Voltage Side to Case
Functional Insulation
N/A
VDC
* Please see Dielectric Withstand section for details regarding test procedure, test values and insulation. The SELV side (-LO) is directly connected to the case
of the BCM in a VIA package.
BCM® in a VIA Package
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Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain High Voltage Side to Low Voltage Side Specification (Forward Direction)
HI Side Input Voltage range,
continuous
VHI_DC
260
410
V
HI Side Input Voltage range,
transient
VHI_TRANS
260
410
V
VHI µController
VµC_ACTIVE
130
V
HI to LO Input Quiescent Current
VHI_DC voltage where µC is initialized,
(powertrain inactive)
Disabled, VHI_DC = 384V
IHI_Q
2
TCASE ≤ 100ºC
4
VHI_DC = 384V, TCASE = 25ºC
HI to LO No Load Power Dissipation
HI to LO Inrush Current Peak
DC HI Side Input Current
Transformation Ratio
LO Side Output Current (continuous)
LO Side Output Current (pulsed)
HI to LO Efficiency (ambient)
5.9
VHI_DC = 384V
PHI_NL
IHI_IN_DC
ILO_OUT_DC
ILO_OUT_PULSE
24
16
VHI_DC = 260V to 410V
25
10
15
At ILO_OUT_DC = 125A, TCASE ≤ 95ºC
4.1
1/32
TCASE ≤ 95°C
125
A
2ms pulse, 25% Duty cycle, ILO_OUT_AVG ≤ 50% rated
ILO_OUT_DC
167
A
VHI_DC = 384V, ILO_OUT_DC = 125A
96.2
97
VHI_DC = 260V to 410V, ILO_OUT_DC = 125A
95.2
VHI_DC = 384V, ILO_OUT_DC = 62.5A
96.5
97.4
95.8
97
%
hHOT
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = 95°C
HI to LO Efficiency
(over load range)
ηh20%
25A < ILO_OUT_DC < 125A
95
RLO_COLD
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = -40°C
1.6
1.9
2.3
RLO_AMB
VHI_DC = 384V, ILO_OUT_DC = 125A
2.0
2.4
2.8
RLO_HOT
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = 95°C
2.5
2.8
3.2
Frequency of the LO Side Voltage Ripple = 2x FSW
0.95
1.00
1.05
Switching Frequency
LO Side Output Voltage Ripple
FSW
VLO_OUT_PP
CLO_EXT = 0μF, ILO_OUT_DC = 125A, VHI_DC = 384V,
20MHz BW
TCASE ≤ 100ºC
BCM® in a VIA Package
Page 5 of 40
A
V/V
HI to LO Efficiency (hot)
HI to LO Output Resistance
W
A
TCASE ≤ 100ºC
High Voltage to Low Voltage, K = VLO_DC / VHI_DC,
at no load
K
15
VHI_DC = 260V to 410V, TCASE = 25 ºC
VHI_DC = 410V, CLO_EXT = 1000μF, RLOAD_LO = 25% of full
load current
IHI_INR_PK
hAMB
11
mA
Rev 1.1
05/2016
%
%
195
MHz
mV
250
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain High Voltage Side to Low Voltage Side Specification (Forward Direction) Cont.
Effective HI Side Capacitance
(Internal)
CHI_INT
Effective Value at 384VHI_DC
0.4
µF
Effective LO Side Capacitance
(Internal)
CLO_INT
Effective Value at 12VLO_DC
238
µF
Effective LO Side Output Capacitance
(External)
CLO_OUT_EXT
Effective LO Side Output Capacitance
CLO_OUT_AEXT
(External)
Excessive capacitance may drive module into SC
protection
1000
µF
360
ms
CLO_OUT_AEXT Max = N * 0.5 * CLO_OUT_EXT MAX, where
N = the number of units in parallel
Powertrain Protection High Voltage Side to Low Voltage Side (Forward Direction)
Auto Restart Time
tAUTO_RESTART
Startup into a persistent fault condition. Non-Latching
fault detection given VHI_DC > VHI_UVLO+
290
HI Side Overvoltage Lockout
Threshold
VHI_OVLO+
430
440
450
V
HI Side Overvoltage Recovery
Threshold
VHI_OVLO-
410
430
440
V
HI Side Overvoltage Lockout
Hysteresis
VHI_OVLO_HYST
10
V
HI Side Overvoltage Lockout
Response Time
tHI_OVLO
100
µs
1
ms
HI Side Soft-Start Time
tHI_SOFT-START
LO Side Output Overcurrent
Trip Threshold
ILO_OUT_OCP
LO Side Output Overcurrent
Response Time Constant
tLO_OUT_OCP
LO Side Output Short Circuit
Protection Trip Threshold
ILO_OUT_SCP
LO Side Output Short Circuit
Protection Response Time
tLO_OUT_SCP
Overtemperature Shutdown
Threshold
tOTP+
BCM® in a VIA Package
Page 6 of 40
From powertrain active. Fast Current limit protection
disabled during Soft-Start
135
Effective internal RC filter
170
3
187
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125
A
ms
A
1
Temperature sensor located inside controller IC
(Internal Temperature)
210
µs
°C
BCM4414xD1E13A2yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
­Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Powertrain Supervisory Limits High Voltage Side to Low Voltage Side (Forward Direction)
HI Side Overvoltage Lockout
Threshold
VHI_OVLO+
420
434.5
450
V
HI Side Overvoltage Recovery
Threshold
VHI_OVLO-
405
424
440
V
HI Side Overvoltage Lockout
Hysteresis
VHI_OVLO_HYST
10.5
V
HI Side Overvoltage Lockout
Response Time
tHI_OVLO
100
µs
HI Side Undervoltage Lockout
Threshold
VHI_UVLO-
200
226
250
V
HI Side Undervoltage Recovery
Threshold
VHI_UVLO+
225
244
259
V
HI Side Undervoltage Lockout
Hysteresis
VHI_UVLO_HYST
15
V
HI Side Undervoltage Lockout
Response Time
tHI_UVLO
100
µs
20
ms
HI Side Undervoltage Startup Delay
tHI_UVLO+_DELAY
From VHI_DC = VHI_UVLO+ to powertrain active, (i.e One
time Startup delay form application of VHI_DC to VLO_DC)
LO Side Output Overcurrent Trip
Threshold
ILO_OUT_OCP
LO Side Output Overcurrent
Response Time Constant
tLO_OUT_OCP
Overtemperature Shutdown
Threshold
tOTP+
Temperature sensor located inside controller IC
(Internal Temperature)
125
Overtemperature Recovery
Threshold
tOTP–
Temperature sensor located inside controller IC
(Internal Temperature)
105
Undertemperature Shutdown
Threshold
tUTP
Temperature sensor located inside controller IC;
Protection not available for M-Grade units.
Undertemperature Restart Time
BCM® in a VIA Package
Page 7 of 40
tUTP_RESTART
159
Effective internal RC filter
177
2
Startup into a persistent fault condition. Non-Latching
fault detection given VHI_DC > VHI_UVLO+
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A
ms
°C
110
3
115
°C
-45
°C
s
BCM4414xD1E13A2yzz
LO Side Current (A)
150
125
100
75
50
25
0
-60
-40
-20
0
20
40
60
80
100
120
140
Case Temperature (°C)
260V – 410V
Figure 1 — Specified thermal operating area
1. The BCM in a VIA Package is cooled through bottom case (bottom housing).
2. The thermal rating of the BCM in a VIA Package is based on typical measured device efficiency.
3. The case temperature in the graph is the measured temperature of the bottom housing, such that operating internal junction temperature of the
BCM in a VIA Package does not exceed 125°C.
2500
200
175
2000
LO Side Current (A)
LO Side Power (W)
2250
1750
1500
1250
1000
750
500
125
100
75
50
25
250
0
150
260
275
290
305
320
335
350
365
380
395
0
410
260
275
290
HI Side Voltage (V)
PLO_OUT_DC
305
320
PLO_OUT_PULSE
ILO_OUT_DC
LO Side Capacitance
(% Rated CLO_EXT_MAX)
Figure 2 — Specified electrical operating area using rated RLO_HOT
110
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
LO Side Current (% ILO_DC)
Figure 3 — Specified HI side start-up into load current and external capacitance
BCM® in a VIA Package
Page 8 of 40
335
350
365
HI Side Voltage (V)
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100
ILO_OUT_PULSE
380
395
410
BCM4414xD1E13A2yzz
PMBus™ Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
Monitored Telemetry
• The BCM communication version is not intended to be used without a Digital Supervisor.
DIGITAL SUPERVISOR
PMBusTM READ COMMAND
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING RANGE
UPDATE
RATE
REPORTED UNITS
HI Side Voltage
(88h) READ_VIN
± 5%(LL - HL)
130V to 450V
100µs
VACTUAL = VREPORTED x 10-1
HI Side Current
(89h) READ_IIN
± 20%(10 - 20% of FL)
± 5%(20 - 133% of FL)
-0.85A to 5.9A
100µs
IACTUAL = IREPORTED x 10-3
LO Side Voltage[1]
(8Bh) READ_VOUT
± 5%(LL - HL)
4.25V to 14V
100µs
VACTUAL = VREPORTED x 10-1
LO Side Current
(8Ch) READ_IOUT
± 20%(10 - 20% of FL)
± 5%(20 - 133% of FL)
-27A to 190A
100µs
IACTUAL = IREPORTED x 10-2
LO Side Resistance
(D4h) READ_ROUT
± 5%(50 - 100% of FL) at NL
± 10%(50 - 100% of FL)(LL - HL)
1.0mΩ to 3.0mΩ
100ms
RACTUAL = RREPORTED x 10-5
(8Dh) READ_TEMPERATURE_1
± 7°C(Full Range)
- 55ºC to 130ºC
100ms
TACTUAL = TREPORTED
ATTRIBUTE
Temperature[2]
[1]
[2]
Default READ LO side Voltage returned when unit is disabled = -300V.
Default READ Temperature returned when unit is disabled = -273°C.
Variable Parameter
• Factory setting of all below Thresholds and Warning limits are 100% of listed protection values.
• Variables can be written only when module is disabled either EN pulled low or VHI < VHI_UVLO-.
• Module must remain in a disabled mode for 3 ms after any changes to the below variables allowing ample time to commit changes to EEPROM.
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING
RANGE
DEFAULT
VALUE
± 5%(LL - HL)
130V to 435V
100%
± 5%(LL - HL)
130V to 435V
100%
± 5%(LL - HL)
130V to 260V
100%
(5Bh) IIN_OC_FAULT_LIMIT
± 20%(10 - 20% of FL)
± 5%(20 - 133% of FL)
0 to 5.25A
100%
(5Dh) IIN_OC_WARN_LIMIT
± 20%(10 - 20% of FL)
± 5%(20 - 133% of FL)
0 to 5.25A
100%
ATTRIBUTE
DIGITAL SUPERVISOR
PMBusTM COMMAND [3]
CONDITIONS / NOTES
HI Side Overvoltage
Protection Limit
(55h) VIN_OV_FAULT_LIMIT
VHI_OVLO- is automatically 3%
lower than this set point
HI Side Overvoltage
Warning Limit
(57h) VIN_OV_WARN_LIMIT
HI Side Undervoltage
Protection Limit
(D7h) DISABLE_FAULTS
HI Side Overcurrent
Protection Limit
HI Side Overcurrent
Warning Limit
Can only be disabled to a preset
default value
Overtemperature
Protection Limit
(4Fh) OT_FAULT_LIMIT
Internal Temperature
± 7°C(Full Range)
0 to 125°C
100%
Overtemperature
Warning Limit
(51h) OT_WARN_LIMIT
Internal Temperature
± 7°C( Full Range)
0 to 125°C
100%
± 50µs
0 to 100ms
0 ms
Turn on Delay
[3]
(60h) TON_DELAY
Additional time delay to the
Undervoltage Startup Delay
Refer to internal µc datasheet for complete list of supported commands.
BCM® in a VIA Package
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Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted. Please Note: For chassis mount model, Vicor part number 42550 will be
needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to five insertions and extractions. To avoid unnecessary stress on the
connector, the cable should be tied to the chassis.
EXT. BIAS (VDDB) Pin
• 5V supply input, required to power the circuitry internal to the BCM in a VIA package for communication signals such as SCL, SDA, ADDR etc
• Voltage to EXT BIAS pin is needed for PMBus™ enable and disable control. It is not needed for PMBus monitoring voltage, current, power or temperature.
Lower voltage is better. It will help to lower the power dissapation in the internal regulator that is generating 3.3 V voltage for communication circuits.
• Apply voltage to this pin between 4.5V and 9V. The nominal voltage is 5V.
SIGNAL TYPE
STATE
Regular
Operation
INPUT
Startup
ATTRIBUTE
SYMBOL
VDDB Voltage
VVDDB
VDDB Current consumption
IVDDB
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
4.5
5
9
V
50
mA
Inrush Current Peak
IVDDB_INR
VVDDB Slew Rate = 1V/µs
3.5
A
Turn on time
tVDDB_ON
From VVDDB_MIN to PMBus active
1.5
ms
SGND Pin
• This pin is supply return pin for Ext. Bias (VDDB) pin.
• All input and output signals (SCL, SDA, ADDR) are referenced to SGND pin.
Address (ADDR) Pin
• This pin programs only a Fixed and Persistent slave address for BCM in a VIA package.
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during startup and is used until power is reset.
• This pin has 10 kΩ pullup resistor internally between ADDR pin and internal VDD.
• 16 addresses are available. Relative to nominal value of internal VDD (VVDD_NOM = 3.3V), a 206.25mV range per address.
SIGNAL TYPE
MULTI‐LEVEL
INPUT
STATE
Regular
Operation
Startup
BCM® in a VIA Package
Page 10 of 40
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
ADDR Input Voltage
VSADDR
See address section
ADDR leakage current
ISADDR
Leakage current
ADDR registration time
tSADDR
From VVDD_IN_MIN
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MIN
TYP
0
1
MAX
UNIT
3.3
V
1
µA
ms
BCM4414xD1E13A2yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High‐power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip‐flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
Electrical Parameters
Input Voltage Threshold
Output Voltage Threshold
Leakage current
VIH
VVDD_IN = 3.3V
VIL
VVDD_IN = 3.3V
VOH
VVDD_IN = 3.3V
VOL
VVDD_IN = 3.3V
0.4
V
Unpowered device
10
µA
ILEAK‐PIN
Signal Sink Current
ILOAD
2.1
0.8
3
VOL = 0.4V
CI
Signal Noise Immunity
VNOISE_PP
mA
10
10MHz to 100MHz
300
Idle state = 0Hz
10
V
V
4
Total capacitive load of
one device pin
Signal Capacitive Load
V
pF
mV
Timing Parameters
DIGITAL
INPUT/OUTPUT
Regular
Operation
Operating Frequency
FSMB
Free time between
Stop and Start Condition
tBUF
Hold time after Start or
Repeated Start condition
tHD:STA
Repeat Start Condition
Setup time
tSU:STA
First clock is generated
after this hold time
µs
0.6
µs
0.6
µs
tSU:STO
0.6
µs
tHD:DAT
300
ns
Data Setup time
tSU:DAT
100
ns
Clock low time out
tTIMEOUT
25
Clock low period
tLOW
1.3
Clock high period
tHIGH
0.6
35
ms
µs
50
µs
25
ms
Cumulative clock low
extend time
tLOW:SEXT
Clock or Data Fall time
tF
Measured from
(VIL_MAX ‐ 0.15) to (VIH_MIN + 0.15)
20
300
ns
Clock or Data Rise time
tR
0.9 • VVDD_IN_MAX to (VIL_MAX ‐ 0.15)
20
300
ns
tF
VIH
VIL
tHD,STA
SDA
BCM® in a VIA Package
Page 11 of 40
1.3
Data Hold time
tLOW tR
P
KHz
Stop Condition setup time
SCL
VIH
VIL
400
tBUF
tHD,DAT
S
tHIGH
tSU,DAT
tSU,STA
tSU,STO
S
Rev 1.1
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BCM® in a VIA Package
Page 12 of 40
Rev 1.1
05/2016
OUTPUT
INPUT
+VLO
+VHI
VµC_ACTIVE
DC
I
E
LIZ
VHI_OVLO+
VNOM
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STARTUP
E
I
N
U
NP
T
E
OV
OVER VOLTAGE
VHI_UVLO-
VHI_OVLO-
ID
R
TU
S
HI
UT
O
UT
O
IA
IT DE
IN O SI
µc L
N
-O
tHI _UVLO+_DELAY
VHI_UVLO+
I_
VH
UT
NP
RN
TU
O
NR
V
T
OL
AG
tLO_OUT_SCP
W
LO
D
D
LE LLE
L
IT
PU PU
P
IN
LE LE
C
AB AB
_D
I
N
VH
E
EN
ST
RE
T
AR
T
OR
SH
GH
HI
>
ENABLE CONTROL
OVER CURRENT
E
HI
T
S
GE
TA
L
VO
T OFF
U
P
IN RN
E TU
D
I
SHUTDOWN
T
UI
RC
CI
EN
EV
BCM4414xD1E13A2yzz
Timing Diagram (Forward Direction)
BCM4414xD1E13A2yzz
Application Characteristics
30
HI to LO, Full Load Efficiency (%)
27
24
21
18
15
12
9
6
3
0
260
275
290
305
320
335
350
365
380
395
98.0
97.5
97.0
96.5
96.0
95.5
95.0
94.5
94.0
410
-40
-20
0
HI Side Input Voltage (V)
- 40°C
25°C
VHI_DC:
85°C
80
97
72
95
64
93
56
91
48
89
40
87
32
24
PD
83
16
81
8
79
0
0.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
HI to LO, Power Dissipation
HI to LO, Efficiency (%)
99
85
384V
72
95
64
93
56
91
48
89
40
32
PD
24
83
16
81
8
0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
72
95
64
93
56
91
48
89
40
87
32
85
260V
384V
83
16
81
79
8
0.0
0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
Rev 1.1
05/2016
260V
384V
410V
5
4
3
2
1
0
-40
-20
0
20
40
60
Case Temperature (°C)
410V
Figure 8 — Efficiency and power dissipation at TCASE = 85°C
BCM® in a VIA Package
Page 13 of 40
24
PD
LO Side Output Current (A)
VHI_DC :
410V
Figure 7 — Efficiency and power dissipation at TCASE = 25°C
HI to LO, Power Dissipation
HI to LO, Efficiency (%)
97
0.0
384V
LO Side Output Current (A)
80
79
260V
VHI_DC :
99
85
100
80
410V
Figure 6 — Efficiency and power dissipation at TCASE = -40°C
87
80
97
HI to LO, Output Resistance (mΩ)
260V
60
99
LO Side Output Current (A)
VHI_DC :
40
Figure 5 — Full load efficiency vs. temperature; VHI_DC
Figure 4 — No load power dissipation vs. VHI_DC
HI to LO, Efficiency (%)
TTOP SURFACE CASE:
20
Case Temperature (ºC)
HI to LO, Power Dissipation
HI to LO, Power Dissipation (W)
Product is mounted and temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected data from High
Voltage sourced units processing power in forward direction. See associated figures for general trend data.
ILO_DC:
125A
Figure 9 — RLO vs. temperature; Nominal VHI_DC
ILO_DC = 125A at TCASE = 85°C
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100
BCM4414xD1E13A2yzz
80
LO Side Output
Voltage Ripple (mV)
72
64
56
48
40
32
24
16
8
0
0.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
LO Side Output Current (A)
VHI_DC:
384V
Figure 10 — VLO_OUT_PP vs. ILO_DC ; No external CLO_OUT_EXT. Board
mounted module, scope setting : 20MHz analog BW
Figure 11 — Full load ripple, 10 µF CHI_IN_EXT; No external
CLO_OUT_EXT. Boardmounted module, scope setting :
20MHz analog BW
Figure 12 — 0A– 125A transient response:
CHI_IN_EXT = 10µF, no external CLO_OUT_EXT
Figure 13 — 125A – 0A transient response:
CHI_IN_EXT = 10µF, no external CLO_OUT_EXT
Figure 14 — Start up from application of VHI_DC = 384V, 25% ILO_DC,
100% CLO_OUT_EXT
Figure 15 — Start up from application of EN with pre-applied VHI_DC = 384V, 25% ILO_DC, 100% CLO_OUT_EXT
BCM® in a VIA Package
Page 14 of 40
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General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
Length
L
Lug (Chassis) Mount
110.30 / [4.34] 110.55 / [4.35] 110.80 / [4.36] mm / [in]
Length
L
PCB (Board) Mount
112.51 / [4.43] 112.76 / [4.44] 113.01 / [4.45] mm / [in]
Width
W
35.29 / [1.39]
35.54 / [1.40] 35.79 / [1.41]
Height
H
9.019 / [0.355]
9.40 / [0.37] 9.781 / [0.385] mm / [in]
Volume
Vol
Weight
W
Without heatsink
36.93 / [2.25]
cm3/ [in3]
140.5 / [4.96]
g / [oz]
Pin Material
C145 copper, 1/2 hard
Underplate
Low stress ductile Nickel
50
100
Palladium
0.8
6
Soft Gold
0.12
2
BCM4414xD1E13A2yzz (T-Grade)
-40
125
BCM4414xD1E13A2yzz (C-Grade)
BCM4414xD1E13A2yzz (T-Grade),
derating applied, see safe thermal
operating area
-20
125
-40
100
-20
100
Pin Finish
mm / [in]
µin
µin
Thermal
Operating junction temperature
Operating case temperature
Thermal resistance top side
Thermal Resistance Coupling between
top case and bottom case
Thermal resistance bottom side
TINTERNAL
TCASE
BCM4414xD1E13A2yzz (C-Grade),
derating applied, see safe thermal
operating area
RJC_TOP
RHOU
RJC_BOT
°C
Estimated thermal resistance to
maximum temperature internal
component from isothermal top
0.97
°C/W
Estimated thermal resistance of thermal
coupling between the top and bottom
case surfaces
0.57
°C/W
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
0.67
°C/W
54
Ws/°C
Thermal capacity
Assembly
Storage
Temperature
TST
-40
125
°C
BCM4414xD1E13A2yzz (C-Grade)
-40
125
°C
ESDHBM
Human Body Model,
“ESDA / JEDEC JDS-001-2012” Class I-C
(1kV to < 2kV)
1000
ESDCDM
Charge Device Model,
“JESD 22-C101-E” Class II (200V to
< 500V)
200
ESD Withstand
BCM® in a VIA Package
Page 15 of 40
BCM4414xD1E13A2yzz (T-Grade)
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General Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
780
940
pF
Safety
Isolation capacitance
CHI_LO
Unpowered unit
620
Isolation resistance
RHI_LO
At 500VDC
10
MTBF
MΩ
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
2.31
MHrs
Telcordia Issue 2 - Method I Case III;
25°C Ground Benign, Controlled
3.41
MHrs
Agency approvals / standards
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
BCM® in a VIA Package
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BCM in a VIA Package
ILO
IHI
RLO
+
+
K • ILO
VHI
+
IHI_Q
–
V•I
K
+
K • VHI
VLO
–
–
–
Figure 16 — BCM DC model (Forward Direction)
The BCM in a VIA package uses a high frequency resonant tank
to move energy from high voltage side to low voltage side and
vice versa. The resonant LC tank, operated at high frequency, is
amplitude modulated as a function of HI side voltage and LO side
current. A small amount of capacitance embedded in the high
voltage side and low voltage side stages of the module is sufficient
for full functionality and is key to achieving high power density.
The use of DC voltage transformation provides additional
interesting attributes. Assuming that RLO = 0Ω and IHI_Q = 0A,
Eq. (3) now becomes Eq. (1) and is essentially load independent,
resistor R is now placed in series with VHI.
The BCM4414xD1E13A2yzz can be simplified into the preceeding
model.
At no load:
Vin
VHI
VLO = VHI • K
+
–
BCM
SAC
1/32
KK == 1/32
V
Vout
LO
(1)
K represents the “turns ratio” of the BCM.
Rearranging Eq (1):
K=
R
R
Figure 17 — K = 1/32 BCM with series HI side resistor
VLO
(2)
VHI
In the presence of load, VLO is represented by:
VLO = VHI • K – ILO • RLO
The relationship between VHI and VLO becomes:
VLO = (VHI – IHI • R) • K
(3)
(5)
Substituting the simplified version of Eq. (4)
(IHI_Q is assumed = 0A) into Eq. (5) yields:
and ILO is represented by:
I –I
ILO = HI HI_Q
K
(4)
RLO represents the impedance of the BCM, and is a function of the
RDS_ON of the HI side and LO side MOSFETs, PC board resistance of
HI side and LO side boards and the winding resistance of the power
transformer. IHI_Q represents the HI side quiescent current of the
BCM control, gate drive circuitry, and core losses..
BCM® in a VIA Package
Page 17 of 40
Rev 1.1
05/2016
VLO = VHI • K – ILO • R • K2
(6)
This is similar in form to Eq. (3), where RLO is used to represent the
characteristic impedance of the BCM. However, in this case a real R
on the high voltage side of the BCM is effectively scaled by K 2 with
respect to the low voltage side.
Assuming that R = 1Ω, the effective R as seen from the low voltage
side is 1.0mΩ, with K = 1/32.
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A similar exercise should be performed with the additon of a
capacitor or shunt impedance at the high voltage side of the BCM.
A switch in series with VHI is added to the circuit. This is depicted in
Figure 18.
SS
VVin
HI
+
–
C
BCM
SAC
K=
= 1/32
1/32
K
VVout
LO
Low impedance is a key requirement for powering a highcurrent, low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, the benefits are
not useful if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e. well beyond the crossover
frequency of the system.
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables small magnetic
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss core
material at high frequencies also reduces core losses.
Figure 18 — BCM with High side capacitor
The two main terms of power loss in the BCM module are:
A change in VHI with the switch closed would result in a change in
capacitor current according to the following equation:
n No load power dissipation (PHI_NL): defined as the power
dVHI
(7)
Ic(t) = C
dt
Assume that with the capacitor charged to VHI, the switch is
opened and the capacitor is discharged through the idealized BCM.
In this case,
n Resistive loss (RLO): refers to the power loss across Ic= ILO • K
(8)
substituting Eq. (1) and (8) into Eq. (7) reveals:
C dVLO
•
2
dt
K
(9)
ILO =
used to power up the module with an enabled powertrain
at no load.
the BCM module modeled as pure resistive impedance.
Pdissipated = PHI_NL + PRLO
(10)
Therefore,
PLO_OUT = PHI_IN – Pdissipated = PHI_IN – PHI_NL – PRLO
The above relations can be combined to calculate the overall
module efficiency:
The equation in terms of the LO side has yielded a K 2 scaling factor
for C, specified in the denominator of the equation.
PLO_OUT
PHI_IN – PHI_NL – PRLO
h
=
=
PHI_INPHI_IN
A K factor less than unity results in an effectively larger capacitance
on the low voltage side when expressed in terms of the high
voltage side. With a K = 1/32 as shown in Figure 18, C = 1µF would
appear as C = 1024µF when viewed from the low voltage side.
VHI • IHI – PHI_NL – (ILO)2 • RLO
=
VHI • IHI
(
PHI_NL + (ILO)2 • RLO
= 1 –
VHI • IHI
BCM® in a VIA Package
Page 18 of 40
Rev 1.1
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Thermal Considerations
RJC
+ TC_BOT
–
The VIA™ package provides effective conduction cooling from
either of the two module surfaces. Heat may be removed from the
top surface, the bottom surface or both. The extent to which these
two surfaces are cooled is a key component for determining the
maximum power that can be processed by a VIA, as can be seen
from specified thermal operating area in Figure 1. Since the VIA has
a maximum internal temperature rating, it is necessary to estimate
this internal temperature based on a system-level thermal solution.
To this purpose, it is helpful to simplify the thermal solution into a
roughly equivalent circuit where power dissipation is modeled as
a current source, isothermal surface temperatures are represented
as voltage sources and the thermal resistances are represented as
resistors. Figure 19 shows the “thermal circuit” for the VIA module.
s
PDISS
s
Figure 20 — Single-sided cooling VIA thermal model
n Double side cooling: while this option might bring limited
advantage to the module internal components (given the
surface-to-surface coupling provided), it might be appealing in
cases where the external thermal system requires allocating
power to two different elements, like for example heatsinks with
independent airflows or a combination of chassis/air cooling.
+
RJC_TOP
TC_TOP
–
RHOU
–
PDISS
RJC_BOT
s
Current Sharing
TC_BOT
+
The performance of the BCM in a VIA package is based on efficient
transfer of energy through a transformer without the need of
closed loop control. For this reason, the transfer characteristic
can be approximated by an ideal transformer with a positive
temperature coefficient series resistance.
s
Figure 19 — Double sided cooling VIA thermal model
In this case, the internal power dissipation is PDISS, R JC_TOP and
R JC_BOT are thermal resistance characteristics of the VIA module and
the top and bottom surface temperatures are represented as TC_TOP,
and TC_BOT. It is interesting to notice that the package itself provides
a high degree of thermal coupling between the top and bottom
case surfaces (represented in the model by the resistor RHOU). This
feature enables two main options regarding thermal designs:
n Single side cooling: the model of Figure 19 can be simplified by
calculating the parallel resistor network and using one simple thermal resistance number and the internal power dissipation curves; an example for bottom side cooling only is shown in
Figure 20.
Some general recommendations to achieve matched array
impedances include:
n Dedicate common copper planes/wires within the PCB/Chassis
to deliver and return the current to the VIA modules.
n Provide as symmetric a PCB/Wiring layout as possible among
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
(RJC_TOP + RHOU) • RJC_BOT
(14)
RJC_TOP + RHOU + RJC_BOT
BCM® in a VIA Package
Page 19 of 40
When multiple BCM modules of a given part number are
connected in an array they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point of load.
VIA™ modules
In this case, R JC can be derived as following:
RJC =
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
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Dielectric Withstand
VHI
ZHI_EQ1
BCM®1
ZLO_EQ1
R0_1
ZHI_EQ2
BCM®2
The chassis of the BCM in a VIA Package is required to be
connected to Protective Earth when installed in the end application
and must satisfy the requirements of IEC 60950-1 for
Class I products.
VLO
ZLO_EQ2
R0_2
+ DC
Load
ZHI_EQn
BCM®n
ZLO_EQn
R0_n
The BCM in a VIA Package contains an internal safety approved
isolating component (VI ChiP) that provides the Reinforced
Insulation from high voltage side to low voltage side. The isolating
component is individually tested for Reinforced Insulation from
high voltage side to low voltage side at 4242VDC prior to the final
assembly of the VIA™. When the VIA™ assembly is complete the
Reinforced Insulation can only be tested at Basic Insulation values
as specified in the electric strength Test Procedure noted in clause
5.2.2 of IEC 60950-1.
Test Procedure Note from IEC 60950-1
Figure 21 — BCM module array
“For equipment incorporating both REINFORCED INSULATION and
lower grades of insulation, care is taken that the voltage applied
to the REINFORCED INSULATION does not overstress BASIC
INSULATION or SUPPLEMENTARY INSULATION.”
Fuse Selection
Summary
In order to provide flexibility in configuring power systems, BCM in
a VIA package modules are not internally fused. Input line fusing of
BCM in a VIA package products is recommended at system level to
provide thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
n Current rating
(usually greater than maximum current of BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: 10A Littelfuse 505 Series or
10A Littelfuse 487 Series (HI side)
Reverse Operation
BCM modules are capable of reverse power operation. Once the
unit is started, energy will be transferred from low side voltage
back to the high voltage side whenever the low voltage side
exceeds VHI • K. The module will continue operation in this fashion
for as long as no faults occur.
The final VIA assembly provides basic insulation from high voltage
side to case, reinforced insulation from high voltage side to low
voltage side and functional insulation from low voltage side to
case. Both sides of the housing are required to be connected to
Protective Earth to satisfy safety and EMI requirements. Protective
earthing can be accomplished through dedicated wiring harness
(example: ring terminal clamped by mounting screw) or surface
contact (example: pressure contact on bare conductive chassis or
PCB copper layer with no solder mask).
The case is required to be connected to protective earth in the
final installation. The ground connection of the top case has to
be 3 orders of magnitude more resistive than the current return
connection to the bottom case. The bottom case connection
is expected to be 100µΩ (or less). Therefore, the grounding
connection of the top case should be greater than 100mΩ. The
construction of the VIA can be summarized by describing it as a
“Class II” component installed in a “Class I” subassembly. The
insulation from high voltage side to low voltage side can only be
tested at basic insulation values on the completely assembled
VIA product.
VI ChiP Isolation
High voltage side
Low voltage side
The BCM4414xD1E5135yzz has not been qualified for continuous
operation in a reverse power condition. Furthermore fault
protections which help protect the module in forward operation
will not fully protect the module in reverse operation.
SELV
Transient operation in reverse is expected in cases where there is
significant energy storage on the low voltage side and transient
voltages appear on the high voltage side.
RI
Figure 22 — VI Chip before final assembly in the VIA
BCM® in a VIA Package
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VIA BCM Isolation
EMI
Receiver
+HI
+LO
VI ChiP
High voltage side
Low voltage side
SELV
VIA HI Side Circuit
DC
Power
Supply
VIA LO Side Circuit
-HI
Screen
Room /
Filters
LISN
LISN
+HI
+LO
Single
VIA BCM
(DUT)
–HI
–LO
Load
-LO
RI
BI
PE
FI
Figure 24 — Typical test set-up block diagram for
Conducted Emissions
Figure 23 — BCM in a VIA package after final assembly
Hot Swap
Filtering
The BCM in a VIA Package has built-in single stage EMI filtering
with hot-swap circuitry located on high voltage side. Typical test
set-up block diagram for conducted emissions is shown in Figure
24. Hot-swap circuitry provides inrush current limiting through
the MOSFET.
Many applications use a power architecture based on a 380VDC
distribution bus. This supply level is emerging as a new standard
and efficient means for distributing power through boards,
racks and chassis mounted Telecom and Datacom system. The
interconnect between the different modules is accomplished with
a backplane and motherboard. Power is commonly provided to the
various module slots via a 380VDC distribution bus.
Further, along with internal ceramic capacitance, it reduces the
voltage ripple. External LO side filtering can be added as needed.
Ceramic capacitance can be used as a LO side bypass for this
purpose. Moreover, along with hot-swap circuitry, it protects the
VIA from overvoltage transients imposed by a system that would
exceed maximum ratings and induce stresses. VIA HI side and LO
side voltage ranges shall not be exceeded. An internal overvoltage
function prevents operation outside of the normal operating HI
side range. Even when disabled, the VIA is exposed to the applied
voltage and the VIA must withstand it.
Removing the faulty module from the rack is relatively easy,
provided the remaining power modules can support the step
increase in load. Plugging in the replacement module has
more potential for problems, as it will present an uncharged
capacitor load and draw a large inrush current. This could cause a
momentary, but unacceptable interruption or sag to the backplane
power bus if not limited. The problem can also arise if ordinary
power module connectors are used, since the connector pins will
engage and disengage in a random and unpredictable sequence
during insertion and removal.
Given the wide bandwidth of the VIA, the source response
is generally the limiting factor in the overall system response.
Anomalies in the response of the source will appear at the LO side
of the module multiplied by its K factor.
Hot swap or hot plug is the highly desirable feature in many
applications, but it also creates several issues that must be
addressed in the system design. A number of related phenomena
occur with a live insertion and removal event, including bouncing,
arcing between HI side connector pins, larger voltage and current
transients. Hot swap circuitry in the converter modules protects the
module and the rest of the system from the problem associated
with live insertion.
Total load capacitance at the LO side of the VIA shall not exceed
the specified maximum for correct operation of it in startup and
steady state conditions. Owing to the wide bandwidth and small
LO side impedance of the VIA, low frequency bypass capacitance
and significant energy storage may be more densely and efficiently
provided by adding capacitance at the HI side of the VIA. At
frequencies less than 500KHz, the VIA appears as an impedance of
RLO between the source and load.
Within this frequency range, capacitance at the HI side appears as
effective capacitance on the LO side per the relationship defined
in equation (15).
This enable a reduction in the size and number of capacitors used
in a typical system.
CLO
=
CHI
(15)
K2
BCM® in a VIA Package
Page 21 of 40
Rev 1.1
05/2016
To meet the maintenance, reconfiguration, redundancy and system
upgrade, this new BCM module is being designed to address the
function of hot-swapping at the 380VDC distribution bus. This new
module provides a high level of integration for DC-DC converters
in 380VDC distributions, saving the system designer design time
and critical board space. Hot swap circuitry as shown in Figure
29 uses an active MOSFET switching device in the HI side line.
During insertion, the MOSFET is driven into a resistive state to limit
the inrush current, and then when the inserted module’s HI side
capacitor has charged, the MOSFET becomes fully conductive to
avoid the voltage drop losses. Performance verification is further
illustrated through scope plots of circuit’s response to various live
insertion events.
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Hot Swap Test – Scope Pictures
VHI
of VIA
BCM
VHI of ChiP
BCM
IHI of VIA
BCM
VLO of VIA
BCM
ChiP BCM
Charge
Pump
Hot-swap
Controller
Figure 25 — High-Level Diagram for 384 VDC Hot Swap with
ChiP BCM DC-DC converter
Overall, the objective is always remains the same in hot swap
applications; to give system designer the opportunity to build hot
swap capability into redundant power module arrays. This allows
telecoms and other mission critical applications to continue without
interruption even through failure and replacement of one or
possibly more of their power modules.
Figure 27 — Hot swap start-up
Ch1: IHI of BCM#2
Ch2: VLO of BCM#2
Ch3: VHI of BCM#2 shows the fast high side voltage transient at the
high side terminal of BCM#2
Ch4: VHI of ChiP BCM#2 shows the soft start charging the high side
capacitor as shown, time constant depends upon the gate signal.
Hot Swap Test – Test circuit and Procedure
n Two BCMs in parallel with mercury relay#1 open
n Close mercury relay#1 and measure inrush current going
into #2 BCM
+HI
4000 µF
+LO
DC
–HI
Maximum Input
Voltage
Electronic
Load
Max Load
BCM (K)
#1
–LO
Mercury
Relay #1
+HI
+LO
BCM (K)
#2
–HI
–LO
Figure 28 — Same as Figure 30 but at a bigger time scale shows
the appearance of the BCM#2
Figure 26 — Test Circuit
BCM® in a VIA Package
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System Diagram for PMBus™ Interface
5V
EXT_BIAS
BCM in a VIA
Package
SCL
SCL
SDA
SDA
SGND
Host
PMBus™
SGND
ADDR
The BCM in a VIA package provides accurate telemetry monitoring and reporting, threshold and warning limits adjustment, in
addition to corresponding status flags.
The BCM’s internal µC is referenced to low voltage side signal ground.
The BCM provides the host system µC with access to standalone BCM. The standalone BCM is constantly polled for status by the
internal µC. Direct communication to BCM is enabled by a page command. For example, the page (0x00) prior to a telemetry inquiry
points to the internal µC data and pages (0x01) prior to a telemetry inquiry points to the BCM connected data. The BCM constantly
polls it’s data through the PMBus.
The BCM enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The BCM follows the PMBus
command structure and specification.
BCM® in a VIA Package
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PMBus™ Interface
Where:
Refer to “PMBus Power System Management Protocol
SpecificationRevision 1.2, Part I and II” for complete PMBus
specifications details visit http://pmbus.org.
X, is a “real world” value in units (A, V, °C, s)
Y, is a two’s complement integer received from the internal µC
m, b and R are two’s complement integers defined as follows:
Device Address
Command
The PMBus address (ADDR Pin) should be set to one of a
predetermined 16 possible addresses shown in the table below
using a resistor between ADDR pin and SGND pin.
The BCM accepts only a fixed and persistent address and does not
support SMBus address resolution protocol. At initial power‐up, the
BCM internal µC will sample the address pin voltage, and will hold
this address until device power is removed.
Code
m
R
b
TON_DELAY
60h
1
3
0
READ_VIN
88h
1
1
0
READ_IIN
89h
1
3
0
READ_VOUT
8Bh
1
1
0
READ_IOUT
8Ch
1
2
0
READ_TEMPERATURE_1
8Dh
1
0
0
READ_POUT
96h
1
0
0
ID
Slave
Address
HEX
Recommended
Resistor R ADDR (Ω)
1
1010 000b
50h
487
MFR_VIN_MIN
A0h
1
0
0
2
1010 001b
51h
1050
MFR_VIN_MAX
A1h
1
0
0
3
1010 010b
52h
1870
MFR_VOUT_MIN
A4h
1
0
0
4
1010 011b
53h
2800
MFR_VOUT_MAX
A5h
1
0
0
5
1010 100b
54h
3920
MFR_IOUT_MAX
A6h
1
0
0
6
1010 101b
55h
5230
MFR_POUT_MAX
A7h
1
0
0
7
1010 110b
56h
6810
READ_K_FACTOR
D1h
65536
0
0
8
1010 111b
57h
8870
READ_BCM_ROUT
D4h
1
2
0
9
1011 000b
58h
11300
10
1011 001b
59h
14700
11
1011 010b
5Ah
19100
12
1011 011b
5Bh
25500
13
1011 100b
5Ch
35700
14
1011 101b
5Dh
53600
15
1011 110b
5Eh
97600
16
1011 111b
5Fh
316000
[1] Default READ LO side voltage returned when BCM unit is disabled = –300V.
[2]
Default READ Temperature returned when BCM unit is disabled = –273°C.
No special formatting is required when lowering the supervisory
limits and warnings.
Reported DATA Formats
The BCM internal µC employs a direct data format where all
reported internal µC measurements are in Volts, Amperes,
Degrees Celsius, or Seconds. The host uses the following PMBus
specification to interpret received values metric prefixes. Note that
the Coefficients command is not supported:
X=
(
1
m
)
• (Y • 10-R - b)
BCM® in a VIA Package
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Supported Command List
Command
Code
Function
Default Data Content
Data Bytes
PAGE
00h
Access BCM stored information for all connected
devices
00h
1
OPERATION
01h
Turn BCMs on or off
80h
1
ON_OFF_CONFIG
02h
Defines startup when power is applied as well
as immediate on/off control over the BCMs
1Dh
1
CLEAR_FAULTS
03h
Clear all BCM and all internal µC faults
N/A
None
CAPABILITY
19h
Internal µC PMBusTM key capabilities set by factory
20h
1
OT_FAULT_LIMIT
4Fh[1]
BCM over temperature protection
64h
2
OT_WARN_LIMIT
51h[1]
BCM over temperature warning
64h
2
VIN_OV_FAULT_LIMIT
55h[1]
BCM VHI overvoltage warning
64h
2
VIN_OV_WARN_LIMIT
57h[1]
BCM VHI overvoltage protection
64h
2
IIN_OC_FAULT_LIMIT
5Bh[1]
BCM ILO overcurrent protection
64h
2
IIN_OC_WARN_LIMIT
5Dh[1]
BCM ILO overcurrent warning
64h
2
TON_DELAY
60h[1]
Startup delay additional to any BCM fixed delays
00h
2
STATUS_BYTE
78h
Summary of BCM faults
00h
1
STATUS_WORD
79h
Summary of BCM fault conditions
00h
2
STATUS_IOUT
7Bh
BCM overcurrent fault status
00h
1
STATUS_INPUT
7Ch
BCM overvoltage and under voltage fault status
00h
1
STATUS_TEMPERATURE
7Dh
BCM over temperature and under temperature
fault status
00h
1
STATUS_CML
7Eh
Internal µC PMBus Communication fault
00h
1
STATUS_MFR_SPECIFIC
80h
Other BCM status indicator
00h
1
READ_VIN
88h
Reads HI side voltage
FFFFh
2
READ_IIN
89h
Reads HI side current
FFFFh
2
READ_VOUT
8Bh
Reads LO side voltage
FFFFh
2
READ_IOUT
8Ch
Reads LO side current
FFFFh
2
READ_TEMPERATURE_1
8Dh
BCM temperature
FFFFh
2
READ_POUT
96h
Reads LO side power
FFFFh
2
PMBUS_REVISION
98h
Internal µC PMBus compatible revision
22h
1
MFR_ID
99h
Internal µC ID
“VI”
2
MFR_MODEL
9Ah
Internal µC or BCM model
Part Number
18
MFR_REVISION
9Bh
Internal µC or BCM revision
FW and HW revision
18
MFR_LOCATION
9Ch
Internal µC or BCM factory location
“AP”
2
MFR_DATE
9Dh
Internal µC or BCM manufacturing date
MFR_SERIAL
9Eh
Internal µC or BCM serial number
MFR_VIN_MIN
A0h
MFR_VIN_MAX
A1h
MFR_VOUT_MIN
“YYWW”
4
Serial Number
16
BCM Minimum rated VHI
Varies per BCM
2
BCM Maximum rated VHI
Varies per BCM
2
A4h
BCM Minimum rated VLO
Varies per BCM
2
MFR_VOUT_MAX
A5h
BCM Maximum rated VLO
Varies per BCM
2
MFR_IOUT_MAX
A6h
BCM Maximum rated ILO
Varies per BCM
2
MFR_POUT_MAX
A7h
BCM Maximum rated PLO
Varies per BCM
2
D0h[1]
Set BCM EN pin polarity
BCM_EN_POLARITY
02h
1
READ_K_FACTOR
D1h
BCM K factor
Varies per BCM
2
READ_BCM_ROUT
D4h
BCM RLO
Varies per BCM
2
646464646464h
6
00h
2
SET_ALL_THRESHOLDS
DISABLE_FAULT
[1]
D5h[1]
Set BCM supervisory warning and protection thresholds
D7h[1]
Disable BCM overvoltage, overcurrent or
under voltage supervisory faults
The BCM must be in a disabled state during a write message.
BCM® in a VIA Package
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Command Structure Overview
Write Byte protocol:
The Host always initiates PMBus™ communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write
message, the master sends the slave device address followed by a write bit. Once the slave acknowledges, the master proceeds with the
command code and then similarly the data byte.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Command Code
1
8
1
1
A
Data Byte
A
P
x=0
x=0
S
Start Condition
Sr
Repeated start Condition
Rd
Read
Wr
Write
X
Indicated that field is required to have the value of x
A
Acknowledge (bit may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
From Master to Slave
From Slave to Master
…
Continued next line
Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL
Read Byte protocol:
A Read message begins by first sending a Write Command, followed by a REPEATED START Bit and a slave Address. After receiving the
READ bit, the internal µC begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it
terminates the message with a NACK preceding a stop condition signifying the end of a read transfer.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Command Code
1
1
7
A Sr Slave Address
x=0
1
1
Rd
A
x=1
x=0
8
Data Byte
Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL
BCM® in a VIA Package
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A
P
x=1
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Write Word protocol:
When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least significant
bit (LSB) is sent last. Refer to System Management Bus (SMBus) specification version 2.0 for more details.
Note: Extended command and Packet Error Checking Protocols are not supported.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
1
8
A
Command Code
1
Data Byte Low
x=0
8
A
Data Byte High
x=0
1
1
A
P
x=0
Figure 3 — TON_DELAY COMMAND (60h)_WRITE WORD PROTOCOL
Read Word protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
1
Command Code
1
7
A Sr Slave Address
x=0
1
1
Rd
A
8
x=1
x=0
1
Data Byte Low
A
x=0
Figure 4 — MFR_VIN_MIN COMMAND (A0h)_READ WORD PROTOCOL
Write Block protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Data Byte 2
1
A
x=0
...
...
...
8
1
8
Byte Count = N
A
Command Code
x=0
8
Data Byte N
1
A
8
Data Byte 1
x=0
1
1
A
P
1
A
x=0
x=0
Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL
BCM® in a VIA Package
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8
Data Byte High
1
1
A
P
x=1
BCM4414xD1E13A2yzz
Read Block protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
1
8
Data Byte 1
8
1
7
x=0
8
A
1
A Sr Slave Address
Command Code
1
Data Byte 2
A
x=0
x=0
...
...
...
8
Data Byte N
1
1
Rd
A
x=1
x=0
1
1
A
P
8
1
Data Byte = N
A
x=0
x=1
Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL
Write Group Command protocol:
Note that only one command per device is allowed in a group command.
1
7
1
1
S
Slave Address
Wr
A
Command Code
A
First Device
x=0
x=0
First Command
x=0
1
7
Sr Slave Address
Second Device
1
7
Sr Slave Address
Nth Device
8
8
1
1
1
Wr
A
Command Code
A
x=0
x=0
Second Command
x=0
8
8
Data Byte Low
1
1
1
Wr
A
Command Code
A
x=0
x=0
Nth Command
x=0
8
Data Byte Low
1
8
Data Byte Low
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
Rev 1.1
05/2016
...
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE
BCM® in a VIA Package
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Supported Commands Transaction type
Page Command (00h)
A direct communication to the BCM internal µC and a simulated
communication to non-PMBus™ devices is enabled by a page
command. Supported command access privileges with a preselected PAGE are defined in the following table. Deviation from
this table generates a communication error in
STATUS_CML register.
The page command data byte of 00h prior to a command call will
address the internal µC specific data and a page data byte of FFh
would broadcast to all of the connected BCMs. The value of the
Data Byte corresponds to the pin name trailing number with the
exception of 00h and FFh.
Command
Code
PAGE Data Byte
Access Type
00h
01h
PAGE
00h
R/W
R/W
OPERATION
01h
R
R/W
ON_OFF_CONFIG
02h
CLEAR_FAULTS
03h
W
W
CAPABILITY
19h
R
OT_FAULT_LIMIT
4Fh
R/W
OT_WARN_LIMIT
51h
R/W
VIN_OV_FAULT_LIMIT
55h
R/W
VIN_OV_WARN_LIMIT
57h
R/W
IIN_OC_FAULT_LIMIT
5Bh
R/W
IIN_OC_WARN_LIMIT
5Dh
R/W
TON_DELAY
60h
STATUS_BYTE
78h
R/W
STATUS_WORD
79h
R
R
STATUS_IOUT
7Bh
R
R/W
STATUS_INPUT
7Ch
R
R/W
STATUS_TEMPERATURE
7Dh
R
R/W
STATUS_CML
7Eh
R/W
STATUS_MFR_SPECIFIC
80h
R
READ_VIN
88h
READ_IIN
89h
READ_VOUT
8Bh
READ_IOUT
8Ch
R
R
READ_TEMPERATURE_1
8Dh
R
R
READ_POUT
96h
R
R
PMBUS_REVISION
98h
R
MFR_ID
99h
R
MFR_MODEL
9Ah
R
R
MFR_REVISION
9Bh
R
R
MFR_LOCATION
9Ch
R
R
MFR_DATE
9Dh
R
R
MFR_SERIAL
9Eh
R
R
MFR_VIN_MIN
A0h
R
R
MFR_VIN_MAX
A1h
R
R
MFR_VOUT_MIN
A4h
R
R
MFR_VOUT_MAX
A5h
R
R
MFR_IOUT_MAX
A6h
R
R
MFR_POUT_MAX
A7h
R
BCM_EN_POLARITY
D0h
R/W
READ_K_FACTOR
D1h
R
READ_BCM_ROUT
D4h
R
SET_ALL_THRESHOLDS
D5h
R/W
DISABLE_FAULT
D7h
R/W
BCM® in a VIA Package
Page 29 of 40
R
Data Byte
Description
00h
µC
01h
BCM
OPERATION Command (01h)
The Operation command can be used to turn on and off the
connected BCM. Note that the host OPERATION command will not
enable the BCM if the BCM EN pin is disabled in hardware with
respect to the pre‐set pin polarity. Only with the EN pin active, will
the OPERATION command provide ON/OFF control.
If synchronous startup is required in the system, it is recommended
to use the command from host PMBus in order to achieve
simultaneous array startup.
R/W
R
R/W
R
R
Unit is On when asserted (default)
Reserved
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
b
R
R
Rev 1.1
05/2016
This command accepts only two data values: 00h and 80h. If any
other value is sent the command will be rejected and a CML Data
error will result.
R
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ON_OFF_CONFIG Command (02h)
Reserved for Future Use
Unit does not power up until commanded by the
CONTROL pin and operation command
Unit requires that the on/off portion of the
OPERATION command is instructing the unit to run[1]
Unit requires the CONTROL pin to be asserted
to start the unit[2]
Not supported: Polarity of the CONTROL pin[3]
Turn off the output and stop transferring
energy to the output as fast as possible[4]
7
6
5
4
3
2
1
0
0
0
0
1
1
1
0
1
b
[1]
The BCM Enable pin is ALWAYS to be asserted for powerup. The BCM_EN_POLARITY command (D0h) bit[(1) defines the logic level required for the control pin (i.e BCM Enable pin) to be asserted.
[2] With respect to the BCM EN Control Pin if used in system
[3] See MFR_SPECIFIC_00 / BCM_EN_POLARITY to change the Polarity
of the BCM Enable Pin
[4] The BCM powertrain once disabled cannot sink current
CLEAR_FAULTS Command (03h)
This command clears all status bits that have been previously set.
Persistent or active faults are re‐asserted again once cleared. All
faults are latched once asserted in the internal µC. Registered faults
will not be cleared when shutting down the BCM powertrain by
recycling the BCM high side voltage, or toggling the BCM EN pin,
or sending the OPERATION command.
OT_FAULT_LIMIT Command (4Fh),
OT_WARN_ LIMIT Command (51h),
VIN_OV_FAULT_ LIMIT Command (55h),
VIN_OV_WARN_ LIMIT Command (57h),
IIN_OC_FAULT_ LIMIT Command (5Bh),
IIN_OC_WARN_ LIMIT Command (5Dh)
The values of these registers are set in non‐volatile memory and
can only be written when the BCMs are disabled.
The values of the above mentioned fault and warning are set by
default to a 100% of the respective BCM model supervisory limits.
However these limits can be set to a lower value. For example: In
order for a limit percentage to be set to 80% one would send a
write command with a (50h) Data Word.
Any values outside the range of (00h – 64h) sent by a host will be
rejected­, will not override the currently stored value and will set the
Unsupported Data bit in STATUS_CML.
The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one
block over temperature fault and warning limits, VHI overvoltage
fault and warning limits as well as ILO overcurrent fault and warning
limits. A delay prior to a read command of up to 200ms following a
write of new value is required.
The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT
(59h) are set by the factory and cannot be changed by the host.
However, a host can disable the under voltage setting using the
DISABLE_FAULT COMMAND (D7h).
All FAULT_RESPONSE commands are unsupported. The BCM
powertrain supervisory limits and powertrain protection will behave
as described in the BCM datasheet. In general, once a fault is
detected, the BCM powertrain will shut down and attempt to auto‐
restart after a predetermined delay.
CAPABILITY Command (19h)
TON_DELAY Command (60h)
The value of this register word is set in non‐volatile memory and
can only be written when the BCMs are disabled.
Packet Error Checking is not supported
Maximum supported bus speed is 400 KHz
The Device does not have SMBALERT# pin and does
not support the SMBus Alert Response protocol
The maximum possible delay is 100ms. Default value is set to (00h).
Follow this equation below to interpret the reported value.
Reserved
TON_DELAYACTUAL = tREPORTED • 10 -3(s)
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
b
The internal µC returns a default value of 20h. This value indicates
that the PMBus™ frequency supported is up to 400KHz and that
both Packet Error Checking (PEC) and SMBALERT# are
not supported.
BCM® in a VIA Package
Page 30 of 40
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Staggering startup in an array is possible with TON_DELAY
Command. This delay will be in addition to any startup delay
inherent in the BCM module. For example: startup delay from
application of VHI is typically 20ms whereas startup with EN pin is
typically 250µs. When TON_DELAY is greater than zero, the set
delay will be added to both.
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STATUS_BYTE (78h) and STATUS_WORD (79h)
STATUS_WORD
High Byte
Low Byte
STATUS_BYTE
UNIT IS BUSY
Not Supported: UNKNOWN FAULT OR WARNING
UNIT IS OFF
Not Supported: OTHER
Not Supported: FAN FAULT OR WARNING
Not Supported: VOUT_OV_FAULT
POWER_GOOD Negated*
IOUT_OC_FAULT
VIN_UV_FAULT
STATUS_MFR_SPECIFIC
TEMPERATURE FAULT OR WARNING
INPUT FAULT OR WARNING
PMBusTM COMMUNCATION EVENT
IOUT/POUT FAULT OR WARNING
Not Supported: VOUT FAULT OR WARNING
NONE OF THE ABOVE
7
6
5
4
3
2
1
0
7
0
1
1
1
1
0
0
0
1
6
1
5
0
4
1
3
2
1
1
1
0
1
0
b
* equal to POWER_GOOD#
All fault or warning flags, if set, will remain asserted until
cleared by the host or once the internal µC power is removed.
This includes under voltage fault, overvoltage fault, overvoltage
warning, overcurrent warning, over temperature fault, over
temperature warning, under temperature fault, reverse operation,
communication faults and analog controller shutdown fault.
Asserted status bits in all status registers, with the exception of
STATUS_WORD and STATUS_BYTE, can be individually cleared.
This is done by sending a data byte with one in the bit position
corresponding to the intended warning or fault to be cleared. Refer
to the PMBus™ Power System Management Protocol Specification
– Part II – Revision 1.2 for details.
The POWER_GOOD# bit reflects the state of the device and does
not reflect the state of the POWER_GOOD# signal limits. The
POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF
COMMAND (5Fh) are not supported. The POWER_GOOD# bit is
set anytime the BCM is not in the enabled state, to indicate that
the powertrain is inactive and not switching. The POWER_GOOD#
bit is cleared when the BCM completes the enabling state, 5 ms
after the powertrain is activated allowing for soft‐start to elapse.
POWER_GOOD# and OFF bits cannot be cleared as they always
reflect the current state of the device.
If the internal µC is still powered, it will retain the last status it
received from the BCM and this information will be available to
the user via a PMBus Status request. This is in agreement with the
PMBus standard which requires that status bits remain set until
specifically cleared. Note that in this case where the BCM VHI­­­ is lost,
the status will always indicate an under voltage fault, in addition to
any other fault
that occurred.
NONE OF THE ABOVE bit will be asserted if either the STATUS_
MFR_SPECIFIC (80h) or the High Byte of the STATUS WORD
is set.
STATUS_IOUT (7Bh)
IOUT_OC_FAULT
Not Supported: IOUT_OC_LV_FAULT
IOUT_OC_WARNING
Not Supported: IOUT_UC_FAULT
Not Supported: Current Share Fault
Not Supported: In Power Limiting Mode
When Page (00h) is used the POWER_GOOD# bit reflects the ORing of all active BCMs’ POWER_GOOD# bits. When Page
(01h – 04h) is used POWER_GOOD# is clear only when the
BCM is active.
When Page (00h) is used UNIT IS OFF is SET when all BCMs are
not active. When Page (01h – 04h) is used UNIT IS OFF is clear only
when the BCM is active.
The Busy bit can be cleared using CLEAR_ALL Command (03h) or
by writing either data value (40h, 80h) to PAGE (00h) using the
STATUS_BYTE (78h).
Not Supported: POUT_OP_FAULT
Not Supported: POUT_OP_WARNING
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
Unsupported bits are indicated above. A one indicates a fault.
Fault reporting, such as SMBALERT# signal output, and host
notification by temporarily acquiring bus master status is
not supported.
BCM® in a VIA Package
Page 31 of 40
Rev 1.1
05/2016
b
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STATUS_INPUT (7Ch)
The STATUS_CML data byte will be asserted when an unsupported
PMBus™ command or data or other communication fault occured.
VIN_OV_FAULT
STATUS_MFR_SPECIFIC (80h)
VIN_OV_WARNING
Not Supported: VIN_UV_WARNING
Reserved
VIN_UV_FAULT
PAGE Data Byte = (01h - 04h)
Reserved
Not Supported: Unit Off For Insufficient
Input Voltage
Reserved
Reserved
Not Supported: IIN_OC_FAULT
Reserved
Not Supported: IIN_OC_WARNING
BCM UART CML
Not Supported: PIN_OP_WARNING
Analog Controller Shutdown Fault
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
BCM Reverse Operation
b
Unsupported bits are indicated above. A one indicates a fault.
STATUS_TEMPERATURE (7Dh)
Not Supported: UT_WARNING
UT_FAULT
Reserved
Reserved
Reserved
5
4
3
2
1
0
1
0
1
0
0
0
0
4
3
2
1
0
0
0
0
1
1
1
b
The BCM UART is designed to operate with the internal µC UART.
If the BCM UART CML is asserted, it may indicate a hardware or
connection issue between both devices.
Reserved
6
5
0
The BCM has analog protections and internal µC protections. The
analog controller provides an additional layer of protection and
has the fastest response time. The analog controller shutdown
fault, when asserted, indicates that at least one of the powertrain
protection faults is triggered. This fault will also be asserted if
a disabled fault event occurs after asserting any bit using the
DISABLE_FAULTS COMMAND.
OT_WARNING
1
6
0
The reverse operation bit, if asserted, indicates that the BCM is
processing current in reverse. Reverse current reported value is
not supported.
OT_FAULT
7
7
b
Reserved
Reserved
Reserved
Unsupported bits are indicated above. A one indicates a fault.
Reserved
STATUS_CML (7Eh)
Reserved
Reserved
Invalid Or Unsupported Command Received
Reserved
Invalid Or Unsupported Data Received
Reserved
Not Supported: Packet Error Check Failed
Not Supported: Memory Fault Detected
Not Supported: Processor Fault Detected
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
b
Reserved
Other Communication Faults
Not Supported: Other Memory Or Logic
Fault
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
b
Unsupported bits are indicated above. A one indicates a fault.
BCM® in a VIA Package
Page 32 of 40
Rev 1.1
05/2016
When PAGE COMMAND (00h) data byte is equal to (00h), the
BCM Reverse operation, Analog Controller Shutdown Fault, and
BCM UART CML bit will return OR-ing result of active BCMs. The
BCM UART CML will also be asserted if any of the active BCMs
stops responding. The BCM must communicate at least once to
the internal µC in order to trigger this FAULT. The BCM UART CML
can be cleared from the culprit BCM once the internal µC is able
to communicate with it once again or can be cleared using PAGE
(00h) CLEAR_FAULTS (03h) Command.
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READ_VIN Command (88h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side power in the following format:
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s HI side voltage in the following format:
VHI_ACTUAL = VHI_REPORTED • 10 (V)
PLO_ACTUAL = PLO_REPORTED (W)
-1
If PAGE data byte is equal to (00h) command will return the sum of
active BCM’s LO side power.
READ_IIN Command (89h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s HI side current in the following format:
IHI_ACTUAL = IHI_REPORTED • 10 -3(A)
If PAGE data byte is equal (00h) command will return the sum of
active BCM’s HI side current.
READ_VOUT Command (8Bh)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side voltage in the following format:
VLO_ACTUAL = VLO_REPORTED • 10 -1(V)
MFR_VIN_MIN Command (A0h),
MFR_VIN_MAX Command (A1h),
MFR_VOUT_MIN Command (A4h),
MFR_VOUT_MAX Command (A5h),
MFR_IOUT_MAX Command (A6h),
MFR_POUT_MAX Command (A7h)
These values are set by the factory and indicate the device HI side/
LO side voltage and LO side current range and LO side power
capacity.
The internal µC will report rated BCM HI side voltage minimum
and maximum in Volts, LO side voltage minimum and maximum
in Volts, LO side current maximum in Amperes and LO side power
maximum in Watts.
If PAGE data byte is equal to (00h) then:
READ_IOUT Command (8Ch)
n MFR_VIN_MIN COMMAND (A0h) will return the highest If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side current in the following format:
MFR_VIN_MIN of all active BCMs
n MFR_VIN_MAX COMMAND (A1h) will return the lowest
MFR_VIN_MAX of all active BCMs
ILO_ACTUAL = ILO_REPORTED • 10 (A)
-2
n MFR_VOUT_MIN COMMAND (A4h) will return the highest MFR_VOUT_MIN of all active BCMs
If PAGE data byte is equal (00h) command will return the sum of
active BCM’s LO side current.
n MFR_VOUT_MAX COMMAND (A5h) will return the lowest MFR_VOUT_MAX of all active BCMs
n MFR_IOUT_MAX COMMAND (A6h) will return the SUM of READ_TEMPERATURE_1 Command (8Dh)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s temperature in the following format:
MFR_IOUT_MAX of all active BCMs
n MFR_POUT_MAX COMMAND (A7h) will return the SUM of MFR_POUT_MAX of all active BCMs
TACTUAL = ±TREPORTED (°C)
If PAGE data byte is equal (00h) command will return the maximum
temperature of active BCM’s.
READ_POUT Command (96h)
BCM® in a VIA Package
Page 33 of 40
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BCM_EN_POLARITY Command (D0h)
SET_ALL_THRESHOLDS Command (D5h)
Reserved
SET_ALL_THRESHOLDS_BLOCK (6 Bytes)
Reserved
IOUT_OC_WARN_ LIMIT
Reserved
IOUT_OC_FAULT_ LIMIT
Reserved
VIN_OV_WARN_ LIMIT
Reserved
VIN_OV_FAULT_ LIMIT
Reserved
OT_WARN_LIMIT
BCM EN Pin Polarity
OT_FAULT_LIMIT
Reserved
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
5
4
3
2
1
0
64 64 64 64 64 64
b
h
The value of this register is set in non‐volatile memory and can only
be written when the BCMs are disabled.
Values of this register block is set in non‐volatile memory and can
only be written when the BCMs are disabled.
When PAGE COMMAND (00h) data byte is equal to (01h – 04h),
this command defines the polarity of the EN pin. If BCM_EN_
POLARITY is set, the BCM will startup once VHI is greater than the
under voltage threshold.
This command provides a convenient way to configure all the
limits, or any combination of limits described previously using one
command.
The BCM EN PIN is internally pulled-up to 3.3V. If the BCM_EN_
POLARITY is cleared, an external pull-down is then required.
Applying VHI greater than the under voltage threshold will not
suffice to start the BCM.
READ_K_FACTOR Command (D1h)
VHI Overvoltage, Overcurrent and Overtemperature values are all
set to 100% of the BCM datasheet supervisory limits by default
and can only be set to a lower percentage.
To leave a particular threshold unchanged, set the corresponding
threshold data byte to a value greater than (64h).
DISABLE_FAULT Command (D7h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCMs K factor in the following format:
DISABLE_FAULT
MSB
LSB
K_FACTORACTUAL = K_FACTORREPORTED • 2 -16(V/V)
Reserved
Reserved
Reserved
The K factor is defined in a BCM to represent the ratio of the
transformer winding and hence is equal to VLO / VHI.
READ_BCM_ROUT Command (D4h)
If PAGE data byte is equal to (01h - 04h) command will return
a reported individual BCM’s LO side resistance in the following
format:
Reserved
IOUT_OC_FAULT
Reserved
Reserved
Reserved
VIN_OV_FAULT
Reserved
Reserved
Reserved
VIN_UV_FAULT
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
7
0
6
0
5
1
4
0
3
1
2
0
1
0
0
0
b
BCM_RLO_ACTUAL = BCM_RLO_REPORTED • 10 -5(Ω)
Unsupported bits are indicated above. A one indicates that the
supervisory fault associated with the asserted bit is disabled.
The value of these registers is set in non‐volatile memory and can
only be written when the BCMs are disabled.
This command allows the host to disable the supervisory faults
and respective statuses. It does not disable the powertrain analog
protections or warnings with respect to the set limits in the SET_
ALL_THRESHOLDS Command.
The HI side undervoltage can only be disabled to a pre‐set low limit
as shown in the functional reporting range in the BCM data sheet.
BCM® in a VIA Package
Page 34 of 40
Rev 1.1
05/2016
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The internal µC Implementation vs.
PMBus™ Specification Rev 1.2
3. The internal µC unsupported PMBus command code response as
described in the Fault Management and Reporting:
The internal µC is an I2C compliant, SMBus™ compatible device
and PMBus command compliant device. This section denotes some
deviation, perceived as differences from the PMBus Part I and Part II
specification Rev 1.2.
n Deviations from the PMBus specification:
a. PMBus section 10.2.5.3, exceptions
• The busy bit of the STATUS_BYTE as implemented can
be cleared (80h). In order to maintain compatibility with
the specification (40h) can also be used.
1. The internal µC meets all Part I and II PMBus specification
requirements with the following differences to the
transport requirement.
n Manufacturer Implementation of the PMBus Spec
Unmet DC parameter Implementation vs SMBus™ spec
Symbol
[b]
D44TL1A0
a. PMBus section 10.5, setting the response to a detected fault condition
Units
Min
Max
Min
Max
VIL[a]
Input Low Voltage
-
0.99
-
0.8
VIH[a]
Input High Voltage
2.31
-
2.1
VVDD_IN
V
10
22
-
±5
µA
ILEAK_PIN[b]
[a]
Parameter
SMBus™
Rev 2.0
Input Leakage per Pin
• All powertrain responses are pre-set and cannot be
changed. Refer to the BCM datasheet for details.
b. PMBus section 10.6, reporting faults and warnings
to the Host
V
•
VVDD_IN = 3.3V
VBUS = 5V
SMBALERT# signal and Direct PMBus Device to Host
Communication are not supported. However, the Digital
Supervisor will set the corresponding fault status bits and
will wait for the host to poll.
c. PMBus section 10.7, clearing a shutdown due to a fault
2. The internal µC accepts 38 PMBus command codes.
Implemented commands execute functions as described in the
PMBus specification.
•
n Deviations from the PMBus specification:
a. Section 15, fault related commands
There is no RESET pin or EN pin in the internal µC.
Cycling power to the internal µC will not clear a
BCM Shutdown. The BCM will clear itself once the fault
condition is removed. Refer to the BCM datasheet
for details.
d. PMBus Section 10.8.1, corrupted data transmission faults:
• The limits and Warnings unit implemented is percentage
(%) a range from decimal (0-100) of the factory set limits.
• Packet error checking is not supported.
Data Transmission Faults Implementation
This section describes data transmission faults as implemented in the internal µC.
Response to Host
Section
Description
NAK
FFh
STATUS_BYTE
STATUS_CML
CML
Other Fault
10.8.1
Corrupted data
10.8.2
Sending too few bits
X
X
10.8.3
Reading too few bits
X
X
10.8.4
Host sends or reads too
few bytes
X
X
10.8.5
Host sends too many
bytes
10.8.6
Reading too many bytes
10.8.7
Device busy
BCM® in a VIA Package
Page 35 of 40
Unsupported
Data
Notes
No response; PEC not supported
X
X
X
X
X
X
X
Device will ACK own address
BUSY bit in STATUS_BYTE even if
STATUS_WORD is set
X
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Data Content Faults Implementation
This section describes data content fault as implemented in the internal µC.
Response
Section
Description
to Host
STATUS_BYTE
STATUS_CML
NAK
CML
Other
Fault
X
Unsupported
Command
Unsupported
Data
10.9.1
Improperly Set Read Bit In
The Address Byte
X
X
10.9.2
Unsupported Command
Code
X
X
10.9.3
Invalid or Unsupported
Data
X
X
10.9.4
Data Out of Range
X
X
10.9.5
Reserved Bits
BCM® in a VIA Package
Page 36 of 40
Notes
X
No response; not a fault
Rev 1.1
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BCM® in a VIA Package
Page 37 of 40
Rev 1.1
05/2016
.11
2.90
DIM 'B'
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NA
1.150 [29.200]
1.277 [32.430]
1.277 [32.430]
1.61 [40.93]
1.02 [25.96]
1.61 [40.93]
1.61 [40.93]
1.02 [25.96]
1.02 [25.96]
1.61 [40.93]
1.61 [40.93]
1.61 [40.93]
1.61 [40.93]
2814 (1 STAGE) 2223
2814 (0 STAGE) 3623
3414 (1 STAGE) 3623
3714 (1 STAGE) 4623
3814 (0 STAGE) 2361
3814 (0 STAGE) 2361 NBM
4414 (1 STAGE) 2361
4414 (1 STAGE) 6123
5614 (1 STAGE) 2392
5614 (1 STAGE) 9223
2.970 [75.445]
2.490 [63.250]
1.757 [44.625]
1.277 [32.430]
.789 [20.033]
.789 [20.033]
NA
DIM 'B'
DIM 'A'
1.02 [25.96]
PRODUCT
5.57 [141.37]
5.57 [141.37]
4.35 [110.55]
4.35 [110.55]
3.76 [95.59]
3.76 [95.59]
3.75 [95.12]
3.38 [85.93]
2.80 [70.99]
2.84 [72.05]
2.25 [57.11]
DIM 'C'
86(7<&2/8*25
(48,9)25,1387&211(&7,21
$//352'8&76
DIM 'A'
2214 (0 STAGE) 2223
1.171
29.750
,1387
,16(57
72%(
5(029('
35,25
7286(
.37±.015
9.40±.381
DIM 'C'
127(6
.15
3.86
THRU
(4) PL.
RED
BLACK
BLUE
8 WHITE
YELLOW
1.40
35.54
)RUFKDVVLVPRXQWPRGHOV9LFRUSDUWQXPEHU
ZLOOEHQHHGHGIRUDSSOLFDWLRQVUHTXLULQJWKHXVHRIVLJQDOSLQV
86(7<&2/8*25
(48,9)25287387&211(&7,21
352'8&76$1'
86(7<&2/8*25
(48,9)25287387&211(&7,21
352'8&76$1'
287387
,16(57
72%(
5(029('
35,25
7286(
23.98
609.14
BCM4414xD1E13A2yzz
BCM in VIA Package Chassis (Lug) Mount Package Mechanical Drawing
BCM® in a VIA Package
Page 38 of 40
Rev 1.1
05/2016
vicorpower.com
800 927.9474
1.171±.003
29.750±.076
.947±.003
24.058±.076
.112±.003
2.846±.076
.120±.003
3.048±.076
PLATED THRU
.030 [.762]
ANNULAR RING
(6) PL
.11
2.90
.947±.010
24.058±.254
.112±.010
2.846±.254
1.171±.010
29.750±.254
.080
2.032
(6) PL.
.37±.015
9.40±.381
2
1
1
2
DIM 'F'
±.003 [.076]
DIM 'A'
DIM 'F'
±.010 [.254]
10
11
DIM 'G'
±.003 [.076]
DIM 'D'
±.003 [.076]
DIM 'B'
±.003 [.076]
BOTTOM VEW
DIM 'B'
±.010 [.254]
DIM 'D'
±.010 [.254]
12
SEE DETAIL A
13
13
12
(COMPONENT SIDE)
RECOMMENDED HOLE PATTERN
11
10
.182 [4.613]
LONG
DIM 'G'
±.010 [.254]
.103 [2.607]
SHORT
DIM 'L'
(COMPONENT SIDE)
TOP VIEW
DIM 'E'
DIM 'C'
3
4
4
3
.067
1.700
.067±.003
1.700±.076
.452±.003
11.475±.076
.190±.003
4.826±.076
PLATED THRU
.030 [.762]
ANNULAR RING
(2) PL
.452±.010
11.475±.254
.150
3.810
(2) PL.
.025
.635
(5) PL.
.156±.003
3.970±.076
.046
1.168
(3) PL.
.023
.584
TYP
.023
.584
TYP
.040±.003
1.016±.076
PLATED THRU
.008 [.203]
ANNULAR RING
(5) PL
1.40
35.54
5614 (1 STAGE) 2392
5
6
7
8
9
1.61 [40.93]
4414 (1 STAGE) 2361
.859±.003
21.810±.076
.201±.003
5.100±.076
.134±.003
3.400±.076
.268±.003
6.800±.076
.156±.010
3.970±.254
.859±.010
21.810±.254
.268
6.800
.201
5.100
.134
3.400
SEATING
PLANE
DIM 'L'
±.010 [.254]
1.02 [25.96]
1.61 [40.93]
3814 (0 STAGE) 2361 NBM
DIM 'C'
5.57 [141.37]
4.35 [110.55]
3.76 [95.59]
3.76 [95.59]
DIM 'D'
5.171 [131.337]
3.957 [100.517]
3.368 [85.554]
3.368 [85.554]
DIM 'E'
5.65 [143.58]
4.44 [112.76]
3.85 [97.780]
3.85 [97.80]
9
DETAIL A
SCALE 8 : 1
5
6
7
8
DIM 'F'
1.439 [36.553]
1.439 [36.553]
.850 [21.590]
.850 [21.590]
2- SEE PRODUCT DATA SHEET FOR PIN DESIGNATIONS.
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
NOTES:
2.490 [63.250]
1.277 [32.430]
1.277 [32.430]
DIM 'B'
1.277 [32.430]
DIM 'A'
1.02 [25.96]
PRODUCT
3814 (0 STAGE) 2361
DIM 'G'
5.434 [138.026]
4.221 [107.206]
3.632 [92.243]
3.632 [92.243]
BCM4414xD1E13A2yzz
BCM in VIA Package PCB (Board) Mount Package Mechanical Drawing and Recommended Hole Pattern
BCM4414xD1E13A2yzz
Revision History
Revision
Date
1.0
03/3/16
Initial release
n/a
1.1
05/2/16
New Power Pin Nomenclature
All
BCM® in a VIA Package
Page 39 of 40
Description
Rev 1.1
05/2016
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Page Number(s)
BCM4414xD1E13A2yzz
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls
are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of
all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW)
WITH RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY,
FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER
MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable
for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products
and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Pending
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
BCM® in a VIA Package
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vicorpower.com
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