Altera EVB-EP5358HUI 600ma powersoc synchronous buck regulator with integrated inductor Datasheet

Enpirion® Power Datasheet
EP5358xUI 600mA PowerSoC
Synchronous Buck Regulator
with Integrated Inductor
Description
Features
The EP5358xUI (x = L or H) is rated for up to
600mA of continuous output current. The
EP5358xUI
integrates
MOSFET
switches,
control, compensation, and the magnetics in an
advanced 2.5mm
x 2.25mm micro-QFN
Package.
•
Integrated Inductor Technology
•
2.5mm x 2.25mm x 1.1mm uQFN package
•
Total Solution Footprint 14mm 2
•
Low VOUT ripple for RF compatibility
•
High efficiency, up to 93%
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 14mm 2.
•
Up to 600mA continuous output current
•
Less than 1µA standby current
•
5 MHz switching frequency
•
3 pin VID for glitch free voltage scaling
•
VOUT Range 0.6V to VIN – 0.25V
•
Short circuit and over current protection
•
•
UVLO and thermal protection
IC level reliability in a PowerSOC solution
The EP5358xUI uses a 3-pin VID to easily select
the output voltage setting.
Output voltage
settings are available in 2 optimized ranges
providing coverage for typical VOUT settings.
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP5358LUI further has
the option to use an external voltage divider.
The EP5358xUI is a perfect solution for noise
sensitive and space constrained applications that
require high efficiency.
•
Wireless and RF applications
•
Wireless broad band data cards
•
Small form factor optical modules
•
Low noise FPGA IO and Transceivers
•
Advanced Low Power Processors, DSP, IO,
Memory, Video, Multimedia Engines
VIN
10uF
2.2uF
2.25mm
Application
EP5358xUI
AVIN
VSENSE
PVIN
VOUT
VOUT
ENABLE
2.2uF
EP5358HUI
VS0
VS1
VS2
PGND
10uF
AGND
4.75mm
Figure 1: Total Solution Footprint.
Figure 2: Typical Application Schematic
www.altera.com/enpirion
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
EP5358LUI
LOW VID Range
16-pin QFN T&R
EP5358HUI
HIGH VID Range
16-pin QFN T&R
EVB-EP5358LUI
EP5358LUI Evaluation Board
EVB-EP5358HUI
EP5358HUI Evaluation Board
NC(SW)
1
PGND
2
PGND
3
VFB
4
VSENSE
5
AGND
6
NC(SW)
Package
NC(SW)
Comment
16
15
EP5358LUI
Part Number
Pin Assignments (Top View)
14
PVIN
13
AVIN
12 ENABLE
11
10 VS1
9
VOUT
7
VS0
VS2
8
VOUT
Ordering Information
NC(SW)
16
15
2
PGND
3
NC
4
VSENSE
5
AGND
6
14
PVIN
13
AVIN
12 ENABLE
11
VS0
10 VS1
9
7
8
VOUT
PGND
EP5358HUI
1
VOUT
NC(SW)
NC(SW)
Figure 3: EP5358LUI Pin Out Diagram (Top View)
VS2
Figure 4: EP5358HUI Pin Out Diagram (Top View)
Pin Description
PIN
NAME
1, 15,
16
NC(SW)
2,3
PGND
4
VFB/NC
5
VSENSE
6
AGND
7, 8
VOUT
9, 10,
11
VS2, VS1,
VS0
12
13
14
ENABLE
AVIN
PVIN
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal,
ground, or voltage. However, they must be soldered to the PCB. Failure to follow this
guideline may result in part malfunction or damage to the device.
Power ground. Connect these pins together and to the ground electrode of the Input and
output filter capacitors.
EP5358LUI: Feed back pin for external divider option.
EP5358HUI: No Connect
Sense pin for preset output voltages. Refer to application section for proper configuration.
Analog ground. This is the quiet ground for the internal control circuitry, and the ground
return for external feedback voltage divider
Regulated Output Voltage. Refer to application section for proper layout and decoupling.
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP5358LUI: Selects one of seven preset output voltages or an external resistor divider.
EP5358HUI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
Output Enable. Enable = logic high; Disable = logic low
Input power supply for the controller circuitry.
Input Voltage for the MOSFET switches.
www.altera.com/enpirion Page 2
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
-0.3
6.0
V
Voltages on: ENABLE, VSENSE, VSO – VS2
-0.3
VIN+ 0.3
V
Voltages on: VFB (EP5358LUI)
-0.3
2.7
V
150
°C
150
°C
260
°C
2000
V
Input Supply Voltage
Maximum Operating Junction Temperature
TJ-ABS
Storage Temperature Range
TSTG
-65
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
VIN
2.4
5.5
V
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
SYMBOL
TYP
UNITS
θJA
85
°C/W
TJ-TP
+155
°C
25
°C
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards
www.altera.com/enpirion Page 3
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V.
CIN = 4.7µF MLCC, COUT = 10µF
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Operating Input Voltage
Range
VIN
Under Voltage Lock-out –
VIN Rising
VUVLO_R
2.0
V
Under Voltage Lock-out –
VIN Falling
VUVLO_F
1.9
V
Drop Out Resistance
RDO
Input to Output Resistance in 100%
duty cycle operation.
Output Voltage Range
VOUT
EP5358LUI (VDO = ILOAD X RDO)
EP5358HUI
Dynamic Voltage Slew
Rate (VID Change)
VSLEW
EP5358LUI
EP5358HUI
VID Preset VOUT Initial
Accuracy
∆VOUT
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
Line Regulation
∆VOUT_LINE
2.4V ≤ VIN ≤ 5.5V
0.03
%/V
Load Regulation
∆VOUT_LOAD
0A ≤ ILOAD ≤ 600mA
0.48
%/A
Temperature Variation
∆VOUT_TEMPL
-40°C ≤ TA ≤ +85°C
24
ppm/°C
Output Current
IOUT
Shut-down Current
ISD
Enable = Low
OCP Threshold
ILIM
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
Feedback Pin Voltage
Initial Accuracy
VFB
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
Feedback Pin Input
Current
IFB
Note 1
VS0-VS2, Pin Logic Low
VVSLO
0.0
0.3
V
VS0-VS2, Pin Logic High
VVSHI
1.4
VIN
V
VS0-VS2, Pin Input
Current
IVSX
Enable Pin Logic Low
VENLO
Enable Pin Logic High
VENHI
Enable Pin Current
IENABLE
Operating Frequency
FOSC
2.4
350
0.6
1.8
MAX
UNITS
5.5
V
500
V IN-V DO
3.3
4
8
-2
mΩ
V
V/mS
+2
600
%
mA
0.75
µA
1.25
1.4
A
.588
0.6
0.612
<100
Note 1
nA
<100
nA
0.3
1.4
Note 1
V
V
V
<100
nA
5
MHz
Soft Start Operation
Soft Start Slew Rate
∆VSS
EP5358LUI (VID MODE)
EP5358HUI (VID MODE)
2.6
5.2
4
8
5.4
10.8
V/mS
VOUT Rise Time
TRISE
EP5358LUI VFB MODE
146
225
304
uSec
Note 1: Parameter guaranteed by design
www.altera.com/enpirion Page 4
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
95
90
85
80
75
70
65
60
55
50
45
Efficiency (%)
Efficiency (%)
Typical Performance Characteristics
0
200
400
Load Current (mA)
600
Efficiency (%)
Efficiency vs. Load Current: VIN = 5.0V, VOUT (from
top to bottom) = 3.3, 2.5, 1.8, 1.2V
95
90
85
80
75
70
65
60
55
50
45
0
200
400
Load Current (mA)
600
Efficiency vs. Load Current: VIN = 3.7V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
95
90
85
80
75
70
65
60
55
50
45
0
200
400
Load Current (mA)
600
Efficiency vs. Load Current: VIN = 3.3V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 500mA (VID MODE)
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA (VID MODE)
www.altera.com/enpirion Page 5
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 500mA
Output Ripple: VIN = 5.0V, VOUT = 1.2V,
Load = 500mA
Output Ripple: VIN = 5.0V, VOUT = 3.3V
Load = 500mA
Output Ripple: VIN = 3.3V, VOUT = 1.8V
Load = 500mA
Output Ripple: VIN = 3.3V, VOUT = 1.2V,
Load = 500mA
www.altera.com/enpirion Page 6
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Load Transient: VIN = 3.3V, VOUT = 1.8V
Load stepped from 10mA to 500mA
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load stepped from 10mA to 500mA
www.altera.com/enpirion Page 7
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Functional Block Diagram
PVIN
EP5358UI
UVLO
Thermal Limit
Current Limit
ENABLE
NC(SW)
Soft Start
P-Drive
(-)
Logic
VOUT
PWM
Comp
(+)
N-Drive
GND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
Error
Amp
VFB
(+)
DAC
VREF
Voltage
Select
Package Boundry
AVIN
AGND
VS0 VS1 VS2
Figure 5: Functional Block Diagram
www.altera.com/enpirion Page 8
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Detailed Description
Functional Overview
Integrated Inductor: Low-Noise Low-EMI
The EP5358xUI requires only 2 small MLCC
capacitors for a complete DC-DC converter
solution.
The device integrates MOSFET
switches,
PWM
controller,
Gate-drive,
compensation, and inductor into a tiny 2.5mm x
2.25mm x 1.1mm micro-QFN package.
Advanced package design, along with the high
level of integration, provides very low output
ripple and noise. The EP5358xUI uses voltage
mode control for high noise immunity and load
matching to advanced ≤90nm loads. A 3-pin
VID allows the user to choose from one of 8
output voltage settings.
The EP5358xUI
comes with two VID output voltage ranges.
The EP5358HUI provides VOUT settings from
1.8V to 3.3V, the EP5358LUI provides VID
settings from 0.8V to 1.5V, and also has an
external resistor divider option to program
output setting over the 0.6V to VIN-0.25V
range. The EP5358xUI provides the industry’s
highest power density of any 600mA DCDC
converter solution.
The EP5358xUI utilizes a proprietary low loss
integrated inductor.
The integration of the
inductor greatly simplifies the power supply
design process. The inherent shielding and
compact construction of the integrated inductor
reduces the conducted and radiated noise that
can couple into the traces of the printed circuit
board.
Further, the package layout is
optimized to reduce the electrical path length
for the high di/dT input AC ripple currents that
are a major source of radiated emissions from
DC-DC converters. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
The key enabler of this revolutionary
integration is Altera’s proprietary power
MOSFET technology. The advanced MOSFET
switches are implemented in deep-submicron
CMOS to supply very low switching loss at high
switching frequencies and to allow a high level
of integration. The semiconductor process
allows seem-less integration of all switching,
control, and compensation circuitry.
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
Protection features include under-voltage lockout (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Control Matched to sub 90nm Loads
The EP5358xUI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load currents so that low ripple and high
accuracy are maintained over the entire load
range.
The very high switching frequency
allows for a very wide control loop bandwidth
and hence excellent transient performance.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP5358HUI has a soft-start slew rate that
is twice that of the EP5358LUI.
When the EP5358LUI is configured in external
resistor divider mode, the device has a fixed
VOUT ramp time. Therefore, the ramp rate will
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
www.altera.com/enpirion Page 9
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. The maximum total capacitance on
the output, including the output filter capacitor
and bulk and decoupling capacitance, at the
load, is given as:
EP5358LUI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 230uF
EP5358HUI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 115uF
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
EP5358LUI in external divider mode:
-4
COUT_TOTAL_MAX = 2.086x10 /VOUT Farads
The above numbers and formula assume a no
load condition.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense PMOSFET which is compared to a reference
current. When this level is exceeded the PFET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
soft start is initiated.
If the over current
condition still persists, this cycle will repeat.
The ENABLE pin provides a means to shut
down the converter or enable normal
operation.
A logic low will disable the
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
NOTE:
floating.
The ENABLE pin must not be left
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
www.altera.com/enpirion Page 10
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Application Information
VOUT
PVIN
VIN
VOUT
VSENSE
AVIN
ENABLE
10µF
4.7µF
NOTE: The VID pins must not be left floating.
VS0
VS1
VS2
PGND AGND
EP5358L Low VID Range Programming
Figure 6: Application Circuit, EP5358HUI,.
VOUT
PVIN
VIN
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
VOUT
VSENSE
AVIN
ENABLE
4.7µF
10µF
VFB
VS0
The EP5358LUI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitchfree voltage scaling.
VS1
VS2
Table 1: EP5358LUI VID Voltage Select Settings
PGND AGND
VS2
0
0
0
0
1
1
1
1
Figure 7: Application Circuit, EP5358LUI, showing
the VFB function.
Output Voltage Programming
The EP5358xUI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to
AVIN or to AGND to avoid noise coupling into
the device.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
To specify this VID range, order part number
EP5358LUI.
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V.
This
version does not have an external divider
option. To specify this VID range, order part
number EP5358HUI.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
VS1
0
0
1
1
0
0
1
1
VS0
0
1
0
1
0
1
0
1
VOUT
1.50
1.45
1.20
1.15
1.10
1.05
0.8
EXT
Table 1 shows the VS2-VS0 pin logic states for
the EP5358LUI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
EP5358LUI External Voltage Divider
The external divider option is chosen by
connecting VID pins VS2-VS0 to VIN or a logic
“1” or “high”. The EP5358LUI uses a separate
feedback pin, VFB, when using the external
divider. VSENSE must be connected to VOUT as
indicated in figure 8.
www.altera.com/enpirion Page 11
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
4.7uF
PVIN
VSENSE
AVIN
ENABLE
VSO
VS1
VS2
EP5358LUI
VIN
VOUT
VOUT
Ra
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
10µF
Table 2: EP5358HUI VID Voltage Select Settings
VFB
Rb
VS2
0
0
0
0
1
1
1
1
PGND AGND
Figure 8: EP5358LUI using external divider
The output voltage is selected by the following
formula:
VOUT = 0.6V (1 +
Ra
Rb
)
b
=
VS0
0
1
0
1
0
1
0
1
VOUT
3.3
3.0
2.9
2.6
2.5
2.2
2.1
1.8
Custom VID Setting Adjustment
Ra must be chosen as 237KΩ to maintain loop
gain. Then Rb is given as:
R
VS1
0
0
1
1
0
0
1
1
Rs
AVIN
3
VOUT
PVIN
142.2 x10
Ω
VOUT − 0.6
EP5358xUI
4.7uF
VSO
VS1
VS2
VOUT can be programmed over the range of
0.6V to (VIN – 0.25V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
EP5358HUI High VID Range Programming
The EP5358HUI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP5358HUI does not have an
external divider option.
As with the
EP5358LUI, the VID pin settings can be
changed while the device is enabled.
Table 2 shows the VS0-VS2 pin logic states for
the EP5358HUI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
10uF
VSENSE
5.0pF
AGND
ENABLE
PGND
Figure 9: EP5358xUI with RC inserted in VSENSE
path to modify VID output voltages.
It is possible to adjust VOUT for a given VID
setting by inserting a parallel RC combination
in the VSENSE path as shown in figure 9. The
capacitor value is 5.0pF to ensure stability.
Note that the value of VOUT can only be
increased from its nominal setting
(VOUTNEW>VOUTOLD):
For EP5358LUI:
VOUTNEW 
− 1 kOhms
RsL = 711* 
 VOUTOLD 
For EP5358HUI:
VOUTNEW 
− 1 kOhms
RsH = 356 * 
 VOUTOLD 
VOUTNEW is the desired “new” VOUT.
www.altera.com/enpirion Page 12
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
VOUTOLD is the VID table output voltage.
Input Filter Capacitor
For ILOAD ≤ 500mA, CIN = 2.2uF
For ILOAD > 500mA CIN = 4.7uF.
For a given Rs Value, the VOUTNEW for VID
settings is determined by the following
equations:
0402 capacitor case size is acceptable.
EP5358LUI:
The input capacitor must use a X5R or X7R or
equivalent dielectric formulation.
Y5V or
equivalent
dielectric
formulations
lose
capacitance with frequency, bias, and with
temperature, and are not suitable for switchmode DC-DC converter input filter applications.
 Rs  
VOUTNEW = VOUTOLD  L  + 1Volts
 711  
EP5358HUI:
 Rs  
VOUTNEW = VOUTOLD  H  + 1Volts
 356  
Output Filter Capacitor
For VIN ≤ 4.3V, COUT_MIN = 10uF 0603 MLCC.
NOTE: The amount of adjustment is limited to
approximately 15% of the nominal VID setting.
NOTE: Adjusting VOUT using this method will
increase the tolerance of the output voltage.
The larger the adjustment, the greater the
increase in tolerance.
Power-Up/Down Sequencing
For VIN > 4.3V, COUT_MIN = 10uF 0805 MLCC.
Ripple performance can be improved by using
2x10µF 0603 MLCC capacitors (for any
allowed VIN).
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP5358xUI.
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements .
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance.
Pre-Bias Start-up
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
equivalent
dielectric
formulations
lose
capacitance with frequency, bias, and
temperature and are not suitable for switchmode
DC-DC
converter
output
filter
applications.
The EP5358xUI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5358xUI is not pre-biased when the
EP5358xUI is first enabled.
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
www.altera.com/enpirion Page 13
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Layout Recommendation
Figure 10 shows critical components and layer
1 traces of a recommended minimum footprint
EP5358LQI/EP5358HQI layout with ENABLE
tied to VIN. Alternate ENABLE configurations,
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files
on
the
Altera
website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 10
while reading the layout recommendations in
this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EP5358QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP5358QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 10
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Figure 10:Top PCB Layer Critical Components
and Copper for Minimum Footprint
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 10. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT , then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
connect these vias to the ground plane.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 10 this connection is
made at the input capacitor close to the VIN
connection.
www.altera.com/enpirion Page 14
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Recommended PCB Footprint
Figure 11: EP5358xUI Package PCB Footprint
www.altera.com/enpirion Page 15
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Package and Mechanical
Figure 12: EN5358xUI Package Dimensions
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
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trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion Page 16
03541
October 11, 2013
Rev F