LC88FC3H0A 16-bit Microcontroller 512K-byte Flash ROM / 47.5K-byte RAM / 100-pin LC88FC3H0A is a 16-bit Microcontroller with 512K-byte Flash ROM/47.5Kbyte RAM in 100-pin package. Main features are infrared remote controller receiver circuit (supports PPM and Manchester encoding), 16 channels of 12bit resolution ADC, internal reset circuit, CRC circuit and etc. that are software friendly circuits and these peripheral circuit can contribute to less external components. Also, plenty of serial interface circuits (synchronous serial × 3, I2C × 3, UART × 3) can communicate with other LSIs and are suitable for home appliances and white goods which need complicated control. For software development, there is our original software development environment and with On-Chip Debugging function, it is easy to debug with user’s actual application. www.onsemi.com Features 16-channel 12-bit resolution AD converter Infrared remote controller receiver circuit CRC operating circuit Internal Reset Function TQFP 100,14X14 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LC88FC2H0B LC88FC3H0A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P41/INT7 P42 P43/SO1 P44/SI1/SB1 P45/SCK1 P46/PWM0A P47/PWM0B P27 P26/T5O P25/T4O P24/SM0DO P23/SM0DA P22/SM0CK VDD2 VSS2 P21/INT5 P20/INT4 PD5 PD4 PD3 PD2 PD1 PD0 P17/U2TX P16/U2RX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P55/P5INT5 P56/P5INT6 P57/P5INT7 TEST RESB PC0/XT1 PC1/XT2 VSS1 PC3/CF1 PC4/CF2 VDD1 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/U0TX P14/T3OL/U0RX P15/T3OH Function Descriptions Xstromy16 CPU - 4G-byte address space PB6/SM1DO - General-purpose registers: 16 bits 16 registers P70/AN8 P71/AN9 Ports P72/AN10 - I/O Ports 86 P73/AN11 P74/AN12 - Power supply pins 8 (VSS1 to VSS4, VDD1 to VDD4) P75/AN13 P76/AN14 Timer P77/AN15 VSS4 - 16-bit timers 8 VDD4 PA0/SO4 - Base timer serving as a time-of-day clock PA1/SI4/SB4 PA2/SCK4 Serial interfaces PA3/SCS4 PA4/SL0CK - Synchronous SIO interfaces 3 PA5/SL0DA PA6/SL0DO (with automatic transmission capability) PA7 PC2/FILT - Single master I2C/synchronous SIO interface 2 P50/P5INT0 P51/P5INT1 - Slave I2C/synchronous SIO interface P52/P5INT2 P53/P5INT3 - Asynchronous SIO (UART) interfaces 3 P54/P5INT4 Multifrequency 12-bit PWM modules 16-channel 12-bit resolution AD converter Watchdog timer Infrared remote controller receiver circuit CRC operating circuit Real time clock System clock frequency divider CF oscillator circuit, Crystal oscillator circuit, RC oscillator circuit 61-source 14-vector interrupt feature On-chip debugger function PB5/SM1DA PB4/SM1CK PB3 PB2 PB1 PB0 P37/T7O P36/T6O P35/U3TX P34/U3RX P33/INT3 P32/INT2/RMIN P31/INT1 P30/INT0 P07/T0PWMH/U0BRG P06/T0PWML P05/P05INT P04/P04INT P03/P0INT P02/P0INT P01/P0INT P00/P0INT VSS3 VDD3 P40/INT6 Performance 100ns (10.0MHz) VDD=2.7 to 3.6V Ta=40C to +85C Top view Pin Assignment (Top view) Application Home audio, White goods * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 48 of this data sheet. © Semiconductor Components Industries, LLC, 2016 January 2016 - Rev. 1 1 Publication Order Number : LC88FC3H0A/D LC88FC3H0A Function Details Xstromy16 CPU 4G-byte address space General-purpose registers : 16 bits 16 registers Flash ROM 524288 8 bits Programming voltage level : 2.7 to 3.6V. Block-erasable in 2K byte units. Data written in 2-byte units. RAM 48640 8 bits Minimum instruction cycle time (tCYC) 100 ns (10 MHz), VDD = 2.7 to 3.6V Ports Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units : 86 (P0n P1n, P2n, P3n, P4n, P5n, P6n, P7n, PAn PB0 to PB6, PC2, PD0 to PD5) Oscillation/normal withstand voltage I/O ports : 4 (PC0, PC1, PC3, PC4) Reset pins : 1 (RESB) TEST pins : 1 (TEST) Power pins : 8 (VSS1 to 4, VDD1 to 4) Timers Timer 0 : 16-bit timer that supports PWM/toggle outputs <1> 5-bit prescaler <2> 8-bit PWM 2, 8-bit timer + 8-bit PWM mode selectable <3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator. Timer 1 : 16-bit timer with capture registers <1> 5-bit prescaler <2> May be divided into 2 channels of 8-bit timer <3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator Timer 2 : 16-bit timer with capture registers <1> 4-bit prescaler <2> May be divided into 2 channels of 8-bit timer <3> Clock source selectable from system clock, OSC0, OSC1, and external events Timer 3 : 16-bit timer that shpports PWM/toggle outputs <1> 8-bit prescaler <2> 8-bit timer 2ch or 8-bit timer+8-bit PWM mode selectable <3> Clock source selectable from system clock, OSC0, OSC1, and external events Timer 4 : 16-bit timer that supports toggle outputs <1> Clock source selectable from system clock and prescaler 0 Timer 5 : 16-bit timer that supports toggle output <1> Clock source selectable from system clock and prescaler 0 Timer 6 : 16-bit timer that supports toggle outputs <1> Clock source selectable from system clock and prescaler 1 Timer 7 : 16-bit timer that supports toggle output <1> Clock source selectable from system clock and prescaler 1 *Prescaler 0 and 1 are consisted of 4bits and can choose their clock source from OSC0 or OSC1. Base timer <1> Clock may be selected from OSC0 (32.768 kHz crystal oscillator) and frequency-divided output of system clock. <2> Interrupts can be generated in 7 timing schemes. www.onsemi.com 2 LC88FC3H0A Real time clock <1> Calender with Jan. 1, 2000 to Dec.31, 2799 including automatic leapyear calculation function. <2> Consisted of Indipendent second-minuit-hour-day-month-yeare-century counters. Serial interfaces SIO0 : 8-bit synchronous SIO <1> LSB first/MSB first mode selectable <2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) <4> Continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> Interval function (intervals specifiable in 0 to 64tSCK units) <6> Wakeup function SIO1 : 8-bit synchronous SIO <1> LSB first/MSB first mode selectable <2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) <4> Continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> Interval function (intervals specifiable in 0 to 64tSCK units) <6> Wakeup function SIO4 : 8-bit synchronous SIO <1> LSB first/MSB first mode selectable <2> Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) <4> Continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> Interval function (intervals specifiable in 0 to 64tSCK units) <6> Wakeup function SMIIC0 : Single master I2C/8-bit synchronous SIO Mode 0 : Single-master mode communication Mode 1 : Synchronous 8-bit serial I/O (MSB first) SMIIC1 : Single master I2C/8-bit synchronous SIO Mode 0 : Single-master mode communication Mode 1 : Synchronous 8-bit serial I/O (MSB first) SLIIC0 : Slave I2C/8-bit synchronous SIO Mode 0 : I2C slave mode communication Mode 1 : Synchronous 8-bit serial I/O (MSB first) Note: usable only with the external clock source www.onsemi.com 3 LC88FC3H0A UART0 <1> Data length : 8 bits (LSB first) <2> Start bits : 1 bit <3> Stop bits : 1 bit <4> Parity bits : None/even parity/odd parity <5> Transfer rate : 4/8 cycle <6> Baudrate source clock: P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) or Timer4 cycle. <7> Full duplex communication Note : The “cycle” refers to one period of the baudrate clock source. UART2 <1> Data length : 8 bits (LSB first) <2> Start bits : 1 bit <3> Stop bits : 1/2 bit <4> Parity bits : None/even parity/odd parity <5> Transfer rate : 8 to 4096 cycle <6> Baudrate source clock: System clock/OSC0/OSC1/P26 input signal <7> Wakeup function <8> Full duplex communication Note : The “cycle” refers to one period of the baudrate clock source. UART3 <1> Data length : 8 bits (LSB first) <2> Start bits : 1 bit <3> Stop bits : 1/2 bit <4> Parity bits : None/even parity/odd parity <5> Transfer rate : 8 to 4096 cycle <6> Baudrate source clock: System clock/OSC0/OSC1/P36 input signal <7> Wakeup function <8> Full duplex communication Note : The “cycle” refers to one period of the baudrate clock source. AD converter <1> 12/8 bits resolution selectable <2> Analog input: 16 channels <3> Comparator mode PWM PWM0 : Multifrequency 12-bit PWM 2 channels (PWM0A and PWM0B) <1> 2-channel pairs controlled independently of one another <2> Clock source selectable from system clock or OSC1 <3> 8-bit prescaler: TPWMR0= (prescaler value + 1) clock period <4> 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit <5> Fundamental wave PWM mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 High pulse width : 0 to (Fundamental wave period - TPWMR0) <6> Fundamental wave + additional pulse mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 Overall period : Fundamental wave period 16 High pulse width : 0 to (Fundamental wave period - TPWMR0) CRC operating circuit Watchdog timer <1> Driven by the base timer + internal watchdog timer dedicated counter <2> Interrupt or reset mode selectable www.onsemi.com 4 LC88FC3H0A Infrared Remote Controller Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120s when the 32.768kHz crystal oscillator is selected as the reference clock source) 2) Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording 3) X’tal HOLD mode release function Internal Reset Function Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected through option configuration. Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level can be selected by option configuration. Interrupts (peripheral function) 61 sources (33 modules), 14 vector addresses <1> Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. <2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Interrupt Module 1 08000H Watchdog timer (1) 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 0800CH INT0 (1) 5 08014H INT1 (1) 6 08018H INT2 (1) / timer 1 (2) / UART2 (4) 7 0801CH INT3 (1) / timer 2 (4) / SMIIC0 (1) / SLIIC1 (1) 8 08020H INT4 (1) / timer 3 (2) / Infared remote control receiver(4) 9 08024H INT5 (1) / timer 4 (1) / SIO1 (2) 10 0802CH PWM0 (1) / SMIIC1(1) 11 08030H ADC (1) / timer 5 (1) / SIO4(2) 12 08034H INT6 (1) / timer 6 (1) / UART 3 (4) 13 08038H INT7 (1) / SIO0 (2) / SIO0(2) 14 0803CH Port 0 (3) / Port 5 (8) / RTC (1) / CRC (1) 3 priority levels selectable Of interrupts of the same level, the one with the smallest vector address takes precedence. A number enclosed in parentheses denotes the number of sources. Subroutine stack : RAM area Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/division instructions 16 bits × 16 bits (4 tCYC execution time) 16 bits ÷ 16 bits (18 to 19 tCYC execution time) 32 bits ÷ 16 bits (18 to 19 tCYC execution time) www.onsemi.com 5 LC88FC3H0A Oscillator circuits RC oscillator circuit (internal) CF oscillator circuit ( built-in Rf circuit ) Crystal oscillator circuit ( built-in Rf circuit ) SLRC oscillator circuit (internal) VCO oscillator circuit : For system clock : For system clock( OSC1 ) : For low-speed system clock (OSC0) : For system clock (In the case of exception processing) : For timer3, 4, 5, 6, 7 clock System clock divider function Can run on low current. 1/1 to 1/128 of the system clock frequency can be set. Standby function HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation. <1> Oscillation is not stopped automatically. <2> Released by a system reset or occurrence of an interrupt. HOLD mode : Suspends instruction execution and the operation of the peripheral circuits. <1> OSC1, RC, and OSC0 oscillations automatically stop. <2> There are six ways of releasing the HOLD mode: (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt established at SIO0, SIO1 or SIO4 (6) Having an interrupt established at UART2 or UART3 HOLDX mode : Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. <1> OSC1 and RC oscillations automatically stop. <2> OSC0 maintains the state that is established when the HOLDX mode is entered. <3> There are nine ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6,and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt source established at the base timer circuit (6) Having an interrupt established at SIO0, SIO1 or SIO4 (7) Having an interrupt established at UART2 or UATR3 (8) Having an interrupt established at Infared remote control receiver. (9) Having an interrupt source established at the real time clock circuit On-chip debugger function Supports software debugging with the IC mounted on the target board. Supports source line debugging and tracing functions, and breakpoint setting and real time display. Single-wire communication Package form TQFP100, 14 14 : Pb-Free and Halogen Free type www.onsemi.com 6 LC88FC3H0A Development tools On-chip debugger : EOCUIF1 or EOCUIF2 + LC88FC3H0A Programming board Package TQFP 100, 14 14 Programming Board W88F52TQ Flash ROM Programmer Maker ON Semiconductor Model Single / Gang programmer SKK Type C (SanyoFWS) On-board Single programmer FWS-X16DI Type 3 www.onsemi.com 7 Supported Version Application Version After 1.08A Chip Data Version After 2.51 Application Version After 1.08A Chip Data Version After 2.51 Device LC88FC3x0 LC88FC3x0 LC88FC3H0A Package Dimensions unit : mm TQFP 100, 14x14 CASE 932AN-01 ISSUE O www.onsemi.com 8 LC88FC3H0A PB5/SM1DA PB4/SM1CK PB3 PB2 PB1 PB0 P37/T7O P36/T6O P35/U3TX P34/U3RX P33/INT3 P32/INT2/RMIN P31/INT1 P30/INT0 P07/T0PWMH/U0BRG P06/T0PWML P05/P05INT P04/P04INT P03/P0INT P02/P0INT P01/P0INT P00/P0INT VSS3 VDD3 P40/INT6 Pin Assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LC88FC3H0A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P41/INT7 P42 P43/SO1 P44/SI1/SB1 P45/SCK1 P46/PWM0A P47/PWM0B P27 P26/T5O P25/T4O P24/SM0DO P23/SM0DA P22/SM0CK VDD2 VSS2 P21/INT5 P20/INT4 PD5 PD4 PD3 PD2 PD1 PD0 P17/U2TX P16/U2RX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P55/P5INT5 P56/P5INT6 P57/P5INT7 TEST RESB PC0/XT1 PC1/XT2 VSS1 PC3/CF1 PC4/CF2 VDD1 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/U0TX P14/T3OL/U0RX P15/T3OH PB6/SM1DO P70/AN8 P71/AN9 P72/AN10 P73/AN11 P74/AN12 P75/AN13 P76/AN14 P77/AN15 VSS4 VDD4 PA0/SO4 PA1/SI4/SB4 PA2SCK4 PA3/SCS4 PA4/SL0CK PA5/SL0DA PA6/SL0DO PA7 PC2/FILT P50/P5INT0 P51/P5INT1 P52/P5INT2 P53/P5INT3 P54/P5INT4 Top view TQFP100,14×14 (Pb-Free and Halogen Free type) www.onsemi.com 9 LC88FC3H0A System Block Diagram Base timer Watchdog timer FLASH ROM Xstromy16 CPU Timer 0 RAM Timer 1 On-chip debugger Timer 2 Port 0 PLL Timer 3 Port 1 Port 2 Timer 5 Port 3 CF RC X’tal Timer 6 Port 4 Low speed RC Timer 7 Port 5 SIO0 Port 6 SIO1 Port 7 SIO4 Port A SMIIC0 Port B SMIIC1 SLIIC0 UART0 Port C Port D INT0 to INT7 UART2 AD UART3 DA PWM0 Remote control receiver circuit RTC CRC www.onsemi.com 10 LVD/POR Clock generator VCO Timer 4 LC88FC3H0A Pin Description Pin Name I/O VSS1, VSS2, VSS3, VSS4 VDD1, VDD2, VDD3, VDD4 Port 0 – – power sources – + power sources I/O P00 to P07 Port 1 I/O P10 to P17 Port 2 P20 to P27 I/O Description 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units HOLD release input (P00 to P03, P04, P05) Port 0 interrupt input (P00 to P03, P04, P05) Pin functions P06 : Timer 0L output P07 : Timer 0L output/UART0 clock input 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions P10 : SIO0 data output P11 : SIO0 data input/pulse input/output P12 : SIO0 clock input/output P13 : UART0 transmit P14 : Timer 3L output/UART0 receive P15 : Timer 3H output P16 : UART2 receive P17 : UART2 transmit 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions P20 : INT4 input/HOLD release input/timer 3 event input/ timer 2L capture input/timer 2H capture input P21 : INT5 input/HOLD release input/timer 3 event input/ timer 2L capture input/timer 2H capture input P22 : SMIIC0 clock input/output P23 : SMIIC0 bus input/output/data input P24 : SMIIC0 data output (used in 3-wire SIO mode) P25 : Timer 4 output P26 : Timer 5 output Interrupt acknowledge type INT4, INT5 : H level, L level, H edge, L edge, both edges Continued on next page. www.onsemi.com 11 LC88FC3H0A Continued from preceding page. Pin Name Port 3 I/O I/O P30 to P37 Port 4 I/O P40 to P47 Port 5 I/O P50 to P57 Port 6 I/O P60 to P67 Port 7 P70 to P77 I/O Description 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions P30 : INT0 input/HOLD release/timer 2L capture input P31 : INT1 input/HOLD release/timer 2H capture input P32 : INT2 input/HOLD release/timer 2 event input/timer 2L capture input/ Infrared Remote Controller Receiver input P33 : INT3 input/HOLD release/timer 2 event input/timer 2H capture input P34 : UART3 receive P35 : UART3 transmit P36 : Timer 6 output P37 : Timer 7 output Interrupt acknowledge type INT0 to INT3 : H level, L level, H edge, L edge, both edges 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions P40 : INT6 input/HOLD release input P41 : INT7 input/HOLD release input P43 : SIO1 data output P44 : SIO1 data input/bus input/output P45 : SIO1 clock input/output P46 : PWM0A output P47 : PWM0Boutput Interrupt acknowledge type INT6, INT7 : H level, L level, H edge, L edge, both edges 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units HOLD release input Port 0 interrupt input 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions AN0 (P60) to AN7 (P67) : AD converter input port 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Pin functions AN8 (P70) to AN15 (P77) : AD converter input port Continued on next page. www.onsemi.com 12 LC88FC3H0A Continued from preceding page. Pin Name Port A I/O PA0 to PA7 Port B I/o PB0 to PB6 Port C I/O PC0 to PC4 Port D Description I/O I/O PD0 to PD5 TEST I/O RESB I/O 8-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Multiplexed pin functions PA0 : SIO4 data output PA1 : SIO4 data input/pulse input/output PA2 : SIO4 clock input/output PA3 : SIO4 chip select input PA4 : SLIIC0 clock input PA5 : SLIIC0 bus input/output/data input PA6 : SLIIC0 data output (used in 3-wire SIO mode) 7-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units Multiplexed pin functions PB4 : SMIIC1 clock input/output PB5 : SMIIC1 bus input/output/data input PB6 : SMIIC1 data output (used in 3-wire SIO mode) 5-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units(PC2) Pin functions PC0 : 32.768 kHz crystal oscillator input PC1 : 32.768 kHz crystal oscillator output PC2 : FILT of VCO PC3 : Ceramic oscillator input PC4 : Ceramic oscillator output/VCO output 6-bit I/O port I/O specifiable in 1-bit units Pull-up resistors can be turned on and off in 1 bit units TEST pin Used to communicate with on-chip debugger. Connects an external 100 k pull-down resistor. Reset pin www.onsemi.com 13 LC88FC3H0A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of P00 to P07 Output Type Pull-up Resistor CMOS P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 PA0 to PA7 PB0 to PB6 P60 to P67 P70 to p77 PD0 to PD5 PC2 1 bit Able to program special functions’output type from CMOS output or Nch-opendrain Programmable CMOS PC0 PC1 PC3 PC4 N-channel open drain (32.768 kHz crystal oscillator input) Nch-open drain (32.768k kHz crystal oscillator output) CMOS (ceramic oscillator input) CMOS (ceramic oscillator output) None None None None * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins. Example 1 : When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. LSI VDD1 Power supply For buckup VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 www.onsemi.com 14 LC88FC3H0A Example 2 : When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. LSI VDD1 Power supply For buckup VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 www.onsemi.com 15 LC88FC3H0A ■ Absolute Maximum Ratings at Ta=25C, VSS1=VSS2=VSS3=VSS4=0V Parameter Symbol Maximum supply voltage VDD max Input voltage VI (1) Input/output voltage VIO (1) High level output current Peak output current IOPH (1) IOPH (2) IOPH (3) Average output IOMH (1) current (Note 1-1) IOMH (2) IOMH (3) Total output current IOAH (1) IOAH (2) IOAH (3) Applicable Pin /Remarks VDD1, VDD2, VDD3, VDD4 RESB Ports 0, 1, 2 Ports 3, 4, 5 Ports 6, 7 Ports A, B, C, D Ports 0, 1, 2, 3 P40 to P45 Ports 7, A, D PB2 to PB6 P46, P47 PB0, PB1 Port 5, 6 PC0 to PC4 Ports 0, 1, 2, 3 P40 to P45 Ports 5, 6, 7, A PB2 to PB6 Ports D P46, P47 PB0, PB1 Port 5, 6 PC0 to PC4 Pprts 5 PC0 to PC4 Port 6 IOAH (5) Port 5, 6 PC0 to PC4 Ports 1,D1 P20 to P21 P22 to P27 IOAH (6) Ports 1, 2, D IOAH (7) Ports 4 IOAH (8) Ports 0, 3 IOAH (9) Ports 0, 3, 4 IOAH (10) Ports B, 7 IOAH (11) Ports A IOAH (12) Ports 7, A, B IOAH (4) Conditions VDD1=VDD2=VDD3 = VDD4 CMOS output selected Per applicable pin Per applicable pin Per applicable pin CMOS output selected Per applicable pin Per applicable pin Per applicable pin Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Specification VDD [V] min typ max 0.3 +4.6 0.3 VDD +0.3 0.3 VDD +0.3 unit V 7.5 12.5 4.5 5 10 3 10 10 mA 20 20 20 40 20 20 40 20 20 40 Note 1-1 : Average output current refers to the average of output currents measured for a period of 100 ms. Continued on next page. www.onsemi.com 16 LC88FC3H0A Continued from preceding page. Low level output current Parameter Symbol Peak output current IOPL (1) IOAL (5) IOAL (6) Ports 1, 2, D IOAL (7) Port 4 IOAL (8) Port 0, 3 IOAL (9) Port 0, 3, 4 IOAL (10) Port 7, B IOAL (11) Port A IOAL (12) Port 7, A, B IOPL (3) IOML (1) IOML (2) IOML (3) Total output current Conditions Ports 0, 1, 3, 4 Ports 7, D P20, P21, P24 to P27 PA0 to PA4, PA6, PA7 PB0 to PB4, PB6, P22, P23 PA4, PA5 PB4, PB5 Ports 5, 6 PC0 to PC4 Ports 0, 1, 3, 4 Ports 7, D P20, P21, P24 to P27 PA0 to PA4, PA6, PA7 PB0 to PB4, PB6, PB7 P22, P23 PA4, PA5 PB4, PB5 Ports 5, 6 PC0 to PC4 Ports 5 PC0 to PC2 Port 6 PC3 to PC4 Port 5, 6 PC0 to PC4 Ports 1, D P20, P21 P22 to P27 IOPL (2) Average output current (Note 1-1) Applicable Pin /Remarks IOAL (1) IOAL (2) IOAL (3) IOAL (4) TQFP100 Specification VDD [V] min typ max unit Per applicable pin 15 Per applicable pin 20 Per applicable pin 7.5 Per applicable pin 12.5 Per applicable pin 15 Per applicable pin 5 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Ta=40 to +85C Package with thermal resistance bord (Note 1-2) 10 mA 10 20 35 35 70 35 35 70 35 35 70 Allowable power dissipation Pd max Operating ambient temperature Storage ambient temperature Topr 40 +85 Tstg 55 +125 460 mW C Note 1-1 : Average output current refers to the average of output currents measured for a period of 100 ms. Note 1-2 : SEMI standerds thermal resistance board (size : 76.1 114.3 1.6 tmm, glass epoxy) is used. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 17 LC88FC3H0A ■ Allowable Operating Conditions at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter Symbol Applicable Pin/Remarks Operating supply VDD (1) VDD1=VDD2=VDD3 Conditions Specification VDD [V] min typ max unit 0.098s ≤ tCYC ≤ 66s voltage 2.7 3.6 2.0 3.6 0.3VDD VDD +0.7 0.3VDD VDD (Note 2-1) Memory VHD VDD1=VDD2=VDD3 sustaining supply RAM and register contents sustained in HOLD mode voltage High level input VIH (1) voltage Ports 0, 1, 2, 3, 4 2.7 to 3.6 Port 5, A, B VIH (2) VIH (3) Ports 6, 7, D,PC2 2.7 to 3.6 RESB PC0, PC1, PC3, PC4 VIH (4) P22, P23, PA4, PA5, VIL (1) When ports 1, 2, 3, 4, PB4, PB5 I2C side Low level input voltage 5, A and port B, PnFSAn=0 +0.7 2.7 to 3.6 0.75VDD VDD 2.7 to 3.6 0.7VDD VDD 2.7 to 3.6 VSS 0.2VDD 2.7 to 3.6 VSS 0.2VDD 2.7 to 3.6 VSS 0.25VDD 2.7 to 3.6 VSS 0.3VDD 2.7 to 3.6 0.098 66 2.7 to 3.6 0.1 10 V Ports 0, 6, 7, D, PC2 VIL (2) When ports 1, 2, 3, 4, 5, A and port B, PnFSAn=1 VIL (3) CF1, RESB PC0, PC1,PC3, PC4 VIL (4) P22, P23, PA4, PA5, PB4, PB5 I2C side Instruction cycle tCYC time s (Note 2-1) External system clock frequency FEXCF (1) CF1 CF2 pin open System clock frequency division ratio = 1/1 External system clock MHz DUTY505% CF2 pin open System clock frequency 2.7 to 3.6 0.2 20 division ratio = 1/2 Note 2-1 : Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Continued on next page. www.onsemi.com 18 LC88FC3H0A Continued from preceding page. Parameter Oscillation Symbol FmCF frequency range Applicable Pin /Remarks PC3(CF1), PC4(CF2) (Note 2-2) FmSLRC FmVCO(1) FmVCO(2) FmVCO(5) 10 MHz ceramic oscillator mode See Fig. 1. Specification VDD [V] min typ 2.7 to 3.6 max XT1, XT2 Internal low-speed RC oscillation 32.768 kHz crystal oscillator mode See Fig. 2. VCO oscillator When setting FRQSEL=0 See Fig. 9. VCO oscillator When setting FRQSEL=1 See Fig. 9. VCO oscillator unit 10 MHz Internal RC oscillation FmRC FsX'tal Conditions 2.7 to 3.6 0.5 1.0 2.0 2.7 to 3.6 18 30 45 kHz 2.7 to 3.6 32.768 2.7 to 3.6 12 28 2.7 to 3.6 38 70 2.7 to 3.6 MHz Note 2-3 Note 2-2 : See Tables 1 and 2 for oscillator constant values. Note 2-3 : VCO oscillation frequency = Ceramic oscillator frequency Setting point of SELREF Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 19 LC88FC3H0A ■ Electrical Characteristics at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter High level input Symbol IIH (1) current Applicable Pin /Remarks Ports 0, 1, 2 Ports 3, 4, 5 Ports 6, 7 Ports A, B,C, D RESB Low level input IIL (1) current Ports 0, 1, 2 Ports 3, 4, 5 Ports 6, 7 Ports A, B, C, D RESB High level output VOH (1) Ports 0, 1, 2, 3 voltage Conditions Output disabled Pull-up resistor off VIN=VDD (including output Tr. off leakage current) Output disabled Pull-up resistor off VIN=VSS (including output Tr. off leakage current) IOH=0.4mA Ports 5, 6 VOH (2) Ports A, D, PC2 P40 to P45 Specification VDD [V] min typ 2.7 to 3.6 max unit 1 A 2.7 to 3.6 1 3.0 to 3.6 VDD0.4 2.7 to 3.6 VDD0.4 IOH=0.2mA PB2 to PB6 Low level output VOH (3) P46, P47 IOH=1.6mA 3.0 to 3.6 VDD0.4 VOH (4) PB0, PB1 IOH=1.0mA 2.7 to 3.6 VDD0.4 VOH (5) PC0, PC1, IOH=1.0mA PC3, PC4, VOH (6) 3.0 to 3.6 VDD0.4 IOH=0.4mA 2.7 to 3.6 VDD0.4 VOL (1) Ports 0, 1, 3 , 4 IOL=1.6mA voltage Ports 5, 6, 7, D PC2 VOL (2) P20 to P21, P24 to P27 3.0 to 3.6 0.4 2.7 to 3.6 0.4 3.0 to 3.6 0.4 2.7 to 3.6 0.4 V IOL=1.0mA PA0 to PA3 PA6 to PA7 PB0 to PB3, PB6 Pull-up resistor VOL (3) P22, P23, IOL=3.0mA VOL (4) PA4, PA5, PB4, PB5 IOL=1.3mA VOL (5) PC0, PC1, IOL=1.0mA PC3, PC4, VOL (6) 3.0 to 3.6 0.4 IOL=0.4mA 2.7 to 3.6 0.4 Rpu (1) VOH=0.9VDD Ports 0, 1, 2, 3 Ports 4, 5, 6, 7 Hysteresis voltage Rpu (2) Ports A, B, D, PC2 VHYS RESB When ports 1, 2, 3, 4, A, B 3.0 to 3.6 15 35 80 2.7 to 3.6 15 35 100 k 2.7 to 3.6 0.1VDD V 2.7 to 3.6 10 pF PnFSAn=1 Pin capacitance CP All pins Pins other than that under test VIN=VSS f=1 MHz Ta=25C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 20 LC88FC3H0A ■ Serial I/O Characteristics at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Symbol Period tSCK (1) Input clock Serial clock Parameter Low level Applicable Pin/Remarks SCK0 (P12) Conditions Specification VDD [V] See Fig. 6. pulse width tSCKH (1) (1a) tSCKHBSY (1b) Output clock Low level SCK0 (P12) Automatic communication mode See Fig. 6. Automatic communication mode See Fig. 6. Mode other than automatic communication mode See Fig. 6. CMOS output selected See Fig. 6. 2.7 to 3.6 6 tCYC 23 4 4 tSCKL (2) 1/2 pulse width High level tSCK tSCKH (2) 1/2 pulse width tSCKHA (2) tSCKHBSY (2a) tSCKHBSY (2b) Serial input Data setup time tsDI (1) SI0 (P11), SB0 (P11) Data hold time unit 2 tSCKHA (1) tSCK (2) max 2 tSCKHBSY Period typ 4 tSCKL (1) pulse width High level min thDI (1) Automatic communication mode CMOS output selected See Fig. 6. Automatic communication mode CMOS output selected See Fig. 6. Mode other than automatic communication mode See Fig. 6. Specified with respect to rising edge of SIOCLK See Fig. 6. 2.7 to 3.6 6 4 23 tCYC 4 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay tdD0 (1) time SO0 (P10), (Note 4-1-2) SB0 (P11) 1tCYC +0.05 Output clock tdDO (2) (Note 4-1-2) s 2.7 to 3.6 1tCYC +0.05 Note 4-1-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-1-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 21 LC88FC3H0A SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Symbol Period tSCK (3) Input clock Serial clock Parameter Low level Applicable Pin/Remarks Conditions Specification VDD [V] SCK0 (P12) See Fig. 6. pulse width tSCKL (3) tSCKH (3) unit tCYC 1 tSCKHBSY 2 Serial input tsDI (2) SI0 (P11), SB0 (P11) Data hold time max 1 2.7 to 3.6 (3) Data setup time typ 2 pulse width High level min thDI (2) Specified with respect to rising edge of SIOCLK See Fig. 6. 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay time tdD0 (3) SO0 (P10), s (Note 4-2-2) SB0 (P11) 2.7 to 3.6 1tCYC +0.05 Note 4-2-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-2-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 22 LC88FC3H0A SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Symbol Input clock Serial clock Period tSCK (4) Low level tSCKL (4) Applicable Conditions Pin/Remarks Specification VDD [V] SCK1 (P45) See Fig. 6. pulse width typ max unit 4 2 pulse width High level min tSCKH (4) 2 Automatic communication tSCKHA (4) mode 2.7 to 3.6 See Fig. 6. 6 tCYC Automatic communication tSCKHBSY (4a) mode 23 See Fig. 6. Mode other than automatic tSCKHBSY (4b) communication mode 4 See Fig. 6. Output clock Period tSCK (5) SCK1 (P45) CMOS output selected 4 See Fig. 6. Low level tSCKL (5) 1/2 pulse width High level tSCK tSCKH (5) 1/2 pulse width Automatic communication tSCKHA (5) mode CMOS output selected 2.7 to 3.6 6 See Fig. 6. Automatic communication tSCKHBSY (5a) mode 4 CMOS output selected 23 tCYC See Fig. 6. Mode other than automatic tSCKHBSY (5b) communication mode 4 See Fig. 6. Serial input Data setup time Data hold time tsDI (3) SI1 (P44), Specified with respect to SB1 (P44) rising edge of SIOCLK See Fig. 6. thDI (3) 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay tdD0 (4) time SO1 (P43), (Note 4-3-2) SB1 (P44) 1tCYC +0.05 Output clock tdDO (5) (Note 4-3-2) s 2.7 to 3.6 1tCYC +0.05 Note 4-3-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-3-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 23 LC88FC3H0A SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Parameter Symbol Input clock Serial clock Period tSCK (6) Low level tSCKL (6) Applicable Pin/Remarks Conditions Specification VDD [V] SCK1 (P45) See Fig. 6. pulse width Serial input Data hold time max unit 1 2.7 to 3.6 tSCKH (6) tCYC 1 tSCKHBSY 2 (6) Data setup time typ 2 pulse width High level min tsDI (4) SI1 (P44), Specified with respect to SB1 (P44) rising edge of SIOCLK See Fig. 6. thDI (4) 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay time tdD0 (6) SO1 (P43), s (Note 4-4-2) SB1 (P44) 2.7 to 3.6 1tCYC +0.05 Note 4-4-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-4-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 24 LC88FC3H0A SIO4 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-5-1) Parameter Symbol Input clock Serial clock Period tSCK (7) Low level tSCKL (7) Applicable Conditions Pin/Remarks Specification VDD [V] SCK4 (PA2) See Fig. 6. pulse width typ max unit 4 2 pulse width High level min tSCKH (7) 2 Automatic communication tSCKHA (7) mode 2.7 to 3.6 See Fig. 6. 6 tCYC Automatic communication tSCKHBSY (7a) mode 23 See Fig. 6. Mode other than automatic tSCKHBSY (7b) communication mode 4 See Fig. 6. Output clock Period tSCK (8) SCK4 (PA2) CMOS output selected 4 See Fig. 6. Low level tSCKL (8) 1/2 pulse width High level tSCK tSCKH (8) 1/2 pulse width Automatic communication tSCKHA (8) mode CMOS output selected 2.7 to 3.6 6 See Fig. 6. Automatic communication tSCKHBSY (8a) mode 4 CMOS output selected 23 tCYC See Fig. 6. Mode other than automatic tSCKHBSY (8b) communication mode 4 See Fig. 6. Serial input Data setup time Data hold time tsDI (5) SI4 (PA1), Specified with respect to SB4 (PA1) rising edge of SIOCLK See Fig. 6. thDI (5) 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay tdD0 (7) time SO4 (PA0), (Note 4-5-2) SB14(PA1) 1tCYC +0.05 Output clock tdDO (8) (Note 4-5-2) s 2.7 to 3.6 1tCYC +0.05 Note 4-5-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-5-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 25 LC88FC3H0A SIO4 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-6-1) Parameter Symbol Input clock Serial clock Period tSCK (9) Low level tSCKL (9) Applicable Pin/Remarks Conditions Specification VDD [V] SCK4 (P45) See Fig. 6. pulse width Serial input Data hold time max unit 1 2.7 to 3.6 tSCKH (9) tCYC 1 tSCKHBSY 2 (9) Data setup time typ 2 pulse width High level min tsDI (6) SI4 (P44), Specified with respect to SB4 (P44) rising edge of SIOCLK See Fig. 6. thDI (6) 0.03 2.7 to 3.6 0.03 Input clock Serial output Output delay time tdD0 (9) SO4 (P43), s (Note 4-6-2) SB4(P44) 2.7 to 3.6 1tCYC +0.05 Note 4-6-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-6-2 : Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. www.onsemi.com 26 LC88FC3H0A SMIIC0 Simple SIO Mode Input/Output Characteristics (Note 4-7-1) Parameter Input clock Serial clock Period Symbol tSCK (10) Applicable Pin/Remarks SM0CK Conditions Specification VDD [V] See Fig. 6. tSCKL (10) 2.7 to 3.6 pulse width High level Output clock Low level tSCK (11) SM0CK CMOS output selected (P22) See Fig. 6. tSCKL (11) 2 4 1/2 2.7 to 3.6 tSCK tSCKH (11) 1/2 pulse width Serial input Data setup time Data hold time thDI (7) Serial output tsDI (7) Output delay time tdD0 (10) unit 2 pulse width High level max tCYC tSCKH (10) pulse width Period typ 4 (P22) Low level min SM0DA Specified with respect to (P23), rising edge of SIOCLK See Fig. 6. 0.03 SM0DO Specified with respect to (P24), falling edge of SIOCLK SM0DA Specified as interval up to (P23) 0.03 2.7 to 3.6 time when output state starts s 2.7 to 3.6 changing. See Fig. 6. Note 4-7-1 : These specifications are theoretical values. Add margin depending on its use. www.onsemi.com 27 1tCYC +0.05 LC88FC3H0A SMIIC0 I2C Mode Input/Output Characteristics (Note 4-8-1) (Note 4-8-2) (Note 4-8-4) Parameter Symbol Input clock Clock Period tSCL Applicable Pin/Remarks SM0CK Conditions Specification VDD [V] See Fig. 8. tSCLL 2.7 to 3.6 pulse width High level Output clock SM0CK (P22) Low level Specified as interval up to 2.5 changing. tSCLLx 10 time when output state starts 1/2 2.7 to 3.6 pulse width High level tSCL tSCLHx 1/2 pulse width SM0CK and SM0DA tsp SM0CK (P22) See Fig. 8. SM0DA (P23) pins input spike unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 (P22) Low level min 2.7 to 3.6 1 Tfilt suppression time Input tBUF SM0CK (P22) tBUFx Bus release time 2.5 SM0CK (P22) Standard clock mode SM0DA (P23) Specified as interval up to time when output state starts 2.7 to 3.6 changing. between start and Output stop See Fig. 8. SM0DA (P23) 5.5 μs High-speed clock mode Specified as interval up to Tfilt 1.6 time when output state starts changing. tHD;STA SM0CK (P22) SM0DA (P23) When SMIIC register control bit, 2.0 I2CSHDS=0 Input See Fig. 8. Tfilt When SMIIC register control bit 2.5 I2CSHDS=1 Start/restart See Fig. 8. condition hold tHD;STAx time SM0CK (P22) Standard clock mode SM0DA (P23) Specified as interval up to 2.7 to 3.6 4.1 time when output state starts Output changing. μs High-speed clock mode Specified as interval up to 1.0 time when output state starts changing. Input tSU;STA SM0CK (P22) See Fig. 8. 1.0 SM0DA (P23) tSU;STAx SM0CK (P22) Standard clock mode SM0DA (P23) Specified as interval up to time when output state starts setup time changing. Output Restart condition 5.5 2.7 to 3.6 μs High-speed clock mode Specified as interval up to time when output state starts changing. www.onsemi.com 28 Tfilt 1.6 LC88FC3H0A Parameter Symbol tSU;STO Input tSU;STOx Stop condition setup time Output tHD;DAT Input Data hold time Output Input Output tSU;DATx tF Input tF Output SM0CK and SM0DA pins fall time SM0CK (P22) SM0DA (P23) Conditions Specification VDD [V] max Unit Tfilt 4.9 s 1.1 0 2.7 to 3.6 Tfilt 1 1.5 See Fig. 8. 1 SM0CK (P22) Specified as interval up to time when output state starts SM0DA (P23) changing. SM0CK (P22) SM0DA (P23) typ 1.0 SM0CK (P22) Standard clock mode SM0DA (P23) Specified as interval up to 2.7 to 3.6 time when output state starts changing. High-speed clock mode Specified as interval up to time when output state starts changing. SM0CK (P22) See Fig. 8. SM0DA (P23) SM0CK (P22) SM0DA (P23) Min See Fig. 8. tHD;DATx SM0CK (P22) Specified as interval up to time when output state starts SM0DA (P23) changing. tSU;DAT Data setup time Applicable Pin/Remarks 2.7 to 3.6 Tfilt 1tSCL1.5Tfilt See Fig. 8. 2.7 to 3.6 SM0CK (P22) When SMIIC register control bits SM0DA (P23) PSLW=1, P5V=1 SM0CK, SM0DA port output FAST mode Cb ≤ 100pF 3 3.0 to 3.6 300 20+0.1Cb (Note 4-8-3) 250 ns 100 Note 4-8-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-8-2 : The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC1 0 1 tCYC2 1 0 tCYC3 1 1 tCYC4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range : 250 ns ≥ Tfilt > 140 ns Note 4-8-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF Note 4-8-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100 kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400 kHz www.onsemi.com 29 LC88FC3H0A SMIIC1 Simple SIO Mode Input/Output Characteristics (Note 4-9-1) Parameter Input clock Serial clock Period Symbol tSCK (12) Applicable Pin/Remarks SM0CK Conditions Specification VDD [V] See Fig. 6. tSCKL (12) 2.7 to 3.6 pulse width High level Output clock Low level tSCK (13) SM0CK CMOS output selected (PB4) See Fig. 6. tSCKL (13) 2 4 1/2 2.7 to 3.6 tSCK tSCKH (13) 1/2 pulse width Serial input Data setup time Data hold time thDI (8) Serial output tsDI (8) Output delay time tdD0 (12) unit 2 pulse width High level max tCYC tSCKH (12) pulse width Period typ 4 (PB4) Low level min SM0DA Specified with respect to (PB5), rising edge of SIOCLK See Fig. 6. 2.7 to 3.6 0.03 SM0DO Specified with respect to (PB6), falling edge of SIOCLK SM0DA Specified as interval up to (PB5) 0.03 time when output state starts s 2.7 to 3.6 changing. See Fig. 6. Note 4-9-1 : These specifications are theoretical values. Add margin depending on its use. www.onsemi.com 30 1tCYC +0.05 LC88FC3H0A SMIIC1 I2C Mode Input/Output Characteristics (Note 4-10-1) (Note 4-10-2) (Note 4-10-4) Parameter Symbol Input clock Clock Period tSCL Applicable Pin/Remarks SM1CK Conditions Specification VDD [V] See Fig. 8. tSCLL 2.7 to 3.6 pulse width High level Output clock SM1CK (PB4) Low level Specified as interval up to 2.5 changing. tSCLLx 10 time when output state starts 1/2 2.7 to 3.6 pulse width High level tSCL tSCLHx 1/2 pulse width SM0CK and SM0DA tsp SM1CK (PB4) See Fig. 8. SM1DA (PB5) pins input spike unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 (PB4) Low level Min 2.7 to 3.6 1 Tfilt suppression time Input tBUF SM1CK (PB4) See Fig. 8. tBUFx Tfilt SM1CK (PB4) Standard clock mode SM1DA (PB5) Specified as interval up to Bus release time time when output state starts 2.7 to 3.6 changing. between start and Output stop 2.5 SM1DA (PB5) 5.5 μsec High-speed clock mode Specified as interval up to 1.6 time when output state starts changing. tHD;STA SM1CK (PB4) When SMIIC register SM1DA (PB5) control bit, 2.0 I2CSHDS=0 Input See Fig. 8. Tfilt When SMIIC register control bit 2.5 I2CSHDS=1 Start/restart See Fig. 8. condition hold tHD;STAx time SM1CK (PB4) Standard clock mode 2.7 to 3.6 SM1DA (PB5) Specified as interval up to 4.1 time when output state starts Output changing. μsec High-speed clock mode Specified as interval up to 1.0 time when output state starts changing. Input tSU;STA SM1CK (PB4) See Fig. 8. 1.0 SM1DA (PB5) tSU;STAx Tfilt SM1CK (PB4) Standard clock mode SM1DA (PB5) Specified as interval up to time when output state starts setup time changing. Output Restart condition 5.5 2.7 to 3.6 μsec High-speed clock mode Specified as interval up to time when output state starts changing. www.onsemi.com 31 1.6 LC88FC3H0A Parameter Symbol tSU;STO Input tSU;STOx Stop condition setup time Output tHD;DAT Input Data hold time Output Input Output tSU;DATx tF Input tF Output SM0CK and SM0DA pins fall time Conditions Specification VDD [V] SM1CK (PB4) See Fig. 8. SM1DA (PB5) Min typ max 1.0 SM1CK (PB4) Standard clock mode SM1DA (PB5) Specified as interval up to 2.7 to 3.6 time when output state starts changing. High-speed clock mode Specified as interval up to time when output state starts changing. SM1CK (PB4) See Fig. 8. SM1DA (PB5) tHD;DATx SM1CK (PB4) Specified as interval up to SM1DA (PB5) time when output state starts changing. tSU;DAT Data setup time Applicable Pin/Remarks Tfilt 4.9 sec 1.1 0 2.7 to 3.6 Tfilt 1 SM1CK (PB4) See Fig. 8. SM1DA (PB5) unit 1.5 1 SM1CK (PB4) Specified as interval up to SM1DA (PB5) time when output state starts changing. SM1CK (PB4) See Fig. 8. SM1DA (PB5) 2.7 to 3.6 Tfilt 1tSCL-1.5Tfilt 2.7 to 3.6 SM1CK (PB4) When SMIIC register SM1DA (PB5) control bits PSLW=1, PHV=1 SM0CK, SM0DA port output FAST mode Cb ≤ 100pF 3 3 to 3.6 300 20+0.1Cb (Note 4-10-3) 250 ns 100 Note 4-10-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-10-2 : The value of Tfilt is determined by the values of the register SMIC1BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC1 0 1 tCYC2 1 0 tCYC3 1 1 tCYC4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range : 250 ns ≥ Tfilt > 140 ns Note 4-10-3 : Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF Note 4-10-4 : The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100 kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC1BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400 kHz www.onsemi.com 32 LC88FC3H0A SLIIC0 Simple SIO Mode Input/Output Characteristics (Note 4-11-1) Parameter Input clock Serial clock Period Symbol tSCK (13) Applicable Pin/Remarks SL0CK Conditions Specification VDD [V] See Fig. 6. tSCKL (13) 2.7 to 3.6 pulse width High level tSCKH (13) Serial input Data hold time thDI (9) Serial output tsDI (9) Output delay time tdD0 (13) max unit tCYC 2 2 pulse width Data setup time typ 4 (PA4) Low level min SL0DA Specified with respect to (PA5), rising edge of SIOCLK See Fig. 6. 2.7 to 3.6 0.03 SL0DO Specified with respect to (PA6), falling edge of SIOCLK SL0DA Specified as interval up to (PA5) 0.03 time when output state starts s 2.7 to 3.6 changing. See Fig. 6. Note 4-11-1 : These specifications are theoretical values. Add margin depending on its use. www.onsemi.com 33 1tCYC +0.05 LC88FC3H0A SLIIC1 I2C Mode Input/Output Characteristics (Note 4-12-1) (Note 4-12-2) Parameter Symbol Input clock Clock Period tSCL Applicable Pin/Remarks SL0CK Conditions Specification VDD [V] See Fig. 8. tSCLL 2.7 to 3.6 pulse width High level tSCLH tsp SL0CK (PA4) unit Tfilt 2.5 See Fig. 8. SL0DA (PA5) pins input spike max 2 pulse width SL0CK and SL0DA typ 5 (PA4) Low level Min 2.7 to 3.6 1 Tfilt suppression time between start and Input Bus release time tBUF SL0CK (PA4) See Fig. 8. SL0DA (PA5) 2.7 to 3.6 2.5 Tfilt stop tHD;STA SL0CK (PA4) SL0DA (PA5) See Fig. 8. Input time control bit, 2.0 I2CSHDS=0 Start/restart condition hold When SMIIC register When SMIIC register 2.7 to 3.6 control bit Tfilt 2.5 I2CSHDS=1 See Fig. 8. setup time Input Restart condition tSU;STA SL0CK (PA4) SL0DA (PA5) Input Data hold time SL0CK (PA4) SL0DA (PA5) 1.0 Tfilt 2.7 to 3.6 1.0 Tfilt See Fig. 8. 0 Output Specified as interval up to time when output state starts changing. tSU;DAT SL0CK (PA4) SL0DA (PA5) See Fig. 8. SL0CK (PA4) SL0DA (PA5) Specified as interval up to time when output state starts changing. Input tHD;DATx SL0CK (PA4) SL0DA (PA5) Output tSU;DATx 2.7 to 3.6 See Fig. 8. Input tHD;DAT Data setup time See Fig. 8. SL0DA (PA5) tSU;STO Stop condition setup time SL0CK (PA4) 2.7 to 3.6 Tfilt 1 1.5 1 www.onsemi.com 34 2.7 to 3.6 Tfilt 1tSCL1.5Tfilt LC88FC3H0A Parameter Symbol tF Input tF Conditions SL0CK (PA4) SL0DA (PA5) See Fig. 8. SL0CK (PA4) SL0DA (PA5) When SLIIC0 register control bits PSLW=1, PHV=1 Output SL0CK and SL0DA pins fall time Applicable Pin/Remarks Specification VDD [V] Min typ 2.7 to 3.6 3 max Unit 300 20+0.1Cb (Note 4-12-3) SL0CK, SL0DA port output FAST mode 3.0 to 3.6 Cb ≤ 100pF 250 ns 100 Note 4-12-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-12-2 : The value of Tfilt is determined by the values of the register SLIC0PCNT, bits 5 and 4 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC1 0 1 tCYC2 1 0 tCYC3 1 1 tCYC4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range : 250 ns ≥ Tfilt > 140 ns Note 4-12-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100 pF www.onsemi.com 35 LC88FC3H0A UART0 Operating Conditions at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter Transfer rate Symbol UBR0 Applicable Pin/Remarks Conditions U0RX (P13), U0TX (P14), U0BRG (P07) Specification VDD [V] min 2.7 to 3.6 4 typ max unit 8 tBGCYC Note 4-9 : tBGCYC denotes one cycle of the baudrate clock source. UART2 Operating Conditions at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter Transfer rate Symbol UBR2 Applicable Pin/Remarks Conditions Specification VDD [V] min 2.7 to 3.6 8 typ max unit 4096 tBGCYC U2RX (P16), U2TX (P17), Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. UART3 Operating Conditions at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter Transfer rate Symbol UBR3 Applicable Pin/Remarks Conditions Specification VDD [V] min 2.7 to 3.6 8 typ max unit 4096 tBGCYC U3RX (P34), U3TX (P35), Note 4-10 : tBGCYC denotes one cycle of the baudrate clock source. ■ Pulse Input Conditions at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Parameter High/low level pulse width Symbol tPIH (1) tPIL (1) tPIL (2) Applicable Pin/Remarks Conditions INT0 (P30), INT1 (P31), INT2 (P32), INT3 (P33), INT4 (P20), INT5 (P21), INT6 (P40), INT7 (P41) Interrupt source flag can be set. Event inputs for timers 2 and 3 are enabled. RESB Resetting is enabled. www.onsemi.com 36 Specification VDD [V] min 2.7 to 3.6 2 tCYC 2.7 to 3.6 10 s typ max unit LC88FC3H0A ■ AD Converter Characteristics at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V 12-bit AD Conversion Mode Parameter Symbol Resolution NAD Absolute accuracy ETAD Conversion time TCAD12 Analog input voltage range Analog port input current VAIN Applicable Pin /Remarks AN0 (P60) to AN7 (P67), AN8 (P70) to AN15 (P77) Conditions Specification VDD [V] min 2.7 to 3.6 typ max 12 unit bit (Note 6-1) 2.7 to 3.6 16 LSB Conversion time calculated 3.0 to 3.6 2.7 to 3.6 64 128 115 230 s 2.7 to 3.6 VSS VDD V IAINH VAIN=VDD 2.7 to 3.6 IAINL VAIN=VSS 2.7 to 3.6 1 1 A 52 Conversion time calculation formula : TCAD12 = ( AD division ratio +2) tCYC 8-bit AD Conversion Mode Parameter Symbol Resolution NAD Absolute accuracy ETAD Conversion time TCAD8 Analog input voltage range Analog port input current VAIN Applicable Pin /Remarks Conditions AN0 (P60) to AN7 (P67), (Note 6-1) AN8 (P70) to AN15 (P77) Conversion time calculated Specification VDD [V] min 2.7 to 3.6 typ max 8 unit bit 1.5 LSB 3.0 to 3.6 2.7 to 3.6 39 79 71 140 s 2.7 to 3.6 VSS VDD V 2.7 to 3.6 IAINH VAIN=VDD 2.7 to 3.6 IAINL VAIN=VSS 2.7 to 3.6 1 1 A 52 Conversion time calculation formula : TCAD8 = ( AD division ratio +2) tCYC Note 6-1 : The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2 : The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: - The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. - The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. www.onsemi.com 37 LC88FC3H0A ■ Consumption Current Characteristics at Ta=–40 to +85C, VSS1=VSS2=VSS3=VSS4=0V typ : 3.3V Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP (1) IDDOP (2) IDDOP (3) Applicable Pin/Remarks VDD1 =VDD2 =VDD3 =VDD4 Conditions FmCF=10 MHz ceramic oscillator mode FmX'tal=32.768 kHz crystal oscillator mode System clock set to 10 MHz Internal RC oscillation stopped 1/1 frequency division mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768 kHz crystal oscillator mode System clock set to internal RC oscillation 1/1 frequency division mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768 kHz crystal oscillator mode System clock set to 32.768 kHz Internal RC oscillation stopped 1/1 frequency division mode Specification VDD [V] 2.7 to 3.6 min typ max 5.0 12.0 unit mA 2.7 to 3.6 0.8 2.1 2.7 to 3.6 30 136 A Continued on next page. www.onsemi.com 38 LC88FC3H0A Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol Applicable Pin/Remarks Conditions Specification VDD [V] IDDHALT (1) VDD1 =VDD2 =VDD3 =VDD4 HALT mode FmCF=10 MHz ceramic oscillator mode FmX'tal=32.768 kHz crystal oscillator 2.7 to 3.6 mode System clock set to 10 MHz Internal RC oscillation stopped 1/1 frequency division mode IDDHALT (2) HALT mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768 kHz crystal oscillator mode System clock set to internal RC 2.7 to 3.6 oscillation 1/1 frequency division mode IDDHALT (3) HALT mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768 kHz crystal oscillator mode 2.7 to 3.6 System clock set to 32.768 kHz Internal RC oscillation stopped 1/1 frequency division mode min typ max 1.5 3.2 unit mA 0.2 0.8 8.5 78 A Continued on next page. www.onsemi.com 39 LC88FC3H0A Continued from preceding page. Parameter HOLD mode consumption current Symbol Applicable Pin/Remarks IDDHOLD (1) VDD1 IDDHOLD (2) HOLDX mode IDDHOLD (3) consumption current IDDHOLD (4) Conditions HOLD mode CF1=VDD or open (external clock mode) HOLD mode CF1=VDD or open (external clock mode) LVD option selected HOLDX mode CF1=VDD or open (external clock mode) FmX'tal=32.768 kHz crystal oscillator mode HOLDX mode CF1=VDD or open (external clock mode) FmX'tal=32.768 kHz crystal oscillator mode LVD option selected Specification VDD [V] min typ max 2.7 to 3.6 0.2 50 2.7 to 3.6 1.2 53 2.7 to 3.6 4.6 71 2.7 to 3.6 5.6 74 unit A Note 7-1 : The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. ■ F-ROM Programming Characteristics at Ta=+10 to +55C, VSS1=VSS2=VSS3=VSS4=0V Parameter Onboard programming current Onboard programming time Symbol IDDFW (1) tFW (1) tFW (2) Applicable Pin/Remarks VDD1 Conditions Microcontroller erase current current is excluded. Specification VDD [V] min typ max unit 2.7 to 3.6 10 mA 2.7 to 3.6 25 ms 2.7 to 3.6 45 μs 2K-byte erase operation 2-byte programming operation www.onsemi.com 40 LC88FC3H0A ■ Power-on Reset (POR) Characteristics at Ta=40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Specification Parameter Por release voltage Symbol Pin/Remarks Conditions Select from option. (Note 8-1) PORRL Detction voltage POUKS unknown state See Fig 10. (Note 8-2) Power supply rise time Power supply rise time from 0V to 1.6V. PORIS Option selected voltage 2.57V 2.47 2.57 2.72 2.87V 2.77 2.87 3.02 0.7 0.95 min typ max 100 unit V ms Note8-1 : The POR release level can be selected out of 2 levels only when the LVD reset function is disabled. Note8-2 : POR is in an unknown state before transistors start operation. ■ Low Voltage Detection Reset (LVD) Characteristics at Ta=40 to +85C, VSS1=VSS2=VSS3=VSS4=0V Specification Parameter Symbol LVD reset voltage (Note 9-1) LVDET LVD hysteresis width LVHYS Detection LVUKS voltage unknown state Low voltage TLVDW detection minimum width (Replay sensitivity) Pin/Remarks Conditions Select from option. (Note 9-2) See Fig 11. Option selected voltage min typ max unit 2.81V 2.71 2.81 2.96 V 2.81V 60 See Fig 11. (Note 9-3) 0.7 mV 0.95 V LVDET-0.5V See Fig 12. 0.2 ms Note9-1 : LVD reset voltage specification values do not include hysteresis voltage. Note9-2 : LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note9-3 : LVD is in an unknown state before transistors start operation. www.onsemi.com 41 LC88FC3H0A ■ Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins : - Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible. - Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1F or larger. - The VDD1 and VSS1 traces must be thicker than the other traces. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ ■ Power Pin Treatment Conditions 2 (VDD2, 3, 4 and VSS2, 3, 4) Connect capacitors that meet the following condition between the VDD2, 3, 4 and VSS2, 3, 4 pins : - Connect among the VDD2, 3, 4 and VSS2, 3, 4 pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible. - The capacitance of C3 should be approximately 0.1F or larger. - The VDD2, 3, 4 and VSS2, 3, 4 traces must be thicker than the other traces. L3 VSS2,3, 4 C3 VDD2,3, 4 L3’ www.onsemi.com 42 LC88FC3H0A ■ Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our Company -designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. ■ Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Frequency 10 MHz Oscillation Stabilization Time typ max [ms] [ms] C3 [pF] C4 [pF] Rf [] Rd2 [] Operating Voltage Range [V] CSTCE10M0G52-R0 (10) (10) OPEN 680 2.2 to 2.6 0.02 0.2 C1, C2 integrated type CSTLS10M0G53-B0 (15) (15) OPEN 680 2.2 to 3.6 0.02 0.2 C1, C2 integrated type Circuit Constant Vendor Name Resonator MURATA Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) ■ Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our Company -designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. ■ Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Circuit Constant Nominal Frequency Vendor Name Resonator 32.768 kHz EPSON TOYOCOM MC-306 Operating Voltage Range [V] C3 [pF] C4 [pF] Rf2 [] Rd2 [] 10 10 Open 330K Oscillation Stabilization Time typ max [s] [s] 2.2 to 3.6 1.0 3.0 Remarks CL=7.0pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note : The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. CF2 CF1 Rf1 C1 XT1 XT2 Rf2 Rd1 C2 C3 Rd2 C4 CF X’tal Figure 1. CF oscillator circuit Figure 2. XT Oscillator Circuit 0.5VDD Figure 3. AC Timing Measurement Point www.onsemi.com 43 LC88FC3H0A VDD Operating VDD lower limit 0V Power Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Reset Unpredictable Initialization instruction execution User instruction execution Reset Time and Oscillation Stabilization Time HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 State HOLD HALT Instruction execution HOLD Release and Oscillation Stabilization Time Figure 4. Oscillation Stabilization Time Timing Charts www.onsemi.com 44 LC88FC3H0A VDD Note : Reset signal must be present when power supply rises. Determine the value of CRES and RRES so that the reset signal is present for 10 s after the supply voltage gets stabilized. RRES RES CRES Figure 5. Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 DO8 DOx Data transfer period (SIO0 and SIO1 only) tSCK SIOCLK: tSCKL tSCKH tsDI thDI DATAIN: DATAOUT: Data transfer period (SIO0 and SIO1 only) SIOCLK: tSCKL tSCKHA thDI tsDI DATAIN: tdDO DATAOUT: * Remarks: DIx and DOx denote the last bits communicated; x=0 to 32768 Figure 6. Serial I/O Waveforms www.onsemi.com 45 LC88FC3H0A tPIL tPIH Figure 7. Pulse Input Timing Signal Waveform P SDA S Sr P tBUF tHD;STA tR tHD;STA tF tsp SCK tLOW tHIGH tHD;DAT tSU;DAT tSU;STA tSU;STO S : Start condition P : Stop condition Sir : Restart condition Figure 8. I2C Timing 1k PC2/FILT + 2.2F - Cfs VSS1 Cfs=OPEN Figure 9. Recommended FILT Circuit * Take at least 50ms to oscillation to stabilize after PLL is started. www.onsemi.com 46 LC88FC3H0A (a) POR release voltage (PORRL) (b) VDD Reset period Reset period 100μs or longer Unknown-state (POUKS) RES# Figure 10. Waveform observed when only POR is used (LVD not used) (RESET pin : Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Unknown-state (LVUKS) RES# Figure 11. Waveform observed when both POR and LVD functions are used (RESET pin : Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. www.onsemi.com 47 LC88FC3H0A VDD LVD release voltage LVD reset voltage LVDET-0.5V TLVDW VSS Figure 12. Low voltage detection minimum width (Example of momentary power loss / Voltage variation waveform) ORDERING INFORMATION Device LC88FC3H0AUTJ-2H Package Shipping (Qty / Packing) TQFP 100, 14x14 (Pb-Free / Halogen Free) 900 / Tray JEDEC ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 48