TI1 MM74C910N 256-bit tri-state random access read/write memory Datasheet

MM54C910,MM74C910
MM54C910 MM74C910 256-Bit TRI-STATE Random Access Read/Write Memory
Literature Number: SNOS343A
MM54C910/MM74C910 256 Bit TRI-STATEÉ
Random Access Read/Write Memory
General Description
Outputs are in the TRI-STATE (Hi-Z) condition when the
device is writing or disabled.
Features
Y
Y
Y
Y
Y
Y
Y
Supply voltage range
High noise immunity
TTL compatible fan out
Input address register
Low power consumption
3.0V to 5.5V
0.45VCC (typ.)
1 TTL load
250 nW/package (typ.)
(chip enabled or disabled)
250 ns (typ.) at 5.0V
e
Y
Fast access time
TRI-STATE outputs
High voltage inputs
et
The MM54C910/MM74C910 is a 64 word by 4-bit random
access memory. Inputs consist of six address lines, four
data input lines, a WE, and a ME line. The six address lines
are internally decoded to select one of the 64 word locations. An internal address register latches the address information on the positive to negative transition of ME. The
TRI-STATE outputs allow for easy memory expansion.
Address Operation: Address inputs must be stable (tSA)
prior to the positive to negative transition of ME, and (tHA)
after the positive to negative transition of ME. The address
register holds the information and stable address inputs are
not needed at any other time.
Write Operation: Data is written into memory at the selected address if WE goes low while ME is low. WE must be
held low for tWE and data must remain stable tHD after WE
returns high.
Read Operation: Data is nondestructively read from a
memory location by an address operation with WE held
high.
bs
ol
Logic Diagrams
O
Input Protection
TL/F/5914 – 2
TL/F/5914 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/5914
RRD-B30M105/Printed in U. S. A.
MM54C910/MM74C910 256 Bit TRI-STATE Random Access Read/Write Memory
September 1989
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Output Pin
Supply Voltage (VCC)
MM54C910
MM74C910
Temperature (TA)
MM54C910
MM74C910
b 0.3V to VCC a 0.3V
Voltage at Any Input Pin
Power Dissipation
Dual-In-Line
Small Outline
Operating VCC Range
b 0.3V to a 15V
700 mW
500 mW
Min
Max
Units
4.5
4.75
5.5
5.25
V
V
b 55
b 40
a 125
a 85
§C
§C
3.0V to 5.5V
1.5V to 5.5V
6.0V
Standby VCC Range
Absolute Maximum (VCC)
Lead Temperature (TL)
(Soldering, 10 sec.)
260§ C
DC Electrical Characteristics
Min/Max limits apply accross the temperature and power supply range indicated
Parameter
Conditions
Logical ‘‘1’’ Input Voltage
Full Range
VIN(0)
Logical ‘‘0’’ Input Voltage
Full Range
IIN(1)
Logical ‘‘1’’ Input Current
VIN e 15V
VIN e 5V
IIN(0)
Logical ‘‘0’’ Input Current
VIN e 0V
VOUT(1)
Logical ‘‘1’’ Output Voltage
IO e b150 mA
IO e b400 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
IO e 1.6 mA
IOZ
Output Current in High
Impedance State
VO e 5V
VO e 0V
Supply Current
VCC e 5V
Typ
Max
Units
VCC b 1.5
V
0.8
V
2.0
1.0
mA
mA
et
0.005
0.005
b 1.0
b 0.005
mA
VCC b 0.5
2.4
V
V
0.4
V
0.005
b 0.005
1.0
mA
mA
5.0
300
mA
bs
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ICC
Min
e
Symbol
VIN(1)
b 1.0
AC Electrical Characteristics* TA e 25§ C, VCC e 5.0V, CL e 50 pF
Symbol
tACC
tpd
tSA
tHA
tME
tME
Parameter
Min
Max
250
500
ns
Propagation Delay from ME
180
360
ns
Units
Address Input Set-Up Time
140
70
ns
Address Input Hold Time
20
10
ns
Memory Enable Pulse Width
200
100
ns
Memory Enable Pulse Width
400
200
ns
15
ns
Data Input Set-Up Time
0
tHD
Data Input Hold Time
30
tWE
Write Enable Pulse Width
140
t1H, t0H
Delay to TRI-STATE (Note 4)
100
CIN
Input Capacity
Any Input (Note 2)
5.0
pF
COUT
Output Capacity
Any Output (Note 2)
9.0
pF
CPD
Power Dissipation Capacity
(Note 3)
350
pF
O
tSD
Typ
Access Time from Address
70
ns
ns
200
ns
CAPACITANCE
2
AC Electrical Characteristics* (Continued)TA e 25§ C, VCC e 5.0V, CL e 50 pF
Symbol
Parameter
MM54C910
TA e b55§ C to a 125§ C
VCC e 4.5V to 5.5V
Min
MM74C910
TA e b40§ C to a 85§ C
VCC e 4.75V to 5.25V
Max
Min
Units
Max
tACC
Access Time from Address
860
700
ns
tpd1, tpd0
Propagation Delay from ME
660
540
ns
tSA
Address Input Set-Up Time
200
160
ns
tHA
Address Input Hold Time
20
20
ns
tME
Memory Enable Pulse Width
280
260
ns
tME
Memory Enable Pulse Width
750
600
ns
tSD
Data Input Set-Up Time
0
0
ns
tHD
Data Input Hold Time
50
50
ns
tWE
Write Enable Pulse Width
200
t1H, t0H
Delay to TRI-STATE (Note 4)
180
ns
200
e
200
*AC Parameters are guaranteed by DC correlated testing.
ns
Note 2: Capacitance is guaranteed by periodic testing.
et
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 3: CPD determines the no load AC power consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
Note 4: See AC test circuits for t1H, t0H.
Typical Performance Characteristics
ME
WE
Operation
bs
ol
Typical Access Time vs
Ambient Temperature
Truth Table
L
L
H
H
L
H
L
H
Write
Read
Inhibit, Store
Inhibit, Store
Outputs
TRI-STATE
Data
TRI-STATE
TRI-STATE
TL/F/5914 – 4
AC Test Circuits
O
t0H
t1H
TL/F/5914 – 6
TL/F/5914 – 5
3
AC Test Circuits (Continued)
All Other AC Tests
TL/F/5914 – 7
bs
ol
et
Read Cycle
(See Note 1)
e
Switching Time Waveforms
TL/F/5914 – 8
O
Write Cycle
(See Note 1)
TL/F/5914 – 9
4
Switching Time Waveforms (Continued)
e
Read Modify Write Cycle
(See Note 1)
t1H
bs
ol
t0H
et
TL/F/5914 – 10
TL/F/5914 – 12
TL/F/5914 – 11
Note 1: MEMORY ENABLE must be brought high for tME nanoseconds between every address change.
Note 2: tr e tf e 20 ns for all inputs.
Connection Diagram
O
Dual-In-Line Package
Order Number MM54C910 or MM74C910
TL/F/5914 – 3
Top View
5
6
e
et
bs
ol
O
et
e
Physical Dimensions inches (millimeters)
O
bs
ol
Ceramic Dual-In-Line Package (J)
Order Number MM54C910J or MM74C910J
NS Package Number J18A
7
e
bs
ol
et
Molded Dual-In-Line Package (N)
Order Number MM54C910N or MM74C910N
NS Package Number N18A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
O
MM54C910/MM74C910 256 Bit TRI-STATE Random Access Read/Write Memory
Physical Dimensions inches (millimeters) (Continued)
1. Life support devices or systems are devices or
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
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to the user.
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