TI1 CSD17577Q3AT N-channel nexfet power mosfet Datasheet

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CSD17577Q3A
SLPS515A – AUGUST 2014 – REVISED JANUARY 2016
CSD17577Q3A 30 V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free
RoHS Compliant
Halogen Free
SON 3.3 mm × 3.3 mm Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
30
V
Qg
Gate Charge Total (4.5 V)
12
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
•
Point-of-Load Synchronous Buck in Networking,
Telecom, and Computing Systems
Optimized for Control, and Sync FET Applications
3 Description
This 30 V, 4.0 mΩ, SON 3.3 mm × 3.3 mm
NexFET™ power MOSFET is designed to minimize
resistance in power conversion applications.
Top Icon
4.0
mΩ
1.4
V
QTY
MEDIA
PACKAGE
SHIP
13-Inch Reel
CSD17577Q3AT
250
7-Inch Reel
SON 3.3 × 3.3 mm
Plastic Package
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
30
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
35
Continuous Drain Current (Silicon limited),
TC = 25°C
83
D
ID
S
2
7
D
IDM
4
VGS = 10 V
2500
8
G
mΩ
DEVICE
1
3
nC
5.3
CSD17577Q3A
S
S
2.5
VGS = 4.5 V
Ordering Information(1)
2 Applications
•
UNIT
VDS
6
D
5
D
PD
D
Continuous Drain Current (1)
19
Pulsed Drain Current (2)
239
Power Dissipation(1)
2.5
Power Dissipation, TC = 25°C
53
A
A
W
TJ,
Tstg
Operating Junction Temperature,
Storage Temperature
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 28 A, L = 0.1 mH, RG = 25 Ω
39
mJ
P0093-01
(1) Typical RθJA = 50°C/W on a 1 inch2, 2 oz. Cu pad on a
0.06 inch thick FR4 PCB.
(2) Max RθJC = 3.0°C/W, pulse duration ≤100 μs, duty cycle ≤1%
RDS(on) vs VGS
Gate Charge
10
TC = 25°C, I D = 16A
TC = 125°C, I D = 16A
18
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
20
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 16A
VDS = 15V
9
8
7
6
5
4
3
2
1
0
0
3
6
9
12
15
18
21
Qg - Gate Charge (nC)
24
27
30
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD17577Q3A
SLPS515A – AUGUST 2014 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q3A Package Dimensions ........................................ 8
Q3A Recommended PCB Pattern ............................ 9
Q3A Recommended Stencil Pattern ......................... 9
Q3A Tape and Reel Information ............................. 10
4 Revision History
Changes from Original (August 2014) to Revision A
Page
•
Updated Power Dissipation value in Absolute Maximum Ratings table................................................................................. 1
•
Added Community Resources section .................................................................................................................................. 7
•
Updated Package Dimensions drawing. ................................................................................................................................ 8
•
Updated PCB drawing. .......................................................................................................................................................... 9
•
Updated Stencil Pattern drawing ............................................................................................................................................ 9
2
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5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 24 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-source on-resistance
gfs
Transconductance
30
1.1
V
1.4
1.8
V
VGS = 4.5 V, ID = 10 A
5.3
6.4
mΩ
VGS = 10 V, ID = 16 A
4.0
4.8
mΩ
VDS = 15 V, ID = 16 A
76
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
1780
2310
pF
208
270
pF
Crss
RG
Reverse transfer capacitance
79
103
pF
Series gate resistance
1.4
2.8
Ω
Qg
Gate charge total (4.5 V)
13
17
nC
Qg
Gate charge total (10 V)
27
35
nC
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turn on delay time
tr
Rise time
td(off)
Turn off delay time
tf
Fall time
VGS = 0 V, VDS = 15 V, ƒ = 1 MHz
VDS = 15 V, ID = 16 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 10 V,
IDS = 16 A, RG = 0 Ω
2.8
nC
5.1
nC
2.5
nC
6
nC
4
ns
31
ns
20
ns
4
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 16 A, VGS = 0 V
0.8
VDS= 15 V, IF = 16 A,
di/dt = 300 A/μs
8.2
1
nC
V
8.6
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance (1)
THERMAL METRIC
3.0
°C/W
RθJA
Junction-to-ambient thermal resistance (1) (2)
55
°C/W
(1)
(2)
MIN
TYP
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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GATE
www.ti.com
GATE
Source
Source
Max RθJA = 55°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Max RθJA = 190°C/W
when mounted on a
minimum pad area of 2
oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
100
100
90
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
(TA = 25°C unless otherwise stated)
80
70
60
50
40
30
VGS =10V
VGS =6V
VGS =4.5V
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VDS - Drain-to-Source Voltage (V)
0.7
80
70
60
50
40
30
10
0
0.8
TC = 125°C
TC = 25°C
TC = −55°C
20
0
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
G001
3.5
4
G001
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2
1
0
0
3
6
9
12
15
18
21
Qg - Gate Charge (nC)
ID = 16 A
24
27
10
30
0
3
6
G001
27
30
G001
VDS = 15 V
Figure 4. Gate Charge
Figure 5. Capacitance
2
20
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
1.8
1.6
1.4
1.2
1
0.8
0.6
−75 −50 −25
0
25
50
75 100 125 150 175
TC - Case Temperature (ºC)
G001
TC = 25°C, I D = 16A
TC = 125°C, I D = 16A
18
16
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
1.6
100
VGS = 4.5V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
1.8
1.4
1.2
1
0.8
0.6
−75 −50 −25
0
25
50
75 100 125 150 175
TC - Case Temperature (ºC)
G001
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
1
G001
ID = 16 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
100
100
10
1
0.1
0.1
10us
100us
1ms
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
10ms
DC
1
10
VDS - Drain-to-Source Voltage (V)
100
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
1
G001
Single Pulse,
Max RθJC = 3.0°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
40
35
30
25
20
15
10
5
0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs Temperature
6
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6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
3.1
2.9
B
A
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
TYP
3.1
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
4X
0.52
0.32
0.565±0.1
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
4
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
4X
0.55
0.25
8X
4X 1.45
2X
NOTE 4
0.35
0.25
0.1
0.05
C B
C
A
4222499/A 12/2015
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized features are supplier options and may not be on the package.
5. All dimensions do not include mold flash or protrusions.
8
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SLPS515A – AUGUST 2014 – REVISED JANUARY 2016
7.2 Q3A Recommended PCB Pattern
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
METAL UNDER
SOLDER MASK
(0.245)
( 0.2) VIA
TYP
(0.905)
TYP
(1.55)
LAND PATTERN EXAMPLE
1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment application report, SLUA271.
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Q3A Recommended Stencil Pattern
(0.905)
PKG
8X (0.6)
(0.208)
SOLDER MASK EDGE
1
8
8X (0.3)
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
4X 0.705
METAL
TYP
(3.1)
1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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1.75 ±0.10
7.4 Q3A Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF-reflow compatible
10
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PACKAGE OPTION ADDENDUM
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11-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD17577Q3A
ACTIVE
VSONP
DNH
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
17577
CSD17577Q3AT
ACTIVE
VSONP
DNH
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
17577
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Jan-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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www.ti.com/omap
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www.ti.com/wirelessconnectivity
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