MX25L3237D MX25L3237D SERIAL FLASH SPECIFICATION P/N: PM1393 REV. 1.0, JUL. 16, 2009 1 MX25L3237D Contents FEATURES.................................................................................................................................................. 5 GENERAL DESCRIPTION......................................................................................................................... 7 Table 1. Additional Feature Comparison.................................................................................................................... 7 PIN CONFIGURATIONS ............................................................................................................................. 8 PIN DESCRIPTION...................................................................................................................................... 8 BLOCK DIAGRAM....................................................................................................................................... 9 DATA PROTECTION.................................................................................................................................. 10 Table 2. Protected Area Sizes.................................................................................................................................. 11 Table 3. 4K-bit Secured OTP Definition................................................................................................................... 11 Memory Organization............................................................................................................................... 12 Table 4. Memory Organization................................................................................................................................ 12 DEVICE OPERATION................................................................................................................................ 14 Figure 1. Serial Modes Supported........................................................................................................................... 14 COMMAND DESCRIPTION....................................................................................................................... 15 Table 5. Command Set............................................................................................................................................ 15 (1) Write Enable (WREN)........................................................................................................................................ 17 (2) Write Disable (WRDI)......................................................................................................................................... 17 (3) Read Identification (RDID)................................................................................................................................. 17 (4) Read Status Register (RDSR)............................................................................................................................ 18 (5) Write Status Register (WRSR)........................................................................................................................... 19 Table 6. Protection Modes....................................................................................................................................... 19 (6) Read Data Bytes (READ)................................................................................................................................... 20 (7) Read Data Bytes at Higher Speed (FAST_READ)............................................................................................. 20 (8) 2 x I/O Read Mode (2READ).............................................................................................................................. 20 (9) 4 x I/O Read Mode (4READ).............................................................................................................................. 21 (10) Sector Erase (SE)............................................................................................................................................ 21 (11) Block Erase (BE).............................................................................................................................................. 21 (12) Chip Erase (CE)............................................................................................................................................... 22 (13) Page Program (PP).......................................................................................................................................... 22 (14) 4 x I/O Page Program (4PP)............................................................................................................................ 23 (15) Continuously program mode (CP mode).......................................................................................................... 23 (16) Deep Power-down (DP)................................................................................................................................... 24 (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES).................................................... 24 (18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4).................................................. 24 Table 7. ID Definitions . ........................................................................................................................................... 25 (19) Enter Secured OTP (ENSO)............................................................................................................................ 25 (20) Exit Secured OTP (EXSO)............................................................................................................................... 25 P/N: PM1393 REV. 1.0, JUL. 16, 2009 2 MX25L3237D (21) Read Security Register (RDSCUR).................................................................................................................. 25 Table 8. Security Register Definition........................................................................................................................ 26 (22) Write Security Register (WRSCUR)................................................................................................................. 26 POWER-ON STATE................................................................................................................................... 27 ELECTRICAL SPECIFICATIONS.............................................................................................................. 28 ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 28 Figure 2.Maximum Negative Overshoot Waveform................................................................................................. 28 CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 28 Figure 3. Maximum Positive Overshoot Waveform.................................................................................................. 28 Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 29 Figure 5. OUTPUT LOADING................................................................................................................................. 29 Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade) ......................................... 30 Table 10. DC VOLTAGE CHARACTERISTICS ...................................................................................................... 31 Table 11. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ...... 32 Timing Analysis........................................................................................................................................ 33 Figure 6. Serial Input Timing.................................................................................................................................... 33 Figure 7. Output Timing........................................................................................................................................... 33 Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1........................................................ 34 Figure 9. Write Enable (WREN) Sequence (Command 06).................................................................................... 34 Figure 10. Write Disable (WRDI) Sequence (Command 04)................................................................................... 34 Figure 11. Read Identification (RDID) Sequence (Command 9F)........................................................................... 35 Figure 12. Read Status Register (RDSR) Sequence (Command 05)...................................................................... 35 Figure 13. Write Status Register (WRSR) Sequence (Command 01).................................................................... 35 Figure 14. Read Data Bytes (READ) Sequence (Command 03)............................................................................ 36 Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)........................................................ 36 Figure 16. 2 x I/O Read Mode Sequence (Command BB)...................................................................................... 37 Figure 17. 4 x I/O Read Mode Sequence (Command EB)...................................................................................... 37 Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB).................................................. 38 Figure 19. Page Program (PP) Sequence (Command 02)..................................................................................... 39 Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)....................................................................... 39 Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)........................ 40 Figure 22. Sector Erase (SE) Sequence (Command 20)....................................................................................... 40 Figure 23. Block Erase (BE) Sequence (Command D8)........................................................................................ 40 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)................................................................................ 41 Figure 25. Deep Power-down (DP) Sequence (Command B9).............................................................................. 41 Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)... 41 Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)..................................................... 42 Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)............... 42 Figure 29. Power-up Timing..................................................................................................................................... 43 P/N: PM1393 REV. 1.0, JUL. 16, 2009 3 MX25L3237D Table 12. Power-Up Timing .................................................................................................................................... 43 INITIAL DELIVERY STATE...................................................................................................................................... 43 RECOMMENDED OPERATING CONDITIONS......................................................................................... 44 ERASE AND PROGRAMMING PERFORMANCE.................................................................................... 45 Data Retention......................................................................................................................................................... 45 LATCH-UP CHARACTERISTICS.............................................................................................................. 45 ORDERING INFORMATION...................................................................................................................... 46 PART NAME DESCRIPTION..................................................................................................................... 47 PACKAGE INFORMATION........................................................................................................................ 48 REVISION HISTORY ................................................................................................................................ 50 P/N: PM1393 REV. 1.0, JUL. 16, 2009 4 MX25L3237D 32M-BIT [x 1/x 2/x4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure or 8,388,608 x 4 bits (four I/O read mode) structure • 1024 Equal Sectors with 4K byte each (32Mb) - Any Sector can be erased individually • 64 Equal Blocks with 64K byte each (32Mb) - Any Block can be erased individually • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations - VI/O 1.65V to 3.6V for Input/Output • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read (VI/O=2.7V~3.6V) - 1 I/O: 86MHz with 8 dummy cycles - 2 I/O: 75MHz with 4 dummy cycles - 4 I/O: 75MHz with 6 dummy cycles - Fast read (VI/O=1.65V~2.7V) - 1 I/O: 40MHz with 8 dummy cycles - 2 I/O: 33MHz with 4 dummy cycles - 4 I/O: 33MHz with 6 dummy cycles - When VI/O > 2.7V - Fast access time: 86MHz serial clock - Serial clock of four I/O read mode: 75MHz, which is equivalent to 300MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 9us (typical) - Continuously program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector); 0.7s(typ.) /block (64K-byte per block); 25s(typ.) /chip • Low Power Consumption - Low active read current: 25mA(max.) at 86MHz, and 10mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (max.) • Typical 100,000 erase/program cycles • 20 years of data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4K bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm P/N: PM1393 REV. 1.0, JUL. 16, 2009 5 MX25L3237D - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 16-pin SOP (300mil) - 8-land WSON (6 x 5mm) - All Pb-free devices are RoHS Compliant P/N: PM1393 REV. 1.0, JUL. 16, 2009 6 MX25L3237D GENERAL DESCRIPTION MX25L3237D is 32,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two or four I/O read mode, the structure becomes 16,777,216 bits x 2 or 8,388,608 bits x 4. The MX25L3237D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25L3237D provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current. The MX25L3237D utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Additional Feature Comparison Additional Features Part Name MX25L3237D Protection and Security Flexible Block 4K-bit secured Protection OTP (BP0-BP3) V V Read Performance Identifier 2 I/O Read 4 I/O Read RES (command: AB hex) V V 5E (hex) P/N: PM1393 REMS/2/4 RDID (command: (command: 90/EF/DF hex) 9F hex) C2 5E (hex) C2 5E 16 (hex) (if ADD=0) REV. 1.0, JUL. 16, 2009 7 MX25L3237D PIN CONFIGURATIONS PIN DESCRIPTION 16-PIN SOP (300mil) NC/SIO3 VCC VI/O NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 SYMBOL 16 15 14 13 12 11 10 9 CS# SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 4 V I/O VCC SCLK SI/SIO0 P/N: PM1393 Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) SCLK 8-LAND WSON (6x5mm) DESCRIPTION Clock Input WP#/SIO2 Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) NC/SIO3 NC pin (Not connect) or Serial Data Input & Output (for 4xI/O read mode) VCC + 3.0V Power Supply VI/O 1.65V to 3.6V for Input/Output GND Ground REV. 1.0, JUL. 16, 2009 8 MX25L3237D BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 NC/SIO3 SCLK Mode Logic State Machine Sense Amplifier HV Generator Clock Generator Output Buffer SO/SIO1 P/N: PM1393 REV. 1.0, JUL. 16, 2009 9 MX25L3237D DATA PROTECTION The MX25L3237D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). • Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O read mode, the feature of HPM will be disabled. P/N: PM1393 REV. 1.0, JUL. 16, 2009 10 MX25L3237D Table 2. Protected Area Sizes BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status bit BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 32Mb 0 (none) 1 (1block, block 63th) 2 (2blocks, block 62th-63th) 3 (4blocks, block 60th-63th) 4 (8blocks, block 56th-63th) 5 (16blocks, block 48th-63th) 6 (32blocks, block 32th-63th) 7 (64blocks, all) 8 (64blocks, all) 9 (32blocks, block 0th-31th) 10 (48blocks, block 0th-47th) 11 (56blocks, block 0th-55th) 12 (60blocks, block 0th-59th) 13 (62blocks, block 0th-61th) 14 (63blocks, block 0th-62th) 15 (64blocks, all) II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 4K-bit secured OTP definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit definition and table of "4K-bit secured OTP definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. In 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1393 Customer Lock Determined by customer REV. 1.0, JUL. 16, 2009 11 MX25L3237D Memory Organization Table 4. Memory Organization Block 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Sector 1023 : 1008 1007 : 992 991 : 976 975 : 960 959 : 944 943 : 928 927 : 912 911 : 896 895 : 880 879 : 864 863 : 848 847 : 832 831 : 816 815 : 800 799 : 784 783 : 768 Block Address Range 3FF000h 3FFFFFh : : 3F0000h 3F0FFFh 3EF000h 3EFFFFh : : 3E0000h 3E0FFFh 3DF000h 3DFFFFh : : 3D0000h 3D0FFFh 3CF000h 3CFFFFh : : 3C0000h 3C0FFFh 3BF000h 3BFFFFh : : 3B0000h 3B0FFFh 3AF000h 3AFFFFh : : 3A0000h 3A0FFFh 39F000h 39FFFFh : : 390000h 390FFFh 38F000h 38FFFFh : : 380000h 380FFFh 37F000h 37FFFFh : : 370000h 370FFFh 36F000h 36FFFFh : : 360000h 360FFFh 35F000h 35FFFFh : : 350000h 350FFFh 34F000h 34FFFFh : : 340000h 340FFFh 33F000h 33FFFFh : : 330000h 330FFFh 32F000h 32FFFFh : : 320000h 320FFFh 31F000h 31FFFFh : : 310000h 310FFFh 30F000h 30FFFFh : : 300000h 300FFFh 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 P/N: PM1393 Sector 767 : 752 751 : 736 735 : 720 719 : 704 703 : 688 687 : 672 671 : 656 655 : 640 639 : 624 623 : 608 607 : 592 591 : 576 575 : 560 559 : 544 543 : 528 527 : 512 Address Range 2FF000h 2FFFFFh : : 2F0000h 2F0FFFh 2EF000h 2EFFFFh : : 2E0000h 2E0FFFh 2DF000h 2DFFFFh : : 2D0000h 2D0FFFh 2CF000h 2CFFFFh : : 2C0000h 2C0FFFh 2BF000h 2BFFFFh : : 2B0000h 2B0FFFh 2AF000h 2AFFFFh : : 2A0000h 2A0FFFh 29F000h 29FFFFh : : 290000h 290FFFh 28F000h 28FFFFh : : 280000h 280FFFh 27F000h 27FFFFh : : 270000h 270FFFh 26F000h 26FFFFh : : 260000h 260FFFh 25F000h 25FFFFh : : 250000h 250FFFh 24F000h 24FFFFh : : 240000h 240FFFh 23F000h 23FFFFh : : 230000h 230FFFh 22F000h 22FFFFh : : 220000h 220FFFh 21F000h 21FFFFh : : 210000h 210FFFh 20F000h 20FFFFh : : 200000h 200FFFh REV. 1.0, JUL. 16, 2009 12 MX25L3237D Block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Sector 511 : 496 495 : 480 479 : 464 463 : 448 447 : 432 431 : 416 415 : 400 399 : 384 383 : 368 367 : 352 351 : 336 335 : 320 319 : 304 303 : 288 287 : 272 271 : 256 255 : 240 Block Address Range 1FF000h 1FFFFFh : : 1F0000h 1F0FFFh 1EF000h 1EFFFFh : : 1E0000h 1E0FFFh 1DF000h 1DFFFFh : : 1D0000h 1D0FFFh 1CF000h 1CFFFFh : : 1C0000h 1C0FFFh 1BF000h 1BFFFFh : : 1B0000h 1B0FFFh 1AF000h 1AFFFFh : : 1A0000h 1A0FFFh 19F000h 19FFFFh : : 190000h 190FFFh 18F000h 18FFFFh : : 180000h 180FFFh 17F000h 17FFFFh : : 170000h 170FFFh 16F000h 16FFFFh : : 160000h 160FFFh 15F000h 15FFFFh : : 150000h 150FFFh 14F000h 14FFFFh : : 140000h 140FFFh 13F000h 13FFFFh : : 130000h 130FFFh 12F000h 12FFFFh : : 120000h 120FFFh 11F000h 11FFFFh : : 110000h 110FFFh 10F000h 10FFFFh : : 100000h 100FFFh 0FF000h 0FFFFFh : : 0F0000h 0F0FFFh 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P/N: PM1393 Sector 239 : 224 223 : 208 207 : 192 191 : 176 175 : 160 159 : 144 143 : 128 127 : 112 111 : 96 95 : 80 79 : 64 63 : 48 47 : 32 31 : 16 15 : 4 3 2 1 0 Address Range 0EF000h 0EFFFFh : : 0E0000h 0E0FFFh 0DF000h 0DFFFFh : : 0D0000h 0D0FFFh 0CF000h 0CFFFFh : : 0C0000h 0C0FFFh 0BF000h 0BFFFFh : : 0B0000h 0B0FFFh 0AF000h 0AFFFFh : : 0A0000h 0A0FFFh 09F000h 09FFFFh : : 090000h 090FFFh 08F000h 08FFFFh : : 080000h 080FFFh 07F000h 07FFFFh : : 070000h 070FFFh 06F000h 06FFFFh : : 060000h 060FFFh 05F000h 05FFFFh : : 050000h 050FFFh 04F000h 04FFFFh : : 040000h 040FFFh 03F000h 03FFFFh : : 030000h 030FFFh 02F000h 02FFFFh : : 020000h 020FFFh 01F000h 01FFFFh : : 010000h 010FFFh 00F000h 00FFFFh : : 004000h 004FFFh 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh REV. 1.0, JUL. 16, 2009 13 MX25L3237D DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS, REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1393 REV. 1.0, JUL. 16, 2009 14 MX25L3237D COMMAND DESCRIPTION Table 5. Command Set COMMAND (byte) WREN (write enable) WRDI (write disable) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action 06 (hex) 04 (hex) RDID (read RDSR (read identification) status register) 9F (hex) 05 (hex) WRSR (write status register) 01 (hex) Values sets the (WEL) resets the outputs JEDEC to read out the to write new write enable (WEL) write ID: 1-byte values of the values to the latch bit enable latch bit Manufacturer status register status register ID & 2-byte Device ID READ (read data) FAST READ (fast read data) 03 (hex) AD1 (A23-A16) AD2 (A15-A8) AD3 (A7-A0) 0B (hex) AD1 AD2 AD3 Dummy n bytes read out until CS# goes high n bytes read out until CS# goes high 2READ (2 x I/O COMMAND 4READ (4 x I/O 4PP (quad SE (sector BE (block PP (Page read command) CE (chip erase) (byte) read command) page program) erase) erase) program) Note1 1st byte BB (hex) EB (hex) 38 (hex) 20 (hex) D8 (hex) 60 or C7 (hex) 02 (hex) ADD(4) & 2nd byte ADD(2) AD1 AD1 AD1 AD1 Dummy(4) ADD(2) & 3rd byte Dummy(4) AD2 AD2 AD2 Dummy(2) 4th byte AD3 AD3 AD3 5th byte n bytes read n bytes read quad input to to erase the to erase the to erase whole to program the out by 2 x I/O out by 4 x I/O program the selected sector selected block chip selected page until CS# goes until CS# goes selected page high high Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action AD (hex) AD1 AD2 AD3 B9 (hex) AB (hex) REMS (read REMS2 (read RES (read electronic ID for 2x I/O electronic ID) manufacturer & mode) device ID) AB (hex) 90 (hex) EF (hex) x x x x x x x ADD (Note 2) ADD (Note 2) continously program whole chip, the address automatically increases enters deep power down mode release from deep power down mode to read out output the output the 1-byte Device Manufacturer Manufacturer ID ID & Device ID ID & Device ID CP DP (Deep (Continuously power down) program mode) RDP (Release from deep power down) P/N: PM1393 REMS4 (read ID for 4x I/O mode) DF (hex) x x ADD (Note 2) output the Manufacturer ID & device ID REV. 1.0, JUL. 16, 2009 15 MX25L3237D COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action ENSO (enter secured OTP) EXSO (exit secured OTP) B1 (hex) C1 (hex) to enter the 4Kto exit the 4Kbit Secured OTP bit Secured OTP mode mode RDSCUR (read WRSCUR (write ESRY (enable SO DSRY (disable security register) security register) to output RY/BY#) SO to output RY/ BY#) 2B (hex) 2F (hex) 70 (hex) 80 (hex) to read value of security register to set the lockdown bit as "1" (once lockdown, cannot be updated) to enable SO to output RY/BY# during CP mode to disable SO to output RY/BY# during CP mode Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. The MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not allowed to adopt any other code not in the command definition table above becuase it will lead to entering the hidden mode. P/N: PM1393 REV. 1.0, JUL. 16, 2009 16 MX25L3237D (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see Figure 9) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Quad Page Program (4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion - Continuously program mode (CP) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 5E (hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 7 in page 25) The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1393 REV. 1.0, JUL. 16, 2009 17 MX25L3237D (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO (see Figure 12) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP# or is set to "1" to enable Quad SIO2 and SIO3. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 SRWD (status register write protect) bit6 QE (Quad Enable) 1=Quad 1=status enable register write 0=not Quad disable enable bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: Please refer to Table 2 "Protected Area Size". P/N: PM1393 REV. 1.0, JUL. 16, 2009 18 MX25L3237D (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can be set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. (Please refer to Figure 13) The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP is set as 1 during the tW timing, and set as 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 6. Protection Modes Mode Status register condition WP# and SRWD bit status Memory Software Protected Mode (SPM) Status register can be writWP#=1 and SRWD bit=0, or ten in (WEL bit is set to "1") The protected area cannot WP#=0 and SRWD bit=0, or and the SRWD, BP0-BP3 be programmed or erased WP#=1 and SRWD bit=1, bits can be changed Hardware Protected Mode (HPM) The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be programmed or erased Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. P/N: PM1393 REV. 1.0, JUL. 16, 2009 19 MX25L3237D Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O read mode, the feature of HPM will be disabled. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→data out on SO→to end READ operation, CS# can to go high at any time during data out. (please refer to Figure 14) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte address on SI→1-dummy byte (default) address on SI→data out on SO→to end FAST_READ operation, CS# can go high at any time during data out. (please refer to Figure 15) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out (please refer to Figure 16 for 2 x I/O Read Mode Timing Waveform). P/N: PM1393 REV. 1.0, JUL. 16, 2009 20 MX25L3237D While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (9) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK, and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→6 dummy cycles →data out interleave on SIO3, SIO2, SIO1 & SIO0→to end 4READ operation can use CS# to high at any time during data out (please refer to Figure 17 for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→ sending 4 READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (see figure 18 for 4x I/O read enhance performance mode timing waveform). While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (10) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (please refer to Table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (Please refer to Figure 22) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (11) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. P/N: PM1393 REV. 1.0, JUL. 16, 2009 21 MX25L3237D The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI →CS# goes high. (see Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (12) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Figure 24) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP is set as 1 during the tCE timing, and is set as 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". (13) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. (please refer to Figure 19) CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1393 REV. 1.0, JUL. 16, 2009 22 MX25L3237D (14) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (please refer to Figure 20) (15) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# high to low→ sending CP instruction code→ 3-byte address on SI→ Data Byte on SI→CS# goes high to low→ sending CP instruction......→ last desired byte programmed or sending Write Disable (WRDI) instruction to end CP mode→ sending RDSR instruction to verify if CP mode ends. (please refer to Figure 21 of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/ DSRY command are not accepted unless the completion of CP mode. P/N: PM1393 REV. 1.0, JUL. 16, 2009 23 MX25L3237D (16) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (please refer to Figure 25) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 26,27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. (18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. P/N: PM1393 REV. 1.0, JUL. 16, 2009 24 MX25L3237D The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed by two dummy bytes and one bytes address (A7~A0). After that, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 31. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 7. ID Definitions Command Type RDID Command (JEDEC) MX25L3237D memory type 5E electronic ID 5E device ID 5E manufacturer ID C2 RES Command REMS/REMS2/REMS4/ Command manufacturer ID C2 memory density 16 (19) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may be used to store unique serial number for system identifier. After entering the Secured OTP mode, user can follow the standard procedure of reading or programming to read out the data or update data. The Secured OTP data cannot be updated again once it is lock down. The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP mode→CS# goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region. Once security OTP is lock down, only read related commands are valid. (20) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. (21) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) continuously. The sequence of issuing RDSCUR instruction is: CS# goes low→ send ing RDSCUR instruction → Security Register data out on SO→ CS# goes high. P/N: PM1393 REV. 1.0, JUL. 16, 2009 25 MX25L3237D The definition of the Security Register bits is as following: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex-factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, array access is not allowed. Continuously Program Mode(CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. Table 8. Security Register Definition bit7 bit6 bit5 X X X bit4 Continuously Program mode (CP mode) reserved reserved reserved 0=normal program mode 1=CP mode (default=0) volatile bit volatile bit volatile bit volatile bit bit3 bit2 X X LDSO Secured OTP (indicate if indicate bit lock-down) 0=not lockdown 0=non-factory 1=lock-down lock (cannot 1=factory lock program/ erase OTP) reserved reserved volatile bit volatile bit bit1 bit0 non-volatile bit non-volatile bit (22) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is: CS# goes low→sending WRSCUR instruction→CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1393 REV. 1.0, JUL. 16, 2009 26 MX25L3237D POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) P/N: PM1393 REV. 1.0, JUL. 16, 2009 27 MX25L3237D ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE -40°C to 85°C for Industrial grade Ambient Operating Temperature Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3. Figure 3. Maximum Positive Overshoot Waveform Figure 2.Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V 20ns Vcc 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT MIN. TYP MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V P/N: PM1393 CONDITIONS REV. 1.0, JUL. 16, 2009 28 MX25L3237D Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level Output timing referance level VI/O AC Measurement Level 0 0.5VI/O Note: Input pulse rise and fall time are <5ns Figure 5. OUTPUT LOADING VI/O R1 DEVICE UNDER TEST OUT CL R2 CL=30pF Including jig capacitance R1=R2=25K ohm P/N: PM1393 REV. 1.0, JUL. 16, 2009 29 MX25L3237D Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade) SYMBOL PARAMETER NOTES MIN. TYP MAX. UNITS TEST CONDITIONS ILI Input Load Current 1 ±2 uA VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ±2 uA VCC = VCC Max VIN = VCC or GND ISB1 VCC Standby Current 1 20 uA VIN = VCC or GND CS# = VCC ISB2 Deep Power-down Current 20 uA VIN = VCC or GND CS# = VCC ICC1 VCC Read 25 mA f=104MHz fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 20 mA fT=75MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 10 mA f=33MHz SCLK=0.1VCC/0.9VCC, SO=Open 20 mA Program in Progress CS# = VCC 20 mA Program status register in progress CS#=VCC 1 ICC2 VCC Program Current (PP) 1 ICC3 VCC Write Status Register (WRSR) Current ICC4 VCC Sector Erase Current (SE) 1 20 mA Erase in Progress CS#=VCC ICC5 VCC Chip Erase Current (CE) 1 20 mA Erase in Progress CS#=VCC VIL Input Low Voltage -0.5 0.3VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage 0.4 V IOL = 1.6mA VOH Output High Voltage V IOH = -100uA VCC-0.2 Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. P/N: PM1393 REV. 1.0, JUL. 16, 2009 30 MX25L3237D Table 10. DC VOLTAGE CHARACTERISTICS SYMBOL PARAMETER VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage VOH Output High Voltage VCC=VI/O=2.7~3.6V MIN. MAX. -0.5 0.8 2.0 VI/O+0.3 0.45 VI/O-0.4 VI/O=1.65~2.7V MIN. MAX. -0.1 0.25VI/O VI/O-0.4 VI/O+0.4 0.2VI/O 0.8VI/O P/N: PM1393 UNITS V V V V TEST CONDITIONS VCC=VCCmin VI/O=VI/Omax IOL = -100uA IOH = -100uA VCC=VCCmin VI/O=VI/Omax REV. 1.0, JUL. 16, 2009 31 MX25L3237D Table 11. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol fSCLK fRSCLK fTSCLK Alt. Parameter fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR fR Clock Frequency for READ instructions fT Clock Frequency for 2READ instructions Min. Typ. D.C. fQ Clock Frequency for 4READ instructions fPSCLK fP tCH(1) tCLH tCL(1) tCLL tCLCH(2) tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL(3) tCSH tSHQZ(2) tDIS tCLQV tV tCLQX tHO tWHSL(4) tSHWL(4) tDP(2) tRES1(2) tRES2(2) Clock Frequency for 4PP operation Fast Read, 3V V I/O Clock High Time Fast Read, 1.8V V I/O Normal Read Fast Read, 3V V I/O Fast Read, 1.8V V I/O Clock Low Time Normal Read Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write/Erase/Program 1.65V-2.7V Output Disable Time 2.7V-3.6V Loading: 30pF/15pF 3.0V-3.6V 1.65V-2.7V Clock Low to Output Valid 2.7V-3.6V Loading: 30pF/15pF 3.0V-3.6V Output Hold Time Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read P/N: PM1393 5.5 10 13 5.5 10 13 0.1 0.1 5 5 2 5 5 5 15 50 0 20 100 Max. 86/40 (Note 6) Unit MHz 33 75/33 (Note 6) 75/33 (Note 6) 20 MHz MHz MHz 10 8.8 MHz ns ns ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us 8.8 us 30/28 10/8 8/6 30/28 10/8 8/6 REV. 1.0, JUL. 16, 2009 32 MX25L3237D Symbol tW tBP tPP tSE tBE tCE Alt. Parameter Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time Min. Typ. 40 9 1.4 60 0.7 25 Max. 100 300 5 300 2 50 Unit ms us ms ms s s Notes: 1. tCH + tCL must be greater than or equal to 1/f (fC or fR) 2. Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. When VI/O<2.7V, tSLCH=25ns, tSHCH=25ns, tSHQZ=20ns (VCC=2.7V~3.6V), tCLQV=26ns, tDVCH=5ns. 6. While VI/O=1.65V~2.7V, fC=40MHz, fT=fQ=33MHz; while VI/O=2.7V~3.6V, fC=86MHz, fT=fQ=75MHz. 7. Test condition is shown as Figure 4, 5. P/N: PM1393 REV. 1.0, JUL. 16, 2009 33 MX25L3237D Timing Analysis Figure 6. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 7. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO tQLQH tQHQL SI ADDR.LSB IN P/N: PM1393 REV. 1.0, JUL. 16, 2009 34 MX25L3237D Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI High-Z SO Figure 9. Write Enable (WREN) Sequence (Command 06) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 04 High-Z SO P/N: PM1393 REV. 1.0, JUL. 16, 2009 35 MX25L3237D Figure 11. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 Device Identification 0 15 14 13 MSB 3 2 1 0 MSB Figure 12. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 13. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI SO Status Register In 01 7 6 5 4 3 2 1 0 MSB High-Z P/N: PM1393 REV. 1.0, JUL. 16, 2009 36 MX25L3237D Figure 14. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command 24-Bit Address 23 22 21 03 SI 3 2 1 0 MSB Data Out 1 High-Z SO 7 6 5 4 3 Data Out 2 2 1 0 7 MSB Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1393 6 5 4 3 2 1 0 7 MSB REV. 1.0, JUL. 16, 2009 37 MX25L3237D Figure 16. 2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 18 19 20 21 22 23 24 25 26 27 SCLK 8 Bit Instruction BB(hex) SI/SIO0 SO/SIO1 4 dummy cycle 12 BIT Address High Impedance Data Output address bit22, bit20, bit18...bit0 dummy data bit6, bit4, bit2...bit0, bit6, bit4.... address bit23, bit21, bit19...bit1 dummy data bit7, bit5, bit3...bit1, bit7, bit5.... Figure 17. 4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK 8 Bit Instruction SI/SIO0 SO/SIO1 WP#/SIO2 NC/SIO3 6 Address cycles 6 dummy cycle Data Output address bit20, bit16..bit0 dummy data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 dummy data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 dummy data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 dummy data bit7 bit3, bit7.... EB(hex) P/N: PM1393 REV. 1.0, JUL. 16, 2009 38 MX25L3237D Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction WP#/SIO2 NC/SIO3 Performance enhance indicator (Note) 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EB(hex) SI/SIO0 SO/SIO1 6 Address cycles CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... SCLK 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output SI/SIO0 address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... SO/SIO1 address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... WP#/SIO2 address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... NC/SIO3 address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... Note: Performance enhance, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling) P/N: PM1393 REV. 1.0, JUL. 16, 2009 39 MX25L3237D Figure 19. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 7 SI 6 5 4 3 2 Data Byte 3 1 0 MSB 7 6 5 4 3 2 Data Byte 256 1 7 0 MSB 6 5 4 3 2 MSB Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Command Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 6 Address cycle 20 16 12 8 4 0 4 0 4 0 4 0 4 0 SO/SIO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 WP#/SIO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 NC/SIO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 SI/SIO0 38 P/N: PM1393 REV. 1.0, JUL. 16, 2009 40 MX25L3237D Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS# 0 1 6 7 8 9 30 31 31 32 0 1 47 48 20 2122 23 24 6 7 8 0 7 0 7 8 SCLK Command SI S0 AD (hex) Valid Command (1) data in Byte 0, Byte1 24-bit address high impedance data in Byte n-1, Byte n 04 (hex) 05 (hex) status (2) Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). (2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes high will return the SO pin to tri-state. (3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended Figure 22. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Figure 23. Block Erase (BE) Sequence (Command D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 D8 2 1 0 MSB Note: BE command is D8(hex). P/N: PM1393 REV. 1.0, JUL. 16, 2009 41 MX25L3237D Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 25. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power-down Mode Stand-by Mode Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI AB tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1393 Stand-by Mode REV. 1.0, JUL. 16, 2009 42 MX25L3237D Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI AB High-Z SO Deep Power-down Mode Stand-by Mode Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO X 7 6 5 4 3 2 1 Device ID 0 7 MSB MSB 6 5 4 3 2 1 7 0 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Instruction is either 90(hex) or EF(hex) or DF(hex). P/N: PM1393 REV. 1.0, JUL. 16, 2009 43 MX25L3237D Figure 29. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 12. Power-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 200 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1393 REV. 1.0, JUL. 16, 2009 44 MX25L3237D RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC VCC(min) GND tSHSL tVR CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB IN MSB IN SI High Impedance SO Figure A. AC Timing at Device Power-Up Symbol tVR Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1393 REV. 1.0, JUL. 16, 2009 45 MX25L3237D ERASE AND PROGRAMMING PERFORMANCE PARAMETER Min. TYP. (1) Max. (2) UNIT Write Status Register Cycle Time 40 100 ms Sector Erase Cycle Time 60 300 ms Block Erase Cycle Time 0.7 2 s Chip Erase Cycle Time 25 50 s Byte Program Time (via page program command) 9 300 us 1.4 5 ms Page Program Cycle Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time is assumed as the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle with 90% confidence level. Data Retention PARAMETER Condition Min. Data retention 55˚C 20 Max. UNIT years LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1393 REV. 1.0, JUL. 16, 2009 46 MX25L3237D ORDERING INFORMATION PART NO. MX25L3237DMI-12G MX25L3237DZNI-12G CLOCK (MHz) 86 86 OPERATING CURRENT MAX. (mA) 25 25 STANDBY CURRENT MAX. (uA) 20 20 P/N: PM1393 TEMPERATURE PACKAGE Remark -40°C~85°C -40°C~85°C 16-SOP 8-WSON (6x5 mm) Pb-free Pb-free REV. 1.0, JUL. 16, 2009 47 MX25L3237D PART NAME DESCRIPTION MX 25 L 3237D M I 12 G OPTION: G: Pb-free SPEED: 12: 86MHz (when VI/O>2.7V ; it will be 40MHz when VI/O<2.7V) TEMPERATURE RANGE: I: Industrial (-40C to 85C) PACKAGE: M: 300mil 16-SOP ZN: WSON (0.8mm package height) DENSITY & MODE: 3237D: 32Mb Serial Flash with VI/O TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1393 REV. 1.0, JUL. 16, 2009 48 MX25L3237D PACKAGE INFORMATION P/N: PM1393 REV. 1.0, JUL. 16, 2009 49 MX25L3237D P/N: PM1393 REV. 1.0, JUL. 16, 2009 50 MX25L3237D REVISION HISTORY Revision No. Description Page Date 0.01 1. VI/O into two parts: VI/O<2.5V and VI/O > 2.5V P5,28,29,30 APR/07/2008 P44,45 0.02 1. Changed tSHSL spec from 30/50ns to 15/50ns P30 JUN/13/2008 2. Add 6x5mm WSON package P6,8,30,45,47 3. Modified DC voltage spec P31 4. VI/O into two parts: VI/O<2.7 and VI/O>2.7 P5,28,29,30,46 5. Changed Fast Read spec from 40MHz to 33MHz for 2 I/O and 4 I/O P5,31 6. Modified Figure 5 (R1/R2) P28 1.0 1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.) P5,4 JUL/15/2009 2. Revised sector erase time spec from 120ms(max.) to 300ms(max.) P31,46 3. Revised block erase time spec from 1s(typ.) to 0.7s(typ.) P31,46 4. Corrected RDID description: memory type ID P17 5. Removed "low Vcc write inhibit" function P5,10,27,43 6. Added 20 years data retention related condition P5,45 7. Revised fSCLK condition P5,29,30,32 8. Revised the condition of tCH/tCL, VI/O and tSHQZ (2) P32 and clarify fSCLK condition 9. Revised PIN CONFIGURATIONS P8 10. Removed "PRELIMINARY" P5 P/N: PM1393 REV. 1.0, JUL. 16, 2009 51 MX25L3237D Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. Copyright© Macronix International Co., Ltd. 2008~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo, MXSMIO, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. 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