Intersil ISL28023FR60Z Precision digital power monitor with margining Datasheet

DATASHEET
Precision Digital Power Monitor with Margining
ISL28023
Features
The ISL28023 is a bidirectional high-side and low-side digital
current sense and voltage monitor with a serial interface. The
device monitors power supply current, voltage and provides
the digital results along with calculated power. The ISL28023
provides tight accuracy of 0.05% for both voltage and current
monitoring. The auxiliary input provides an additional power
monitor function.
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Bus voltage sense range . . . . . . . . . . . . . . . . . . . . . . 0V to 60V
Voltage gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05%
Current gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05%
Internal temperature sensor accuracy . . . . . . . . . . . . +1.0°C
High or low (RTN) side sensing
Bidirectional current sensing
Auxiliary low voltage channel
∆∑ADC, 16-bit native resolution
Programmable averaging modes
Internal 3.3V regulator
Internal temperature sense
Overvoltage/undervoltage and current fault monitoring with
500ns detection delay
• 8-bit voltage output DAC
• I2C/SMBus/PMBus interface that handles 1.2V supply
• 55 I2C slave addresses
The VCC power can either be externally supplied or internally
regulated, which allows the ISL28023 to handle a
common-mode input voltage range from 0V to 60V. The wide
range permits the device to handle telecom, automotive and
industrial applications with minimal external circuitry.
An 8-bit voltage DAC enables a DC/DC converter output
voltage margining. Fault indication includes a Bus Voltage
window and overcurrent fast fault logic indication. A
temperature sensing option includes both internal
temperature sensor and a bias/monitor circuit for external
diode sensing.
Applications
The ISL28023 serial interface is PMBus compatible and
operates down to 1.2V voltage. It draws an average current of
just 800µA and is available in the space saving 24 Ld QFN
4mmx4mm package. The part operates across the full
industrial temperature range from -40°C to +125°C.
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Related Literature
AN1955, “Design Ideas for Intersil Digital Power Monitors”
Data processing servers
DC power distribution
Telecom equipment
Portable communication equipment
DC/DC, AC/DC converters
Many I2C DAC and ADC with alert applications
RSH
Vreg_in
VIN
SMBALERT1
GND
3.3V
Vreg
1µF
A0
A1
Ext_Temp
Place Diode
Near RSH
Phase
ISL85415
VBUS
Lo
AUXP
0.1µF
AUXM
A2
ADC
16-Bit
SCL
I2C
SMBUS
VIN
VINM
SW MUX
GND
VCC,FS,SS
VCC
ISL28023
VINP
Sync,Comp
Vreg_Out
VIN = 4.5V 36V
SDA
PMBus
REG
MAP
BOOT
AUXV
SMBALERT2
R2
FB
8-Bit
DAC
R1
Vmcu
LOAD
VOUT = 0.6 +
(0.6 – DAC OUT)
* R2/R1
GPIO/Int
VIN
MCU
R_pullUp
R3
To SMBAlert1
R_pullUp
En
Temp
Sense
GND
PG
I2CVCC
DAC OUT
SCL
SDA
GPIO
FIGURE 1. APPLICATION DIAGRAM
June 17, 2015
FN8389.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28023
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Error Correction (PEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Device Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global IC Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary and Auxiliary Channel Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMB Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
32
32
35
36
38
42
42
SMBus/I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SMBus, PMBus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
46
46
46
47
Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shunt Resistor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lossless Current Sensing (DCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Trace as a Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
48
49
49
50
51
53
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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June 17, 2015
ISL28023
Block Diagram
GND
DAC_OUT
PRIMARY CH
I2CVCC
INTERNAL
POWER
3.3V
LS
LS
SMBCLK
REG
VREG_IN
{
VCC
DAC (8-BIT)
VREG_OUT
Temp_V
VBUS_S
VBUS
I2C
SM BUS
PM BUS
TEMP
SENSE
SMBDAT
REF
A0
A1
VINP
ADC 16BIT
CM = 0 to 60V
VINM
A2
FIR AND
DIGITAL
LOGIC
16
REG MAP
OSC
SW Mux
AUX CH
AUXP
UV
DAC
EXT_CLK
UV_SET
VBUS_S
CM = 0 to VCC
VBUS_S
AUXM
DIV
DIGITAL FILTER
0, 2, 4, 8µS
VIN_P
AUXV
OV/
TEMP
DAC
VIN_M
{
OC
DAC
CLOCK
OV_TEMP_SET
Temp_V
OC_SET
SMBALERT2
SMBALERT1
ONLY FOR PRI CHL
FIGURE 2. BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VBUS OPTION
(V)
PACKAGE
(RoHS Compliant
PKG.
DWG. #
ISL28023FR12Z
280 23R12Z
12
24 Ld QFN
L24.4x4D
ISL28023FR60Z
280 23R60Z
60
24 Ld QFN
L24.4x4D
ISL28023EVAL1Z
Evaluation Board
ISL28023EVKIT1Z
Evaluation Kit
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28023. For more information on MSL please see techbrief TB363.
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June 17, 2015
ISL28023
Pin Configuration
VBUS
VREG_IN
VINP
VINM
NC
VREG_OUT
ISL28023
(24 LD QFN)
TOP VIEW
24
23
22
21
20
19
NC
1
18 VCC
GND
2
17 I2CVCC
AUXP
3
16 A2
GND
DAC_OUT
6
13 GND
7
8
9
10
11
12
EXT_CLK
14 A0
SMBALERT2
5
SMBALERT1
AUXV
NC
15 A1
SMBDAT
4
SMBCLK
AUXM
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE/DIR
1, 9, 20
NC
N/A
2
GND
Power
3
AUXP
Analog Input
Auxiliary port differential input (plus)
4
AUXM
Analog Input
Auxiliary port differential input (minus)
5
AUXV
Analog Input
Auxiliary port single ended input
6
DAC_OUT
Analog Output
7
SMBCLK
Digital Input
8
SMBDAT
10
SMBALERT1
Digital Output
SMBus Alert1, open-drain output
11
SMBALERT2
Digital Output
CPU interrupt signal: It is used as CPU interrupt signal
12
EXT_CLK
Digital Input
13
GND
Power
14
A0
Digital Input
SMBus/I2C address input
15
A1
Digital Input
SMBus/I2C address input
16
A2
Digital Input
SMBus/I2C address input
17
I2CVCC
Power
I2C level shifter power supply. This pin should be connected to VCC pin if level shifter is not used.
18
VCC
Power
Chip power supply
19
VREG_OUT
Power
Voltage regulator output, proper decoupling capacitor should be connected to this pin
21
VINM
Analog Input
Current sense minus input
22
VINP
Analog Input
Current sense plus input
23
VREG_IN
Power
Voltage regulator input. This pin should be connected to ground in case voltage regulator is not used.
24
VBUS
Power
VBUS voltage sense
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PIN DEFINITION
No connect
Ground
DAC voltage output
SMBus/I2C clock input
Digital Input/Output SMBus/I2C data
4
External ADC clock input
Ground
FN8389.4
June 17, 2015
ISL28023
TABLE 1. DPM PORTFOLIO COMPARISON - ISL28022 vs ISL28023 vs ISL28025
DESCRIPTION
BASIC DIGITAL
POWER MONITOR
FULL FEATURE
DIGITAL POWER MONITOR
DIGITAL POWER MONITOR
IN TINY PACKAGE
PART NUMBER
ISL28022
ISL28023
ISL28025
PACKAGE
MSOP10, QFN16
QFN24
WLCSP-16
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
0V to 60V
Opt 1: 0V to 60V
Opt 2: 0V to 16V
Opt 1: 0V to 60V
Opt 2: 0V to 16V
ADC
16-bit
16-bit
16-bit
25°C Gain Error
0.30%
0.25%
0.25%
Current Measure LSB Step
10µV
2.5µV
2.5µV
25°C Offset
75µV
30µV
30µV
Temperature Range
0V to 60V Input Range
Primary
Differential Shunt Input
X
X
X
Channel
Independent Bus Voltage
X
X
X
LV Aux
Differential Shunt Input
X
Channel
Independent Bus Voltage
X
X
VBus LSB Step
Low Voltage Bus
0.25mV
0.25mV
1mV/0.25mV
1mV/0.25mV
High Voltage Bus
4mV
External Temperature Sensor Input
X
HV Internal Regulator (3.3VOUT)
X
X
2 Outputs
2 Outputs
Fast OC/OV/UV Alert Outputs
Margin DAC
X
Internal Temperature Sensor
X
X
X
X
X
X
55 Addresses
55 Addresses
I2C Level Translators
X
X
PMBus
X
X
User Select Conversion Mode/Sample Rate
X
Peak Min/Max Current Registers
Slave Address Locations
16 Addresses
I2C/SMBus
X
X
X
High Speed (3.4MHz) I2C Mode
X
X
X
External Clock Input
X
X
X
Power Shutdown Mode
X
X
X
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FN8389.4
June 17, 2015
ISL28023
Absolute Maximum Ratings
Thermal Information
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
I2CVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
VBUS (ISL28023FR60), VREG_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63V
VBUS (ISL28023FR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.684V
Common Mode Input Voltage (VINP, VINM). . . . . . . . . . . . . . . . . . . . . . . 63V
Differential Input Voltage (VINP, VINM) . . . . . . . . . . . . . . . . . . . . . . . . . ±63V
AUXV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC-GND
Common Mode Input Voltage (AUXP, AUXM) . . . . . . . . . . . . . . . . . VCC-GND
Differential Input Voltage (AUXP, AUXM) . . . . . . . . . . . . . . . . . . . . .VCC-GND
Input Voltage (Digital Pins) . . . . . . . . . . . . . . . . . GND-0.3 to I2CVCC + 0.3V
Output Voltage (Digital Pins) . . . . . . . . . . . . . . . . GND-0.3 to I2CVCC + 0.3V
Output Current (VREG_OUT, DAC_OUT) . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Open-Drain Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Open-Drain Voltage (SMBALERT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 6kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD-78B) . . . . . . . . . . . . . . . . . ±100mA (at +125°C)
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
24 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . .
38
2.5
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
±81.91
mV
PRIMARY CHANNEL
VSHUNT
VSHUNT Measurement Range (VINP - VINM)
0
Step_shunt
1LSB Step Shunt Voltage
2.5
Vshunt_vos
VSHUNT Offset Voltage
±2.5
±50
µV
Vshunt_TC
VSHUNT Offset Voltage vs Temperature
T = -40°C to +125°C
±0.04
±0.3
µV/°C
VSHUNT Vos vs Common Mode
ISL28023FR60Z
VBUS = 0V to 60V
±0.16
±1.6
µV/V
ISL28023FR12Z
VBUS = 0V to 16.384V
±0.16
±1.6
µV/V
VSHUNT Vos vs Power Supply
VCC = ±10% of VCC nominal
±0.45
VIN Input Leakage Current
VIN = VSHUNT input path selected, OC
detector disabled
15
20
µA
VIN = VSHUNT input path selected, OC
detector enabled
30
40
µA
VIN = VSHUNT input path disabled, OC
detector disabled
0.05
0.1
µA
Vshunt_CMRR
Vshunt_PSRR
Ivin
VBUS
Step_Vbus
Usable Bus Voltage Measurement Range
1LSB Step Bus Voltage
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6
µV
µV/V
ISL28023FR60Z
0
60
V
ISL28023FR12Z
0
16.384
V
ISL28023FR60Z
1
mV
ISL28023FR12Z
0.25
mV
FN8389.4
June 17, 2015
ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
PARAMETER
Vbus_vos
Vbus_TC
Vbus_Vco
Vbus_PSRR
Zin_Vbus
DESCRIPTION
VBUS Offset Voltage
VBUS Offset Voltage vs Temperature
TEST CONDITIONS
MIN
(Note 6)
Input Impedance VBUS
MAX
(Note 6)
UNIT
ISL28023FR60Z
-20
±1
20
mV
ISL28023FR12Z
-5
± 1.5
5
mV
ISL28023FR60Z; T = -40°C to +125°C
±4
±100
µV/°C
ISL28023FR12Z; T = -40°C to +125°C
±4
±100
µV/°C
VBUS Voltage Coefficient
VBUS Vos vs Power Supply
TYP
50
ppm/V
ISL28023FR60Z;
VCC = ± 10% of VCC nominal
±500
µV/V
ISL28023FR12Z
VCC = ± 10% of VCC nominal
±125
µV/V
ISL28023FR60Z
600
kΩ
ISL28023FR12Z
150
kΩ
AUX CHANNEL
Vshunt_aux
VSHUNT Aux Measurement Range
(AuxP - AuxM)
0
±81.91
mV
Step_shunt_aux
1LSB Step Shunt Aux Voltage
2.5
Vshunt_aux_vos
VSHUNT Aux Offset Voltage
±2.5
±50
µV
Vshunt_aux_TC
VSHUNT Aux Offset Voltage vs Temperature T = -40°C to +125°C
±0.01
±0.1
µV/°C
±0.1
±4
µV/V
Vshunt_aux_CMRR VSHUNT Aux Vos vs Common Mode
VBUS = 0V to VCC
Vshunt_aux_PSRR VSHUNT Aux Vos vs Power Supply
VCC = ± 10% of VCC nominal
Zin_aux_in
Vauxv
AUX Input Impedance
µV
±0.45
µV/V
Aux = AUXVshunt input path selected
1
MΩ
Aux = AUXVshunt input path disabled
10
MΩ
Usable AVXV Voltage Measurement Range
0
VCC
V
Step_auxv
1LSB Step AUXV Voltage
100
Vauxv_vos
Vauxv Offset Voltage
±0.3
±4
mV
Vauxv_TC
Vauxv Offset Voltage vs Temperature
T = -40°C to +125°C
±0.2
±22
µV/°C
Vauxv Vos vs Power Supply
VCC = ±10% of VCC nominal
±1
mV/V
Auxv Input Impedance
Input path selected
200
kΩ
Input path disabled
10
MΩ
16
Bits
Vauxv_PSRR
Zin_auxv
µV
ADC PARAMETERS
ADC Resolution
Primary Shunt Voltage Gain Error
±0.05
±0.25
%
±60
ppm/°C
±0.05
±0.2
%
10
±70
ppm/°C
±0.02
±0.25
%
±65
ppm/°C
±0.2
%
±65
ppm/°C
T = -40°C to +125°C
Primary Bus Voltage Gain Error
T = -40°C to +125°C
Aux Shunt Voltage Gain Error
T = -40°C to +125°C
Aux Bus Voltage Gain Error
±0.02
T = -40°C to +125°C
Differential Non-linearity
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7
±1
LSB
FN8389.4
June 17, 2015
ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
PARAMETER
DESCRIPTION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ADC[2:0] = 0h
64
70.4
µs
ADC[2:0] = 1h
128
140.8
µs
ADC[2:0] = 2h
256
281.6
µs
TEST CONDITIONS
ADC TIMING
ts Power-up
ADC Conversion Time Resolution
ADC[2:0] = 3h
512
563.2
µs
ADC[2:0] = 4, 5h
1.024
1.126
ms
ADC[2:0] = 6, 7h
2.048
2.253
ms
125
% of FS
THRESHOLD DETECTORS
Overvoltage (OV) VBUS Threshold Voltage
Range
Vbus_Thres_Rng[2:0] = ALL
25
Overvoltage (OV) VBUS Threshold DAC Step Vbus_Thres_Rng[2:0] = ALL
Size
Undervoltage (UV) VBUS Threshold Voltage Vbus_Thres_Rng[2:0] = ALL
Range
1.56
0
% of FS
100
% of FS
Undervoltage (UV) VBUS Threshold DAC
Step Size
Vbus_Thres_Rng[2:0] = ALL
VBUS Threshold Detector Full-Scale
Settings
ISL28025FI60Z
Vbus_Thres_Rng[2:0] = 0; OT_SEL = 0
48
V
Vbus_Thres_Rng[2:0] = 1; OT_SEL = 0
24
V
Vbus_Thres_Rng[2:0] = 2; OT_SEL = 0
12
V
VBUS Threshold Detector Full-scale
Settings
ISL28025FI12Z
Over-temperature Threshold Detector
Range
1.56
% of FS
Vbus_Thres_Rng[2:0] = 3; OT_SEL = 0
5
V
Vbus_Thres_Rng[2:0] = 4; OT_SEL = 0
3.3
V
Vbus_Thres_Rng[2:0] = 5; OT_SEL = 0
2.5
V
Vbus_Thres_Rng[2:0] = 0; OT_SEL = 0
12
V
Vbus_Thres_Rng[2:0] = 1; OT_SEL = 0
6
V
Vbus_Thres_Rng[2:0] = 2; OT_SEL = 0
3
V
Vbus_Thres_Rng[2:0] = 3; OT_SEL = 0
2.5
V
Vbus_Thres_Rng[2:0] = 4; OT_SEL = 0
0.825
V
Vbus_Thres_Rng[2:0] = 5; OT_SEL = 0
0.625
V
OT_SEL = 1
-40
Over-temperature Threshold Detector
Resolution Error
135
±5
Overcurrent (OC) VSHUNT Threshold
Voltage Range
OCRNG = ALL
Overcurrent (OC) VSHUNT Threshold DAC
Step Size
OCRNG = ALL
VSHUNT Threshold Detector Full-scale
Settings
25
°C
°C
125
% of FS
1.56
% of FS
OCRNG = 0
80
mV
OCRNG = 1
40
mV
8
Bits
±1
LSB
MARGINING DAC, ANALOG OUTPUT
Resolution
DNL
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FN8389.4
June 17, 2015
ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
TYP
MAX
(Note 6)
UNIT
INL
MDAC[7:0] = 0 to 256
±3
LSB
Gain Error
DAC_MS[2:0] = 0
±2.5
%
Offset Error
DAC_MS[2:0] = 0
±2
mV
Output Voltage
VMS
MIN
(Note 6)
DAC Mid-scale
0.055
V
DAC_MS[2:0] = 0
0.4
V
DAC_MS[2:0] = 1
0.5
V
DAC_MS[2:0] = 2
0.6
V
DAC_MS[2:0] = 3
0.7
V
DAC_MS[2:0] = 4
0.8
V
DAC_MS[2:0] = 5
0.9
V
DAC_MS[2:0] = 6
1.0
V
DAC_MS[2:0] = 7
1.2
V
1
V/µs
Slew Rate
Output Current
Short Circuit Current
2*Vms
1
mA
DAC_OUT = VCC
17
mA
DAC_OUT = GND
4.2
mA
Start-up Time
100
µs
VOLTAGE REGULATOR SPECIFICATION
Input Voltage at REG_IN
4.5
Output Regulation Voltage
3.18
60
V
3.3
3.35
V
Line Regulation
VIN = 4.5V to 60V
53
150
µV/V
Load Regulation
ILOAD = 3.3mA to 6mA
0.2
1.4
mV/mA
Capacitance Drive
0.01
10
µF
Output Short Circuit
T = -40°C to +125°C
10
mA
Max Load Current
T = -40°C to +125°C
6
mA
1
ms
Start-up Time
TEMPERATURE SENSOR
Temperature Sensor Measurement Range
Temperature Accuracy
-40
T = +25°C
125
°C
+1
°C
Temperature Resolution
0.5
°C
Measurement Time
0.5
ms
SMBus/I2C INTERFACE SPECIFICATIONS
VIL
SMBDAT and SMBCLK Input Buffer LOW
Voltage
-0.3
0.3 x
I2CVCC
V
VIH
SMBDAT and SMBCLK Input Buffer HIGH
Voltage
0.7 x I2CVCC
I2CVCC +
0.3
V
Hysteresis
VOL
SMBDAT and SMBCLK Input Buffer
Hysteresis
SMBDAT Output Buffer LOW Voltage,
Sinking 3mA
Submit Document Feedback
9
0.05 x
I2CVCC
I2CVCC = 5V, IOL = 3mA
0
0.02
V
0.4
V
FN8389.4
June 17, 2015
ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
MIN
(Note 6)
MAX
(Note 6)
UNIT
10
pF
SMBCLK Frequency
400
kHz
tIN
Pulse Width Suppression Time at SMBDAT Any pulse narrower than the max spec
and SMBCLK Inputs
is suppressed
50
ns
tAA
SMBCLK Falling Edge to SMBDAT Output
Data Valid
900
ns
tBUF
Time the Bus Must be Free Before the Start SMBDAT crossing 70% of I2CVCC during
of a New Transmission
a STOP condition, to SMBDAT crossing
70% of I2CVCC during the following
START condition
tLOW
Clock LOW Time
tHIGH
PARAMETER
CPIN
fSMBCLK
DESCRIPTION
SMBDAT and SMBCLK Pin Capacitance
TEST CONDITIONS
TYP
TA = +25°C, f = 1MHz, I2CVCC = 5V,
VIN = 0V, VOUT = 0V
SMBCLK falling edge crossing 30% of
I2CVCC, until SMBDAT exits the 30% to
70% of I2CVCC window
1300
ns
Measured at the 30% of I2CVCC
crossing
1300
ns
Clock HIGH Time
Measured at the 70% of I2CVCC
crossing
600
ns
tSU:STA
START Condition Setup Time
SMBCLK rising edge to SMBDAT falling
edge. Both crossing 70% of I2CVCC
600
ns
tHD:STA
START Condition Hold Time
From SMBDAT falling edge crossing
30% of I2CVCC to SMBCLK falling edge
crossing 70% of I2CVCC
600
ns
tSU:DAT
Input Data Setup Time
From SMBDAT exiting the 30% to 70%
of VCC window, to SMBCLK rising edge
crossing 30% of I2CVCC
100
ns
tHD:DAT
Input Data Hold Time
From SMBCLK falling edge crossing
30% of I2CVCC to SMBDAT entering the
30% to 70% of I2CVCC window
20
tSU:STO
STOP Condition Setup Time
From SMBCLK rising edge crossing 70%
of I2CVCC, to SMBDAT rising edge
crossing 30% of I2CVCC
600
ns
tHD:STO
STOP Condition Hold Time
From SMBDAT rising edge to SMBCLK
falling edge. Both crossing 70% of
I2CVCC
600
ns
Output Data Hold Time
From SMBCLK falling edge crossing
30% of I2CVCC, until SMBDAT enters
the 30% to 70% of I2CVCC window
0
ns
SMBDAT and SMBCLK Rise Time
From 30% to 70% of I2CVCC
20 + 0.1 x Cb
300
tF
SMBDAT and SMBCLK Fall Time
From 70% to 30% of I2CVCC
20 + 0.1 x Cb
300
ns
Cb
Capacitive Loading of SMBDAT or SMBCLK Total on-chip and off-chip
10
400
pF
SMBDAT and SMBCLK Bus Pull-up Resistor Maximum is determined by tR and tF
Off-chip
For Cb = 400pF, max is about
2kΩ~2.5kΩ
For Cb = 40pF, max is about
15kΩ~20kΩ
1
tDH
tR
RPU
900
ns
ns
kΩ
POWER SUPPLY
Vvcc
Vi2cvcc
Power Supply Voltage at VCC
Power Supply Voltage at I2CVCC
f = DC to 400kHz
Only ADC in Conversion Mode
All other blocks are disabled
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10
3.0
3.3
5.5
V
1.2
3.3
5.5
V
690
830
µA
FN8389.4
June 17, 2015
ISL28023
Electrical Specifications TA = +25°C, I2CVCC = VCC = 3.3V, VINP = VBUS = 12V, VSENSE = VINP -VINM = 80mV, AUXP-AUXM = 80mV, AuxV = 3V,
Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Only ADC in Idle Mode
All other blocks are disabled
640
705
µA
Only Threshold Detectors
All three detectors are active
760
945
µA
Only Margin DAC
All other blocks are disabled
240
286
µA
Fully Enabled Chip Current
All functional blocks enabled
1240
1545
µA
Fully Disabled Chip Current
All functional blocks disabled
5
15
µA
Ivreg_in
Voltage Regulator
Vreg_in = 4.5V to 60V; Rload = open
26
35
µA
Ii2cvcc
I2C Supply Current
SMBCLK = 100kHz; I2CVCC = 3.3V
15
µA
I2C Idle supply current
Input signals are static
100
nA
Ii2cvcc_pd
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Compliance to datasheet limits is assured by one or
more of the following methods: production test, characterization and design.
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FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified.
9
50
8
40
7
30
VOS (µV)
6
HITS
T = +125°C
5
4
3
10
0
-10
T = +25°C
-20
50.0
37.5
25.0
12.5
0
-12.5
-50
3.0
-25.0
-40
0
-37.5
-30
1
-50.0
2
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
VOS (µV)
FIGURE 3. PRIMARY VSHUNT VOS
FIGURE 4. PRIMARY VSHUNT VOS vs VCC
7
80
6
60
5
40
VOS (µV)
HITS
T = -40°C
20
4
3
VCC = 5V
VCC = 3.3V
20
0
2
-20
-40
-60
0.300
0.225
0.150
0.075
0
-0.075
-0.150
-0.225
0
-0.300
1
VCC = 3V
-40
-20
0
40
60
80
100 120 140 160
TEMPERATURE (°C)
VOS TC (µV/C)
FIGURE 5. PRIMARY VSHUNT VOS TC (-40°C TO +125°C)
FIGURE 6. PRIMARY VSHUNT VOS vs TEMPERATURE
4.5
500
4.0
400
3.5
300
3.0
200
CMRR (nV/V)
HITS
20
2.5
2.0
1.5
100
0
-100
-200
1.0
-300
0.5
PRIMARY CMRR (nV/V)
FIGURE 7. PRIMARY VSHUNT CMRR, CMV = (0V TO 60V)
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12
500
375
250
125
-125
-250
-375
-500
0
-400
0
-500
-60 -40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 8. PRIMARY VSHUNT CMRR vs TEMPERATURE
(CMV = 0V TO 60V)
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
20
130
15
125
10
120
5
115
CMRR (dB)
VOS (µV)
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
0
-5
110
105
-10
100
-15
95
-20
0
8
16
24
32
40
48
56
TIME = 2.048ms
TIME = 1.024ms
TIME = 0.512ms
90
64
TIME = 0.128ms
TIME = 0.64ms
10
100
1k
10k
100k
FREQUENCY (Hz)
CMV (V)
FIGURE 9. PRIMARY VSHUNT CMRR vs CMV
FIGURE 10. PRIMARY VSHUNT AC CMRR vs FREQUENCY
95
TO CMV = 60V
75
65
55
VINPUT = 80MVP-P SINE WAVE
FREQUENCY = 100Hz
ADC TIMING = 64µs
45
35
-80
-70
-60
-50
-40
-30
-20
-10
ABS (CHANGE IN VOLTAGE) (mV)
180
85
VMEAS (mVP-P)
TIME = 0.256ms
160
SMBALERT2
SOURCE
140
120
100
SMBALERT1
SINK
80
60
40
20
0
0.01
0
SMBALERT2
SINK
0.1
1
10
CURRENT LOAD (mA)
CMV (mV)
FIGURE 11. PRIMARY VSHUNT COMMON MODE RANGE
FIGURE 12. SMBALERT CURRENT DRIVES
8
6
7
5
6
4
4
HITS
HITS
5
3
3
2
2
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0
GAIN ERROR (%)
FIGURE 13. PRIMARY VSHUNT ADC GAIN ERROR
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13
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
1
1
VSHUNT GAIN ERROR TC (ppm/°C)
FIGURE 14. PRIMARY VSHUNT ADC GAIN ERROR TC
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
0.5
0.5
0.4
VCC = 3V + 3.3V
0.3
MEASUREMENT ERROR (%)
MEASUREMENT ERROR (%)
0.4
0.2
0.1
0
-0.1
-0.2
-0.3
VCC = 5V
-0.4
VCC = 3.3V
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
-0.5
-60 -40
0.08
-20
0
VINPUT (V)
1
60
80
TIME = 0.64ms
-1
TIME = 0.64ms
GAIN (dB)
TIME = 0.256ms
-7
TIME = 0.512ms
-9
TIME = 1.024ms
-11
PRIMARY VSHUNT
-3
TIME = 0.128ms
-5
100 120 140 160
1
50mVP-P SINE WAVE
-3
PRIMARY VBUS
-5
-7
-9
-11
TIME = 2.048ms
-13
-13
-15
10
100
1k
10k
-15
10
100k
100
1k
10k
FIGURE 17. PRIMARY VSHUNT BANDWIDTH vs ADC TIMING
FIGURE 18. PRIMARY VSHUNT AND VBUS vs FREQUENCY
20
10
VINPUT = 25mV
9
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
10
7
VOS (mV)
6
5
4
3
VINPUT = 25mV
15
8
HITS
40
FIGURE 16. PRIMARY VSHUNT MEASUREMENT ERROR vs
TEMPERATURE
-1
GAIN (dB)
20
TEMPERATURE (°C)
FIGURE 15. PRIMARY VSHUNT MEASUREMENT ERROR vs INPUT
T = +125°C
5
0
-5
T = -40°C
T = +25°C
-10
2
-15
VOS (mV)
FIGURE 19. PRIMARY VBUS VOS
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14
20
15
10
5
0
-5
-10
-15
-20
1
0
VCC = 3V
VCC = 5V
-20
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
FIGURE 20. PRIMARY VBUS VOS vs VCC
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
12
20
VINPUT = 25mV
15
10
5
VOS (mV)
HITS
6
4
VCC = 3.3V
VCC = 3V
10
8
0
-5
VCC = 5V
-10
2
-20
-60
100
75
50
25
0
-25
-50
-100
-75
-15
0
0
40
60
80
100 120 140 160
TEMPERATURE (°C)
6
7
ISL28023-12 (1V TO 16V)
ISL28023-60 (12V TO 60V)
5
ISL28023-60
(12V TO 60V)
5
6
ISL28023-12 (1V TO 16V)
4
HITS
4
3
3
2
2
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
1
1
GAIN ERROR TC (ppm/C)
GAIN ERROR (%)
FIGURE 23. PRIMARY VBUS ADC GAIN ERROR
FIGURE 24. PRIMARY VBUS ADC GAIN ERROR TC
0.7
0.7
VCC (12) = 3V
0.5
MEASUREMENT ERROR (%)
MEASUREMENT ERROR (%)
20
FIGURE 22. PRIMARY VBUS VOS vs TEMPERATURE
8
HITS
-20
VOS TC (µV/C)
FIGURE 21. PRIMARY VBUS VOS TC
0
VINPUT = 25mV
-40
VCC (60) = 3V
0.3
0.1
-0.1
VCC (12) = 3.3V
-0.3
VCC (60) = 5V
VCC (12) = 5V
-0.5
-0.7
VCC (60) = 3.3V
0
8
16
24
32
40
48
56
64
VINPUT (V)
FIGURE 25. PRIMARY VBUS MEASUREMENT ERROR vs INPUT
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15
VCC (60) = 3V
VCC (12) = 3.3V
0.5
VCC (12) = 3V
0.3
0.1
-0.1
VCC (60) = 3.3V
VCC (12) = 5V
-0.3
VCC (60) = 5V
-0.5
-0.7
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 26. PRIMARY VBUS MEASUREMENT ERROR vs TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
14
50
12
40
30
20
8
VOS (µV)
HITS
10
6
0
-10
-20
4
-30
2
T = -40°C
10
T = +125°C
T = +25°C
-50
30.0
22.5
VOS (µV)
15.0
0
-7.5
-15.0
-22.5
-30.0
7.5
-40
0
3
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
FIGURE 27. AUXILIARY VSHUNT VOS
FIGURE 28. AUXILIARY VSHUNT VOS vs VCC
12
20
10
10
VCC = 3V
VCC = 3.3V
0
6
VOS (µV)
HITS
8
4
-10
-20
VCC = 5V
2
0.100
0.075
0.050
0.025
0
-0.025
-0.050
-0.075
0
-0.100
-30
-40
-60
-40
-20
0
VOS TC (µV/C)
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 29. AUXILIARY VSHUNT VOS TC (-40°C TO +125°C)
FIGURE 30. AUXILIARY VSHUNT VOS vs TEMPERATURE
7
7
6
5
5
CMRR (µV/V)
HITS
3
4
3
2
1
-1
-3
1
7.00
5.25
3.50
1.75
0
-1.75
-3.50
-5.25
-7.00
-5
0
CMRR (µV/V)
FIGURE 31. AUXILIARY VSHUNT CMRR, CMV = (0V TO 3.3V)
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16
-7
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 32. AUXILIARY VSHUNT CMRR vs TEMPERATURE
(CMV = 0V TO 3.3V)
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
20
95
VCC = 6V
15
85
TO CMV = VCC
VMEAS (mVP-P)
10
VOS (µV)
5
0
-5
75
65
55
-10
-20
VINPUT = 80mVP-P SINE WAVE
FREQUENCY = 100Hz
ADC TIMING = 64µs
45
-15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
35
-80
5.5 6.0
-70
-60
-50
CMV (V)
-40
-30
-20
-10
0
CMV (mV)
FIGURE 33. AUXILIARY VSHUNT VOS vs CMV
FIGURE 34. AUXILIARY VSHUNT COMMON MODE RANGE
6
7
6
4
5
3
4
HITS
HITS
5
2
3
2
1
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
1
0
VAUXSHUNT MEASUREMENT ERROR (%)
VAUXSHUNT GAIN ERROR (ppm/°C)
FIGURE 36. AUXILIARY VSHUNT ADC GAIN ERROR TC
0.5
0.5
0.4
0.4
0.3
MEASUREMENT ERROR (%)
MEASUREMENT ERROR (%)
FIGURE 35. AUXILIARY VSHUNT ADC GAIN ERROR
VCC = 3V
0.2
VCC = 3.3V
0.1
0
-0.1
-0.2
VCC = 5V
-0.3
-0.4
-0.5
-0.08
0.3
VCC = 3.3V
0.2
0.1
0
-0.1
VCC = 3V
VCC = 5V
-0.2
-0.3
-0.4
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
VINPUT (V)
FIGURE 37. AUXILIARY VSHUNT MEASUREMENT ERROR vs INPUT
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17
-0.5
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 38. AUXILIARY VSHUNT MEASUREMENT ERROR vs
TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
1
1
-1
-1
TIME = 0.64ms
TIME = 0.64ms
-3
-9
-11
TIME = 0.256ms
TIME = 0.512ms
GAIN (dB)
GAIN (dB)
-5
-7
-3
TIME = 0.128ms
TIME = 1.024ms
-5
-7
-9
-11
TIME = 2.048ms
-13
-13
-15
10
100
1k
FREQUENCY (Hz)
10k
-15
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 39. AUXILIARY VBUS BANDWIDTH vs ADC TIMING
FIGURE 40. AUXILIARY VSHUNT AND VBUS vs FREQUENCY
12
2.0
VINPUT = 25mV
10
VINPUT = 25mV
1.5
1.0
VOS (mV)
8
HITS
AUX VSHUNT
AUX VBUS
6
4
T = +125°C
0.5
T = -40°C
T = +25°C
0
-0.5
-1.0
2
-2.0
3.0
5.00
3.75
2.50
1.25
0
-1.25
-2.50
-3.75
-5.00
-1.5
0
3.5
4.0
FIGURE 41. AUXILIARY VBUS VOS
5.0
5.5
6.0
FIGURE 42. AUXILIARY VBUS VOS vs VCC
12
2.0
VINPUT = 25mV
10
1.5
VCC = 3V
1.0
VOS (mV)
8
HITS
4.5
VCC (V)
VOS (mV)
6
4
VCC = 3.3V
0.5
0
-0.5
-1.0
2
VOS TC (µV/°C)
FIGURE 43. AUXILIARY VBUS VOS TC
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18
20
15
10
5
0
-5
-10
-15
-20
0
VCC = 5V
-1.5
-2.0
-60
-40
-20
0
VINPUT = 25mV
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 44. AUXILIARY VBUS VOS vs TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
HITS
4.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
HITS
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
VAUXSHUNT GAIN ERROR TC (ppm/°C)
GAIN ERROR (%)
FIGURE 46. AUXILIARY VBUS ADC GAIN ERROR TC
0.5
0.5
0.4
0.4
0.3
VCC = 3V
0.2
MEASUREMENT ERROR (%)
MEASUREMENT ERROR (%)
FIGURE 45. AUXILIARY VBUS ADC GAIN ERROR
VCC = 3.3V
0.1
0
-0.1
VCC = 5V
-0.2
-0.3
-0.4
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC = 3.3V
0.3
0.2
0.1
0
VCC = 5V
-0.1
VCC = 3V
-0.2
-0.3
-0.4
-0.5
-60 -40
5.5
-20
0
AUX V (V)
FIGURE 47. AUXILIARY VBUS MEASUREMENT ERROR vs INPUT
3.5
14
2.5
TEMPERATURE (°C)
12
10
HITS
8
6
4
3.500
2.625
1.750
0.875
0
-0.875
-1.750
-2.625
60
80
100 120 140 160
VCC = 3.3V
VCC = 3V
1.5
0.5
-0.5
Teqn_3.3 = -5.286*10-11 * Tmeas5 + 7.458 * 10-9
-1.5
-2.5
2
-3.500
40
FIGURE 48. AUXILIARY VBUS MEASUREMENT ERROR vs
TEMPERATURE
16
0
20
TEMPERATURE (°C)
VCC = 5V
-3.5
-60
-40
-20
* Tmeas4 - 1.712 * 10-6 * Tmeas3 + 1.996 * 10-4
* Tmeas2 - 1.01 * Tmeas1 + 0.813
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 49. INTERNAL TEMPERATURE ACCURACY AT T = +25°C
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19
FIGURE 50. INTERNAL TEMPERATURE SENSOR ACCURACY
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
5
8
4
7
3
TEMPERATURE (°C)
9
HITS
6
5
4
3
2
1
2
1
0
-1
T = -40°C
-2
T = +25°C
-3
-5
3.500
2.625
1.750
0.875
0
-0.875
-1.750
-2.625
-4
-3.500
0
T = +125°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
TEMPERATURE (°C)
FIGURE 51. INTERNAL TEMPERATURE ACCURACY AT T = -40°C
FIGURE 52. INTERNAL TEMPERATURE ACCURACY vs VCC
9
6
8
5
7
4
5
HITS
HITS
6
4
3
3
2
2
TEMPERATURE (°C)
3.500
2.625
1.750
0.875
FIGURE 54. INTERNAL TEMPERATURE ACCURACY AT T = +125°C
80
MODE = Nmrl+OC
MODE = Nmrl+DACOEn
70
MODE = Nmrl+UV
1000
800
600
MODE = Nmrl+DACEn
400
MODE = Nmrl+OV
MODE = Nmrl
200
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
0
TEMPERATURE (°C)
FIGURE 53. INTERNAL TEMPERATURE ACCURACY AT T = +85°C
1200
-0.875
-1.750
-2.625
0
3.500
2.625
1.750
0.875
0
-0.875
-1.750
-2.625
-3.500
0
-3.500
1
1
60
50
40
MODE = ADC PD,
MODE = PD
30
20
10
0
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 55. SUPPLY CURRENT vs TEMPERATURE
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20
0
-60 -40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 56. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
1000
7
MODE = Nmrl+OC
MODE = Nmrl+DACOEn
MODE = Nmrl+UV
800
600
400
MODE = Nmrl+DACEn
MODE = Nmrl
MODE = Nmrl+OV
6
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
1200
5
MODE = ADC PD,
MODE = PD
4
3
2
1
200
0
3.0
3.5
4.0
4.5
5.0
5.5
0
3.0
6.0
3.5
4.0
4.5
-8.6
0
-8.8
-0.05
MODE = Nmrl
-9.2
-9.4
MODE = Nmrl+OC
-9.6
-9.8
-60
6.0
MODE = PD,
MODE = ADCPD
-0.10
-0.15
-0.20
-0.25
-40
-20
0
20
40
60
80
-0.30
-60
100 120 140 160
-40
-20
0
TEMPERATURE (°C)
20
0
0
-20
MODE = Nmrl+OC
MODE = Nmrl
-80
-100
60
80
100 120 140 160
MODE = ADCPD
-5
MODE = PD
-10
-15
-20
-25
-30
-120
-140
-60 -40
OFFSET CURRENT (nA)
5
-60
40
FIGURE 60. PRIMARY VSHUNT BIAS CURRENT vs TEMPERATURE
(POWER-DOWN MODE)
40
-40
20
TEMPERATURE (°C)
FIGURE 59. PRIMARY VSHUNT BIAS CURRENT vs TEMPERATURE
OFFSET CURRENT (nA)
5.5
FIGURE 58. SUPPLY CURRENT vs SUPPLY VOLTAGE
(POWER-DOWN MODES)
BIAS CURRENT (µA)
BIAS CURRENT (µA)
FIGURE 57. SUPPLY CURRENT vs SUPPLY VOLTAGE
-9.0
5.0
VCC (V)
TEMPERATURE (°C)
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 61. PRIMARY VSHUNT BIAS CURRENT OFFSET vs
TEMPERATURE
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21
-35
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 62. PRIMARY VSHUNT BIAS CURRENT OFFSET vs
TEMPERATURE (POWER-DOWN MODE)
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
0.001
0
0
BIAS CURRENT (µA)
BIAS CURRENT (µA)
-2
-4
-6
MODE = Nmrl
MODE = Nmrl+OC
-8
-10
-12
MODE = ADC PD
-0.001
-0.002
-0.003
MODE = PD
-0.004
-0.005
-0.006
0
8
16
24
32
40
48
56
-0.007
64
0
8
16
24
CMV (V)
5
1.0
0
0.8
-5
0.6
MODE = Nmrl+OC
-15
-20
MODE = Nmrl
-25
-30
-35
-40
8
16
24
32
40
48
56
0
-0.4
-0.6
MODE = ADC PD
0
8
16
24
32
40
48
56
64
CMV (V)
0
FIGURE 66. PRIMARY VSHUNT OFFSET CURRENT vs COMMON MODE
VOLTAGE (POWER-DOWN MODES)
20
VCC = 6V
VCM = 3.3V
-1.0
MODE = Nmrl
-2.0
-2.5
MODE = ADCPD
-3.0
VCC = 6V
VCM = 3.3V
15
OFFSET CURRENT (nA)
-0.5
BIAS CURRENT (µA)
64
-0.2
-1.0
64
FIGURE 65. PRIMARY VSHUNT OFFSET CURRENT vs COMMON MODE
VOLTAGE
-3.5
-60
56
MODE = PD
0.2
CMV (V)
-1.5
48
0.4
-0.8
0
40
FIGURE 64. PRIMARY VSHUNT BIAS CURRENT vs COMMON MODE
VOLTAGE (POWER-DOWN MODES)
OFFSET CURRENT (nA)
OFFSET CURRENT (nA)
FIGURE 63. PRIMARY VSHUNT BIAS CURRENT vs COMMON MODE
VOLTAGE
-10
32
CMV (V)
10
MODE = Nmrl
5
0
-5
MODE = ADCPD
-10
-15
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 67. AUXILIARY VSHUNT BIAS CURRENT vs TEMPERATURE
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22
-20
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 68. AUXILIARY VSHUNT BIAS CURRENT OFFSET vs
TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
0
OFFSET CURRENT (nA)
-0.05
BIAS CURRENT (µA)
0.12
VCC = 6V
VCM = 3.3V
-0.10
-0.15
-0.20
VCC = 6V
VCM = 3.3V
0.10
0.08
0.06
0.04
0.02
-0.25
-60 -40
-20
0
20
40
60
80
0
-60 -40
100 120 140 160
FIGURE 69. AUXILIARY VSHUNT POWER DOWN BIAS CURRENT vs
TEMPERATURE
BIAS CURRENT (µA)
20
40
60
80
100 120 140 160
FIGURE 70. AUXILIARY VSHUNT POWER DOWN BIAS CURRENT
OFFSET vs TEMPERATURE
VCC = 6V
-2
-3
MODE = ADCPD
-4
-5
VCC = 6V
20
OFFSET CURRENT (nA)
MODE = Nmrl
-1
15
10
5
MODE = ADCPD
0
-5
MODE = Nmrl
-10
-15
-20
0
-25
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
FIGURE 71. AUXILIARY VSHUNT BIAS CURRENT vs COMMON MODE
VOLTAGE
0
0.20
-0.0006
-0.0008
-0.0010
-0.0012
-0.0014
-0.0016
VCC = 6V
0.18
OFFSET CURRENT (nA)
-0.0004
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
-0.0018
-0.0020
FIGURE 72. AUXILIARY VSHUNT BIAS CURRENT OFFSET vs COMMON
MODE VOLTAGE
VCC = 6V
-0.0002
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCM (V)
VCM (V)
BIAS CURRENT (µA)
0
25
0
-6
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCM (V)
FIGURE 73. AUXILIARY VSHUNT POWER DOWN BIAS CURRENT vs
COMMON MODE VOLTAGE
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0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCM (V)
FIGURE 74. AUXILIARY VSHUNT POWER DOWN BIAS CURRENT
OFFSET vs COMMON MODE VOLTAGE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
6
3.50
5
3.45
VREG OUTPUT (V)
ILOAD = 3mA
HITS
4
3
2
ILOAD = 6mA
3.40
3.35
3.30
ILOAD = 0mA
3.25
0
3.20
-60
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
3.40
1
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
VREG (V)
FIGURE 75. VREG OUTPUT VOLTAGE DISTRIBUTION
FIGURE 76. VREG OUTPUT vs TEMPERATURE
3.40
0
3.38
-5
VREG CHANGE (mV)
VREG OUTPUT (V)
3.36
3.34
3.32
3.30
3.28
3.26
3.24
-10
-15
-20
3.22
3.20
0
8
16
24
32
40
48
56
-25
64
0.1
1
VREG INPUT (V)
8
8
7
7
6
6
5
5
4
4
3
3
0
8
16
24
32
40
48
56
VREG INPUT VOLTAGE (V)
FIGURE 79. VREG INPUT CURRENT vs INPUT VOLTAGE
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100
FIGURE 78. VREG OUTPUT vs CURRENT LOAD
IREG (µA)
IREG (µA)
FIGURE 77. VREG OUTPUT vs INPUT VOLTAGE
2
10
ILOAD (mA)
64
2
-60
-40
-20
0
20
40
60
80
100 120 140 160
TEMPERATURE (°C)
FIGURE 80. VREG INPUT CURRENT vs TEMPERATURE
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
1.2
0.2
NORMALIZED DAC OUTPUT (%)
NORMALIZED DAC OUTPUT (%)
0.4
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
3.0
3.5
4.0
4.5
5.0
5.5
1.0
0.8
0.6
0.4
0.2
0
-0.2
-60 -40
6.0
-20
0
VCC (V)
FIGURE 81. MARGIN DAC vs VCC
40
60
80
100 120 140 160
FIGURE 82. NORMALIZED DAC OUTPUT vs TEMPERATURE
200
1.0
180
0.8
160
0.6
140
0.4
DAC OUT
SOURCE
120
DNL (LSB)
ABS (DAC OUTPUT CHANGE) (mV)
20
TEMPERATURE (°C)
DAC OUT
SINK
100
80
0.2
0
-0.2
60
-0.4
40
-0.6
20
-0.8
0
0.1
1
10
-1.0
0
20
40
60
80 100 120 140 160 180 200 220 240 260
CURRENT LOAD (mA)
CODE
FIGURE 83. MARGIN DAC vs CURRENT LOAD
FIGURE 84. MARGIN DAC DNL
0
-0.5
-1.0
INL (LSB)
-1.5
INPUT
-2.0
-2.5
SMBALERT
-3.0
-3.5
-4.0
-4.5
0
20
40
60
80 100 120 140 160 180 200 220 240 260
CODE
FIGURE 85. MARGIN DAC INL PER CODE
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25
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
TIME (µs)
FIGURE 86. OV OR UV OR OC ALERT RESPONSE TIME
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
500
SAMPLE SIZE = 1024
70
60
50
40
30
20
10
0
50
250
450
650
850
RANGE OF MEASUREMENT (µV)
SIGMA OF MEASUREMENT (µV)
80
400
350
300
250
200
150
100
50
0
1050 1250 1450 1650 1850 2050
SAMPLE SIZE = 1024
450
50
250
450
650
SIGMA OF MEASUREMENT (µV)
12
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
10
8
6
4
2
0
0
40
FIGURE 88. PRIMARY SHUNT STABILITY: RANGE vs ACQUISITION TIME
35
RANGE OF MEASUREMENT (µV)
FIGURE 87. PRIMARY SHUNT STABILITY: STDEV vs ACQUISITION TIME
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
30
25
20
15
10
5
0
80 120 160 200 240 280 320 360 400 440 480 520
0
40
80 120 160 200 240 280 320 360 400 440 480 520
INTERNAL AVERAGING
FIGURE 89. PRIMARY SHUNT STABILITY: STDEV vs INTERNAL
AVERAGING
INTERNAL AVERAGING
FIGURE 90. PRIMARY SHUNT STABILITY: RANGE vs INTERNAL
AVERAGING
500
70
60
50
40
30
20
10
0
50
250
450
650
850 1050 1250 1450 1650 1850 2050
ADC TIMING (µs)
FIGURE 91. AUXILIARY SHUNT STABILITY: STDEV vs ACQUISITION TIME
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RANGE OF MEASUREMENT (µV)
SIGMA OF MEASUREMENT (µV)
80
SAMPLE SIZE = 1024
850 1050 1250 1450 1650 1850 2050
ADC TIMING (µs)
ADC TIMING (µs)
SAMPLE SIZE = 1024
450
400
350
300
250
200
150
100
50
0
50
250
450
650
850 1050 1250 1450 1650 1850 2050
ADC TIMING (µs)
FIGURE 92. AUXILIARY SHUNT STABILITY: RANGE vs ACQUISITION
TIME
FN8389.4
June 17, 2015
ISL28023
Typical Performance Curves
TA = +25°C, VCC = 3.3V, VINP = VBUS = 12V, AUXP = AUXV = 3V,
VSHUNT = VAUXSHUNT = 80mV, Conversion Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128; unless otherwise specified. (Continued)
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
7
6
5
4
3
2
1
0
0
40
25
RANGE OF MEASUREMENT (µV)
SIGMA OF MEASUREMENT (µV)
8
The ISL28023 is a digital current, voltage and power monitoring
device for high and low-side power monitoring in positive and
negative voltage applications.
The digital power monitor (DPM) requires an external shunt
resistor to enable current measurements. The shunt resistor
translates the bus current to a voltage. The DPM measures the
voltage across the shunt resistors and reports the measured
value out digitally via an I2C interface. A register within the DPM
is reserved to store the value of the shunt resistor. The stored
current sense resistor value allows the DPM to output a current
value to an external digital device.
The ISL28023 has two channels which allow the user to monitor
the voltage, current and power on two power supply rails. The two
channels for the DPM consist of a primary channel and an
auxiliary channel. The primary channel will allow and measure
voltages from 0V to 60V or from 0V to 16.384V, depending on
the option of the ISL28023. The auxiliary channel can tolerate
and measure voltage from 0V to VCC.
The ISL28023 has continuous fault detection for the primary
channel. The DPM can be configured to set an alert in the
instance of an overvoltage, undervoltage and/or overcurrent
event. The response time of the alert is 500ns from the event.
The ISL28023 has a temperature sensor with fault detection.
An 8-bit margin DAC, controllable through I2C communication, is
incorporated into the DPM. The voltage margining feature allows
for the adjustment of the regulated voltage to the load. The
margin DAC can help in proving the load robustness versus the
applied supply voltage.
The ISL28023 offers a 3.3V voltage regulator that can be used to
power the chip in addition to low power peripheral circuitry. The
DPM has an I2C power pin that allows the I2C master to set the
digital communication supply voltage to the chip. The operating
supply voltage for the DPM ranges from 3V to 5.5V. The device
will accept I2C supply voltages between 1.2V and 5.5V.
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15
10
5
0
40
80 120 160 200 240 280 320 360 400 440 480 520
INTERNAL AVERAGING
INTERNAL AVERAGING
Overview
20
0
80 120 160 200 240 280 320 360 400 440 480 520
FIGURE 93. AUXILIARY SHUNT STABILITY: STDEV vs INTERNAL
AVERAGING
SAMPLE SIZE = 1024
ADC TIMING = 2.048ms
FIGURE 94. AUXILIARY SHUNT STABILITY: RANGE vs INTERNAL
AVERAGING
The ISL28023 accepts SMBus protocols up to 3.4MHz. The
device is PMBus compliant up to 400MHz. The device has packet
error code (PEC) functionality. The PEC protocol uses an 8-bit
cyclic redundance check (CRC-8) represented by the polynomial
x8+x2+x1+1. The ISL28023 can be configured for up to 55
unique slave addresses using 3 address select bits. The large
amount of addressing allows 55 parts to communicate on a
single I2C bus. It also gives the designer the flexibility to select a
unique address when another slave address conflicts with the
DPM on the same I2C bus.
Pin Descriptions
VBUS
VBUS is the power bus voltage input pin. The pin should be
connected to the desired power supply bus to be monitored. The
voltage range for the pin is from 0V to 60V or 0V to 16V
depending on the ISL28023 version.
VINP
VINP is the shunt voltage monitor positive input pin. The pin
connects to the most positive voltage of the current shunt
resistor. The voltage range for the pin is from 0V to 60V or 0V to
16V depending on the ISL28023 version. The maximum
measurable voltage differential between VINP and VINM is
80mV.
VINM
VINM is the shunt voltage monitor negative input pin. The pin
connects to the most negative voltage of the current shunt resistor.
The voltage range for the pin is from 0V to 60V or 0V to 16V
depending on the ISL28023 version. The maximum measurable
voltage differential between VINP and VINM is 80mV.
AUXV
AUXV is the power bus voltage input pin. The pin should be
connected to the desired power supply bus to be monitored. The
voltage range for the pin is from 0V to VCC.
FN8389.4
June 17, 2015
ISL28023
AUXP
ADDRESS PINS (A0, A1, A2)
AUXP is the auxiliary shunt voltage monitor positive input pin.
The pin connects to the most positive voltage of the auxiliary
current shunt resistor. The voltage range for the pin is from 0V to
VCC. The maximum measurable voltage differential between
AUXP and AUXM is 80mV.
A0, A1 and A2 are address selectable pins. The address pins are
I2C/SMBus slave address select pins that are multilogic
programmable for a total of 55 different address combinations.
AUXM
AUXM is the auxiliary shunt voltage monitor negative input pin.
The pin connects to the most negative voltage of the auxiliary
current shunt resistor. The voltage range for the pin is from 0V to
VCC. The maximum measurable voltage differential between
AUXP and AUXM is 80mV.
VCC
VCC is the positive supply voltage pin. VCC is an analog power
pin. VCC supplies power to the device. The allowable voltage
range is from 3V to 5.5V.
I2CVCC
I2CVCC is the positive supply voltage pin. I2CVCC is an analog
power pin. I2CVCC supplies power to the digital communication
circuitry, I2C, of the device. The allowable voltage range is from
1.2V to 5.5V.
GND
Device ground. For single supply systems, the pin connects to
system ground. For dual supply systems, the pin connects to the
negative voltage supply in the system.
VREG_IN
VREG_IN is the voltage regulator input pin. The operable input
voltage range to the regulator is 4.5V to 60V.
VREG_OUT
VREG_OUT is the voltage regulator output pin. The regulated
output voltage of 3.3V is sourced from the VREG_OUT pin.
There are four selectable levels for the address pins, I2CVCC,
GND, SCL/SMBCLK, and SDA/SMBDAT. See Table 49 for more
details in setting the slave address of the device.
SMBDAT
SDA/SMBDAT is the serial data input/output pin. SDA/SMBDAT
is a bidirectional pin used to transfer data to and from the device.
The pin is an open drain output and may be wired with other
open drain/collector outputs. The input buffer is always active
(not gated). The open drain output requires a pull-up resistor for
proper functionality. The pull-up resistor should be connected to
I2CVCC of the device.
SMBCLK
SCL/SMBCLK is the serial clock input pin. The SCL/SMBCLK
input is responsible for clocking in all data to and from the
device. The input buffer on the pin is always active (not gated).
The input pin requires a pull-up resistor to I2CVCC of the device.
SMBALERT PINS (SMBALERT1, SMBALERT2)
The SMBALERT pins are output pins. The SMBALERT1 is an open
drain output and requires a pull-up resistor to a power supply up
to 24V. The SMBALERT2 has a push/pull output stage. The
SMBALERT pins are fault acknowledgment pins. The pin can be
connected to peripheral circuitry to halt operations when a fault
event occurs.
EXTCLK
EXT_CLK is the external clock pin. EXT_CLK is an input pin. The
pin provides a connection to the system clock. The system clock
is connected to the ADC. The acquisitions rate of the ADC can be
varied through the EXT_CLK pin. The pin functionality is set
through a control register bit.
DAC_OUT
DAC_OUT is the margin DAC output pin. The output of the DAC
voltage ranges from 0V to 2.4V. The voltage DAC is controlled
through internal registers.
TABLE 2. ISL28023 REGISTER DESCRIPTIONS
REGISTER
ADDRESS
(HEX)
REGISTER NAME
FUNCTION
POWER ON RESET
VALUE (HEX)
NUMBER ACCESS
OF BYTES TYPE
PAGE
IC DEVICE DETAILS
19
CAPABILITY
PMBus Supportability
B0
1
R
31
20
VOUT_MODE
Describes the ADC Read Back Format
40
1
R
31
99
PMBUS_REV
PMBus Revision
22
1
R
31
AD
IC_DEVICE_ID
Device ID
49534C3238303233
8
R
31
AE
IC_DEVICE_REV
Device Revision and Silicon Version
000002
3
R
31
GLOBAL IC CONTROLS
12
RESTORE_DEFAULT_ALL
Soft Reset
N/A
0
W
32
01
OPERATION
Turns the Device On and Off
80
1
R/W
32
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FN8389.4
June 17, 2015
ISL28023
TABLE 2. ISL28023 REGISTER DESCRIPTIONS (Continued)
REGISTER
ADDRESS
(HEX)
REGISTER NAME
FUNCTION
POWER ON RESET
VALUE (HEX)
NUMBER ACCESS
OF BYTES TYPE
PAGE
PRIMARY AND AUXILIARY CHANNEL CONTROLS
D2
SET_DPM_MODE
Configures the ISL28023
0A
1
R/W
32
D3
DPM_CONV_STATUS
Indicates the Status of a Conversion
N/A
1
R
32
D4
CONFIG_ICHANNEL
Shunt Inputs (Primary and Auxiliary) Configuration
0387
2
R/W
33
38
IOUT_CAL_GAIN
Calibration that Enables Primary Current Measurements
0000
2
R/W
33
D5
CONFIG_VCHANNEL
Bus Inputs (Primary and Auxiliary) Configuration
0387
2
R/W
34
D7
CONFIG_PEAK_DET
Enables Primary Channel Current Peak Detector
00
1
R/W
34
E2
CONFIG_EXCITATION
Enables Temp Measurements on the Auxiliary Shunt Input
00
1
R/W
34
0000
2
R
35
MEASUREMENT REGISTERS
D6
READ_VSHUNT_OUT
Primary Shunt Measurement Value
8B
READ_VOUT
Primary Bus Measurement Value
0000
2
R
35
8C
READ_IOUT
Primary Current Measurement Value
0000
2
R
35
D8
READ_PEAK_MIN_IOUT
Primary Current Max Measurement Value
7FFF
2
R
35
D9
READ_PEAK_MAX_IOUT
Primary Current Min Measurement Value
8001
2
R
35
96
READ_POUT
Primary Power Measurement Value
0000
2
R
35
E0
READ_VSHUNT_OUT_AUX
Axillary Shunt Measurement Value
0000
2
R
36
E1
READ_VOUT_AUX
Auxiliary Bus Measurement Value
0000
2
R
36
8D
READ_TEMPERATURE_1
Internal Temperature Measurement Value
0000
2
R
36
003F
2
R/W
36
THRESHOLD DETECTORS
DA
VOUT_OV_THRESHOLD_SET Overvoltage/Over-temperature Threshold Configuration
DB
VOUT_UV_THRESHOLD_SET Undervoltage Threshold Configuration
DC
IOUT_OC_THRESHOLD_SET Overcurrent Threshold Configuration
00
1
R/W
37
003F
2
R/W
37
SMB ALERT
DD
CONFIG_INTR
Configure the Behavior of the Interrupts
0000
2
R/W
39
DE
FORCE_FEEDTHR_ALERT
Configure the Path of the Interrupt Signal
00
1
R/W
40
1B
SMBALERT_MASK
Alert Mask for the SMBALERT1 Pin
N/A
2
R/W
41
DF
SMBALERT2_MASK
Alert Mask for the SMBALERT2 Pin
N/A
1
R/W
41
03
CLEAR_FAULTS
Clears All Faults
N/A
0
W
40
7A
STATUS_VOUT
Alert Bits related to the Primary Bus
00
1
R/W
40
7B
STATUS_IOUT
Alert Bit related to the Primary Shunt
00
1
R/W
40
7D
STATUS_TEMPERATURE
Alert Bit related to Temperature
00
1
R/W
40
7E
STATUS_CML
Alert Bits related to Communication Errors
00
1
R/W
41
78
STATUS_BYTE
Alert Bits related to Temperature and Device Status
00
1
R/W
41
79
STATUS_WORD
Alert Bits related to all Primary Inputs
0000
2
R/W
41
VOLTAGE MARGIN
E4
CONFIG_VOL_MARGIN
Configures the Margin DAC
00
1
R/W
43
E3
SET_VOL_MARGIN
Value to Load into the Margin DAC
80
1
R/W
43
Configures External Clock; Enable/Disable SMBALERT2
00
1
R/W
42
EXTERNAL CLOCK CONTROL
E5
CONFIG_EXT_CLK
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FN8389.4
June 17, 2015
ISL28023
Communication Protocol
The DPM chip communicates with the host using PMBus
commands. PMBus command structure is an industry SMBus
standard for communicating with power supplies and converters.
All communications to and from the chip use the SMBCLK and
SMBDAT to communicate to the DPM master. The SMB pins
require a pull-up resistor to enable proper operation. The default
logic state of the communication pins are high when the bus is in
an idle state.
The SMBus standard is a variant of the I2C communication
standard with minor differences with timing and DC parameters.
SMBus supports packet error corrections (PEC) for data integrity
certainty. The PMBus is the standardization of the SMBus
register designation. The standardization is specific to power and
converter devices.
The DPM employs the following command structures from the
I2C communication standard;
1. Send Byte
2. Write Byte/Word
3. Read Byte/Word
4. Read Block
5. Write Block
Packet Error Correction (PEC)
Packet Error Correction is often used in environments where data
being transferred to and from the device can be compromised.
Applications where the device is connected by way of a cable is
common use of PEC. The cable’s integrity may be compromised
resulting in error transactions between the master and the
device. The ISL28023 uses an 8-bit cyclic redundance check
(CRC-8). Figure 95 is an example of a flow algorithm for CRC-8
protocol.
Public Function crc8Decode(binStr As String) As Byte
Declaration of variables
Dim crc8(0 To 7) As Byte, index As Byte, doInvert As Byte
The input to the subroutine is a binary string consisting of
the slave address, the register address and data inputted to or received
from the part. Anything input into or received from the device is part of the
binary string (binStr) to be calculated by this routine.
Clear the crc8 variable. This variable is used to return the PEC value.
For index = 0 To UBound(crc8)
crc8(index) = 0
Next index
index = 0
While index <> (Len(binStr))
index = index + 1
The If statement below reads the binary value of each bit in the binary
string (binStr).
If Mid(binStr, index, 1) = "1" Then
doInvert = 1 Xor crc8(7)
Else
doInvert = 0 Xor crc8(7)
End If
crc8(7) = crc8(6)
crc8(6) = crc8(5)
crc8(5) = crc8(4)
crc8(4) = crc8(3)
crc8(3) = crc8(2)
crc8(2) = crc8(1) Xor doInvert
crc8(1) = crc8(0) Xor doInvert
crc8(0) = doInvert
Wend
crc8Decode = 0
For index = 0 To 7 'This assembles the crc8 value in byte form.
crc8Decode = crc8(index) * 2 ^ index + crc8Decode
Next index ‘crc8Decode is returned from this routine.
End Function
FIGURE 95. AN ALGORITHM TO CALCULATE A CRC8 (PEC) BYTE VALUE.
FIGURE 96. READ/WRITE SMBUS PROTOCOLS WITH AND WITHOUT PEC. DIAGRAMS COPIED FROM A SMBUS SPECIFICATION DOCUMENT. THE
DOCUMENT CAN BE UPLOADED AT http://smbus.org/specs/
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FN8389.4
June 17, 2015
ISL28023
IC Device Details
0X99 PMBUS REV (R)
0X19 CAPABILITY (R)
The PMBUS Rev register is a readable byte register that describes
the PMBUS revision that the DPM is compliant to.
The capability register is a read only byte register that describes
the supporting communication standard by the DPM chip.
TABLE 3. 0x19 CAPABILITY REGISTER DEFINITION
BIT
NUMBER
D7
D[6:5]
D4
D[3:0]
Bit Name
PEC
Max Bus Speed
SMB Alert
Support
N/A
Default
Value
1
01
1
0000
The DPM chip supports packet error correction (PEC) protocol.
The maximum PMBus bus speed that the DPM supports is
400kHz. The DPM supports a higher speed option that is not
compliant to the PMBus standard. The higher speed option is
discussed later in the datasheet. The DPM chip has SMB alert
pins which supports SMB alert commands.
0X20 VOUT MODE (R)
The VOUT Mode register is a readable byte register that describes
the method to calculate read back values from the DPM such as
voltage, current, power and temperature. The value for the
register is 0x40. The register value represents a direct data read
back format. For unsigned registers such as VBUS, the register
value is calculated using Equation 1.
Register Value
 15

 Bit_Val  2n  

n 


n  0


(EQ. 1)
Otherwise, Equation 2 is used for signed readings.
TABLE 4. 0x99 PMBUS REV REGISTER DEFINITION
BIT NUMBER
D[7:4]
D[3:0]
Bit Name
PMBUS Rev Part I
PMBUS Rev Part II
Default Value
0010
0010
PMBUS Rev part 1 is a PMBus specification pertaining to
electrical transactions and hardware interface. PMBUS Rev
part 2 specification pertains to the command calls used to
address the DPM.
A nibble of 0000 translates to revision 1.0 of either PMBUS
revision. A nibble of 0001 equals 1.1 of either PMBUS revision.
0XAD IC DEVICE ID (BR)
The IC Device ID is a block readable register that reports the
device product name being addressed. The product ID that is
stored in the register is “ISL28023”. Each character is stored as
an ASCII number. A 0x30 equals ASCII “0”. A 0x49 translates to
an ASCII “I”. Figure 97 illustrates the convention for performing a
block read.
0XAE IC_DEVICE_REV (BR)
The IC Device Revision is a block readable register that reports
back the revision number of the silicon and the version of the
silicon. The register is 3 bytes in length.
TABLE 5. 0xAE IC DEVICE REV REGISTER DEFINITION
BIT NUMBER
D[23:12]
D[11]
D[10:0]
Bit Name
N/A
Silicon Version
Silicon Revision
1
000 0000 0010
Default Value 0000 0011 0000


 Bit_Val  2n     Bit_Val  215 

n  
15



n  0

14
Register Value

(EQ. 2)
n is the bit position within the register value. Bit_Val is the value
of the bit either 1 or 0.
SILICON VERSION D[11]
Data Bit11 of the IC Revision register reports the version of the
silicon.
TABLE 6. D[11] SILICON VERSION BIT DEFINED
D16
STATUS
0
60V
1
12V
FIGURE 97. BLOCK READ SMBUS PROTOCOLS WITH AND WITHOUT PEC. DIAGRAMS COPIED FROM SMBUS SPECIFICATION DOCUMENT. THE
DOCUMENT CAN BE UPLOADED AT http://smbus.org/specs/
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FN8389.4
June 17, 2015
ISL28023
Global IC Controls
POST TRIGGER STATE D[4]
0X12 RESET DEFAULT ALL (S)
Data bit 4 of the Set DPM Mode register controls the post ADC
state once an acquisition has been made in the trigger mode.
The Restore Default All register is a send byte command that
restores all registers to the default state defined in Table 2.
0X01 OPERATION (R/W)
The Operation register is a read writable byte register that
controls the overall power up state of the chip. Data Bit 7 of the
register configures the power status of the chip. The power status
is defined in Table 7. Yellow shading in the table is the default
setting of the bit at power-up.
TABLE 7. 0x01 OPERATION REGISTER BIT7 DEFINED
D7
STATUS
0
Power-Down
1
Normal Operation
Primary and Auxiliary Channel Controls
TABLE 11. 0xD2 SET DPM MODE REGISTER BIT4 DEFINED
D4
POST TRIGGER STATE
0
Idle Mode after a Trigger Measurement
1
PD Mode after Trigger Measurement
ADC MODE TYPE D[3]
Data bit 3 of the Set DPM Mode register controls the behavior of
the ADC to either triggered or continuous. The continuous mode
has the ADC continuously acquiring DAT in a systematic manor
described by data Bits[2:0] in the SET DPM MODE register. The
triggered mode instructs the ADC to make an acquisition
described by data Bits[2:0]. The beginning of a triggered cycle
starts once writing to the Set DPM Mode register commences.
The trigger mode is useful for reading a single measurement per
acquisition cycle.
TABLE 12. 0xD2 SET DPM MODE REGISTER BIT3 DEFINED
0XD2 SET DPM MODE (R/W)
The Set DPM Mode is a read writable byte register that controls
the data acquisition behavior of the chip.
TABLE 8. 0xD2 SET DPM MODE REGISTER DEFINITION
BIT
NUMBER
D[7]
D6
D[5]
D[4]
D[3]
D[2:0]
Bit Name
N/A
ADC
Enable
ADC
State
Post
Trigger
State
ADC
Mode
Type
Operating
Mode
Default Value
0
0
0
0
1
010
ADC ENABLE D[6]
D3
ADC MODE TYPE
0
Trigger
1
Continuous
OPERATING MODE D[2:0]
The Operating Mode bits of the Set DPM Mode register controls the
state machine within the chip. The state machine globally controls
the overall functionality of the chip. Table 13 shows the various
measurement states the chip can be configured to, as well as the
mode bit definitions to achieve a desired measurement state. The
shaded row is the default setting upon power-up.
TABLE 13. 0xD2 SET DPM MODE REGISTER BITS 2 TO 0 DEFINED
Data bit 6 of the Set DPM Mode register controls the ADC power
state within the DPM chip. At power-up, the ADC is powered up
and is available to take data.
D[2:0]
MEASUREMENT INPUT
0
Primary Channel Shunt Voltage
TABLE 9. 0xD2 SET DPM MODE REGISTER BIT6 DEFINED
1
Primary Channel VBUS Voltage
2
Primary Shunt and VBUS Voltages
3
Auxiliary Channel Shunt Voltage
D6
ADC PD
0
Normal Mode
1
ADC Powered Down
4
Auxiliary Channel VBUS Voltage
5
Auxiliary Shunt and VBUS Voltages
ADC STATE D[5]
6
Internal Temperature
Data Bit5 of the Set DPM Mode register controls the ADC state.
The idle state of the ADC does not acquire data from any input of
the DPM. Normal operating mode has the ADC acquiring data in
a systematic way.
7
All
TABLE 10. 0xD2 SET DPM MODE REGISTER BIT5 DEFINED
D5
ADC STATE
0
Normal State
1
ADC in Idle State
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0XD3 DPM CONVERSION STATUS (R)
The DPM conversion status register is a readable byte register
that reports the status of a conversion when the DPM is
programmed in the trigger mode.
TABLE 14. 0xD3 DPM CONVERSION STATUS REGISTER DEFINITION
BIT NUMBER
D[7:2]
D[1]
D[0]
Bit Name
N/A
CNVR
OVF
Default Value
0
0
0
FN8389.4
June 17, 2015
ISL28023
CNVR: CONVERSION READY D[1]
The Conversion Ready bit indicates when the ADC has finished a
conversion and has transferred the reading(s) to the appropriate
register(s). The CNVR is only operable when the ADC state is set
to trigger. The CNVR is in a high state when the conversion is in
progress. When the CNVR bit transitions from a high state to a
low state and remains at a low state, the conversion is complete.
The CNVR initializes or reinitializes when writing to the Set DPM
Mode register.
respect to the auxiliary average setting. Table 17 defines the list
of selectable averages the DPM can be set to. The shaded row
indicates the default setting.
TABLE 17. AUXILIARY/ PRIMARY VSHUNT NUMBER OF SAMPLES TO
AVERAGE DEFINED
AVG[3:0]
CONVERTER AVERAGES
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0XD4 CONFIGURE ICHANNEL (R/W)
0
1
0
1
32
The Configure IChannel register is a read/writable word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage shunt inputs.
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
512
1
0
1
0
1024
1
0
1
1
2048
1
1
X
X
4096
OVF: MATH OVERFLOW FLAG D[0]
The Math Overflow Flag (OVF) bit is set to indicate the current and
power data being read from the DPM is overranged and
meaningless.
TABLE 15. 0xD4 CONFIGURE ICHANNEL REGISTER DEFINITION
BIT
NUMBER D[15:14]
Bit
Name
N/A
Default
Value
00
D[13:10]
D[9:7]
D[6:3]
D[2:0]
Aux Shunt Aux Shunt Prim Shunt Prim Shunt
Sample Conversion Sample Conversion
Time
AVG
Time
AVG
00 00
11 1
000 0
111
SHUNT VOLTAGE CONVERSION TIME D[9:7], D[2:0]
The Shunt Voltage Conversion Time bits set the acquisition speed
of the ADC when measuring either the primary or auxiliary
voltage shunt channels of the DPM. The primary and auxiliary
VSHUNT channels have independent timing control bits allowing
for the primary VSHUNT channel to have a unique acquisition time
with respect to the auxiliary VSHUNT channel. Table 16 is a list of
the selectable VSHUNT ADC time settings. The shaded row
indicates the default setting.
TABLE 16. AUXILIARY/ PRIMARY VSHUNT CONVERSION TIMES DEFINED
Config_Ichannel: D[9:7],D[2:0]
0
0
64µs
0
0
1
128µs
0
1
0
256µs
0
1
1
512µs
1
0
X
1.024ms
1
1
X
2.048ms
SHUNT VOLTAGE SAMPLE AVERAGE D[13:10], D[6:3]
The Shunt Voltage Sample Average bits set the number of
averaging samples for a unique sampling time. The DPM will
record all samples and output the average resultant to the
respective VSHUNT register. The primary and auxiliary VSHUNT
channels have independent average settings allowing for the
primary VSHUNT channel to have a unique average setting with
33
The IOUT Calibration Gain register is a read/writable word
register that is used to calculate current and power
measurements for the primary channel of the DPM. When the
register is programmed, the DPM calculates the current and
power based on the primary channels VBUS and VSHUNT
measurements. The calculation resultant is stored in the
READ_IOUT and READ_POUT registers.
The calibration register value can be calculated as follows:
1. Calculate the full-scale current range that is desired. This can
be calculated using Equation 3.
Current FS
CONVERSION TIME
0
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0X38 IOUT CALIBRATION GAIN (R/W)
Vshunt FS
R shunt
(EQ. 3)
2. RSHUNT is the value of the shunt resistor. VshuntFS is the
full-scale range of the primary channel, which equals 80mV.
3. From the current full-scale range, the current LSB can be
calculated using Equation 4. Current full-scale is the outcome
from Equation 3. ADCres is the resolution of shunt voltage
reading. The output of the ADC is a signed 15-bit binary
number. Therefore, the ADCres value equals 215 or 32768.
Current LSB
Current FS
ADC res
(EQ. 4)
4. From Equation 4, the calibration resistor value can be
calculated using Equation 5. The resolution of the math that
is processed internally in the DPM is 2048 or 11 bits of
resolution. The VSHUNT LSB is set to 2.5µV. Equation 5 yields a
15-bit binary number that can be written to the calibration
register. The calibration register format is represented in
Table 18.
FN8389.4
June 17, 2015
ISL28023
CalRegval
 Math res Vshunt LSB 
integer 

  CurrentLSB Rshunt 
CalRegval
integer 
The default state of the register configures the auxiliary VSHUNT
input to measure the differential voltage across the AUXP and
AUXM inputs. The maximum measurable voltage that can be
applied to the inputs is 80mV.


Current

R
LSB shunt  

0.00512
(EQ. 5)
Setting the Ext Temp En bit to 1 activates the current sourcing
circuitry at the auxiliary VSHUNT input. Connecting a diode
between AUXP and AUXM will enable external temperature
measurement functionality.
TABLE 18. 0x38 IOUT_CAL_GAIN DEFINITION
BIT
NUMBER
D[15]
D[14:0]
Bit Name
N/A
IOUT_CAL_GAIN
Default Value
0
000 0000 0000 0000
SMBCLK
VBUS_Vsense
VBUS
I2C
SM BUS
PM BUS
VINP
To µC
SMBDAT
CM = 0 to 60V
VINM
The Configure Vchannel register is a read/writable word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage bus inputs.
A0
AUX_Vsense
AUXV
SW Mux
0XD5 CONFIGURE VCHANNEL (R/W)
ADC
16-BIT
A1
A2
EXT_TEMP_EN
TABLE 19. 0xD5 CONFIGURE VCHANNEL REGISTER DEFINITION
BIT
NUMBER
Bit Name
Default Value
20µA and/or 100µA
D[15:14] D[13:10]
N/A
D[9:7]
D[6:3]
D[2:0]
AuxV
Sample
AVG
AuxV
Conversion
Time
VBUS
Sample
AVG
VBUS
Conversion
Time
00 00
11 1
000 0
111
00
The ADC configuration of the sampling average and conversion
time settings for VBUS and AuxV channels have the same setting
choices as the VSHUNT primary and auxiliary channels.
0XD7 CONFIGURE PEAK DETECTOR (R/W)
The Configure Peak Detector register is a read/writable byte
register that toggles the minimum and maximum current
tracking feature. A Peak Detect Enable bit setting of 1 enables
the current peak detect feature of the DPM. The feature is
discussed in more detail in “0xD8 Read Peak Min IOUT (R)” on
page 35.
TABLE 20. 0xD7 CONFIGURE PEAK DETECTOR REGISTER DEFINITION
BIT
NUMBER
D[7:1]
D[0]
Bit Name
N/A
Peak Detect En
Default Value
0000 000
0
AUXP
CM = 0 to VCC
AUXM
FIGURE 98. SIMPLIFIED CIRCUIT DIAGRAM OF AN EXTERNAL
TEMPERATURE APPLICATION
The external temperature measurement mode forces two
currents (20µA/100µA) through the diode. The differential
voltage between the AUXP and AUXM pins for each current forced
are measured and stored by way of a sample and hold circuitry.
The timing for the two current measurement is 1µs. The
maximum voltage that can be measured between the auxiliary
Vshunt pins is ±VCC.
Upon completion of the two current measurements, the ADC
measures the difference between the two stored differential
voltage values. The measured value by the ADC yields the  Vbe
voltage for the two currents. The maximum  Vbe voltage that
the temperature circuit can measure is 80mV. The DPM stores
the measured value from the ADC in the READ_TEMPERATURE_1
register. Using Equation 2 to calculate the register signed integer
value, the  Vbe voltage can be calculated using Equation 6.
0XE2 CONFIGURE EXCITATION (R/W)
Vbe
The Configure Excitation register is a read/writable byte register
that changes the measurement functionality of the auxiliary
VSHUNT input.
Registervalue is the READ_TEMPERATURE_1 signed integer
value. The Aux_VshuntLSB equals 10µV.
TABLE 21. 0xE2 CONFIGURE EXCITATION REGISTER DEFINITION
BIT NUMBER
D[15:1]
D[0]
Bit Name
N/A
Ext Temp En
Default Value
0000 0000 0000 000
0
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34
Register Value Aux_Vshunt LSB
(EQ. 6)
Equation 7 yields the absolute temperature from the current
measurements.
T
 q   
 n  k  




  273
 I 2  
ln 
 
 I 1  
Vbe
(EQ. 7)
FN8389.4
June 17, 2015
ISL28023
The  Vbe value calculated in Equation 6 is used to calculate the
temperature in centigrade (°C).
from VSHUNT and the IOUT_CAL_GAIN register. Equation 10
yields the current for the primary channel.
The value of the two currents that are sourced from the part
during the temperature measurement are 100µA and 20µA. I2
equal 100µA. The variable k is Boltzmann constant equal to
1.3806503*10-23m2kg/S2. The variable q is the electron
charge constant equal to = 1.6*10-19C. The variable n is the
ideality factor of the temperature diode. A typical value is near 1.
Current
The external temperature feature is a function of the Auxiliary
VSHUNT conversion time as well as converter averaging. The
settings for the aforementioned registers directly impacts the
accuracy of the measurement and the timing.
Register value Current LSB
(EQ. 10)
The Registervalue is calculated using Equation 2 on page 31. The
CurrentLSB is calculated using Equation 4 on page 33.
0XD8 READ PEAK MIN IOUT (R)
0XD9 READ PEAK MAX IOUT (R)
ENTERING\EXITING THE EXTERNAL TEMPERATURE
MODE
Writing a 1 to D[0] of register 0xE2 will not configure the Aux
inputs to external temperature sense mode. The following series
of commands need to be sent to enable external temperature
sense functionality.
1. Power-down the ADC -- Set BitD[6] of register 0xD2 to 1.
2. Enable the Ext Temp bit -- Set BitD[0] of register 0xDE2 to 1.
3. Power ADC + and set measurement mode to temperature-Set BitD[6] to 0 and set Bits[D2:0] to 6 for register 0xD2.
The external temperature feature is functional in both trigger and
continuous modes. Undoing the series of commands listed above
will exit the external temperature mode.
0XD6 READ VSHUNT OUT (R)
The Read VSHUNT Out register is a readable word register that
stores the signed measured digital value of the primary VSHUNT
input of the DPM. Using Equation 2 to calculate the integer value
of the register, Equation 8 calculates the floating point measured
value for the primary VSHUNT channel.
Register value vshunt LSB
(EQ. 8)
VshuntLSB is the numerical weight of each level for the VSHUNT
channel, which equals 2.5µV.
0X8B READ VOUT (R)
The Read VOUT register is a readable word register that stores the
unsigned measured digital value of the primary VBUS input of the
DPM. Using Equation 1 to calculate the integer value of the
register, Equation 9 calculates the floating point measured value
for the primary VBUS channel.
Vbus
Register value vbus LSB
The Read Peak Min/Max IOUT registers are readable word
registers that store the minimum and maximum current value of
an averaging cycle for the current passing through the primary
shunt.
The min/max current tracking is enabled by setting the Peak
Detect Enable bit in the CONFIG_PEAK_DET (0xD7) register. The
current peak detect feature only works for the current register.
Measurement Registers
Vshunt
FIGURE 99. THE ISL28023 TRACKS MINIMUM AND MAXIMUM
AVERAGE CURRENT READINGS
(EQ. 9)
VbusLSB is the numerical weight of each level for the VBUS
channel. The VbusLSB equals 1mV for the 60V version of the
DPM and 250µV for the 12V version of the DPM.
0X8C READ IOUT (R)
At the conclusion of each primary channel current, the DPM will
record and store the minimum and maximum values of the
current measured. The feature operates for both the trigger and
continuous modes. Disabling the Peak Detector Enable bit will
turn off the feature as well as clear the Read Peak Min/Max IOUT
registers.
0X96 READ POUT (R)
The Read POUT register is a signed readable word register that
reports the digital value of the power from the primary channel.
The register uses the values from READ_IOUT and
READ_VSHUNT_OUT registers to calculate the power.
The units for the power register are in watts. The power can be
calculated using Equation 11.
Power
Register value  Power LSB  40000
(EQ. 11)
The Registervalue is calculated using Equation 2. The PowerLSB
can be calculated from Equation 12.
Power LSB
Current LSB Vbus LSB
(EQ. 12)
The VBUSLSB equals 1mV for the 60V version of the DPM and
250µV for the 12V version of the DPM. The CurrentLSB is the
value yielded from Equation 4 on page 33.
The Read IOUT register is a readable word register that stores the
signed measured digital value of the current passing through the
primary channel’s shunt. The register uses the measured value
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June 17, 2015
ISL28023
0XE0 READ VSHUNT OUT AUX (R)
The Read VSHUNT Out Aux register is a readable word register
that stores the signed measured digital value of the auxiliary
VSHUNT input. Use Equation 2 to calculate the integer value of the
register, Equation 13 calculates the floating point measured
value for the auxiliary VSHUNT channel.
Vshunt_aux
Register value vshunt_aux LSB
(EQ. 13)
Vshunt_auxLSB is the numerical weight of each level for the
auxiliary VSHUNT channel. The Vshunt_auxLSB equals 2.5µV.
0XE1 READ VOUT AUX (R)
The Read VOUT Aux register is a readable word register that
stores the unsigned measured digital value of the auxiliary VBUS
input of the DPM. Using Equation 1 to calculate the integer value
of the register, Equation 14 calculates the floating point
measured value for the auxiliary VBUS channel.
Vbus
Register value vbus LSB
(EQ. 14)
VBUSLSB is the numerical weight of each level for the auxiliary
VBUS channel. The auxiliary VBUSLSB equals 100µV. The voltage
range for the auxiliary VBUS is 0 to VCC.
0X8D READ TEMPERATURE (R)
The read temperature register is a readable word register that
reports out the internal temperature of the chip. The register is a
16-bit signed register. Bit15 of the register is the signed bit. The
register value can be calculated using Equation 15.
Register Value
 14

 Bit_Val  2n     Bit_Val  215 

n  
15




n
0



(EQ. 15)
n is the bit position within the register value. Bit_Val is the value
of the bit either 1 or 0. The register value multiplied by 0.016
yields the internal temperature reading in Centigrade (°C).
FIGURE 100. SIMPLIFIED BLOCK DIAGRAM OF THE THRESHOLD
FUNCTIONS WITHIN THE DPM
0XDA VOUT OV THRESHOLD SET (R/W)
The VOUT OV Threshold Set register is a read writable word
register that controls the threshold voltage level to the
overvoltage comparator. The description of the functionality
within this register is found in Table 22.
The compared reference voltage level to the OV comparator is
generated from a 6-bit DAC. The 6-bit DAC has 4 or 6 voltage
ranges to improve detection voltage resolution for a specific
voltage range.
TABLE 22. 0xDA VOUT OV THRESHOLD SET REGISTER DEFINITION
BIT NUMBER D[15:10]
Threshold Detectors
The DPM has three integrated comparators that allow for real
time fault detection of overvoltage, undervoltage for the primary
VBUS input and an overcurrent detection for the primary VSHUNT
input. An over-temperature detection is available by multiplexing
the input to the overvoltage comparator.
Bit Name
N/A
Default Value 0000 00
D[9]
D[8:6]
D[5:0]
OV_OT SEL Vbus_Thres_Ryng Vbus_OV_OT_Set
0
0 00
11 1111
OV_OT_SEL D[9]
The OV_OT_SEL bit configures the multiplexer to the input of the
OV comparator to either compare for over-temperature or
overvoltage. Setting the OV_OT_SEL to a 1 configures the OV
comparator to detect for an over-temperature condition.
VBUS_THRES_RNG D[8:6]
The Vbus_Thres_Rng bits sets the threshold voltage range for the
overvoltage and undervoltage DACs. There are 6 selectable
ranges for the 60V version of the DPM. Only 4 selectable ranges
for the 12V version of the DPM. Table 23 defines the range
settings for the VBUS threshold detector. The yellow shaded row
denotes the default setting.
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FN8389.4
June 17, 2015
ISL28023
The temperature threshold reference level has one range setting
which equals +125°C at full-scale.
TABLE 23. Vbus_Thres_Rng BITS DEFINED
Vbus_Thres_Rng: D[8:6]
Vbus_12V
(RANGE)
Vbus_60V
(RANGE)
0
0
0
12
48
0
0
1
6
24
VBUS_UV_SET D[4:0]
The Vbus_UV_Set bits control the undervoltage level to the input
of the UV comparator. The LSB of the DAC is 1.56% of the
full-scale range chosen using the Vbus_Thres_Rng bits.
The undervoltage ranges from 0% to 100% of the full-scale range
set by the Vbus_Thres_Rng bits.
TABLE 26. Vbus_UV_Set BITS DEFINED
0
1
0
3
12
Vbus_UV_Set: D[5:0]
0
1
1
1.25
5
00 0000
0%
1
0
0
X
3.3
00 0001
1.56% of FS
00 0010
3.12% of FS
...............
....................
1
0
1
X
2.5
UV THRESHOLD VALUE
VBUS_OV_OT_SET D[5:0]
11 1101
(100 - 4.68)% of FS
The Vbus_OV_OT_Set bits controls the voltage/temperature level
to the input of the OV comparator. The LSB of the DAC is 1.56%
of the full-scale range chosen using the Vbus_Thres_Rng bits. For
the temperature feature, the LSB for the temperature level is
5.71°C. The mathematical range is -144°C to +221.4°C.
11 1110
(100 - 3.12)% of FS
11 1111
(100 - 1.56)% of FS
The overvoltage range starts at 25% of the full-scale range
chosen using the Vbus_Thres_Rng bits and ends at 125% of the
chosen full-scale range. The same range applies to the
temperature measurements.
TABLE 24. Vbus_OV_OT_Set BITS DEFINED
Vbus_OV_OT_Set: D[5:0] OV THRESHOLD VALUE OT THRESHOLD VALUE
00 0000
25% of FS
-144
00 0001
(25 + 1.56)% of FS
-138.3
00 0010
(25 + 3.12)% of FS
-132.6
...............
....................
....................
11 1101
(125 to 4.68)% of FS
210
11 1110
(125 to 3.12)% of FS
215.7
11 1111
(125 to 1.56)% of FS
221.4
Table 24 defines an abbreviated breakdown to set the OV/OT
comparator level. The shaded row is the default condition.
0XDB VOUT UV THRESHOLD SET (R/W)
The VOUT UV Threshold Set register is a read writable byte
register that controls the threshold voltage level to the
undervoltage comparator. The description of the functionality
within this register is found in Table 25.
The compared reference voltage level to the UV comparator is
generated from a 6-bit DAC. The 6-bit DAC has 4 to 6 voltage
ranges that are determined by the Vbus_Thres_Rng bits in the
VOUT OV Threshold Set register.
TABLE 25. 0xDB VOUT UV THRESHOLD SET REGISTER DEFINITION
BIT NUMBER
D[7:6]
D[5:0]
Bit Name
N/A
Vbus_UV_Set
Default Value
00
00 0000
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Table 26 defines an abbreviated breakdown to set the
undervoltage comparator levels. The shaded row is the default
condition.
0XDC IOUT OC THRESHOLD SET (R/W)
The IOUT OC Threshold Set register is a read/writable word
register that controls the threshold current level to the
overcurrent comparator. The description of the functionality
within this register is found in Table 27.
TABLE 27. 0xDC IOUT OC THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER
D[15:10]
D[9]
D[8:7]
D[6]
D[5:0]
Bit Name
N/A
Iout_Dir
N/A
VSHUNT
Thres
Rng
Vshunt_OC_Set
Default
Value
0000 00
0
00
0
11 1111
The overcurrent threshold is defined through the VSHUNT reading.
The product of the current through the shunt resistor defines the
VSHUNT voltage to the DPM. The current through the shunt
resistor is directly proportional the VSHUNT voltage measured by
the DPM. An overvoltage threshold for VSHUNT is the same as an
overcurrent threshold.
IOUT_ DIR D[9]
The Iout_Dir bit controls the polarity of the VSHUNT voltage
threshold. The bit functionality allows an overcurrent threshold to
be set for currents flowing from VINP to VINM and the reverse
direction. Table 28 defines the range settings for the VBUS
threshold detector. The yellow shaded row denotes the default
setting.
TABLE 28. Vbus_Thres_Rng BITS DEFINED
Iout_Dir: D[9]
CURRENT DIRECTION
0
VINP to VINM
1
VINM to VINP
FN8389.4
June 17, 2015
ISL28023
VSHUNT_THRES_RNG D[6]
TABLE 30. Vshunt_OC_Set BITS DEFINED
The Vshunt_Thres_Rng bit sets the overvoltage threshold range
for the overcurrent DAC. The selectable VSHUNT range improves
the overvoltage threshold resolution for lower full-scale current
applications. Table 29 defines the range settings for the VBUS
threshold detector. The yellow shaded row denotes the default
setting.
Vshunt_OC_Set: D[5:0]
OC THRESHOLD VALUE
00 0000
25% of FS
00 0001
(25 + 1.56)% of FS
00 0010
(25 + 3.12)% of FS
TABLE 29. Vshunt_Thres_Rng BIT DEFINED
Vshunt_Thres_Rng: D[6]
VSHUNT (RANGE)
0
80mV
1
40mV
VSHUNT_OC_SET D[5:0]
The Vshunt_OC_Set bits control the VSHUNT voltage level to the
input of the OC comparator. The LSB of the DAC is 1.56% of the
full-scale range chosen using the Vshunt_Thres_Rng bits.
The overvoltage range starts at 25% of the full-scale range
chosen using Vbus_Thres_Rng bits and ends at 125% of the
chosen full-scale range.
...............
....................
11 1101
(125 - 4.68)% of FS
11 1110
(125 - 3.12)% of FS
11 1111
(125 - 1.56)% of FS
SMB Alert
The DPM has two alert pins (SmbAlert1, SmbAlert2) to alert the
peripheral circuitry that a failed event has occurred. SmbAlert1
output is an open drain allowing the user the flexibility to connect
the alert pin to other components requiring different logic
voltage levels than the DPM. The SmbAlert2 has a push/pull
output stage for driving pins with logic voltage levels equal to the
voltage applied to I2CVCC pin. The push/pull output is useful for
driving peripheral components that require the DPM to source
and sink a current. The alert pins are commonly connected to an
interrupt pin of a microcontroller or an enable pin of a device.
The SMB Alert registers control the functionality of the SMB Alert
pins. The threshold comparators are the inputs to the SMB Alert
registers. The outputs are the SMB Alert pins. Figure 101 is a
simple functional block diagram of the SMB Alert features.
FIGURE 101. SIMPLIFIED BLOCK DIAGRAM OF THE SMB ALERT FUNCTIONS WITHIN THE DPM
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0XDD CONFIGURE INTERRUPTS (R/W)
The Configure Interrupt register is a read/writable word register
that controls the behavior of the two SMB alert pins. The
definition of the control bits within the Configure Interrupt
register is defined in Table 31.
UV_FIL D[6:5]
TABLE 31. 0xDD CONFIGURE INTERRUPT REGISTER DEFINITION
BIT
NUMBER
D
[15]
D
[14:12]
Bit Name N/A ALERT2
FeedTh
Default
Value
0
000
D
[11:9]
D
D
D
D D D
[8:7] [6:5] [4:3] [2] [1] [0]
ALERT1
FeedTh
OC
FIL
OV
FIL
UV
FIL
000
00
00
00
OC OV UV
EN EN EN
0
0
0
ALERT2_FEEDTHR D[14:12]
The Alert2_FeedThr bits determine whether the bit from each
alert comparator is digitally conditioned or not. The alert
comparators, digital filters and latching bits are the same for
both SMB alert channels. Table 32 defines the functionality of
the Alert2_FeedThr bits.
TABLE 32. Alert2_FeedThr BITS DEFINED
Alert2_FeedThr BITS
D[14:12]
D[14]
0
D[13]
1
D[13]
2
BIT VAL
FUNCTIONALITY
0
OV/OT Digitally Conditioned
1
OV/OT Pass Through
0
UV Digitally Conditioned
1
UV Pass Through
0
OC Digitally Conditioned
1
OC Pass Through
ALERT1_FEEDTHR D[11:9]
The Alert1_FeedThr bits determine whether the bit from each
alert comparator is digitally conditioned or not. The alert
comparators, digital filters and latching bits are the same for
both SMB alert channels. Table 33 defines the functionality of
the Alert1_FeedThr bits.
TABLE 33. Alert1_FeedThr BITS DEFINED
Alert1_FeedThr Bits D[11:9] BIT VAL
D[11]
D[10]
D[9]
0
1
2
requires an error event to be at least 8µs in duration before
passing the result to the SMB alert pins. There is one OC digital
filter for both SMB alert pins. Configuring OC_FIL bits will change
the OC digital filter setting for both SMB alert pins. See Table 34
for the filter selections.
FUNCTIONALITY
0
OV/OT Digitally Conditioned
1
OV/OT Pass Through
0
UV Digitally Conditioned
1
UV Pass Through
0
OC Digitally Conditioned
1
OC Pass Through
OC_FIL D[8:7]
The UV_FIL bits control the digital filter for the undervoltage
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
requires an error event to be at least 8µs in duration before
passing the result to the SMB alert pins. There is one UV digital
filter for both SMB alert pins. Configuring UV_FIL bits will change
the UV digital filter setting for both SMB alert pins. See Table 34
for the filter selections.
OV_FIL D[4:3]
The OV_FIL bits control the digital filter for the overvoltage
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
requires an error event to be at least 8µs in duration before
passing the result to the SMB alert pins. There is one OV digital
filter for both SMB alert pins. Configuring OV_FIL bits will change
the OV digital filter setting for both SMB alert pins. See Table 34
for the filter selections.
TABLE 34. DIGITAL GLITCH FILTER SETTINGS DEFINED
OC_FIL D[8:7]
UV_FIL D[6:5]
OV_FIL D[4:3]
FILTER TIME
(µs)
0
0
0
0
1
2
1
0
4
1
1
8
OC_EN D[2]
The OC_EN enable bit controls the power to the overcurrent DAC
and comparator. Setting the bit to 1 enables the overcurrent
circuitry.
OV_EN D[1]
The OV_EN enable bit controls the power to the overvoltage DAC
and comparator. Setting the bit to 1 enables the overvoltage
circuitry.
UV_EN D[0]
The UV_EN enable bit controls the power to the undervoltage DAC
and comparator. Setting the bit to 1 enables the undervoltage
circuitry.
The OC_FIL bits control the digital filter for the overcurrent
circuitry. The digital filter will prevent short duration events from
passing to the output pins. The filter is useful in preventing high
frequency power glitches from triggering a shutdown event. The
filter time delay ranges from 0µs to 8µs. An 8µs filter setting
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ISL28023
0XDE FORCE FEEDTHROUGH ALERT REGISTER (R/W)
VOUT OV WARNING D[6]
The Force Feedthrough Alert Register is a read/writable byte
register that controls the polarity of the interrupt. The definition
of the control bits within the Force Feedthrough Alert register is
defined in Table 35.
TABLE 35. 0xDE FORCE FEEDTHROUGH ALERT REGISTER DEFINITION
The VOUT OV Warning bit is set to 1 when an overvoltage fault
occurs on the VBUS input. The VBUS overvoltage threshold is set
from the VOUT OV Threshold Set register. In the event of a VBUS
overvoltage condition, the VOUT OV Warning is latched to 1.
Writing a 1 to the VOUT OV Warning bit will clear the warning
resulting in a bit value equal to 0.
BIT
NUMBER
D[7:4]
D[3]
D[2]
D[1]
D[0]
VOUT UV WARNING D[5]
Bit Name
N/A
A2POL
A1POL
FORCE A2
FORCE A1
Default
Value
0000
0
0
0
0
A2POL D[3], A2POL D[2]
The AxPOL bits control the polarity of an interrupt. A2POL bit
defines the SMBALERT2 pin active interrupt state. A1POL bit
defines the SMBALERT1 pin active interrupt state. Table 36
defines the functionality of the bit.
TABLE 36. AxPol BIT DEFINED
The VOUT UV Warning bit is set to 1 when an undervoltage fault
occurs on the VBUS input. The VBUS undervoltage threshold is set
from the VOUT UV Threshold Set register. In the event of a VBUS
undervoltage condition, the VOUT UV Warning is latched to 1.
Writing a 1 to the VOUT UV Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7B STATUS IOUT (R/W)
The Status IOUT register is a read/writable byte register that
reports an overcurrent warning for the VSHUNT input.
TABLE 39. 0x7B STATUS IOUT REGISTER DEFINITION
A2POL D[3], A1POL D[2]
INTERRUPT
ACTIVE STATE
0
low
1
high
BIT NUMBER
D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
N/A
IOUT OC
Warning
N/A
Default
Value
0
0
0
0 0000
FORCEA2 D[1], FORCEA1 D[0]
The FORCEAx bits allow the user to force an interrupt by setting
the bit. FORCEA2 bit controls the SMBALERT2 pin state.
FORCEA1 bit controls the SMBALERT1 pin state. Table 37 defines
the functionality of the bit.
TABLE 37. FORCEAx BIT DEFINED
FORCEA2 D[1], FORCEA1 D[0]
INTERRUPT STATUS
0
Normal
1
Interrupt Forced
0X03 CLEAR FAULTS (S)
The Clear Faults register is a send byte command that clears all
faults pertaining to the status registers. Upon execution of the
command, the status registers return to the default state defined
in Table 2.
0X7A STATUS VOUT (R/W)
The Status VOUT register is a read/writable byte register that
reports over and undervoltage warnings for the VBUS input.
TABLE 38. 0x7A STATUS VOUT REGISTER DEFINITION
BIT NUMBER
D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
VOUT OV
Warning
VOUT UV
Warning
N/A
Default
Value
0
0
0
0 0000
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IOUT OC WARNING D[5]
The IOUT OC Warning bit is set to 1 when an overcurrent fault
occurs on the VSHUNT input. The VSHUNT overcurrent threshold is
set from the IOUT OC Threshold Set register. In the event of a
VSHUNT overcurrent condition, the IOUT OC Warning is latched
to 1. Writing a 1 to the IOUT OC Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7D STATUS TEMPERATURE (R/W)
The Status Temperature register is a read/writable byte register
that reports an over-temperature warning initiated from the
internal temperature sensor.
TABLE 40. 0x7D STATUS TEMPERATURE REGISTER DEFINITION
BIT NUMBER
D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
OT
Warning
N/A
N/A
Default Value
0
0
0
0 0000
OT WARNING D[6]
The OT Warning bit is set to 1 when an over-temperature fault
occurs from the internal temperature sensor. The
over-temperature threshold is set from the VOUT OV Threshold
Set register. In the event of an over-temperature condition, the OT
Warning bit is latched to 1. Writing a 1 to the OT Warning bit will
clear the warning resulting in a bit value equal to 0.
FN8389.4
June 17, 2015
ISL28023
0X7E STATUS CML (R/W)
TEMPERATURE D[2]
The Status CML register is a read/writable byte register that
reports warnings and errors associated with communications,
logic and memory.
The Temperature bit is set to 1 when an over-temperature fault
occurs from the internal temperature sensor. This bit is the same
action bit as the OT Warning bit in the Status Temperature
register. The over-temperature threshold is set from the VOUT OV
Threshold Set register. In the event of an over-temperature
condition, the Temperature bit is latched to 1. Writing a 1 to the
Temperature bit will clear the warning resulting in a bit value
equal to 0.
TABLE 41. 0x7E STATUS CML REGISTER DEFINITION
BIT NUMBER
Bit Name
D[7]
D[6]
USCMD USDATA
Default Value
0
0
D[5]
D[4:2]
PECERR
N/A
0
0 00
D[1]
D[0]
COMERR N/A
0
0
USCMD D[7]
The USCMD bit is set to 1 when an unsupported command is
received from the I2C master. Reading from an undefined
register is an example of an action that would set the USCMD bit.
The USCMD bit is a latched bit. Writing a 1 to the USCMD bit
clears the warning resulting in a bit value equal to 0.
USDATA D[6]
The USDATA bit is set to 1 when an unsupported data is received
from the I2C master. Writing a word to a byte register is an
example of an action that would set the USDATA bit. The USDATA
bit is a latched bit. Writing a 1 to the USDATA bit clears the
warning resulting in a bit value equal to 0.
PECERR D[5]
The PECERR bit is set to 1 when a packet error check (PEC) event
has occurred. Writing the wrong PEC to the DPM is an example of
an action that would set the PECERR bit. The PECERR bit is a
latched bit. Writing a 1 to the PECERR bit clears the warning
resulting in a bit value equal to 0.
COMERR D[1]
The COMERR bit is set to 1 for communication errors that are not
handled by the USCMD, USDATA and PECERR errors. Reading
from a write only register is an example of an action that would
set the COMERR bit. The COMERR bit is a latched bit. Writing a 1
to the COMERR bit clears the warning resulting in a bit value
equal to 0.
0X78 STATUS BYTE (R/W)
The Status Byte register is a read/writable byte register that is a
hierarchal register to the Status Temperature and Status CML
registers. The Status Byte registers bits are set if an over
temperature or a CML error has occurred.
BIT NUMBER
D[7]
D[6:3]
D[2]
D[1]
D[0]
Bit Name
BUSY
N/A
Temperature
CML
N/A
Default Value
0
000 0
0
0
0
BUSY D[7]
The BUSY bit is set to 1 when the DPM is busy and unable to
respond. The BUSY bit is a latched bit. Writing a 1 to the BUSY bit
clears the warning resulting in a bit value equal to 0.
41
The CML bit is set to 1 when any errors occur within the Status
CML register. There are four Status CML error bits that can set
the CML bit. The CML bit is a latched bit. Writing a 1 to the CML
bit clears the warning resulting in a bit value equal to 0.
0X79 STATUS WORD (R/W)
The Status Word register is a read writable word register that is a
hierarchal register to the Status VOUT, Status IOUT and Status
Byte registers. The Status Word registers bits are set when any
errors previously described occur. The register generically reports
all errors.
TABLE 43. 0x79 STATUS WORD REGISTER DEFINITION
BIT NUMBER
D[15]
D[14]
D[13:8]
D[7:0]
Bit Name
VOUT
IOUT
N/A
See Status Byte
Default
Value
0
0
00 0000
0000 0000
VOUT D[15]
The VOUT bit is set to 1 when any errors occur within the Status
VOUT register. Whether either or both an undervoltage or
overvoltage fault occurs, the VOUT bit will be set. The VOUT bit is a
latched bit. Writing a 1 to the VOUT bit clears the warning
resulting in a bit value equal to 0.
IOUT D[14]
The IOUT bit is set to 1 when an overcurrent fault occurs. This bit
is the same action bit as the IOUT OC Warning bit in the Status
IOUT register. In the event of an overcurrent condition, the IOUT bit
is latched to 1. Writing a 1 to the IOUT bit will clear the warning
resulting in a bit value equal to 0.
0X1B SMBALERT MASK (BR/BW)
0XDF SMBALERT2 MASK (BR/BW)
TABLE 42. 0x78 STATUS BYTE REGISTER DEFINITION
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CML D[1]
The SMBALERT registers are block read/writable registers that
mask error conditions from electrically triggering the respective
SMBALERT pin.
The SMBALERT can mask bits of any of the status registers.
Masking lower level bits prevents hierarchal bit from being set.
For example, a COMERR bit being masked will not set the CML
bit of the Status Byte register.
To mask a bit, the first data byte is the register address of the
bit(s) to be masked. The second and third data bytes are the
masking bits of the register. A masking bit of 1 prevents the
signal from triggering an interrupt.
FN8389.4
June 17, 2015
ISL28023
All alert bits are masked as the default state for both the SMB
alert pins. The master needs to send instructions to unmask the
alert bits.
As an example, a user would like to allow the COMERR bit to
trigger a SMBALERT2 interrupt while masking the rest of the
alerts within the Status CML register. The command that is sent
from the master to the DPM is the slave address, SMBALERT2
register address, Status CML register address and the mask bit
value. In a hexadecimal format, the data sent to the DPM is as
follows; 0x80 DF 7E FD.
To read the mask status of any alert register, a four byte write
command, without PEC, consisting of the slave address of the
device, the SMB mask register address, the number of bytes to
be read back and the register address of the mask to be read.
Once the write command has commenced, a read command
consisting of the device slave address and the register address of
the SMB mask will return the mask of the desired alert register.
As an example, a user would like to read the status of the Status
Byte register. The first command sent to the DPM is in
hexadecimal bytes is 0x82 1B 01 78. The second command is a
standard read. The slave address is 0x83 (0x82 + read bit set)
and the register address is 0x1B.
SMBALERT1 RESPONSE ADDRESS
It is common that the SMBALERT1 pin of each ISL28023 device
is shared to a single GPIO pin of the microcontroller. The
SMBALERT1 pin is an open drain allowing for multiple devices to
be OR’ed to a single GPIO pin.
External Clock Control
The DPM has an external clock feature that allows the chip to be
synchronized to an external clock. The feature is useful in limiting
the number of clocks running asynchronously within a system.
0XE5 CONFIGURE EXTERNAL CLOCK (R/W)
The Configure External Clock register is a read writable byte
register that controls the functionality of the external clock
feature.
TABLE 44. 0xE5 CONFIGURE EXTERNAL CLOCK REGISTER DEFINITION
BIT NUMBER
Bit Name
D[7]
D[6]
ExtCLK_EN SMBLALERT2
OEN
Default
Value
0
0
D[5:4}
D[3:0]
N/A
EXTClkDIV
00
0000
EXTCLK_EN D[7]
The ExtClk_EN bit enables the external clock feature. The
ExtClk_En default bit setting is 0 or disabled. A bit setting of 1
disables the internal oscillator of the DPM and connects circuitry
such that the system clock is routed from the external clock pin.
SMBALERT2_OEN D[6]
The SMBALERT2_OEN bit within the Configure External Clock
register either enables or disables the buffer that drives the
SMBALERT2 pin.
TABLE 45. SMBALERT2_OEN BIT DEFINED
The SMBALERT1 Response Address command reports the slave
address of the device that has triggered alert. The SMB Respond
Address command is shown in Figure 102.
SMBALERT_OEN
SMBALERT2 STATUS
0
Disabled
1
Enabled
EXTCLKDIV D[3:0]
The EXTCLKDIV bits control an internal clock divider that is useful
for fast system clocks. The internal clock frequency from pin to
chip is represented in Equation 16.
FIGURE 102. THE COMMAND STRUCTURE OF THE SMBALERT
RESPONSE ADDRESS
The alert response address is 0x18. In the event of multiple
alerts pulling down the GPIO line, the alert respond command
will return the lowest slave address that is connected to the I2C
bus. Upon clearing the lowest slave address alert, the alert
command will return the lowest slave address of the remaining
alerts that are activated.
The alert response is operable when the interrupt active state is
forced low by the device at the SMBALERT1 pin. Changing
SMBALERT1 interrupt polarity or forcing an interrupt will enable
the alert response. By design, the open drain of the SMBALERT1
pin allows for ANDing of the interrupt via a pull-up resistor. The
alert response command is valid for only the SMBALERT1 pin.
The alert response command will return a 0x19 when there are
no errors that are detected.
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freq internal
f EXTCLK
( ClkDiv 8)  8
(EQ. 16)
fEXTCLK is the frequency of the signal driven to the External Clock
pin. ClkDiv is the decimal value of the clock divide bits.
Voltage Margin
The voltage margining feature within the DPM is commonly used
as a means of testing the robustness of a system. The voltage
DAC from the DPM is connected to a summation circuit allowing
the voltage sourced from the DAC to raise or lower the overall
voltage supply to system. A simplified block diagram is
illustrated in Figure 103.
FN8389.4
June 17, 2015
ISL28023
LOAD D[2]
The Load bit programs the Set VOL Margin register to the DAC.
The DAC is programmed when the Load bit is programmed from
a 0 to a 1.
DAC_OEN D[1]
The DAC_OEN bit either enables or disables the output of the
margin DAC. Setting the bit to a 1 connects the output of the
margin DAC to the DAC_OUT pin.
DAC_EN D[0]
FIGURE 103. SIMPLIFIED BLOCK DIAGRAM OF THE MARGIN DAC
FUNCTIONS WITHIN THE DPM
The voltage margining feature can be used to improve accuracy
of the voltage applied to the load of a system. For nonfeedback
driving applications, the sense resistor used to measure current
to the load reduces the voltage to the load. The voltage drop from
the sense resistor can be a large percentage with respect to the
supply voltage for point of load applications.
0XE4 CONFIGURE VOL MARGIN (R/W)
The Configure VOL Margin register is a read/writable byte
register that controls the functionality of the voltage margin DAC.
The DAC_EN bit either enables or disables the margin DAC
circuitry. Setting the bit to a 1 powers up the margin DAC making
it operational to use.
0XE3 SET VOL MARGIN (R/W)
The Set VOL Margin register is an unsigned read/writable byte
register that controls the output voltage of the margin DAC
referenced to the half-scale setting.
TABLE 48. 0xE3 SET VOL MARGIN REGISTER DEFINITION
BIT NUMBER
D[7:0]
Bit Name
MDAC[7:0]
Default
Value
0000 0000
TABLE 46. 0xE4 CONFIGURE VOL MARGIN REGISTER DEFINITION
BIT NUMBER
D[7:6]
D[5:3]
D[2]
D[1]
D[0]
Bit Name
N/A
MDAC_HS
Load
DAC_OEN
DAC_EN
Default
Value
00
00 0
0
0
0
MDAC_HS D[5:3]
MDACLSB
The MDAC_HS bits control the half-scale output voltage from the
margin DAC. There are 8 half-scale voltages the margin DAC can
be programmed to. Table 47 lists the selections.
TABLE 47. MDAC_HS BITS DEFINED
MDAC_HS[2:0]
The full-scale voltage is twice the half-scale range minus the DAC
LSB for the margin DAC half-scale range. A half-scale setting of
1.0V has a full-scale setting of 1.992V. The LSB for the margin
DAC is a function of the half-scale setting. Using Equation 17, the
LSB for the margin DAC is calculated as;
HALF-SCALE VOLTAGE (V)
0
0
0
0.4
0
0
1
0.5
0
1
0
0.6
0
1
1
0.7
1
0
0
0.8
1
0
1
0.9
1
1
0
1.0
1
1
1
1.2
 2 MDACHS
2 MDACHS
8
256
2
(EQ. 17)
MDACHS is the half-scale setting for the voltage DAC.
The VOL margin register value for programming the DAC to a
specific voltage is calculated using Equation 18.
MDACvalue
 Voutdesired 

 MDACLSB 
integer 
(EQ. 18)
The value for VOUTdesired ranges from 0V to two times the
MDACHS value minus one MDACLSB.
The voltage at the DAC_OUT is the value of the MDAC_HS setting
when the Set VOL Margin register equals 0x80.
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June 17, 2015
ISL28023
SMBus/I2C Serial Interface
All I2C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 104). A START condition is ignored
during the power-up sequence.
The ISL28023 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28023 operates as a slave device in all
applications.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW-to-HIGH transition of SDA while SCL is
HIGH (see Figure 104). A STOP condition at the end of a read
operation or at the end of a write operation places the device in its
standby mode.
The ISL28023 uses two bytes data transfer, all reads and writes
are required to use two data bytes. All communication over the
I2C interface is conducted by sending the MSByte of each byte of
data first, followed by the LSByte.
SMBus, PMBus Support
The ISL28023 supports SMBus and PMBus protocol, which is a
subset of the global I2C protocol. SMBCLK and SMBDAT have the
same pin functionality as the SCL and SDA pins, respectively. The
SMBus operates at 100kHz. The PMBus protocol standardizes
the functionality of each register by address.
Protocol Conventions
For normal operation, data states on the SDA line can change
only during SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating START and STOP conditions (see
Figure 104). On power-up, the SDA pin is in the input mode.
SCL
SDA
DATA
STABLE
START
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 104. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 105. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
WRITE
ADDRESS
BYTE
IDENTIFICATION
BYTE
1 n n n n n n 0
SIGNALS FROM
THE ISL28023
S
T
O
P
DATA
BYTE
DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 106. BYTE WRITE SEQUENCE (SLAVE ADDRESS INDICATED BY nnnnnn)
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FN8389.4
June 17, 2015
ISL28023
Device Addressing
Following a start condition, the master must output a slave
address byte. The 7 MSBs are the device identifiers. The A0, A1
and A2 pins control the bus address (these bits are shown in
Table 49). There are 55 possible combinations depending on the
A0, A1 and A2 connections.
The last bit of the slave address byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 102).
After loading the entire slave address byte from the SDA bus, the
device compares with the internal slave address. Upon a correct
compare, the device outputs an acknowledge on the SDA line.
TABLE 49. I2C SLAVE ADDRESSES
A2
A1
A0
SLAVE ADDRESS
GND
GND
GND
1000 000
GND
GND
I2CVCC
1000 001
GND
GND
SDA
1000 010
GND
GND
SCL
1000 011
GND
I2CVCC
GND
1000 100
GND
I2CVCC
I2CVCC
1000 101
GND
I2CVCC
SDA
1000 110
GND
I2CVCC
SCL
1000 111
GND
SDA
GND
1001 000
GND
SDA
I2CVCC
1001 001
GND
SDA
SDA
1001 010
GND
SDA
SCL
1001 011
GND
SCL
GND
1001 100
GND
SCL
I2CVCC
1001 101
GND
SCL
SDA
1001 110
GND
SCL
SCL
1001 111
I2CVCC
GND
GND
1010 000
...............
..............
..............
..................
I2CVCC
SCL
SCL
1011 111
SDA
GND
GND
1100 000
SDA
GND
VCC
Do Not Use. Reserved
...............
..............
..............
..................
SDA
SCL
SCL
1101 111
SCL
GND
GND
1110 000
...............
..............
..............
..................
SCL
SDA
X
Do Not Use. Reserved
SCL
SCL
X
Do Not Use. Reserved
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FN8389.4
June 17, 2015
ISL28023
Following the slave byte is a one byte word address. The word
address is either supplied by the master device or obtained from
an internal counter. On power-up, the internal address counter is
set to address 00h, so a current address read starts at address
00h. When required, as part of a random read, the master must
supply the one word address bytes, as shown in Figure 108.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the registers, the slave byte must be “1nnnnnnx”
in both places.
Write Operation
A write operation requires a START condition, followed by a valid
identification byte, a valid Address byte, two data bytes and a
STOP condition. The first data byte contains the MSB of the data,
the second contains the LSB. After each of the four bytes, the
device responds with an ACK. At this time, the I2C interface
enters a standby state.
Read Operation
A read operation consists of a three byte instruction, followed by
two data bytes (see Figure 108). The master initiates the operation
issuing the following sequence: A START, the identification byte
with the R/W bit set to “0”, an address byte, a second START and a
second identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL28023 responds with an ACK. Then the
ISL28023 transmits two data bytes as long as the master
responds with an ACK during the SCL cycle following the eighth bit
of the first byte. The master terminates the read operation (issuing
no ACK then a STOP condition) following the last bit of the second
data byte (see Figure 108).
The data bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT
SDA
IDENTIFICATION
BYTE WITH
n
n
n
n
n
n
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
DATA BYTE 1
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE 2
R/W
FIGURE 107. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES
Group Command
The DPM has a feature that allows the master to configure the
settings of all DPM chips at once. The configuration command for
each device does not have to be same. Device 1 on an I2C bus could
be configured to set the voltage threshold of the OV comparator
while device 2 is configured for the acquisition time of the VBUS
input. To achieve the scenario described without group command,
the master sends two write commands, one to each slave device.
Each command sent from the master has a start bit and a stop bit.
The group command protocol concatenates the two commands but
replaces the stop bit of the first command and the start bit of the
second command with a repeat start bit. The actions sent in a Group
Command format will execute once the stop bit has been sent. The
stop bit signifies the end of a packet.
The broadcast feature saves time in configuring the DPM as well
as measuring signal parameters in time synchronization. The
broadcast should not be used for DPM read backs. This will
cause all devices connected to the I2C bus to talk to the master
simultaneously.
S
T
O
P
A
C
K
1 n n n n n n 1
1 n n n n n n 0
A
C
K
SIGNALS FROM
THE SLAVE
SLAVE ADDRESS
BYTE
1
S
T IDENTIFICATION
A
BYTE WITH
R
R/W = 1
T
ADDRESS
BYTE
R/W = 0
address byte in the read operation instruction and increments by
one during transmission of each pair of data bytes.
A
C
K
A
C
K
FIRST READ
DATA BYTE
SECOND READ
DATA BYTE
FIGURE 108. READ SEQUENCE (SLAVE ADDRESS SHOWN AS nnnnnn)
FIGURE 109. BYTE TRANSACTION SEQUENCE FOR INITIATING DATA RATES ABOVE 400kbs
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FN8389.4
June 17, 2015
ISL28023
Clock Speed
TIME = 1.024ms
125
GAIN (dB)
120
TIME = 2.048ms
TIME = 0.512ms
115
110
105
TIME = 0.128ms
100
TIME = 0.256ms
TIME = 0.64ms
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 110. CMRR vs FREQUENCY
The CMRR vs Frequency graph best represents the response of
the ISL28023 when an aberrant signal is applied to the circuit.
The graph was generated by shorting the ISL28023 VSHUNT
inputs without any filtering and applying a 0 to 20V sine wave to
the shunt inputs, VINP and VINM. A 0 to 3V sine wave was applied
to the auxiliary VSHUNT inputs, AuxP and AuxM. The voltage range
from a 1024 sample set was recorded for each frequency
applied to shunt input. CMRR results prior to 10kHz are mostly a
result of the variability of the measurement due to the
programmed acquisition time. The input is not able to bleed
through the noise floor.
The CMRR can be improved by designing a filter stage before the
ISL28023. The purpose of the filter stage is to attenuate the
amplitude of the unwanted signal to the noise level of the
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47
R1
C1
FIGURE 111. SIMPLIFIED FILTER DESIGN TO IMPROVE NOISE
PERFORMANCE TO THE ISL28023
R1 and C1 at both shunt inputs are single ended low pass filters.
The value of the series resistor to the ISL28023 can be a larger
value than the shunt resistor, RSH. A larger series resistor to the
input allows for a lower cutoff frequency filter design to the
ISL28023. The ISL28023 inputs can source up to 20µA of
transient current in the measurement mode. The transient or
switching offset current can be as large as 10µA. The switching
offset current combined with the series resistance, R1, creates
an error offset voltage. A balance of the value of R1 and the
shunt measurement error should be achieved for this filter
design.
The common mode voltage of the shunt input stage ranges from
0V to 60V. The capacitor voltage rating for C1 and CSH should
comply with the nominal voltage being applied to the input.
95
90
10
R1
ISL28023
130
C1
CSH
The purity of the signal being measured by the ISL28023 is not
always ideal. Environmental noise or noise generated from a
regulator can degrade the measurement accuracy. The
ISL28023 maintains a high CMRR ratio from DC to
approximately 10kHz, as shown in Figure 110.
FROM
SOURCE
LOAD
Signal Integrity
Measuring large currents requires low value sense resistors. A
large valued capacitor is required to filter low frequencies if the
shunt capacitor, CSH is connected directly in parallel to the sense
resistor, RSH. For more manageable capacitor values, it may be
better to directly connect the shunt resistor across the shunt inputs
of the ISL28023. The connection is illustrated in Figure 111. A
single pole filter constructed of 2 resistors, R1, and CSH will
improve capacitor value selections for low frequency filtering.
RSH
The device supports high-speed digital transactions up to
3.4Mbs. To access the high speed I2C feature, a master byte
code of 0000 1xxx is attached to the beginning of a standard
frequency read/write I2C protocol. The x in the master byte
signifies a “Do not care state”. X can either equal a 0 or a 1. The
master byte code should be clocked into the chip at frequencies
equal or less than 400kHz. The master code command
configures the internal filters of the ISL28023 to permit data bit
frequencies greater than 400kHz. Once the master code has
been clocked into the device, the protocol for a standard read/
write transaction is followed. The frequency at which the
standard protocol is clocked in at can be as great as 3.4MHz. A
stop bit at the end of a standard protocol will terminate the high
speed transaction mode. Appending another standard protocol
serial transaction to the data string without a stop bit, will
resume the high speed digital transaction mode. Figure 109
illustrates the data sequence for the high speed mode. The
minimum I2C supply voltage when operating at clock speeds of
400kHz is 1.8V.
ISL28023. Figure 111 is a simple filter example to attenuate
unwanted signals.
Fast Transients
An small isolation resistor placed between ISL28023 inputs and
the source is recommended. In hot swap or other fast transient
events, the amplitude of a signal can exceed the recommended
operating voltage of the part due to the line inductance. The
isolation resistor creates a low pass filter between the device and
the source. The value of the isolation resistor should not be too
large. A large value isolation resistor can effect the
measurement accuracy. The value of the isolation resistor
combined with the offset current creates an offset voltage error
at the shunt input. The input of the Bus channel is connected to
the top of a precision resistor divider. The accuracy of the resistor
divider determines the gain error of the Bus channel. The input
resistance of the Bus channel is 600kΩ. Placing an isolation
resistor of 10Ω will change the gain error of the Bus channel by
0.0016%.
FN8389.4
June 17, 2015
ISL28023
External Clock
RSH
Vreg_in
VIN
SMBALERT1
GND
1uF
3.3V
Vreg
A0
A1
VINM
AUXP
AUXM
I2CVCC
GPIO/Int
GPIO
MCU
GPIO
FIGURE 112. SIMPLIFIED SCHEMATIC OF THE ISL28023
SYNCHRONIZED TO A MCU SYSTEM CLOCK
ExtClkDiv = 0
ExtClkDiv = 1
-1.5
-3.5
SCL
SDA
System_Clock
Figure 113 illustrates a simple mathematical diagram of the
ECLK pin internal connection. The external clock divide is
controlled by way of the EXTCLKDIV bit in register 0xE5.
0.5
LOAD
VOUT = 0.6 +
(0.6 – DAC OUT)
* R2/R1
Temp
Sense
EXT CLK
VIN
To SMBAlert1
8-Bit
DAC
Vmcu
R1
FB
SMBALERT2
GND
R2
AUXV
DAC OUT
En
FIGURE 113. EXTERNAL CLOCK MODE
SDA
PMBus
REG
MAP
Boot
SYNC
SCL
ExtClkDiv = 3
-5.5
GAIN (dB)
Lo
0.1µF
A2
ADC
16-Bit
I2C
SMBUS
ISL85415
VBUS
R_pullUp
Phase
VIN
R_pullUp
Ext_Temp
Place Diode
Near RSH
SW MUX
Gnd
VCC,FS,SS
Sync,Comp
VCC
ISL28023
VINP
PG
Vreg_Out
VIN = 4.5V TO 36V
ExtClkDiv = 4
-7.5
ExtClkDiv = 14
-9.5
-11.5
The ISL28023 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 4.0MHz
with a frequency divide setting of 0 (internal divide by 8) results
in acquisition times that equal the internal oscillator frequency
when enabled. The ADC modulator is optimized for frequencies
of 500kHz. Operating internal clock frequencies beyond 500kHz
may result in measurement accuracy errors due to the modulator
not having enough time to settle.
Suppose an external clock frequency of 5.5MHz is applied with a
divide by 88 internal frequency setting, the system clock speed is
62.5kHz or 8x slower than the internal system clock. The
acquisition times for this example will increase by 8. For a
channel’s conversion time setting of 2.048ms, the ISL28023 will
have an acquisition time of 256µs.
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48
-13.5
FreqExtClk = 16MHz
ADC TIME SETTING
(Config_Ichannel) = 0
-15.5
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 114. MEASUREMENT BANDWIDTH vs EXTERNAL CLK
FREQUENCY
Figure 114 illustrates how changing the system clock frequency
effects the measurement bandwidth (the ADC acquisition time).
The bandwidth of the external clock circuitry is 25MHz.
Figure 115 shows the bandwidth of the external clock circuitry
when the external clock division bits equals to 0.
0.5
-0.5
-1.5
-2.5
GAIN (dB)
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be susceptible to crosstalk from a controlled source. Instead
of filtering the environmental noise from the measurement,
another approach would be to synchronize the measurement to
the source. The variability and accuracy of the measurement will
improve.
-3.5
-4.5
-5.5
-6.5
-7.5
ExtDiv = 0; (FreqInt = FreqExtClk /8)
-8.5
0.01
0.1
1
10
100
ExtClk FREQUENCY (MHz)
FIGURE 115. EXTERNAL CLOCK BANDWIDTH vs MEASUREMENT
ACCURACY
FN8389.4
June 17, 2015
ISL28023
The external clock pin can accept signal frequencies above
25MHz by programming the system clock frequency such that
the internal clock frequency is below 25MHz.
measurable current expected. The power rating equation is
represented in Equation 20.
P res_rating
V shunt_range Imeas Max
(EQ. 20)
0.5
A general rule of thumb is to multiply the power rating calculated
in Equation 20 by 2. This allows the sense resistor to survive an
event when the current passing through the shunt resistor is
greater than the measurable maximum current. The higher the
ratio between the power rating of the chosen sense resistor and
the calculated power rating of the system (Equation 20), the less
the resistor will heat up in high current applications.
-0.5
-1.5
GAIN (dB)
-2.5
-3.5
-4.5
-5.5
-6.5
ExtClk FREQUENCY = 45MHz
-7.5
-8.5
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
ExtClkDiv BIT VALUE
FIGURE 116. EXTERNAL CLOCK vs EXTERNAL BIT VALUE
Figure 116 illustrates the effects of dividing the external clock
frequency on the VSHUNT measurement accuracy.
Figures 115 and 116 were generated by applying a DC voltage to
the VSHUNT input and measuring the signal by way of an ADC
conversion.
Overranging
It is not recommended to operate the ISL28023 outside the set
voltage range. In the event of measuring a shunt voltage beyond
the maximum set range (80mV) and lower than the clamp
voltage of the protection diode (1V), the measured output
reading may be within the accepted range but will be incorrect.
Shunt Resistor Selection
In choosing a sense resistor, the following resistor parameters
need to be considered: the resistor value, resistor temperature
coefficient and resistor power rating.
The sense resistor value is a function of the full-scale voltage
drop across the shunt resistor and the maximum current
measured for the application. The maximum measurable range
for the VSHUNT input (VINP-VINM) of the ISL28023 is 80mV. The
ISL28023 allows the user to define a unique range other than
±80mV.
Once the voltage range for the input is chosen and the maximum
measurable current is known, the sense resistor value is
calculated using Equation 19.
R sense
V shunt_range
(EQ. 19)
Imeas Max
In choosing a sense resistor, the sense resistor power rating
should be taken into consideration. The physical size of a sense
resistor is proportional to the power rating of the resistor. The
maximum power rating for the measurement system is
calculated as the Vshunt_range multiplied by the maximum
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49
The temperature coefficient (TC) of the sense resistor directly
degrades the current measurement accuracy. The surrounding
temperature of the sense resistor and the power dissipated by
the resistor will cause the sense resistor value to change. The
change in resistor temperature with respect to the amount of
current that flows through the resistor is directly proportional to
the ratio of the power rating of the resistor versus the power
being dissipated. A change in sense resistor temperature results
in a change in sense resistor value. Overall, the change in sense
resistor value contributes to the measurement accuracy for the
system. The change in a resistor value due to a temperature rise
can be calculated using Equation 21.
R sense
R sense Rsense TC  Temperature
(EQ. 21)
Temperature is the change in temperature in Celsius. Rsense TC
is the temperature coefficient rating for a sense resistor. Rsense
is the resistance value of the sense resistor at the initial
temperature.
Table 50 is a shunt resistor look up table for select full-scale
current measurement ranges (ImeasMax). Table 50 also provides
the minimum rating for each shunt resistor.
TABLE 50. SHUNT RESISTOR VALUES AND POWER RATINGS FOR
SELECT MEASURABLE CURRENT RANGES
RSENSE/PRATING
VSHUNT RANGE (PGA SETTING)
ImeasMax
80mV
100µA
800Ω/8µW
1mA
80Ω/80µW
10mA
8Ω/800µW
100mA
800mΩ/8mW
500mA
160mΩ/40mW
1A
80mΩ/80mW
5A
16mΩ/400mW
10A
8mΩ/800mW
50A
1.6mΩ/4W
100A
0.8mΩ/8W
500A
0.16mΩ/40W
FN8389.4
June 17, 2015
ISL28023
It is often hard to readily purchase shunt resistor values for a
desired measurable current range. Either the value of the shunt
resistor does not exist or the power rating of the shunt resistor is
too low. A means of circumventing the problem is to use two or
more shunt resistors in parallel to set the desired current
measurement range. For example, an application requires a
full-scale current of 100A with a maximum voltage drop across
the shunt resistor of 80mV. From Table 50, this requires a sense
resistor of 0.8mΩ, 8W resistor. Assume the power ratings and
the shunt resistor values to chose from are 1mΩ4W, 2mΩ/4W
and 4mΩ/4W.
Using Equation 22, the power dissipated to each shunt resistor
yields 3.2W for the 2mΩ shunt resistors and 1.6W for the 4mΩ
shunt resistor. All shunt resistors are within the specified power
ratings.
Lossless Current Sensing (DCR)
A DCR sense circuit is an alternative to a sense resistor. The DCR
circuit utilizes the parasitic resistance of an inductor to measure
the current to the load. A DCR circuit remotely measures the
current through an inductor. The lack of components in series
with the regulator to the load makes the circuit lossless.
Let’s use a 1mΩ and a 4mΩ resistor in parallel to create the
shunt resistor value of 0.8mΩ. Figure 117 shows an illustration of
the shunt resistors in parallel.
DCR CIRCUIT
Rsen
Buck
Regulator
0.004
Csen
VINM
The power to each shunt resistor should be calculated before
calling a solution complete. The power to each shunt resistor is
calculated using Equation 22.
2
P shuntRes
V shunt_range
(EQ. 22)
R sense
The power dissipated by the 1mΩ resistor is 6.4W. 1.6W is
dissipated by the 4mΩ resistor. 1.6W exceeds the rating limit of
1W for the 1mΩ sense resistor. Another approach would be to
use three shunt resistors in parallel as illustrated in Figure 118.
0.004
0.002
0.002
FIGURE 118. INCREASING THE NUMBER OF SHUNT RESISTORS IN
PARALLEL TO CREATE A SHUNT RESISTOR VALUE
REDUCES THE POWER DISSIPATED BY EACH SHUNT
RESISTOR.
V c( F)
Rdcr
  j  ( f )  L  R dcr 

I L
1

j


(
f
)

C

R
sen
sen


LOAD
FB
FIGURE 117. A SIMPLIFIED SCHEMATIC ILLUSTRATING THE USE OF
TWO SHUNT RESISTORS TO CREATE A DESIRED
SHUNT VALUE
ADC
16-BIT
Rsen + Rdcr
PHASE
Lo
0.001
VINP
FIGURE 119. A SIMPLIFIED CIRCUIT EXAMPLE OF A DCR
A properly matched DCR circuit has an equivalent circuit seen by
the ADC equals to Rdcr in Figure 119. Before deriving the transfer
function between the inductor current and voltage seen by the
ISL28023, let’s review the definition of an inductor and capacitor
in the Laplacian domain.
Xc( f )
1
j ( f )  C
XL( f )
j ( f )  L
(EQ. 23)
Xc is the impedance of a capacitor related to the frequency and
XL is the impedance of an inductor related to frequency. ω equals
to 2f. f is the chop frequency dictated by the regulator. Using
Ohms law, the voltage across the DCR circuit in terms of the
current flowing through the inductor is defined in Equation 24.
V dcr( f )
R dcr  j ( f )  L i L
(EQ. 24)
In Equation 24, Rdcr is the parasitic resistance of the inductor.
The voltage drop across the inductor (Lo) and the resistor (Rdcr)
circuit is the same as the voltage drop across the resistor (Rsen)
and the capacitor (Csen) circuit. Equation 25 defines the voltage
across the capacitor (Vcsen) in terms of the inductor current (IL).
  1  ( j w( f )  L)  

 
R dcr  
R dcr 
I L
1

j


(
f
)

C

R
sen
sen


(EQ. 25)
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50
FN8389.4
June 17, 2015
ISL28023
L
R dcr
(EQ. 26)
C sen R sen
If Equation 26 holds true, the numerator and denominator of the
fraction in Equation 25 cancels reducing the voltage across the
capacitor to the equation represented in Equation 27.
Vc
R dcr i L
(EQ. 27)
Most inductor datasheets will specify the average value of the
Rdcr for the inductor. Rdcr values are usually sub 1mΩ with a
tolerance averaging 8%. Common chip capacitor tolerances
average to 10%.
Inductors are constructed out of metal. Metal has a high
temperature coefficient. The temperature drift of the inductor
value could cause the DCR circuit to be untuned. An untuned
circuit results in inaccurate current measurements along with a
chop signal bleeding into the measurement. To counter the
temperature variance, a temperature sensor may be incorporated
into the design to track the change in component values.
A DCR circuit is good for gross current measurements. As
discussed, inductors and capacitors have high tolerances and are
temperature dependent which will result in less than accurate
current measurements.
In Figure 119, there is a resistor in series with the ISL28023
negative shunt terminal, VINM, with the value of Rsen + Rdcr. The
resistor’s purpose is to counter the effects of the bias current
from creating a voltage offset at the input of the ADC.
Layout
The layout of a current measuring system is equally important as
choosing the correct sense resistor and the correct analog
converter. Poor layout techniques can result in severed traces,
signal path oscillations, magnetic contamination which all
contribute to poor system performance.
TRACE WIDTH
Matching the current carrying density of a copper trace with the
maximum current that will pass through is critical in the
performance of the system. Neglecting the current carrying
capability of a trace will result in a large temperature rise in the
trace, and the loss in system efficiency due to the increase in
resistance of the copper trace. In extreme cases, the copper
trace could be severed because the trace could not pass the
current. The current carrying capability of a trace is calculated
using Equation 28.
1
Trace width
 Imax 

0.44 
 k T 
0.725
(EQ. 28)
current passes through the trace. TraceThickness is the thickness
of the trace specified to the PCB fabricator in mils. A typical
thickness for general current carrying applications (<100mA) is
0.5oz copper or 0.7mils. For larger currents, the trace thickness
should be greater than 1.0oz or 1.4mils. A balance between
thickness, width and cost needs to be achieved for each design.
The coefficient k in Equation 28 changes depending on the trace
location. For external traces, the value of k equals 0.048 while
for internal traces the value of k reduces to 0.024. The k values
and Equation 28 are stated per the ANSI IPC-2221(A) standards.
TRACE ROUTING
It is always advised to make the distance between voltage
source, sense resistor and load as close as possible. The longer
the trace length between components will result in voltage drops
between components. The additional resistance will reduce the
efficiency of a system.
The bulk resistance, , of copper is 0.67µΩ/in or 1.7µΩ/cm at
+25°C. The resistance of trace can be calculated from
Equation 29.
R trace

Trace length
(EQ. 29)
Trace width  Trace thickness
Figure 120 illustrates each dimension of a trace.
TRACE
THICKNESS
TRACE
WIDTH
E
AC
TR GTH
N
LE
FIGURE 120. ILLUSTRATION OF THE TRACE DIMENSIONS FOR A STRIP
LINE TRACE
For example, assume a trace has 2oz of copper or 2.8mil
thickness, a width of 100mil and a length of 0.5in. Using
Equation 29, the resistance of the trace is approximately 2mΩ.
Assume 1A of current is passing through the trace. A 2mV
voltage drop would result from trace routing.
Current flowing through a conductor will take the path of least
resistance. When routing a trace, avoid orthogonal connections
for current bearing traces.
CURRENT FLOW
The relationship between the inductor load current (IL) and the
voltage across the capacitor simplifies if the following
component selection holds true;
Trace Thickness
Imax is the largest current expected to pass through the trace. T
is the allowable temperature rise in Celsius when the maximum
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FIGURE 121. AVOID ROUTING ORTHOGONAL CONNECTIONS FOR
TRACES THAT HAVE HIGH CURRENT FLOWS
FN8389.4
June 17, 2015
ISL28023
Orthogonal routing for high current flow traces will result in
current crowding, localized heating of the trace and a change in
trace resistance.
The utilization of arcs and 45° traces in routing large current flow
traces will maintain uniform current flow throughout the trace.
Figure 122 illustrates the routing technique.
CURRENT BEARING TRACE
LANDING PAD
SENSE TRACE
SENSE RESISTOR
CU
RR
EN
T
FL
O
W
CURRENT FLOW
SENSE TRACE
LANDING PAD
FIGURE 122. USE ARCS AND 45 DEGREE TRACES TO SAFELY ROUTE
TRACES WITH LARGE CURRENT FLOWS
CONNECTING SENSE TRACES TO THE CURRENT SENSE
RESISTOR
Ideally, a 4 terminal current sense resistor would be used as the
sensing element. Four terminal sensor resistors can be hard to
find in specific values and in sizes. Often a two terminal sense
resistor is designed into the application.
Sense lines are high impedance by definition. The connection
point of a high impedance line reflects the voltage at the
intersection of a current bearing trace and a high impedance
trace.
The high impedance trace should connect at the intersection
where the sense resistor meets the landing pad on the PCB. The
best place to make current sense line connection is on the inner
side of the sense resistor footprint. The illustration of the
connection is shown in Figure 123. Most of the current flow is at
the outer edge of the footprint. The current ceases at the point
the sense resistor connects to the landing pad. Assume the
sense resistor connects at the middle of each landing pad, this
leaves the inner half of each landing pad with little current flow.
With little current flow, the inner half of each landing pad is
classified as high impedance and perfect for a sense connection.
Current sense resistors are often smaller than the width of the
traces that connect to the footprint. The trace connecting to the
footprint is tapered at a 45° angle to control the uniformity of the
current flow.
CURRENT BEARING TRACE
FIGURE 123. CONNECTING THE SENSE LINES TO A CURRENT SENSE
RESISTOR
MAGNETIC INTERFERENCE
The magnetic field generated from a trace is directly proportional
to the current passing through the trace and the distance from
the trace the field is being measured at. Figure 124 illustrates
the direction the magnetic field flows versus current flow.
B

o I
2 r
FIGURE 124. THE CONDUCTOR ON THE LEFT SHOWS THE MAGNETIC
FIELD FLOWING IN A CLOCKWISE DIRECTION FOR A
CURRENT FLOWING INTO THE PAGE. A CURRENT FLOW
OUT OF THE PAGE HAS A COUNTERCLOCKWISE
MAGNETIC FLOW
The equation in Figure 124 determines the magnetic field, B, the
trace generates in relation to the current passing through the
trace, I, and the distance the magnetic field is being measured
from the conductor, r. The permeability of air, µo, is 4 *10-7 H/m.
When routing high current traces, avoid routing high impedance
traces in parallel with high current bearing traces. A means of
limiting the magnetic interference from high current traces is to
closely route the paths connected to and from the sense resistor.
The magnetic fields will cancel outside the two traces and add
between the two traces. Figure 125 illustrates a magnetic field
insensitive layout.
If possible, do not cross traces with high current. If a trace
crossing cannot be avoided, cross the trace in an orthogonal
manner and the furthest layer from the current bearing trace.
The interference from the current bearing trace will be limited.
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FN8389.4
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ISL28023
.
LANDING
PAD
Current Flow In
SENSE
TRACE
SENSE
TRACE
LANDING
PAD
Current Flow Out
TO
RE THE
SI S
ST EN
O S
R E
Sense Neg(‐)
E
NS
SE
E OR
TH IST
O M ES
FR R
SENSE
RESISTOR
The length of the
trace between the
two sense lines
defines the sense
resistor value.
Sense Pos(+)
TO SENSE CIRCUITRY
B to  B from
CURRENT FLOW
B to  B from
CURRENT FLOW
FIGURE 126. ILLUSTRATES A LAYOUT EXAMPLE OF A CURRENT
SENSE RESISTOR MADE FROM A PCB TRACE
For the example discussed, the width of the trace in Figure 126
illustration would equal 2.192in and the length between the
sense lines equals 1.832in.
B to  B from
FIGURE 125. CLOSELY ROUTED TRACES THAT CONNECT TO THE SENSE
RESISTOR REDUCES THE MAGNETIC INTERFERENCE
SOURCED FROM THE CURRENT FLOWING THROUGH THE
TRACES
A Trace as a Sense Resistor
In previous sections, the resistance and the current carrying
capabilities of a trace were discussed. In high current sense
applications, a design may utilize the resistivity of a current
sense trace as the sense resistor. This section will discuss how to
design a sense resistor from a copper trace.
Suppose an application needs to measure current up to 200A.
The design requires the least amount of voltage drop for
maximum efficiency. The full-scale voltage range of 40mV is
chosen. From Ohms law, the sense resistor is calculated to be
200µΩ. The power rating of the resistor is calculated to be 8W.
Assume the PCB trace thickness of the board equals
2oz/2.8mils and the maximum temperature rise of the trace is
20°C. Using Equation 28, the calculated trace width is 2.192in.
The trace width, thickness and the desired sense resistor value is
known. Utilizing Equation 29, the trace length is calculated to be
1.832in.
Figure 126 illustrates a layout example of a current sense
resistor defined by a PCB trace. The serpentine pattern of the
resistor reduces current crowding as well as limiting the
magnetic interference caused by the current flowing through the
trace.
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The width of the resistor is long for some applications. A means
of shortening the trace width is to connect two traces in parallel.
For calculation ease, assume the resistive traces are routed on
the outside layers of a PCB. Using Equations 28 and 29, the
width of the trace is reduced from 2.192in to 1.096in.
When using multiple layers to create a trace resistor, use
multiple vias to keep the trace potentials between the two
conductors the same. Vias are highly resistive compared to a
copper trace. Multiple vias should be employed to lower the
voltage drop due to current flowing through resistive vias.
Figure 127 illustrates a layout technique for a multiple layered
trace sense resistor.
VIA
TRACE
VIA
TRACE
PCB
TOP
PCB
BOTTOM
VIA
TRACE
(A) Cross Section View
(B) Top View
FIGURE 127. LAYOUT EXAMPLE OF A MULTIPLE LAYER TRACE
RESISTOR
FN8389.4
June 17, 2015
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
June 17, 2015
FN8389.4
Add Related Literature section to page 1.
Added DPM Portfolio Comparison table on page 5.
Removed Typical Applications section (which included Figures 127 through 135) and made into an appnote
(AN1955).
October 27, 2014
FN8389.3
On page 37 VBUS_OV_OT_SET [1st Paragraph) changed the step size to 5.71 and added a sentence. Added
a column to the Table 24. Changed the table title on Table 30 to Vshunt_OC_Set (page 38)
June 27, 2014
FN8389.2
Removed ISL28023EVAL2Z information and added ISL28023EVKIT1Z (Evaluation Kit) to the Ordering
Information on page 3.
June 12, 2014
FN8389.1
Changed AUXN to AUXM in Figures 1, 112, 127, 128, 129, 131, 132, 133, and 135.
Updated Notes 4 and 5 to correct package notes required.
Page 51 the equation reference of 15 becomes 28
Figure 120 changed "OF A STRIP" to "FOR A STRIP" in the title.
Figure 124 changed "CURRENT FLOW OUT" to "A CURRENT FLOW OUT" in the title.
Equation 25 was updated by adding “ IL” to the first portion of equation.
Added evaluation board information to Ordering Information on page 3.
May 2, 2014
FN8389.0
Initial Release.
About Intersil
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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FN8389.4
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ISL28023
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 11/13
4.00
4X 2.5
A
20X 0.50
B
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
19
1
18
4.00
2.45 (+ 0.10mm)
(- 0.15mm)
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 50 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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FN8389.4
June 17, 2015