TI1 ISO7321CDR Robust emc, low power, dual-channel digital isolator Datasheet

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ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
ISO732x Robust EMC, Low Power, Dual-Channel Digital Isolators
1 Features
3 Description
•
•
•
•
ISO732x provide galvanic isolation up to 3000 VRMS
for 1 minute per UL and 4242 VPK per VDE. These
devices have two isolated channels comprised of
logic input and output buffers separated by silicon
dioxide (SiO2) insulation barriers. ISO7320 has both
channels in the same direction while ISO7321 has
the two channels in opposite direction. In case of
input power or signal loss, default output is 'low' for
devices with suffix 'F' and 'high' for devices without
suffix 'F'. See Device Functional Modes for further
details. Used in conjunction with isolated power
supplies, these devices prevent noise currents on a
data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry. ISO732x have integrated noise filters for
harsh industrial environment where short noise
pulses may be present at the device input pins.
ISO732x have TTL input thresholds and operate from
3 V to 5.5 V supply levels. Through innovative chip
design and layout techniques, electromagnetic
compatibility of ISO732x have been significantly
enhanced to enable system-level ESD, EFT, Surge
and Emissions compliance.
1
•
•
•
•
•
•
•
•
•
Signaling Rate: 25 Mbps
Integrated Noise Filter on the Inputs
Default Output 'High' and 'Low' Options
Low Power Consumption: Typical ICC per Channel
at 1 Mbps:
– ISO7320: 1.2 mA (5 V Supplies),
0.9 mA (3.3 V Supplies)
– ISO7321: 1.7 mA (5 V Supplies),
1.2 mA (3.3 V Supplies)
Low Propagation Delay: 33 ns
Typical (5V Supplies)
3.3 V and 5 V Level Translation
Wide Temperature Range: –40°C to 125°C
65 KV/μs Transient Immunity,
Typical (5V Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: > 25 Years
Operates from 3.3 V and 5 V Supplies
Narrow Body SOIC-8 Package
Safety and Regulatory Approvals:
– 4242 VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 3000 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 Standards
– CQC Certification per GB4943.1-2011
Device Information(1)
PART NUMBER
ISO7320FC
ISO7321C
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
BODY SIZE (NOM)
SOIC (8)
4,90mm x 3,91mm
ISO7321FC
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCO
VCCI
2 Applications
•
PACKAGE
ISO7320C
Isolation
Capacitor
INx
OUTx
GNDI
GNDO
(1)
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
(2)
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7320C, ISO7320FC, ISO7321C, ISO7321FC
SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics, 5 V ...................................
Electrical Characteristics, 3.3 V ................................
Switching Characteristics, 5 V ..................................
Switching Characteristics, 3.3 V ...............................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Applications and Implementation ...................... 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 PCB Material ......................................................... 17
11.2 Layout Guidelines ................................................. 17
11.3 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Revision B (April 2015) to Revision C
Page
•
Added "and DINEN 61010-1" to the 4242 VPK in the Features ........................................................................................... 1
•
Deleted "(Approval Pending)" from the the CSA Component Acceptance list item in Features ........................................... 1
•
Changed From: VCC1 To: VCCI in Figure 11 ........................................................................................................................... 9
•
Changed From: VCC1 To: VCCI and From: VCC2 To: VCCO in Figure 13 .................................................................................. 9
•
Deleted IEC from the section title: Insulation and Safety-Related Specifications for D-8 Package .................................... 11
•
Changed the CTI Test Conditions in Insulation and Safety-Related Specifications for D-8 Package ................................ 11
•
Changed VISO Test Condition in the Insulation Characteristics table ................................................................................... 12
Changes from Revision A (March 2015) to Revision B
•
Page
Changed from device status From: Product Preview To: Production .................................................................................... 1
Changes from Original (January 2015) to Revision A
Page
•
Changed from First page only to the full datasheet. ............................................................................................................. 1
•
Changed VCC1 to VCCI, VCC2 to VCCO, GND1 to GNDI, GND2 to GND0 and added foot notes to the Simplified Schematic.. 1
2
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SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
5 Pin Configuration and Functions
1
INA
2
INB
3
GND1
4
ISO7321
D PACKAGE
(TOP VIEW)
8
VCC2
7
OUTA
6
OUTB
5
GND2
VCC1
1
OUTA
2
INB
3
GND1
4
Isolation
VCC1
Isolation
ISO7320
D PACKAGE
(TOP VIEW)
8
VCC2
7
INA
6
OUTB
5
GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
ISO7320
ISO7321
INA
2
7
I
Input, channel A
INB
3
3
I
Input, channel B
GND1
4
4
–
Ground connection for VCC1
GND2
5
5
–
Ground connection for VCC2
OUTA
7
2
O
Output, channel A
OUTB
6
6
O
Output, channel B
VCC1
1
1
–
Power supply, VCC1
VCC2
8
8
–
Power supply, VCC2
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SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Supply voltage, VCC1 , VCC2 (2)
Voltage
(2)
INx, OUTx
MIN
MAX
–0.5
6
–0.5
VCC+ 0.5 (3)
Output current, IO
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
V
V
±15
mA
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
(2)
(3)
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
VESD
(1)
(2)
(1)
UNIT
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
tui
Input pulse duration
1 / tui
TJ
5.5
4
2
5.5
0
0.8
40
-40
V
mA
V
V
ns
0
Ambient temperature
UNIT
mA
Junction temperature
TA
(1)
3
MAX
–4
Signaling rate
(1)
TYP
25
25
Mbps
136
°C
125
°C
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
D PACKAGE
THERMAL METRIC (1)
(8) PINS
RθJA
Junction-to-ambient thermal resistance
121
RθJCtop
Junction-to-case (top) thermal resistance
67.9
RθJB
Junction-to-board thermal resistance
61.6
ψJT
Junction-to-top characterization parameter
21.5
ψJB
Junction-to-board characterization parameter
61.1
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
PD (ISO7320)
Maximum power dissipation by ISO7320
PD1 (ISO7320)
Maximum power dissipation by side-1 of ISO7320
PD2 (ISO7320)
Maximum power dissipation by side-2 of ISO7320
PD (ISO7321)
Maximum power dissipation by ISO7321
PD1 (ISO7321)
Maximum power dissipation by side-1 of ISO7321
PD2 (ISO7321)
Maximum power dissipation by side-2 of ISO7321
(1)
4
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 12.5 MHz 50% duty-cycle square
wave
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 12.5 MHz 50% duty-cycle square
wave
UNIT
°C/W
56
15
mW
41
67
33.5
mW
33.5
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
6.5 Electrical Characteristics, 5 V
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 11
TEST CONDITIONS
VCCO (1)– 0.5
4.7
IOH = –20 μA; see Figure 11
VCCO (1) – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input current
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13.
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
MAX
UNIT
V
0.2
0.4
0
0.1
V
460
mV
μA
10
μA
–10
25
65
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
ICC2
ICC1
ICC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
0.4
0.9
2
3.2
0.8
1.4
3.2
4.4
1.4
2.3
4.9
6.8
10 Mbps
CL = 15pF
25 Mbps
CL = 15pF
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
1.7
2.8
10 Mbps
CL = 15pF
2.5
3.7
25 Mbps
CL = 15pF
3.7
5.4
mA
ISO7321
ICC1 , ICC2
ICC1 , ICC2
Supply current for VCC1 and VCC2
ICC1 , ICC2
(1)
mA
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.6 Electrical Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 11
TEST CONDITIONS
VCCO (1)– 0.5
3
IOH = –20 μA; see Figure 11
VCCO (1)– 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input current
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 13
IOL = 4 mA; see Figure 11
IOL = 20 μA; see Figure 11
MAX
V
0.2
0.4
0
0.1
450
V
mV
10
μA
μA
-10
25
UNIT
50
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7320
ICC1
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
ICC2
ICC1
ICC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
0.2
0.5
1.5
2.5
0.5
0.8
2.2
3.2
0.9
1.4
3.3
4.7
10 Mbps
CL = 15pF
25 Mbps
CL = 15pF
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
1.2
2
10 Mbps
CL = 15pF
1.7
2.5
25 Mbps
CL = 15pF
2.5
3.6
mA
ISO7321
ICC1 , ICC2
ICC1 , ICC2
Supply current for VCC1 and VCC2
ICC1 , ICC2
(1)
mA
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
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6.7 Switching Characteristics, 5 V
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o) (2)
tsk(pp)
Channel-to-channel output skew time
(3)
TYP
MAX
20
33
57
ns
4
ns
ISO7320
2
ISO7321
17
23
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(3)
See Figure 11
MIN
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
See Figure 11
See Figure 12
UNIT
ns
ns
2.4
ns
2.1
ns
7.5
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.8 Switching Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
PWD
tsk(o)
(1)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
TYP
MAX
22
37
66
ns
3
ns
ISO7320
3
ISO7321
16
28
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
6
MIN
Part-to-part skew time
Output signal rise time
(3)
See Figure 11
Pulse width distortion |tPHL – tPLH|
tr
(1)
(2)
TEST CONDITIONS
Propagation delay time
See Figure 11
See Figure 12
UNIT3
ns
ns
3.1
ns
2.6
ns
7.4
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.9 Typical Characteristics
7
4
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
5
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
3.5
Supply Current (mA)
Supply Current (mA)
6
4
3
2
1
3
2.5
2
1.5
1
0.5
0
0
0
5
10
15
20
Data Rate (Mbps)
TA = 25°C
25
30
0
CL = 15 pF
Figure 1. ISO7320 Supply Current vs Data Rate
15
20
Data Rate (Mbps)
25
30
D002
No Load
Figure 2. ISO7320 Supply Current vs Data Rate
3
3.5
2.5
3
Supply Current (mA)
Supply Current (mA)
10
TA = 25°C
4
2.5
2
1.5
1
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0.5
2
1.5
1
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
0.5
0
0
0
5
10
TA = 25°C
15
20
Data Rate (Mbps)
25
30
0
CL = 15 pF
10
15
20
Data Rate (Mbps)
TA = 25°C
Figure 3. ISO7321 Supply Current vs Data Rate
25
30
D004
No Load
Figure 4. ISO7321 Supply Current vs Data Rate
0.9
VCC at 3.3 V
VCC at 5 V
VCC at 3.3 V
VCC at 5 V
0.8
Low-Level Output Voltage (V)
5
5
D003
6
High-Level Output Voltage (V)
5
D001
4
3
2
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-15
-10
-5
High-Level Output Current (mA)
0
0
5
10
Low-Level Output Current (mA)
D005
TA = 25°C
15
D006
TA = 25°C
Figure 5. High-Level Output Voltage vs High-Level Output
Current
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Figure 6. :Low-Level Output Voltage vs Low-Level Output
Current
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2.48
2.46
43
VCC Rising
VCC Falling
41
Propagation Delay Time (ms)
Power Supply Under-Voltage Threshold (V)
Typical Characteristics (continued)
2.44
2.42
2.4
2.38
2.36
35
33
31
0
50
100
Free-Air Temperature (qC)
150
27
140
25
23
21
19
tGS at 3.3 V
tGS at 5 V
30
65
Free-Air Temperature (qC)
100
135
D008
Figure 8. Propagation Delay Time vs Free-Air Temperature
160
17
-5
D007
29
15
-40
tPHL at 3.3 V
tPLH at 5 V
tPLH at 3.3 V
tPHL at 5 V
29
25
-40
Peak-to-Peak Output Jitter (ps)
Input Glitch Suppression Time (ms)
37
27
2.34
-50
Figure 7. Power Supply Under Voltage Threshold vs FreeAir Temperature
120
100
80
60
40
20
Output Jitter at 3.3 V
Output Jitter at 5 V
0
-5
30
65
Free-Air Temperature (qC)
100
135
D009
Figure 9. Input Glitch Suppression Time vs Free-Air
Temperature
8
39
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0
5
10
15
Data Rate (Mbps)
20
25
D010
Figure 10. Peak-to-Peak Output Jitter vs Data Rate
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
(1)
VI
50 W
VCCI
VI
OUT
50%
50%
0V
VO
CL
tPLH
(2)
tPHL
90%
10%
50%
VO
VOH
50%
VOL
tr
tf
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms
VI
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VCC
ISOLATION BARRIER
VCC
IN
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
CL
50%
fs low V
OL
NOTE A
A.
VOH
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
Note A
GNDO
VOH or VOL
–
+ VCM –
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitioned from
0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low ± Frequency
Channel
(DC...100 kbps)
PWM
VREF
LPF
0
Polarity and
Threshold Selection
IN
OUT
1 S
High ± Frequency
Channel
(100 kbps ...25 Mbps )
DCL
VREF
Polarity and Threshold Selection
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
10
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8.3 Feature Description
PRODUCT
CHANNEL DIRECTION
ISO7320C
MAX DATA RATE
DEFAULT OUTPUT
High
Same
ISO7320FC
3000 VRMS / 4242 VPK
ISO7321C
(1)
Low
25 Mbps
High
Opposite
ISO7321FC
(1)
RATED ISOLATION
Low
See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Minimum internal gap (internal
clearance)
Distance through insulation
VIO = 500 V, TA = 25°C
400
V
13
µm
12
Ω
11
Ω
10
RIO
Isolation resistance, input to
output (1)
CIO
Isolation capacitance, input to
output (1)
VIO = 0.4 sin (2πft), f = 1 MHz
1.5
pF
CI
Input capacitance (2)
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1.8
pF
(1)
(2)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
10
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
SPECIFICATION
UNIT
VIOWM
Maximum isolation working voltage
TEST CONDITIONS
400
VRMS
VIORM
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VPK
VIOTM
Maximum transient overvoltage per
DIN V VDE V 0884-10
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
6000
VPK
VISO
Withstand isolation voltage per UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100%
production)
3000
VRMS
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
8.3.1.3 Regulatory Information
VDE
CSA
Approved under CSA
Certified according to DIN V VDE
Component Acceptance Notice
V 0884-10 (VDE V 08845A, IEC 60950-1, and IEC
10):2006-12
61010-1
UL
CQC
Recognized under UL 1577
Component Recognition
Program
Certified according to GB4943.12011
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Surge Isolation
Voltage, 6000 VPK
Maximum Repetitive Peak
Voltage, 566 VPK
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
Single protection, 3000 VRMS
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Certificate number: 40016131
Master contract number:
220991
(1)
12
File number: E181974
(1)
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
Certificate number:
CQC15001121656
Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
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8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Maximum case temperature
MIN
TYP
MAX
RθJA = 121 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
188
RθJA = 121 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
287
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
400
Safety Limiting Current (mA)
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
200
100
0
0
50
100
150
Case Temperature (qC)
200
D011
Figure 15. θJC Thermal Derating Curve per DIN V VDE V 0884-10
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8.4 Device Functional Modes
Table 2. Function Table (1)
VCCI
VCCO
OUTA, OUTB
INA, INB
ISO7320C, ISO7321C
ISO7320FC, ISO7321FC
H
H
H
PU
(1)
(2)
(3)
PU
L
L
L
Open
H (2)
L (3)
PD
PU
X
H (2)
L (3)
X
PD
X
Undetermined
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level; Open = Not connected
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
VCCI
VCCI
Input (Devices With Suffix F)
VCCI
VCCI
VCCI
VCCI
VCCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
VCCO
40 W
OUTx
Figure 16. Device I/O Schematics
14
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO732x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7321 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VCC1
VCC2
ISO7321
Figure 17. Typical ISO7321 Application Circuit
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
ISO7320:
ISO7321:
At VCC1 = VCC2 = 5 V
At VCC1 = VCC2 = 5 V
•
•
•
ICC1 = 0.3838 + (0.0431 x f)
ICC2 = 2.74567 + (0.08433 x f) + (0.01 x f x CL)
ICC1 and ICC2 = 1.5877 + (0.066 x f) + (0.00123 x f x CL)
At VCC1 = VCC2 = 3.3 V
At VCC1 = VCC2 = 3.3 V
•
•
•
ICC1 = 0.2394 + (0.02355 x f)
ICC2 = 2.10681 + (0.04374 x f) + (0.007045 x f x CL)
ICC1 and ICC2 = 1.187572 + (0.019399 x f) + (0.0019029 x
f x CL)
ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive
load measured in pF.
9.2.2 Detailed Design Procedure
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO732x
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.2.3 Application Performance Curves
Typical eye diagrams of ISO732x below indicate low jitter and wide open eye at the maximum data rate of 25
Mbps.
Figure 18. Eye Diagram at 25 Mbps, 5 V and 25°C
16
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Figure 19. Eye Diagram at 25 Mbps, 3.3 V and 25°C
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SLLSEK8C – JANUARY 2015 – REVISED APRIL 2015
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 & VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
11 Layout
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 20. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7320C
Click here
Click here
Click here
Click here
Click here
ISO7320FC
Click here
Click here
Click here
Click here
Click here
ISO7321C
Click here
Click here
Click here
Click here
Click here
ISO7321FC
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
DeviceNet is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Isolation Glossary, SLLA353
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: ISO7320C ISO7320FC ISO7321C ISO7321FC
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
.041
[1.04]
DETAIL A
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
1
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
8
8X (.024)
[0.6]
8
SYMM
5
4
6X (.050 )
[1.27]
8X (.024)
[0.6]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
1
6X (.050 )
[1.27]
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SYMM
SYMM
5
4
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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13-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7320CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7320C
ISO7320CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7320C
ISO7320FCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7320FC
ISO7320FCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7320FC
ISO7321CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7321C
ISO7321CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7321C
ISO7321FCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7321FC
ISO7321FCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7321FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
13-Apr-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7320CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7320FCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7321CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7321FCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7320CDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7320FCDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7321CDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7321FCDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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