DATASHEET 19MHz Radiation Hardened 40V Dual Rail-to-Rail Input-Output, Low-Power Operational Amplifier ISL70244SEH Features The ISL70244SEH features two low-power amplifiers optimized to provide maximum dynamic range. These op amps feature a unique combination of rail-to-rail operation on the input and output as well as a slew enhanced front end that provides ultra fast slew rates positively proportional to a given step size; thereby increasing accuracy under transient conditions, whether it’s periodic or momentary. They also offer low power, low offset voltage and low temperature drift, making it ideal for applications requiring both high DC accuracy and AC performance. With <5µs recovery for Single Event Transients (SET) (LETTH = 86.4MeV•cm2/mg), the number of filtering components needed is drastically reduced. The ISL70244SEH is also immune to single-event latch-up as it is fabricated in Intersil’s proprietary PR40 Silicon On Insulator (SOI) process. • Electrically screened to DLA SMD # 5962-13248 Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer They are designed to operate over a single supply range of 2.7V to 40V or a split supply voltage range of ±1.35V to ±20V. Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply controls and process controls. The ISL70244SEH is available in a 10 Ld hermetic ceramic flatpack that operates across the temperature range of -55°C to +125°C. Related Literature • <5µs recovery from SET (LETTH = 86.4MeV•cm2/mg) • Unity gain stable • Rail-to-rail input and output • Wide gain·bandwidth product . . . . . . . . . . . . . . . . . . . . 19MHz • Wide single and dual supply range. . . 2.7V to 40V maximum • • • • Low input offset voltage . . . . . . . 400µV (+25°C, maximum) Low current consumption (per amplifier) . . . . 1.2mA, typical No phase reversal with input overdrive Slew rate - Large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V/µs • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - High dose rate (50-300rad(Si)/s). . . . . . . . . . . 300krad(Si) - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)* - SEL/SEB LETTH (VS = ±19V) . . . . . . . . . 86.4MeV•cm2/mg * Product capability established by initial characterization. Applications • Precision instruments • AN1888, “ISL70244SEH Evaluation Board User’s Guide” • Active filter blocks • AN1961, “ISL70244SEH Single Event Effects Report” • Data acquisition • ISL70244SEH SMD 5962-13248 • Power supply control • AN1870, “ISL70444SEH Radiation Test Report” • Process control • ISL70444SEH Neutron Test Report ILOAD 1400 Rs - R3 R1 R2 CAPTURED EVENTS VSRC 1200 L O A D + V+ ISL70244SEH VOU T + V- R4 VREF R2 = R4 = 100kO Gain = R2/R1 = 10 V+ = 36V; V- = 0V; VREF = 18V VOUT = VREF + Gain(ILOAD* RS) 1 800 600 400 5 1 200 R1 = R3 = 10kO FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, HIGH-SIDE CURRENT SENSE AMPLIFIER September 1, 2016 FN8592.2 1000 0 0 0.2 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TRANSIENT DURATION (µs) FIGURE 2. TYPICAL SINGLE EVENT TRANSIENT DURATION AT +25°C LET = 60MeV•cm2/ mg IN UNITY GAIN (VS = ±18V) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014-2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL70244SEH Pin Configuration ISL70244SEH (10 LD FLATPACK) TOP VIEW OUTA 1 -INA 2 +INA 3 NC 4 V- 5 V+ 10 - + + - 9 OUTB 8 -INB 7 +INB 6 LID Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT ESD CIRCUIT 5 V- DESCRIPTION Circuit 3 Negative power supply 7 +INB Circuit 1 Amplifier B noninverting input 8 -INB Circuit 1 Amplifier B inverting input 9 OUTB Circuit 2 Amplifier B output 10 V+ Circuit 3 Positive power supply 1 OUTA Circuit 2 Amplifier A output 2 -INA Circuit 1 Amplifier A inverting input 4 NC - 3 +INA Circuit 1 Amplifier A noninverting input 6 LID NA Unbiased, tied to package lid This pin is not electrically connected internally. V+ 600Ω V+ 600Ω -IN V+ +IN CAPACITIVELY TRIGGERED ESD CLAMP OUT V- FIGURE 3. CIRCUIT 1 Submit Document Feedback 2 V- FIGURE 3. CIRCUIT 2 V- FIGURE 3. CIRCUIT 3 FN8592.2 September 1, 2016 ISL70244SEH Ordering Information PART NUMBER (Note 1) ORDERING SMD NUMBER (Note 2) TEMP RANGE (°C) PACKAGE (RoHS COMPLIANT) 5962F1324801VXC ISL70244SEHVF -55 to +125 10 Ld Flatpack 5962F1324801V9A ISL70244SEHVX -55 to +125 Die N/A ISL70244SEHF/PROTO -55 to +125 10 Ld Flatpack N/A ISL70244SEHX/SAMPLE -55 to +125 Die N/A ISL70244SEHEV1Z PKG. DWG. # K10.A K10.A Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. Submit Document Feedback 3 FN8592.2 September 1, 2016 ISL70244SEH Absolute Maximum Ratings (V+ Thermal Information V -) . Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld Flatpack Package (Notes 3, 4). . . . . 44 10 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Supply Voltage Differential to . . . . . . . . . . . . . . . . . . 42V Maximum Supply Voltage Differential (V+ to V-) (Note 5) . . . . . . . . . . . 38V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . 42V or (V- - 0.5V) to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . 42V or (V- - 0.5V) to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . ±20mA ESD Tolerance Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . 750V Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 39.6V Split Rail Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.35V to ±19.8V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. 5. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) for SEB. Refer to Single Event Effects Test Report for more information. Electrical Specifications VS = ±19.8V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s PARAMETER SYMBOL Offset Voltage VOS TEST CONDITIONS VCM = 0V VCM = V+ V+ to VV- + MIN (Note 6) TYP MAX (Note 6) UNIT -400 25 400 µV -500 110 500 µV - 0.5 - µV/°C Offset Voltage Temperature Coefficient TCVOS VCM = Input Offset Channel-to-Channel Match VOS VCM = V+ - 135 800 µV VCM = V- - 128 800 µV Input Bias Current IB IOS Common-Mode Input Voltage Range VCMIR Common-Mode Rejection Ratio CMRR -500 210 500 nA VCM = V+ -500 200 500 nA VCM = V- -650 290 650 nA - 0.5V -500 200 500 nA VCM = V- + 0.5V -650 257 650 nA -30 0 30 nA -50 0 50 nA V- - V+ V VCM = V- to V+ - 112 - dB V- PSRR Open-Loop Gain Output Voltage High (VOUT to Submit Document Feedback AVOL V+) VOH 4 V+ VCM = V+ to V- VCM = Power Supply Rejection Ratio 2V VCM = 0V VCM = Input Offset Current - 2V to 70 - - dB VCM = V+ - 0.5V to V- + 0.5V - 111 - dB VCM = V+ - 0.5V to V- + 0.5V 80 - - dB V- = to V+ V+ = -18V; 0.5V to 18V; V+ = 18V; V- = -0.5V to -18V - 128 - dB 83 - - dB - 125 - dB 90 - - dB RL = No Load - 26 160 mV RL = 10kΩ - 78 175 mV RL = 10kΩ to ground FN8592.2 September 1, 2016 ISL70244SEH Electrical Specifications VS = ±19.8V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s (Continued) PARAMETER SYMBOL Output Voltage Low (VOUT to V-) VOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT RL = No load - 21 160 mV RL = 10kΩ - 64 175 mV Output Short-Circuit Current ISRC Sourcing; VIN = 0V, VOUT = -18V 10 - - mA Output Short-Circuit Current ISNK Sinking; VIN = 0V, VOUT = +18V 10 - - mA Unity gain - 1.6 2.2 mA TA = +25°C post HDR/LDR radiation - - 2.2 mA TA = -55°C to +125°C - 2.2 2.8 mA 17 19 - MHz Supply Current/Amplifier IS AC SPECIFICATIONS Gain Bandwidth Product GBWP AV = 1, RL = 10k Voltage Noise Density en f = 10kHz - 11.3 - nV/√Hz Current Noise Density in f = 10kHz - 0.312 - pA/√Hz Large Signal Slew Rate SR AV = 1, RL = 10kΩVO = 10VP-P 60 - - V/µs Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER SYMBOL Offset Voltage VOS TEST CONDITIONS VCM = 0V VCM = V+ to VV+ V- + MIN (Note 6) TYP MAX (Note 6) UNIT -400 20 400 µV -500 80 500 µV - 0.5 - µV/°C Offset Voltage Temperature Coefficient TCVOS VCM = Input Offset Channel-to-Channel Match VOS VCM = V+ - 132 800 µV VCM = V- - 127 800 µV VCM = 0V -400 226 400 nA VCM = V+ -400 182 400 nA VCM = V- -580 260 580 nA VCM = V+ - 0.5V -400 181 400 nA VCM = V- + 0.5V -580 224 580 nA -30 0 30 nA -50 0 50 nA V- - V+ V VCM = V- to V+ - 92 - dB VCM = V- to V+ 70 - - dB VCM = V+ - 0.5V to V- + 0.5V - 91 - dB VCM = V+ - 0.5V to V- + 0.5V 74 - - dB Input Bias Current IB Input Offset Current IOS Common-Mode Input Voltage Range VCMIR Common-Mode Rejection Ratio CMRR Submit Document Feedback 5 - 2V to 2V VCM = V+ to V- FN8592.2 September 1, 2016 ISL70244SEH Electrical Specifications VS = ±2.5V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER SYMBOL Power Supply Rejection Ratio PSRR Open-Loop Gain AVOL Output Voltage High (VOUT to V+) Output Voltage Low (VOUT to VOH V -) VOL Supply Current/Amplifier IS MIN (Note 6) TYP MAX (Note 6) UNIT V- = -2.5V; V+ = 4.5V to 2.5V; V+ = 2.5V; V- = -4.5V to -2.5V - 123 - dB V- = -2.5V; V+ = 4.5V to 2.5V; V+ = 2.5V; V- = -4.5V to -2.5V TA = +125°C, TA = +25°C OR TA = +25°C with HDR/LDR radiation 80 - - dB V- = -2.5V; V+ = 4.5V to 2.5V; V+ = 2.5V; V- = -4.5V to -2.5V TA = -55°C 70 - - dB - 118 - dB RL = 10kΩ to ground TA = +125°C, TA = +25°C OR TA = +25°C with HDR/LDR radiation 90 - - dB RL = 10kΩ to ground TA = -55°C 80 - - dB RL = No Load - 15 85 mV RL = 10kΩ - 23 105 mV RL = 600Ω - - 400 mV RL = No load - 11 85 mV RL = 10kΩ - 18 105 mV RL = 600Ω - - 400 mV Unity gain - 1.2 1.5 mA TA = +25°C post HDR/LDR radiation - - 1.5 mA TA = -55°C to +125°C - 1.7 2.0 mA TEST CONDITIONS RL = 10kΩ to ground AC SPECIFICATIONS Gain Bandwidth Product GBWP AV = 1, RL = 10k 15 17 - MHz Voltage Noise Density en f = 10kHz - 12.3 - nV/√Hz Current Noise Density in f = 10kHz - 0.313 - pA/√Hz Large Signal Slew Rate SR AV = 1, RL = 10kΩVO = 3VP-P - 35 - V/µs Submit Document Feedback 6 FN8592.2 September 1, 2016 ISL70244SEH Electrical Specifications VS = ±1.35V, VCM = VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER SYMBOL Offset Voltage VOS VOS Input Offset Channel-to-Channel Match TEST CONDITIONS MIN (Note 6) IB IOS Common-Mode Input Voltage Range UNIT VCM = 0V -400 51 400 µV -500 80 500 µV - 79 800 µV 119 800 µV VCM = V+ VCM = 0V -375 110 375 nA VCM = V+ -375 180 375 nA VCM = V- -565 225 565 nA - 0.5V -375 180 375 nA VCM = V- + 0.5V -565 223 565 nA -30 0 30 nA -50 0 50 nA V- - V+ V - 14 50 mV VCM = Input Offset Current MAX (Note 6) VCM = V+ to V- VCM = V- Input Bias Current TYP V+ VCM = V+ to V- VCMIR Output Voltage High (VOUT to V+) VOH RL = No load RL = 10kΩ - 19 70 mV Output Voltage Low (VOUT to V-) VOL RL = No Load - 10 50 mV RL = 10kΩ - 14 70 mV Unity gain - 1.1 1.5 mA TA = +25°C post HDR/LDR radiation - - 1.5 mA TA = -55°C to +125°C - 1.6 2.0 mA 10 15 - MHz Supply Current/Amplifier IS AC SPECIFICATIONS Gain Bandwidth Product GBWP AV = 1, RL = 10k Voltage Noise Density en f = 10kHz - 12 - nV/√Hz Current Noise Density in f = 10kHz - 0.312 - pA/√Hz NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 7 FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. 120 300 200 80 60 100 IBIAS (nA) OFFSET VOLTAGE (µV) 100 40 20 0 0 -100 -20 -200 -40 -60 -20 -15 -10 -5 0 5 10 15 -300 -20 20 -15 -10 COMMON-MODE VOLTAGE (V) FIGURE 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 250 250 5 10 15 20 IB+ 200 IB+ 200 CURRENT (nA) CURRENT (nA) 0 FIGURE 5. IBIAS vs COMMON-MODE VOLTAGE 300 150 IB- 100 IB- 150 100 50 50 0 -100 -5 COMMON-MODE VOLTAGE (V) -50 0 50 TEMPERATURE (°C) 100 0 -100 150 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 7. IBIAS vs TEMPERATURE (VS = ±2.5V) FIGURE 6. IBIAS vs TEMPERATURE (VS = ±18V) 2.5 300 IB+ 2.0 200 CURRENT (nA) CURRENT (nA) 250 IB150 100 IOS 1.0 0.5 50 0 -100 1.5 -50 0 50 100 TEMPERATURE (°C) FIGURE 8. IBIAS vs TEMPERATURE, (VS = ±1.5V) Submit Document Feedback 8 150 0 -100 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 9. IOS vs TEMPERATURE (VS = ±18V) FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 3.5 2.5 3.0 CURRENT (nA) CURRENT (nA) 2.0 1.5 IOS 1.0 0.5 0 -100 2.5 2.0 IOS 1.5 1.0 0.5 -50 0 50 100 0 -100 150 -50 TEMPERATURE (°C) 70 70 60 60 50 50 40 VOS 20 10 0 -100 50 100 150 FIGURE 11. IOS vs TEMPERATURE (VS = ±1.5V) VOLTAGE (µV) VOLTAGE (µV) FIGURE 10. IOS vs TEMPERATURE (VS = ±2.5V) 30 0 TEMPERATURE (°C) 40 VOS 30 20 10 -50 0 50 100 0 -100 150 -50 TEMPERATURE (°C) 0 50 100 150 TEMPERATURE (°C) FIGURE 12. VOS vs TEMPERATURE (VS = ±18V) FIGURE 13. VOS vs TEMPERATURE (VS = ±2.5V) 135 50 ±18V 130 40 AVOL (dB) VOLTAGE (µV) 125 30 VOS 20 ±2.5V 120 ±1.5V 115 110 10 0 -100 105 -50 0 50 100 TEMPERATURE (°C) FIGURE 14. VOS vs TEMPERATURE (VS = ±1.5V) Submit Document Feedback 9 150 100 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 15. AVOL vs TEMPERATURE vs SUPPLY VOLTAGE FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 0.0 +25°C +125°C 2.0 -55°C CURRENT (mA) CURRENT (mA) -0.5 2.5 -1.0 -1.5 -2.0 +25°C 1.5 1.0 -55°C 0.5 +125°C -2.5 0 10 20 SUPPLY DIFFERENTIAL 30 (V+ TO V -) 0.0 40 0 (V) 10 20 30 SUPPLY DIFFERENTIAL (V+ TO V-) (V) 40 FIGURE 17. POSITIVE SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 16. NEGATIVE SUPPLY CURRENT vs SUPPLY VOLTAGE 135 135 130 130 ±18V ±2.5V 120 ±1.5V 115 125 PSRR- (dB) PSRR+ (dB) 125 ±18V 120 115 110 110 105 105 100 -75 -25 25 75 100 -75 125 ±2.5V ±1.5V -25 75 125 FIGURE 18. PSRR+ vs TEMPERATURE vs SUPPLY VOLTAGE FIGURE 19. PSRR- vs TEMPERATURE vs SUPPLY VOLTAGE 120 70 100 90 ±18V 60 ±2.5V 50 ±1.5V 80 CURRENT (mA) 110 CMRR (dB) 25 TEMPERATURE (°C) TEMPERATURE (°C) ±18V ±15V ±5V 40 30 ±2.5V 60 20 ±1.5V 50 10 70 40 -75 -25 25 75 125 TEMPERATURE (°C) FIGURE 20. CMRR vs TEMPERATURE vs SUPPLY VOLTAGE Submit Document Feedback 10 0 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 21. SHORT-CIRCUIT CURRENT vs TEMPERATURE FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 50 70 RL = 2kΩ 60 30 (VS+ - VOUT) (mV) (VS+ - VOUT) (mV) 40 RL = 10kΩ 20 RL = OPEN 10 RL = 2kΩ 50 40 RL = 10kΩ 30 20 RL = OPEN 10 0 -75 -25 25 75 TEMPERATURE (°C) 125 0 -75 175 -25 25 75 TEMPERATURE (°C) 125 175 FIGURE 23. (VS = ±2.5V) VOH vs TEMPERATURE FIGURE 22. (VS = ±1.5V) VOH vs TEMPERATURE 350 50 300 200 (VS- + VOUT) (mV) (VS+ - VOUT) (mV) 40 250 RL = 2kΩ 150 100 RL = 10kΩ RL = OPEN 30 RL = 10kΩ 20 10 50 0 -75 RL = 2kΩ RL = OPEN -25 25 75 125 0 -75 175 -25 TEMPERATURE (°C) 70 350 60 300 RL = 2kΩ 50 40 RL = 10kΩ 30 125 175 FIGURE 25. (VS = ±1.5V) VOL vs TEMPERATURE (VS- - VOUT) (mV) (VS- + VOUT) (mV) FIGURE 24. (VS = ±18V) VOH vs TEMPERATURE 25 75 TEMPERATURE (°C) 20 10 RL = 2kΩ 250 200 150 100 RL = 10kΩ RL = OPEN 50 RL = OPEN 0 -75 -25 25 75 TEMPERATURE (°C) 125 FIGURE 26. (VS = ±2.5V) VOL vs TEMPERATURE Submit Document Feedback 11 175 0 -75 -25 25 75 TEMPERATURE (°C) 125 175 FIGURE 27. (VS = ±18V) VOL vs TEMPERATURE FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 10 INPUT NOISE CURRENT (pA/√Hz) 1,000 100 10 1 0.01 0.1 1 10 100 FREQUENCY (Hz) 1k 10k SIMULATION 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 29. INPUT NOISE CURRENT SPECTRAL DENSITY (VS = ±18V) 200 200 200 SIMULATION 150 150 100 100 100 100 50 50 50 50 0 0 GAIN -50 -50 GAIN (dB) 150 PHASE (°) GAIN (dB) 200 0.1 0.1 100k FIGURE 28. INPUT NOISE VOLTAGE SPECTRAL DENSITY (VS = ±18V) 1 0 150 0 GAIN -50 -50 PHASE (°) INPUT NOISE VOLTAGE (nV/√Hz) 10,000 -100 -100 -100 -100 -150 -150 -150 -150 -200 -200 -250 1G -250 -200 -250 0 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 30. OPEN-LOOP FREQUENCY RESPONSE (CL = 0.01pF) FIGURE 31. OPEN-LOOP FREQUENCY RESPONSE (CL = 10pF) 200 SIMULATION 0 1 10 100 1M -250 10M 100M 1G 1k 10k 100k FREQUENCY (Hz) 200 200 200 SIMULATION 100 100 100 100 50 50 50 50 0 0 GAIN -50 -50 -100 -100 -150 PHASE -200 -250 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 12 0 -50 -150 -200 -200 -250 1G -250 0 150 0 GAIN -50 -100 -150 FIGURE 32. OPEN-LOOP FREQUENCY RESPONSE (CL = 22pF) Submit Document Feedback GAIN (dB) 150 PHASE (°) 150 150 GAIN (dB) -200 PHASE PHASE (°) PHASE -100 PHASE 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M -150 -200 -250 1G FIGURE 33. OPEN-LOOP FREQUENCY RESPONSE (CL = 47pF) FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 200 SIMULATION 150 100 100 50 50 0 0 GAIN -50 -50 PHASE (°) GAIN (dB) 150 -100 -100 -150 CMRR (dB) 200 -150 PHASE -200 -200 -250 0 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M -250 1G 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 100 ±2.5V 1k 50 100M G = 1000 40 ±1.5V 30 ±18V G = 100 20 G = 10 10 0 -10 G=1 -20 -30 -40 ±2.5V 1k 10k 100k 1M 10M -50 100 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 37. CLOSED LOOP GAIN vs FREQUENCY RESPONSE FIGURE 36. PSRR vs FREQUENCY 20 10 RF = 10kΩ 0 0 -10 RF = 100Ω -20 GAIN (dB) GAIN (dB) 10M 60 FREQUENCY (Hz) 10 10k 100k 1M FREQUENCY (Hz) 70 GAIN (dB) PSRR (dB) ±18V FIGURE 35. CMRR vs FREQUENCY FIGURE 34. OPEN-LOOP FREQUENCY RESPONSE (CL = 100pF) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 100 ±1.5V RF = 1kΩ -30 -40 RL = 5kΩ RL = 2kΩ RL = 10kΩ -10 RL = 1kΩ -20 -50 -60 -70 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 38. FEEDBACK RESISTANCE (RF) vs FREQUENCY RESPONSE Submit Document Feedback 13 -30 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 39. LOAD RESISTANCE vs FREQUENCY RESPONSE FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) 10 10 0 0 12pF 27pF -20 GAIN (dB) GAIN (dB) -10 47pF 68pF -30 -50 100 ±2.5V ±18V -20 -30 ACL = 1 RL = 10kΩ VS = ±18V -40 ±1.5V -10 1k 10k 100k 1M 10M -40 100M 100 1k 10k ±1.5V 25 15 +25°C 10 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 0.0 100M 70 400 60 350 +125°C 40 -55°C +25°C 20 0.5 1.0 1.5 2.0 STEP SIZE (V) 2.5 3.0 3.5 FIGURE 43. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±1.5V) 450 50 +125°C 20 5 SLEW RATE (V/µs) SLEW RATE (V/µs) 100M -55°C 30 ±2.5V SLEW RATE (V/µs) CROSSTALK REJECTION (dB) ±18V 80 -55°C 300 250 +25°C +125°C 200 150 100 10 0 10M 35 FIGURE 42. CROSSTALK REJECTION vs FREQUENCY 30 1M FIGURE 41. SUPPLY VOLTAGE vs FREQUENCY RESPONSE FIGURE 40. UNITY GAIN RESPONSE vs LOAD CAPACITANCE 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 100 100k FREQUENCY (Hz) FREQUENCY (Hz) 50 0 1 2 3 4 5 6 STEP SIZE (V) FIGURE 44. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±2.5V) Submit Document Feedback 14 0 0 5 10 15 STEP SIZE (V) 20 25 FIGURE 45. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±18V) FN8592.2 September 1, 2016 ISL70244SEH Typical Performance Curves Unless otherwise specified, VS ± 18V, VCM = 0, VO = 0V, TA = +25°C. (Continued) (INPUT) 200mV/DIV (INPUT) 200mV/DIV (OUTPUT) AV = -100 RL = 2kΩ RF = 100kΩ, Rg = 1kΩ VIN = 400mVP-P (OUTPUT) AV = -100 RL = 1kΩ RF = 100kΩ, Rg = 1kΩ VIN = 400mVP-P VS = ±18V 1µs/DIV VS = ±5V 1µs/DIV FIGURE 47. SATURATION RECOVERY (VS = ±5V) FIGURE 46. SATURATION RECOVERY (VS = ±18V) 40 VS = ±18V 35 (INPUT) 200mV/DIV RL = 10kΩ OVERSHOOT (%) 30 AV = -100 RL = 2kΩ RF = 100kΩ, Rg = 1kΩ VIN = 400mVP-P AV = 1 20 OS+ 15 (OUTPUT) 10 VS = ±2.5V 5 0 1 10 CAPACITANCE (pF) 1µs/DIV FIGURE 48. SATURATION RECOVERY (VS = ±2.5V) OS- VOUT = 25mVP-P 25 100 FIGURE 49. OVERSHOOT (%) vs LOAD CAPACITANCE 2V/DIV, INPUT 2V/DIV, OUTPUT No Output Phase Reversal VS = ±5V VIN = 12VP-P 10µs/DIV FIGURE 50. INPUT OVERDRIVE RESPONSE Submit Document Feedback 15 FN8592.2 September 1, 2016 ISL70244SEH Post High Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 19.8V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 10 30 VS = ±19.8V 8 20 6 4 GROUNDED GROUNDED CURRENT (nA) VOLTAGE (µV) VS = ±19.8V 2 0 -2 BIASED -4 -6 10 0 BIASED -10 -20 -8 -10 0 50 100 150 krad(Si) 200 250 -30 300 10 CURRENT (nA) CURRENT (nA) 200 250 300 VS = ±19.8V 1.0 BIASED 0 -10 GROUNDED -20 BIASED 0.5 0 -0.5 GROUNDED -1.0 -1.5 -30 -40 0 50 100 150 krad(Si) 200 250 -2.0 300 FIGURE 53. IBIAS- SHIFT vs HIGH DOSE RATE RADIATION 0.80 0 50 200 250 300 VS = ±19.8V 0.60 0.40 CURRENT (mA) GROUNDED 0.00 -0.20 BIASED -0.40 150 krad(Si) 0.80 0.40 0.20 100 FIGURE 54. IOS SHIFT vs HIGH DOSE RATE RADIATION VS = ±19.8V 0.60 CURRENT (mA) 150 krad(Si) 1.5 20 BIASED 0.20 0.00 GROUNDED -0.20 -0.40 -0.60 -0.60 -0.80 100 2.0 VS = ±19.8V 30 50 FIGURE 52. IBIAS+ SHIFT vs HIGH DOSE RATE RADIATION FIGURE 51. VOS SHIFT vs HIGH DOSE RATE RADIATION 40 0 0 50 100 150 200 250 krad(Si) FIGURE 55. I+ vs HIGH DOSE RATE RADIATION Submit Document Feedback 16 300 -0.80 0 50 100 150 krad(Si) 200 250 300 FIGURE 56. I- vs HIGH DOSE RATE RADIATION FN8592.2 September 1, 2016 ISL70244SEH Post Low Dose Rate Radiation Characteristics Unless otherwise specified, VS ± 19.8V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 30 30 VS = ±19.8V VS = ±19.8V 20 20 GROUNDED CURRENT (nA) VOLTAGE (µV) 10 0 BIASED -10 -20 -30 GROUNDED 10 0 BIASED -10 -20 0 10 20 30 40 50 60 70 80 90 -30 100 0 10 20 30 40 krad(Si) FIGURE 57. VOS SHIFT vs LOW DOSE RATE RADIATION 40 1.0 CURRENT (nA) CURRENT (nA) BIASED -10 100 BIASED 0.5 0 -0.5 -1.0 -20 GROUNDED -30 0 10 20 30 GROUNDED -1.5 40 50 60 70 80 90 -2.0 100 0 10 20 30 40 krad(Si) 0.80 60 70 80 90 100 FIGURE 60. IOS vs LOW DOSE RATE RADIATION 0.80 VS = ±19.8V 0.60 VS = ±19.8V 0.60 BIASED 0.40 0.20 CURRENT (mA) 0.40 GROUNDED 0.00 -0.20 -0.40 0.20 0.00 GROUNDED -0.20 -0.40 BIASED -0.60 -0.80 50 krad(Si) FIGURE 59. IBIAS- vs LOW DOSE RATE RADIATION CURRENT (mA) 90 VS = ±19.8V 1.5 0 -40 80 2.0 20 10 70 FIGURE 58. IBIAS+ vs LOW DOSE RATE RADIATION VS = ±19.8V 30 50 60 krad(Si) 0 10 20 -0.60 30 40 50 60 70 80 krad(Si) FIGURE 61. I+ vs LOW DOSE RATE RADIATION Submit Document Feedback 17 90 100 -0.80 0 10 20 30 40 50 60 krad(Si) 70 80 90 100 FIGURE 62. I- vs LOW DOSE RATE RADIATION FN8592.2 September 1, 2016 ISL70244SEH Applications Information Functional Description The ISL70244SEH contains two high speed, low power op amps designed to take advantage of its full dynamic input and output voltage range with rail-to-rail operation. By offering low power, low offset voltage and low temperature drift coupled with its high bandwidth and enhanced slew rates upwards of 50V/µs, these op amps are ideal for applications requiring both high DC accuracy and AC performance. The ISL70244SEH is manufactured in Intersil’s PR40 silicon-on-insulator process, which makes this device immune to single-event latch-up and provides excellent radiation tolerance. This makes it the ideal choice for high reliability applications in harsh radiation-prone environments. Operating Voltage Range The devices are designed to operate with a split supply rail from ±1.35V to ±20V or a single supply rail from 2.7V to 40V. The ISL70244SEH is fully characterized in production for supply rails of 5V (±2.5V) and 36V (±18V). The power supply rejection ratio is typically 120dB with a nominal ±18V supply. The worst case common-mode rejection ratio over-temperature is within 1.5V to 2V of each rail. When VCM is inside that range, the CMRR performance is typically >110dB with ±18V supplies. The minimum CMRR performance over the -55°C to +125°C temperature range and radiation is >70dB over the full common-mode input range for power supply voltages from ±2.5V (5V) to ±18V (36V). Input Performance The slew enhanced front end is a block that is placed in parallel with the main input stage and functions based on the input differential voltage. long term reliability of the part and is not recommended. Figure 21 on page 10 shows the typical short-circuit currents that can be expected. The ISL70244SEH’s current limiting circuitry will automatically lower the current limit of the device if short-circuit conditions carry on for extended periods of time in an effort to protect itself from malfunction. However, extended operation in this mode will degrade the output rail-to-rail performance by pulling VOH/VOL away from the rails. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL70244SEH is immune to output phase reversal, even when the input voltage is 1V beyond the supplies. This is illustrated in Figure 50 on page 15. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: (EQ. 1) T JMAX = T MAX + JA x PD MAXTOTAL Where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I qMAX + V S - V OUTMAX ---------------------------R L Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, series connected 600Ω current limiting resistors and an anti-parallel diode pair across the inputs. (EQ. 2) Where: • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier V+ • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier - 600Ω VIN + 600Ω VOUT RL V- FIGURE 63. INPUT ESD DIODE CURRENT LIMITING, UNITY GAIN Output Short-Circuit Current Limiting The output current limit has a worst case minimum limit of ±8mA but may reach as high as ±100mA. The op amp can withstand a short-circuit to either rail for a short duration (<1s) as long as the maximum operating junction temperature is not violated. This applies to only one amplifier at a given time. Continued use of the device in these conditions may degrade the Submit Document Feedback 18 • VOUTMAX = Maximum output voltage swing of the application Unused Channel Configuration The ISL70244SEH is a dual op amp. If the application does not require the use of both op amps, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This results in higher-than-expected supply currents and possible noise injection into the active channel. The proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (Figure 64). + FIGURE 64. PREVENTING OSCILLATIONS IN UNUSED CHANNELS FN8592.2 September 1, 2016 ISL70244SEH Die Characteristics Die Dimensions Assembly Related Information SUBSTRATE POTENTIAL 2410µm x 1961µm (95 mils x 77 mils) Thickness: 483µm ±25µm (19 mils ±1 mil) Interface Materials Floating Additional Information WORST CASE CURRENT DENSITY GLASSIVATION <2x105A/cm2 Type: Nitrox Thickness: 15kÅ TRANSISTOR COUNT 365 TOP METALLIZATION Weight of Packaged Device Type: AlCu (99.5%/0.5%) Thickness: 30kÅ 0.3958 grams (typical) Lid Characteristics BACKSIDE FINISH Silicon Finish: Gold Potential: Unbiased, tied to package pin 6 Case Isolation to Any Lead: 20x109 Ω (minimum) PROCESS PR40 Metallization Mask Layout Submit Document Feedback 19 FN8592.2 September 1, 2016 ISL70244SEH TABLE 1. DIE LAYOUT X-Y COORDINATES PAD NAME PAD NUMBER X (µm) Y (µm) dX (µm) dY (µm) BOND WIRES PER PAD OUTB 1 1015.5 664.0 110 110 1 V+ 2 557.0 664.0 110 110 1 OUTA 3 -317.0 664.0 110 110 1 -INA 4 -1015.5 658.0 110 110 1 +INA 5 -1015.5 270.5 110 110 1 V- 12 -1015.5 -918.0 110 110 1 +INB 21 1015.5 62.0 110 110 1 -INB 22 1015.5 449.5 110 110 1 NOTE: 7. Origin of coordinates is the centroid of the die. Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 1, 2016 FN8592.2 Updated x-axis and y-axis label on Figure 2 on page 1. Updated Note 2. June 12, 2015 FN8592.1 Updated Related Literature Section on page 1. In the Ordering Information Table on page 3, updated FG name from “ISL70244SEHVX/SAMPLE and ISL70244SEHF/SAMPLE” to ISL70244SEHX/SAMPLE. September 22, 2014 FN8592.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 20 FN8592.2 September 1, 2016 ISL70244SEH Ceramic Metal Seal Flatpack Packages (Flatpack) K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B) 10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE e A INCHES A -A- D -BPIN NO. 1 ID AREA b E1 0.004 M H A-B S D S S1 0.036 M Q H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 BASE METAL (c) b1 M MIN MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.290 - 7.37 3 E 0.240 0.260 6.10 6.60 - E1 - 0.280 - 7.11 3 E2 0.125 - 3.18 - - E3 0.030 - 0.76 - 7 2 e LEAD FINISH M 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - 0.04 - N (b) MILLIMETERS SYMBOL 10 SECTION A-A 10 Rev. 0 3/07 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 21 For the most recent package outline drawing, see K10.A. FN8592.2 September 1, 2016