STMicroelectronics M48T35-70PC6F 5v, 256 kbit (32 kb x 8) timekeeper sram Datasheet

M48T35
M48T35Y
5V, 256 Kbit (32 Kb x 8) TIMEKEEPER® SRAM
Features
■
Integrated, ultra low power SRAM, real time
clock, power-fail control circuit and battery
■
BYTEWIDE™ RAM-like clock access
■
BCD coded year, month, day, date, hours,
minutes, and seconds
■
Frequency test output for real time clock
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
(VPFD = Power-fail Deselect Voltage):
– M48T35: VCC = 4.75 to 5.5V
– 4.5V ≤ VPFD ≤ 4.75V
– M48T35Y: VCC = 4.5 to 5.5V
– 4.2V ≤ VPFD ≤ 4.5V
■
Self-contained battery and crystal in the
CAPHAT™ DIP package
■
SOIC package provides direct connection for a
SNAPHAT® housing containing the battery and
crystal
■
SNAPHAT® housing (battery and crystal) is
replaceable
■
Pin and function compatible with JEDEC
standard 32 Kb x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
August 2007
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
Rev 7
1/29
www.st.com
1
Contents
M48T35 M48T35Y
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
M48T35 M48T35Y
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 21
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package mechanical data . . . 22
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data . . 23
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mechanical data . 24
PMDIP28 – 28-pin plastic DIP, hybrid, package mechanical data . . . . . . . . . . . . . . . . . . . 25
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
M48T35 M48T35Y
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
4/29
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline . . . . . . . . . . . . . . . . . . . 21
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 22
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 23
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 24
PMDIP28 – 28-pin plastic DIP, hybrid, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M48T35 M48T35Y
1
Summary description
Summary description
The M48T35/Y TIMEKEEPER® RAM is a 32Kb x 8 non-volatile static RAM and real time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery backed-up memory and real time clock solution.
The M48T35/Y is a non-volatile pin and function equivalent to any JEDEC standard 32Kb x
8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT houses the M48T35/Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in
plastic anti-static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28BR12SH” (see Table 18 on page 27).
Figure 1.
Logic diagram
VCC
15
8
A0-A14
W
DQ0-DQ7
M48T35
M48T35Y
E
G
VSS
AI01620B
5/29
Summary description
Table 1.
M48T35 M48T35Y
Signal names
A0-A14
Address inputs
DQ0-DQ7
Data inputs / outputs
E
Chip enable
G
Output enable
W
WRITE Enable
VCC
Supply voltage
VSS
Ground
Figure 2.
DIP connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
M48T35 22
8 M48T35Y 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01621B
Figure 3.
SOIC connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7
22
M48T35Y
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AI01622B
6/29
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M48T35 M48T35Y
Figure 4.
Summary description
Block diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
W
VPFD
G
VSS
AI01623
7/29
Operation modes
2
M48T35 M48T35Y
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T35/Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible BYTEWIDE
clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35/Y includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T35/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below the
Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Mode
VCC
Deselect
4.75 to 5.5V
or
4.5 to 5.5V
WRITE
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up
Mode
READ
1. See Table 11 on page 20 for details.
Note:
2.1
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Read mode
The M48T35/Y is in the READ Mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The unique address specified by the 15 Address Inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last address input signal is stable, providing
that the E and G access times are also satisfied.
If the E and G access times are not met, valid data will be available after the latter of the
Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV.
8/29
M48T35 M48T35Y
Operation modes
If the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 5.
Read mode AC waveforms
tAVAV
VALID
A0-A14
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note:
WRITE Enable (W) = High.
Table 3.
Read mode AC characteristics
M48T35/Y
Parameter(1)
Symbol
Unit
Min
Max
tAVAV
READ Cycle Time
70
ns
tAVQV
Address Valid to Output Valid
70
ns
tELQV
Chip Enable Low to Output Valid
70
ns
tGLQV
Output Enable Low to Output Valid
35
ns
tELQX(2)
Chip Enable Low to Output Transition
5
ns
tGLQX(2)
Output Enable Low to Output Transition
5
ns
tEHQZ
(2)
tGHQZ(2)
tAXQX
Chip Enable High to Output Hi-Z
25
ns
Output Enable High to Output Hi-Z
25
ns
Address Transition to Output Transition
10
ns
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF.
2.2
Write mode
The M48T35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE Cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
9/29
Operation modes
M48T35 M48T35Y
WRITE Cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
Write enable controlled, write AC waveform
tAVAV
VALID
A0-A14
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7.
Chip enable controlled, write AC waveforms
tAVAV
A0-A14
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
Table 4.
Symbol
Write mode AC characteristics
M48T35/Y
Parameter(1)
Unit
Min
Max
tAVAV
WRITE Cycle Time
70
ns
tAVWL
Address Valid to WRITE Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
10/29
M48T35 M48T35Y
Table 4.
Symbol
Operation modes
Write mode AC characteristics (continued)
M48T35/Y
Parameter(1)
Unit
Min
Max
tWLWH
WRITE Enable Pulse Width
50
ns
tELEH
Chip Enable Low to Chip Enable High
55
ns
tWHAX
WRITE Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to WRITE Enable High
30
ns
tDVEH
Input Valid to Chip Enable High
30
ns
tWHDX
WRITE Enable High to Input Transition
5
ns
tEHDX
Chip Enable High to Input Transition
5
ns
tWLQZ
(2)(3)
WRITE Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to WRITE Enable High
60
ns
tAVEH
Address Valid to Chip Enable High
60
ns
WRITE Enable High to Output Transition
5
ns
tWHQX(2)(3)
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on
page 19, Table 10, and Table 11 on page 20).
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T35/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)
plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent
WRITE Cycles prior to processor stabilization. Normal RAM operation can resume trec after
VCC exceeds VPFD (max).
For more information on Battery Storage Life refer to the Application Note AN1012.
11/29
Clock operations
3
Clock operations
3.1
Reading the clock
M48T35 M48T35Y
Updates to the TIMEKEEPER® registers (see Table 5) should be halted before clock data is
read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM
array are only data registers and not the actual clock counters, so updating the registers can
be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h.
As long as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the count; that is, the day, date, and the time that
were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the Control Register 7FF8h is the WRITE Bit. Setting the WRITE Bit to a '1,' like
the READ Bit, halts updates to the TIMEKEEPER® registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see Table 5). Resetting the
WRITE Bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits
marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE Bit is reset, the next clock update will occur within one second.
See the Application Note AN923, “TIMEKEEPER® Rolling Into the 21st Century” for
information on Century Rollover.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T35/Y is shipped from STMicroelectronics with the STOP Bit set to a '1.'
When reset to a '0,' the M48T35/Y oscillator starts within 1 second.
12/29
M48T35 M48T35Y
Table 5.
Clock operations
Register map
Data
Function/Range
Address
D7
D6
7FFFh
D5
D4
D3
10 Years
7FFEh
0
0
0
10 M.
7FFDh
0
0
10 Date
7FFCh
0
FT
7FFBh
0
0
7FFAh
0
7FF9h
ST
7FF8h
W
CEB
CB
10 Hours
10 Minutes
10 Seconds
R
S
D2
D1
D0
BCD Format
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Century/
Day
00-01/0107
0
Day
Hours
Hours
00-23
Minutes
Minutes
00-59
Seconds
Seconds
00-59
Calibration
Control
Keys:
S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to '0' upon power for normal operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
CEB = Century Enable Bit
CB = Century Bit
Note:
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to
CEB.
3.4
Calibrating the clock
The M48T35/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency
error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits
properly set, the accuracy of each M48T35/Y improves to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 15).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T35/Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 15. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register
7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
13/29
Clock operations
M48T35 M48T35Y
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If
a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T35/Y may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit
in the Day Register is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator
Running), DQ0 will toggle at 512 Hz during a READ of the Seconds Register. Any deviation
from 512 Hz indicates the degree and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for
correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output
frequency.
The FT Bit MUST be reset to '0' for normal clock operations to resume. The FT Bit is
automatically Reset on power-down.
For more information on calibration, see Application Note AN934, “TIMEKEEPER®
Calibration.”
3.5
Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Note:
14/29
The WRITE Bit must be set in order to write to the CENTURY Bit.
M48T35 M48T35Y
Clock operations
Figure 8.
Crystal accuracy across temperature
ppm
20
0
-20
-40
ΔF = -0.038 ppm (T - T )2 ± 10%
0
F
C2
-60
T0 = 25 °C
-80
-100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
°C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.6
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass capacitor value of 0.1µF (as shown in Figure 10
on page 16) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
15/29
Clock operations
M48T35 M48T35Y
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 10. Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
16/29
M48T35 M48T35Y
4
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD
(1)(2)(3)
Parameter
Ambient Operating Temperature
Value
Unit
Grade 1
0 to 70
°C
Grade 6
–40 to 85
°C
–40 to 85
°C
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
260
°C
M48T35
–0.3 to 7
V
M48T35Y
–0.3 to 7
V
M48T35
–0.3 to 7
V
M48T35Y
VIO
Input or Output Voltages
VCC
Supply Voltage
–0.3 to 7
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
17/29
DC and AC parameters
5
M48T35 M48T35Y
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
M48T35
M48T35Y
Unit
4.75 to 5.5
4.5 to 5.5
V
0 to 70
–40 to 85
°C
Load Capacitance (CL)
100
100
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC measurement load circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL = 100pF or 5pF
CL includes JIG capacitance
Table 8.
18/29
AI01030
Capacitance
Symbol
Parameter(1)(2)
CIN
COUT(3)
Min
Max
Unit
Input Capacitance
10
pF
Output Capacitance
10
pF
1.
Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2.
At 25°C, f = 1MHz.
3.
Outputs deselected.
M48T35 M48T35Y
DC and AC parameters
Table 9.
DC characteristics
Symbol
Parameter
M48T35
Test condition(1)
M48T35Y
Unit
Min
Max
Min
Max
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±1
±1
µA
ILO(2)(2)
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
±1
µA
ICC
Supply Current
Outputs open
50
30
mA
ICC1
Supply Current (Standby)
TTL
E = VIH
3
3
mA
ICC2
Supply Current (Standby)
CMOS
E = VCC – 0.2V
2
2
mA
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.4
2.4
2.4
V
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. Outputs deselected.
Figure 12. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
trec
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
19/29
DC and AC parameters
Table 10.
M48T35 M48T35Y
Power down/up AC characteristics
Parameter(1)
Symbol
tPD
tF
(2)
tFB(3)
Min
E or W at VIH before Power Down
Unit
0
µs
300
µs
M48T35
10
µs
M48T35Y
10
µs
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSS VCC Fall Time
Max
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
trec(4)(4)
VPFD (max) to Inputs Recognized
40
200
ms
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. trec (min) = 20ms for industrial temperature Grade 6 device.
Table 11.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)(5)
Expected Data Retention Time
Min
Typ
Max
Unit
M48T35
4.5
4.6
4.75
V
M48T35Y
4.2
4.35
4.5
V
M48T35
M48T35Y
3.0
V
3.0
V
Grade 1
10(4)
YEARS
Grade 6
10(5)
YEARS
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. All voltages referenced to VSS.
3. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).
4. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
5. At 25°C, VCC = 0V.
20/29
M48T35 M48T35Y
6
Package mechanical information
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline
A2
A1
B1
B
A
L
C
e1
eA
e3
D
N
E
1
Note:
PCDIP
Drawing is not to scale.
Table 12.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data
mm
inches
Symbol
Typ
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
21/29
Package mechanical information
M48T35 M48T35Y
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT,
package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 13.
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package
mechanical data
mm
inches
Symbol
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
28
e
CP
22/29
Max
1.27
0.050
28
0.10
0.004
M48T35 M48T35Y
Package mechanical information
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHTK
Note:
Drawing is not to scale.
Table 14.
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package
mechanical data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
23/29
Package mechanical information
M48T35 M48T35Y
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHTK
Note:
Drawing is not to scale.
Table 15.
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
mechanical data
mm
inches
Symbol
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
24/29
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48T35 M48T35Y
Package mechanical information
Figure 17. PMDIP28 – 28-pin plastic DIP, hybrid, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
Note:
PMDIP
Drawing is not to scale.
Table 16.
PMDIP28 – 28-pin plastic DIP, hybrid, package mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
9.27
9.53
0.365
0.375
A1
0.38
B
0.43
0.58
0.017
0.023
C
0.20
0.33
0.008
0.013
0.015
D
37.34
37.85
1.470
1.490
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
33.02
1.300
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.67
0.075
0.105
N
28
28
25/29
Part numbering
7
M48T35 M48T35Y
Part numbering
Table 17.
Ordering information scheme
Example:
M48T
35
–70
PC
1
E
Device type
M48T
Supply voltage and write protect voltage
35(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
35Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed
–70 = 70ns
Package
PC = PCDIP28
MH(2) = SOH28
PM = PMDIP28 (NND)(3)
Temperature range
1 = 0 to 70°C
6 = –40 to 85°C(4)
Shipping method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = ECOPACK package, tubes
F = ECOPACK package, tape & reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = ECOPACK package, tubes
1. The M48T35 part is offered with the PCDIP28 (e.g., CAPHAT) package only.
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered
separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in
Tape & Reel form (see Table 18 on page 27).
3. This package is not to be used for New Design.
4. Available in SOIC package only.
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
26/29
M48T35 M48T35Y
Part numbering
Table 18.
SNAPHAT battery table
Part number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
Package
SH
SH
27/29
Revision history
8
Revision history
Table 19.
28/29
M48T35 M48T35Y
Document revision history
Date
Revision
Changes
Nov- 1999
1.0
First Issue
07-Feb-2000
1.1
tDR Description changed (Table 9)
04-Jun-2001
2.0
Reformatted; temp/voltage info. added to tables (Table 8, 9, 3, 4, 10,
11); add Century Bit text
31-Jul-2001
2.1
Formatting changes based on latest document reviews
06-Mar-2002
2.2
Add PMDIP Packaging option, which is “Not for New Design” (NND)
(Table 17, 16, and Figure 17)
20-May-2002
2.3
Modify reflow time and temperature footnotes (Table 6)
26-Jun-2002
2.4
Add footnote to table (Table 11)
31-Mar-2003
3.0
v2.2 template applied; data retention condition updated (Table 11)
10-Dec-2003
4.0
Reformatted; update DC Characteristics (Table 9)
31-Mar-2004
5.0
Reformatted; update Pb-free package information (Table 6, 17)
05-Dec20-05
6.0
Updated template, Lead-free text, and remove footnote (Table 9, 17)
01-Aug-2007
7.0
Reformatted; added lead-free second level interconnect information to
cover page and Section 6: Package mechanical information.
M48T35 M48T35Y
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29/29