MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* • • • • KVP05 AYWWG G 1 Features • • • • 8 8 SOIC−8 D SUFFIX CASE 751 220 ps Typical Propagation Delay Input Clock Frequency > 3 GHz 0.2 ps Typical RMS Random Clock Period Jitter LVPECL Mode Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.6 V Open Input Default State Q Output Will Default LOW with Inputs Open These are Pb−Free Devices* 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948R 1 1 DFN8 MN SUFFIX CASE 506AA K M A L = MC100 = Date Code = Assembly Location = Wafer Lot 4 KU05 ALYWG G 6N MG G Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 2 1 Publication Order Number: MC100LVEP05/D MC100LVEP05 Table 1. PIN DESCRIPTION D0 D0 D1 1 8 2 7 6 3 Pin VCC Q Function D0*, D1*, D0**, D1** ECL Data Inputs Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Q * Pins will default LOW when left open. ** Pins will default to VCC/2when left open. D1 4 5 VEE Table 2. TRUTH TABLE Figure 1. 8−Lead Pinout (Top View) and Logic Diagram D0 D1 D0 D1 Q Q L L H H L H L H H H L L H L H L L L L H H H H L Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−8 DFN8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V > 2 kV Pb Pkg Level 1 Level 1 Pb−Free Pkg Level 3 Level 1 UL 94 V−0 @ 0.125 in 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100LVEP05 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder 3 sec @ 260°C 265 °C qJC Thermal Resistance (Junction−to−Case) (Note 2) 35 to 40 °C/W VI VCC VI VEE DFN8 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 15 25 32 17 27 36 19 28 38 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 4) 555 730 900 555 730 900 555 730 900 mV VIH Input HIGH Voltage (Single−Ended) 1355 1620 1355 1620 1355 1620 mV VIL Input LOW Voltage (Single−Ended) 555 900 555 900 555 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Notes 5, 6) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 D D 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 4. All loading with 50 W to VCC − 2.0 V. 5. Single−ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100LVEP05 Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 15 25 32 17 27 36 19 28 38 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 8) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 D D 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 8. All loading with 50 W to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100LVEP05 Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −2.375 V to −3.6 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 15 25 32 17 27 36 19 28 38 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1600 −1945 −1600 −1945 −1600 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current VEE+1.2 0.0 VEE+1.2 0.0 150 D D 0.5 −150 VEE+1.2 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 V to −3.6 V or VCC = 2.375 V to 3.6 V; VEE = 0 V (Note 13) −40°C Symbol Min Characteristic fmax Maximum Frequency (Figure 2) 3.0 tPLH, tPHL Propagation Delay to Output Differential 160 tJITTER RMS Random Clock Jitter fin (Figure 2) VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Times (20% − 80%) Max Min Typ 85°C Max 3.0 210 260 0.2 1 150 800 1200 70 120 170 3.0 GHz Q Typ 25°C 170 Min Typ Max 3.0 220 270 0.2 1 150 800 1200 80 130 180 210 Unit GHz 260 320 ps 0.2 1.5 ps 150 800 1200 mV 100 150 200 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. http://onsemi.com 5 MC100LVEP05 10 VOUTamplitude (mVpp) 850 9 750 8 3.3 V 650 7 6 550 5 4 450 3 2 350 1 250 1.0 0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 Figure 2. Fmax @ 255C Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 6 MC100LVEP05 ORDERING INFORMATION Package Shipping† MC100LVEP05DG SOIC−8 (Pb−Free) 98 Units / Rail MC100LVEP05DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100LVEP05DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100LVEP05DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100LVEP05MNTXG DFN8 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC100LVEP05 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVEP05 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B −U− 4 M A −V− S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 9 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVEP05 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.10 C A 0.10 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 8X 0.08 C SEATING PLANE (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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