The following document contains information on Cypress products. Although the document is marked with the name “Spansion”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes ® NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC ® programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense ® capacitive touch-sensing controllers, and Wireless BLE Bluetooth Low-Energy and USB connectivity solutions, Cypress is committed to providing its customers worldwide with consistent innovation, bestin-class support and exceptional system value. MB9AAA0N Series 32-bit ARM® Cortex®-M3 based Microcontroller MB9AFAA1L/M/N, MB9AFAA2L/M/N Data Sheet (Full Production) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number MB9AAA0N_DS706-00067 CONFIDENTIAL Revision 2.0 Issue Date June 30, 2015 D a t a S h e e t Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 CONFIDENTIAL MB9AAA0N Series 32-bit ARM® Cortex®-M3 based Microcontroller MB9AFAA1L/M/N, MB9AFAA2L/M/N Data Sheet (Full Production) Description The MB9AAA0N Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power consumption mode and competitive cost. The MB9AAA0N Series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as LCD Controller, Motor Control Timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE7 product categories in FM3 Family Peripheral Manual. Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. Publication Number MB9AAA0N_DS706-00067 Revision 2.0 Issue Date June 30, 2015 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 20MHz Operation Frequency Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Up to 128 Kbytes Read cycle: 0 wait-cycle Security function for code protection [SRAM] This series contains a total of up to 16 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core. SRAM1: Up to 16 Kbytes LCD controller (LCDC) Selectable from 44 SEG × 4 COM (Max) or 40 SEG × 8 COM (Max) Internal divide resistor is contained (selectable from 10 kΩ or 100 kΩ for the resistor value) LCD drive power supply (bias) pin (VV4 to VV0) Interrupt function synchronized with the LCD module frame frequency With blinking function Inverted display function Multi-function Serial Interface (Max 8 channels) Operation mode is selectable from the followings for each channel. UART CSIO I 2C [UART] Full duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available 2 [I C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported 2 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t A/D Converter (Max 16 channels) [12-bit A/D Converter] Successive Approximation type Conversion time: Min 1.0 s Priority conversion available (priority at 2 levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4 steps) D/A Converter (Max 2 channels) R-2R type 10-bit resolution Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 84 high-speed general-purpose I/O Ports@100 pin Package Some ports are 5V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer × 3ch. Input capture × 4ch. Output compare × 6ch. A/D activation compare × 1ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. IGBT mode is contained. The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 3 D a t a S h e e t HDMI-CEC/Remote Control Receiver (Up to 2 channels) HDMI- CEC receiver / Remote control receiver Operating modes supporting the following standards can be selected SIRCS NEC/Association for Electric Home Appliances HDMI-CEC Capable of adjusting detection timings for start bit and data bit Equipped with noise filter HDMI-CEC transmitter Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. External Interrupt Controller Unit Up to 16 external interrupt input pins Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption mode except RTC, Stop, Deep Standby RTC and Deep Standby Stop modes. Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: Sub Clock: Built-in High-speed CR Clock: Built-in Low-speed CR Clock: Main PLL Clock 4 MHz to 20 MHz 32.768 kHz 4 MHz 100 kHz [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Viser reset 4 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported. Sleep Timer RTC Stop Deep Standby RTC Deep Standby Stop The back up register is 16 byte Debug Serial Wire JTAG Debug Port (SWJ-DP) Power Supply Wide range voltage: VCC = 1.8 V to 5.5 V VCC = 2.2 V to 5.5 V (when LCDC is used) June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 5 D a t a S h e e t Product Lineup Memory size Product name MB9AFAA1L/M/N MB9AFAA2L/M/N 64 Kbytes 12 Kbytes 128 Kbytes 16 Kbytes On-chip Flash memory On-chip SRAM SRAM1 Function Product name Pin count MB9AFAA1L MB9AFAA2L MB9AFAA1M MB9AFAA2M MB9AFAA1N MB9AFAA2N 64 80 Cortex-M3 20 MHz 1.8 V to 5.5 V 37SEG×4COM (Max) or 33SEG×8COM (Max) 100 CPU Freq. Power supply voltage range LCD Controller (LCDC) 24SEG×4COM (Max) or 20SEG×8COM (Max) 44SEG×4COM (Max) or 40SEG×8COM (Max) Multi-function Serial Interface 8ch. (Max) (UART/CSIO/I2C) Base Timer 8ch. (Max) (PWC/ Reload timer/PWM/PPG) A/D activation 1ch. compare Input capture 4ch. Free-run timer 3ch. MF1 unit (Max) Output compare 6ch. Timer Waveform 3ch. generator PPG 3ch. (IGBT mode) HDMI-CEC/ Remote Control 2ch. (Max) Receiver Real-time clock (RTC) 1 unit Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 8 pins (Max)+ NMI × 1 11 pins (Max)+ NMI × 1 16 pins (Max)+ NMI × 1 General-purpose I/O ports 52 pins (Max) 67 pins (Max) 84 pins (Max) 12-bit A/D converter 9ch. (1 unit) 12ch. (1 unit) 16ch. (1 unit) 10-bit D/A converter 2ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz Built-in CR Low-speed 100 kHz Debug Function SWJ-DP Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for accuracy of built-in CR. 6 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Packages Product name Package LQFP: FPT-64P-M38 (0.5mm pitch) LQFP: FPT-64P-M39 (0.65mm pitch) LQFP: FPT-80P-M37 (0.5mm pitch) LQFP: FPT-80P-M40 (0.65mm pitch) LQFP: FPT-100P-M23 (0.5mm pitch) QFP: FPT-100P-M06 (0.65mm pitch) MB9AFAA1L MB9AFAA2L MB9AFAA1M MB9AFAA2M - - MB9AFAA1N MB9AFAA2N : Supported Note : See Package Dimensions for detailed information on each package. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 7 D a t a S h e e t Pin Assignment FPT-64P-M38/M39 VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 / SEG00 P62 / SCK5_0 / ADTG_3 / SEG01 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 / SEG11 P50 / SIN3_1 / INT00_0 / VV4 2 47 P22 / SOT0_0 / TIOB7_1 / SEG12 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 / SEG13 P52 / SCK3_1 / INT02_0 4 45 P19 / AN09 / SCK2_2 / SEG19 P30 / TIOB0_1 / INT03_2 / COM7 / SEG43 5 44 P18 / AN08 / SOT2_2 / SEG20 P31 / SCK6_1 / TIOB1_1 / INT04_2 / COM6 / SEG42 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 / COM5 / SEG41 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 / COM4 / SEG40 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 / COM3 9 40 P17 / AN07 / SIN2_2 / INT04_1 / SEG21 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 / COM2 10 39 P15 / AN05 / IC03_2 / SEG23 P3B / TIOA1_1 / RTO01_0 / COM1 11 38 P14 / AN04 / INT03_1 / IC02_2 / SEG24 P3C / TIOA2_1 / RTO02_0 / COM0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 / SEG25 P3D / TIOA3_1 / RTO03_0 / SEG37 13 36 P12 / AN02 / SOT1_1 / IC00_2 / SEG26 P3E / TIOA4_1 / RTO04_0 / SEG36 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 / SEG27 P3F / TIOA5_1 / RTO05_0 / SEG35 15 34 P10 / AN00 / SEG28 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 / SEG31 P4A / TIOB1_0 / SEG30 P4B / TIOB2_0 / IGTRG / SEG29 P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 8 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t FPT-80P-M37/M40 VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 / SEG00 P62 / SCK5_0 / ADTG_3 / SEG01 P63 / INT03_0 / SEG02 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 / SEG03 P0D / RTS4_0 / TIOA3_2 / SEG04 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P07 / ADTG_0 / SEG07 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (TOP VIEW) VCC 1 60 P20 / INT05_0 / CROUT_0 / SEG10 P50 / SIN3_1 / INT00_0 / VV4 2 59 P21 / SIN0_0 / INT06_1 / WKUP2 / SEG11 P51 / SOT3_1 / INT01_0 / VV3 3 58 P22 / SOT0_0 / TIOB7_1 / SEG12 P52 / SCK3_1 / INT02_0 / VV2 4 57 P23 / SCK0_0 / TIOA7_1 / SEG13 P53 / SIN6_0 / TIOA1_2 / INT07_2 / VV1 5 56 P1B / AN11 / SOT4_1 / IC01_1 / SEG17 P54 / SOT6_0 / TIOB1_2 / VV0 6 55 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 / SEG18 P55 / SCK6_0 / ADTG_1 / SEG39 7 54 P19 / AN09 / SCK2_2 / SEG19 P56 / INT08_2 / SEG38 8 53 P18 / AN08 / SOT2_2 / SEG20 P30 / TIOB0_1 / INT03_2 / COM7 / SEG43 9 52 AVSS P31 / SCK6_1 / TIOB1_1 / INT04_2 / COM6 / SEG42 10 51 AVRH P32 / SOT6_1 / TIOB2_1 / INT05_2 / COM5 / SEG41 11 50 AVCC P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 / COM4 / SEG40 12 49 P17 / AN07 / SIN2_2 / INT04_1 / SEG21 LQFP - 80 31 32 33 34 35 36 37 38 39 40 P4A / SCK3_2 / TIOB1_0 / SEG30 P4B / TIOB2_0 / IGTRG / SEG29 P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS VCC 30 P10 / AN00 / SEG28 41 29 42 20 P48 / SIN3_2 / INT14_1 / SEG32 19 VSS P49 / SOT3_2 / TIOB0_0 / SEG31 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 / SEG27 P3F / TIOA5_1 / RTO05_0 / SEG35 28 43 INITX 18 27 P12 / AN02 / SOT1_1 / IC00_2 / SEG26 P3E / TIOA4_1 / RTO04_0 / SEG36 P47 / X1A 44 26 17 P46 / X0A P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 / SEG25 P3D / TIOA3_1 / RTO03_0 / SEG37 25 45 VCC 16 24 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 / SEG24 P3C / TIOA2_1 / RTO02_0 / COM0 23 46 VSS 15 22 P15 / AN05 / SOT0_1 / IC03_2 / SEG23 P3B / TIOA1_1 / RTO01_0 / COM1 21 P16 / AN06 / SCK0_1 / SEG22 47 C 48 14 P45 / TIOA5_0 / SEG33 13 P44 / TIOA4_0 / SEG34 P39 / DTTI0X_0 / ADTG_2 / COM3 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 / COM2 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 9 D a t a S h e e t FPT-100P-M23 P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 / SEG00 P62 / SCK5_0 / ADTG_3 / SEG01 P63 / INT03_0 / SEG02 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 / SEG03 P0D / RTS4_0 / TIOA3_2 / SEG04 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P09 / RTS4_2 / TIOB0_2 / SEG05 P08 / CTS4_2 / TIOA0_2 / SEG06 P07 / SCK4_2 / ADTG_0 / SEG07 P06 / SOT4_2 / TIOB5_2 / INT01_1 / SEG08 P05 / SIN4_2 / TIOA5_2 / INT00_1 / SEG09 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 VSS (TOP VIEW) VCC 1 75 VSS P50 / SIN3_1 / INT00_0 / VV4 2 74 P20 / INT05_0 / CROUT_0 / SEG10 P51 / SOT3_1 / INT01_0 / VV3 3 73 P21 / SIN0_0 / INT06_1 / WKUP2 / SEG11 P52 / SCK3_1 / INT02_0 / VV2 4 72 P22 / SOT0_0 / TIOB7_1 / SEG12 P53 / SIN6_0 / TIOA1_2 / INT07_2 / VV1 5 71 P23 / SCK0_0 / TIOA7_1 / RTO00_1 / SEG13 P54 / SOT6_0 / TIOB1_2 / VV0 6 70 P1F / AN15 / FRCK0_1 / ADTG_5 P55 / SCK6_0 / ADTG_1 / SEG39 7 69 P1E / AN14 / RTS4_1 / DTTI0X_1 / SEG14 P56 / INT08_2 / SEG38 8 68 P1D / AN13 / CTS4_1 / IC03_1 / SEG15 P30 / TIOB0_1 / INT03_2 / COM7 / SEG43 9 67 P1C / AN12 / SCK4_1 / IC02_1 / SEG16 P31 / SCK6_1 / TIOB1_1 / INT04_2 / COM6 / SEG42 10 66 P1B / AN11 / SOT4_1 / IC01_1 / SEG17 P32 / SOT6_1 / TIOB2_1 / INT05_2 / COM5 / SEG41 11 65 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 / SEG18 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 / COM4 / SEG40 12 64 P19 / AN09 / SCK2_2 / SEG19 P34 / TIOB4_1 / FRCK0_0 13 63 P18 / AN08 / SOT2_2 / SEG20 P35 / TIOB5_1 / INT08_1 / IC03_0 14 62 AVSS P36 / SIN5_2 / INT09_1 / IC02_0 15 61 AVRH P37 / SOT5_2 / INT10_1 / IC01_0 16 60 AVCC P38 / SCK5_2 / INT11_1 / IC00_0 17 59 P17 / AN07 / SIN2_2 / INT04_1 / SEG21 P39 / DTTI0X_0 / ADTG_2 / COM3 18 58 P16 / AN06 / SCK0_1 / SEG22 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 / COM2 19 57 P15 / AN05 / SOT0_1 / IC03_2 / SEG23 P3B / TIOA1_1 / RTO01_0 / COM1 20 56 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 / SEG24 P3C / TIOA2_1 / RTO02_0 / COM0 21 55 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 / SEG25 P3D / TIOA3_1 / RTO03_0 / SEG37 22 54 P12 / AN02 / SOT1_1 / IC00_2 / SEG26 P3E / TIOA4_1 / RTO04_0 / SEG36 23 53 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 / SEG27 P3F / TIOA5_1 / RTO05_0 / SEG35 24 52 P10 / AN00 / SEG28 VSS 25 51 VCC 45 46 47 48 49 50 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS 39 P48 / SIN3_2 / INT14_1 / SEG32 44 38 INITX P4D / SOT7_1 / TIOB4_0 / DA0 37 P47 / X1A 43 36 P46 / X0A P4C / SCK7_1 / TIOB3_0 / CEC0 35 42 34 VSS VCC P4B / TIOB2_0 / IGTRG / SEG29 33 C 41 32 P45 / TIOA5_0 / SEG33 40 31 P44 / TIOA4_0 / SEG34 P49 / SOT3_2 / TIOB0_0 / SEG31 30 P4A / SCK3_2 / TIOB1_0 / SEG30 29 28 P42 / TIOA2_0 27 P41 / TIOA1_0 / INT13_1 P43 / TIOA3_0 / ADTG_7 26 VCC P40 / TIOA0_0 / INT12_1 LQFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 10 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t FPT-100P-M06 P50 / SIN3_1 / INT00_0 / VV4 VCC VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 / SEG00 P62 / SCK5_0 / ADTG_3 / SEG01 P63 / INT03_0 / SEG02 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 / SEG03 P0D / RTS4_0 / TIOA3_2 / SEG04 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P09 / RTS4_2 / TIOB0_2 / SEG05 P08 / CTS4_2 / TIOA0_2 / SEG06 P07 / SCK4_2 / ADTG_0 / SEG07 P06 / SOT4_2 / TIOB5_2 / INT01_1 / SEG08 P05 / SIN4_2 / TIOA5_2 / INT00_1 / SEG09 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC VSS P20 / INT05_0 / CROUT_0 / SEG10 P21 / SIN0_0 / INT06_1 / WKUP2 / SEG11 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (TOP VIEW) P51 / SOT3_1 / INT01_0 / VV3 81 50 P22 / SOT0_0 / TIOB7_1 / SEG12 P52 / SCK3_1 / INT02_0 / VV2 82 49 P23 / SCK0_0 / TIOA7_1 / RTO00_1 / SEG13 P53 / SIN6_0 / TIOA1_2 / INT07_2 / VV1 83 48 P1F / AN15 / FRCK0_1 / ADTG_5 P54 / SOT6_0 / TIOB1_2 / VV0 84 47 P1E / AN14 / RTS4_1 / DTTI0X_1 / SEG14 P55 / SCK6_0 / ADTG_1 / SEG39 85 46 P1D / AN13 / CTS4_1 / IC03_1 / SEG15 P56 / INT08_2 / SEG38 86 45 P1C / AN12 / SCK4_1 / IC02_1 / SEG16 P30 / TIOB0_1 / INT03_2 / COM7 / SEG43 87 44 P1B / AN11 / SOT4_1 / IC01_1 / SEG17 P31 / SCK6_1 / TIOB1_1 / INT04_2 / COM6 / SEG42 88 43 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 / SEG18 P32 / SOT6_1 / TIOB2_1 / INT05_2 / COM5 / SEG41 89 42 P19 / AN09 / SCK2_2 / SEG19 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 / COM4 / SEG40 90 41 P18 / AN08 / SOT2_2 / SEG20 P34 / TIOB4_1 / FRCK0_0 91 40 AVSS P35 / TIOB5_1 / INT08_1 / IC03_0 92 39 AVRH P36 / SIN5_2 / INT09_1 / IC02_0 93 38 AVCC P37 / SOT5_2 / INT10_1 / IC01_0 94 37 P17 / AN07 / SIN2_2 / INT04_1 / SEG21 P38 / SCK5_2 / INT11_1 / IC00_0 95 36 P16 / AN06 / SCK0_1 / SEG22 P39 / DTTI0X_0 / ADTG_2 / COM3 96 35 P15 / AN05 / SOT0_1 / IC03_2 / SEG23 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 / COM2 97 34 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 / SEG24 P3B / TIOA1_1 / RTO01_0 / COM1 98 33 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 / SEG25 P3C / TIOA2_1 / RTO02_0 / COM0 99 32 P12 / AN02 / SOT1_1 / IC00_2 / SEG26 P3D / TIOA3_1 / RTO03_0 / SEG37 100 31 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 / SEG27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P3E / TIOA4_1 / RTO04_0 / SEG36 P3F / TIOA5_1 / RTO05_0 / SEG35 VSS VCC P40 / TIOA0_0 / INT12_1 P41 / TIOA1_0 / INT13_1 P42 / TIOA2_0 P43 / TIOA3_0 / ADTG_7 P44 / TIOA4_0 / SEG34 P45 / TIOA5_0 / SEG33 C VSS VCC P46 / X0A P47 / X1A INITX P48 / SIN3_2 / INT14_1 / SEG32 P49 / SOT3_2 / TIOB0_0 / SEG31 P4A / SCK3_2 / TIOB1_0 / SEG30 P4B / TIOB2_0 / IGTRG / SEG29 P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS VCC P10 / AN00 / SEG28 QFP - 100 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 11 D a t a S h e e t List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 1 1 1 79 2 2 2 80 - 3 3 81 3 - - - - 4 4 82 4 - - - - 5 5 83 - 6 6 84 - 7 7 85 - 8 8 86 12 CONFIDENTIAL Pin name VCC P50 INT00_0 SIN3_1 VV4 P51 INT01_0 SOT3_1 (SDA3_1) VV3 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) VV2 P52 INT02_0 SCK3_1 (SCL3_1) P53 SIN6_0 TIOA1_2 INT07_2 VV1 P54 SOT6_0 (SDA6_0) TIOB1_2 VV0 P55 SCK6_0 (SCL6_0) ADTG_1 SEG39 P56 INT08_2 SEG38 I/O circuit type Pin state type - R W R W E F R W E F R W R V J U J S MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 5 9 9 87 6 10 10 88 7 11 11 89 8 12 12 90 - - 13 91 - - 14 92 - - 15 93 - - 16 94 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Pin name P30 TIOB0_1 INT03_2 COM7 SEG43 P31 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 COM6 SEG42 P32 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 COM5 SEG41 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 COM4 SEG40 P34 FRCK0_0 TIOB4_1 P35 IC03_0 TIOB5_1 INT08_1 P36 IC02_0 SIN5_2 INT09_1 P37 IC01_0 SOT5_2 (SDA5_2) INT10_1 I/O circuit type Pin state type K S K S K S K S E H E F E F E F 13 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 - - 17 95 9 13 18 96 10 14 19 97 11 15 20 98 12 16 21 99 13 17 22 100 14 18 23 1 15 19 24 2 16 - 20 - 25 26 3 4 14 CONFIDENTIAL Pin name P38 IC00_0 SCK5_2 (SCL5_2) INT11_1 P39 DTTI0X_0 ADTG_2 COM3 P3A RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 COM2 P3B RTO01_0 (PPG00_0) TIOA1_1 COM1 P3C RTO02_0 (PPG02_0) TIOA2_1 COM0 P3D RTO03_0 (PPG02_0) TIOA3_1 SEG37 P3E RTO04_0 (PPG04_0) TIOA4_1 SEG36 P3F RTO05_0 (PPG04_0) TIOA5_1 SEG35 VSS VCC I/O circuit type Pin state type E F L U L U L U L U J U J U J U - MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 - - 27 5 - - 28 6 - - 29 7 - - 30 8 - 21 31 9 - 22 32 10 17 18 23 24 25 33 34 35 11 12 13 19 26 36 14 20 27 37 15 21 28 38 16 - 29 39 17 30 40 18 31 41 19 22 - 23 - June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Pin name P40 TIOA0_0 INT12_1 P41 TIOA1_0 INT13_1 P42 TIOA2_0 P43 TIOA3_0 ADTG_7 P44 TIOA4_0 SEG34 P45 TIOA5_0 SEG33 C VSS VCC P46 X0A P47 X1A INITX P48 INT14_1 SIN3_2 SEG32 P49 TIOB0_0 SEG31 SOT3_2 (SDA3_2) P4A TIOB1_0 SEG30 SCK3_2 (SCL3_2) I/O circuit type Pin state type E F E F E H E H J U J U - D M D N B C J S J U J U 15 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 24 32 42 20 25 33 43 21 26 34 44 22 27 35 45 23 28 36 46 24 29 37 47 25 30 38 48 26 31 39 49 27 32 33 40 41 50 51 28 29 34 42 52 30 35 43 53 31 36 44 54 32 16 CONFIDENTIAL Pin name P4B TIOB2_0 SEG29 IGTRG P4C TIOB3_0 SCK7_1 (SCL7_1) CEC0 P4D TIOB4_0 SOT7_1 (SDA7_1) DA0 P4E TIOB5_0 INT06_2 SIN7_1 DA1 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 SEG28 P11 AN01 SIN1_1 INT02_1 FRCK0_2 WKUP1 SEG27 P12 AN02 SOT1_1 (SDA1_1) IC00_2 SEG26 I/O circuit type Pin state type J U G Q O Z O Y C P H D A A A B - Q J Q L Q J MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 37 45 55 33 46 56 34 47 57 35 - 48 58 36 40 49 59 37 41 42 43 50 51 52 60 61 62 38 39 40 44 53 63 41 45 54 64 42 38 - 39 - June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Pin name P13 AN03 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 SEG25 P14 AN04 INT03_1 IC02_2 SEG24 SIN0_1 P15 AN05 IC03_2 SEG23 SOT0_1 (SDA0_1) P16 AN06 SCK0_1 (SCL0_1) SEG22 P17 AN07 SIN2_2 INT04_1 SEG21 AVCC AVRH AVSS P18 AN08 SOT2_2 (SDA2_2) SEG20 P19 AN09 SCK2_2 (SCL2_2) SEG19 I/O circuit type Pin state type Q J Q K Q J Q J Q K - Q J Q J 17 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 - 55 65 43 - 56 66 44 - - 67 45 - - 68 46 - - 69 47 - - 70 48 46 57 71 49 - - 47 58 72 50 18 CONFIDENTIAL Pin name P1A AN10 SIN4_1 INT05_1 IC00_1 SEG18 P1B AN11 SOT4_1 (SDA4_1) IC01_1 SEG17 P1C AN12 SCK4_1 (SCL4_1) IC02_1 SEG16 P1D AN13 CTS4_1 IC03_1 SEG15 P1E AN14 RTS4_1 DTTI0X_1 SEG14 P1F AN15 ADTG_5 FRCK0_1 P23 SCK0_0 (SCL0_0) TIOA7_1 SEG13 RTO00_1 P22 SOT0_0 (SDA0_0) TIOB7_1 SEG12 I/O circuit type Pin state type Q K Q J Q J Q J Q J F X J U J U MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 48 59 73 51 - 60 74 52 - - 75 76 53 54 49 61 77 55 50 62 78 56 51 63 79 57 52 64 80 58 53 65 81 59 - - 82 60 - - 83 61 84 62 85 63 66 - - - June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Pin name P21 SIN0_0 INT06_1 WKUP2 SEG11 P20 INT05_0 CROUT_0 SEG10 VSS VCC P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P05 TIOA5_2 SIN4_2 INT00_1 SEG09 P06 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 SEG08 P07 ADTG_0 SEG07 SCK4_2 (SCL4_2) P08 TIOA0_2 CTS4_2 SEG06 I/O circuit type Pin state type J T J S E E E E E E E E E E J S J S J U J U 19 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 - - 86 64 54 67 87 65 55 68 88 66 56 69 89 67 - 70 90 68 - 71 91 69 57 72 92 70 - 73 93 71 58 74 94 72 59 75 95 73 20 CONFIDENTIAL Pin name P09 TIOB0_2 RTS4_2 SEG05 P0A SIN4_0 INT00_2 P0B SOT4_0 (SDA4_0) TIOB6_1 P0C SCK4_0 (SCL4_0) TIOA6_1 P0D RTS4_0 TIOA3_2 SEG04 P0E CTS4_0 TIOB3_2 SEG03 P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P63 INT03_0 SEG02 P62 SCK5_0 (SCL5_0) ADTG_3 SEG01 P61 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 SEG00 I/O circuit type Pin state type J U G F G H G H J U J U E I J S J U J U MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 60 76 96 74 61 77 97 75 62 78 98 76 63 79 99 77 64 80 100 78 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Pin name P60 SIN5_0 TIOA2_2 INT15_1 WKUP3 CEC1 P80 SIN7_2 P81 SOT7_2 (SDA7_2) P82 SCK7_2 (SCL7_2) VSS I/O circuit type Pin state type G R G H G H G H - 21 D a t a S h e e t List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC 22 CONFIDENTIAL Pin No Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. LQFP64 9 58 8 34 35 36 37 38 39 40 44 45 - LQFP80 66 7 13 74 12 42 43 44 45 46 47 48 49 53 54 55 56 - LQFP100 84 7 18 94 70 12 30 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 QFP100 62 85 96 72 48 90 8 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Pin No Pin name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 Function description Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin LQFP80 14 30 9 15 5 31 10 6 16 76 32 11 75 17 70 33 12 71 21 18 34 22 19 35 - LQFP100 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 30 22 90 43 12 91 31 23 44 13 32 24 82 45 14 83 QFP100 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 8 100 68 21 90 69 9 1 22 91 10 2 60 23 92 61 TIOA6_1 Base timer ch.6 TIOA pin 56 69 89 67 TIOB6_1 Base timer ch.6 TIOB pin 55 68 88 66 46 47 - 57 58 - 71 72 - 49 50 - TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 - 23 D a t a S h e e t Pin No Pin function Pin name Function description Debugger SWCLK Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin J-TAG reset input pin J-TAG test clock input pin J-TAG test data input pin J-TAG test mode state input/output pin J-TAG debug data output pin SWDIO External Interrupt 24 CONFIDENTIAL SWO TRSTX TCK TDI TMS TDO INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT10_1 INT11_1 INT12_1 INT13_1 INT14_1 INT15_1 NMIX External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin LQFP64 50 LQFP80 62 LQFP100 78 QFP100 56 52 64 80 58 53 49 50 51 52 53 2 54 3 4 35 38 5 8 40 6 7 48 27 60 57 65 61 62 63 64 65 2 67 3 4 43 73 46 9 12 49 10 60 55 11 59 35 5 8 29 76 72 81 77 78 79 80 81 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 5 14 8 15 16 17 27 28 39 96 92 59 55 56 57 58 59 80 60 65 81 61 82 31 71 34 87 90 37 88 52 43 89 51 23 83 92 86 93 94 95 5 6 17 74 70 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function GPIO Pin No Pin name P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 Function description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 49 50 51 52 53 54 55 56 57 34 35 36 37 38 39 40 44 45 48 47 46 LQFP80 61 62 63 64 65 66 67 68 69 70 71 72 42 43 44 45 46 47 48 49 53 54 55 56 60 59 58 57 LQFP100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 QFP100 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 51 50 49 25 D a t a S h e e t Pin function GPIO 26 CONFIDENTIAL Pin No Pin name P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E LQFP64 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 61 62 63 28 30 31 LQFP80 9 10 11 12 13 14 15 16 17 18 19 21 22 26 27 29 30 31 32 33 34 35 2 3 4 5 6 7 8 76 75 74 73 77 78 79 36 38 39 LQFP100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 96 95 94 93 97 98 99 46 48 49 QFP100 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 74 73 72 71 75 76 77 24 26 27 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function Multifunction Serial 0 Pin No Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multifunction Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Multifunction Serial 2 SIN2_2 SOT2_2 (SDA2_2) SCK2_2 (SCL2_2) Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 48 - LQFP80 59 46 LQFP100 73 56 QFP100 51 34 47 58 72 50 - 47 57 35 46 57 71 49 - 48 58 36 35 43 53 31 36 44 54 32 37 45 55 33 40 49 59 37 44 53 63 41 45 54 64 42 27 D a t a S h e e t Pin function Multifunction Serial 3 Pin No Pin name SIN3_1 SIN3_2 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Multifunction Serial 4 28 CONFIDENTIAL SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 Function description Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.4 CTS input pin LQFP64 2 - LQFP80 2 29 LQFP100 2 39 QFP100 80 17 3 3 3 81 - 30 40 18 4 4 4 82 - 31 41 19 54 - 67 55 - 87 65 82 65 43 60 55 68 88 66 - 56 66 44 - - 83 61 56 69 89 67 - - 67 45 - - 84 62 - 70 71 - 90 69 86 91 68 85 68 47 64 69 46 63 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function Multifunction Serial 5 Pin No Pin name SIN5_0 SIN5_2 SOT5_0 (SDA5_0) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_2 (SCL5_2) Multifunction Serial 6 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multifunction Serial 7 SIN7_1 SIN7_2 SOT7_1 (SDA7_1) SOT7_2 (SDA7_2) SCK7_1 (SCL7_1) SCK7_2 (SCL7_2) Function description Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 60 - LQFP80 76 - LQFP100 96 15 QFP100 74 93 59 75 95 73 - - 16 94 58 74 94 72 - - 17 95 8 5 12 5 12 83 90 - 6 6 84 7 11 11 89 - 7 7 85 6 10 10 88 27 61 35 77 45 97 23 75 26 34 44 22 62 78 98 76 25 33 43 21 63 79 99 77 29 D a t a S h e e t Pin function Multifunction Timer 0 Pin No Pin name DTTI0X_0 DTTI0X_1 DTTI0X_2 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) IGTRG 30 CONFIDENTIAL Function description Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. PPG IGBT mode external trigger input pin LQFP64 9 59 35 36 37 38 39 LQFP80 13 75 43 55 44 56 45 46 47 LQFP100 18 69 95 13 70 53 17 65 54 16 66 55 15 67 56 14 68 57 QFP100 96 47 73 91 48 31 95 43 32 94 44 33 93 45 34 92 46 35 10 14 19 97 - - 71 49 11 15 20 98 12 16 21 99 13 17 22 100 14 18 23 1 15 19 24 2 24 32 42 20 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function LCD Controller Pin No Pin name VV0 VV1 VV2 VV3 VV4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 Function description LCD controller power supply I/O pin LCD controller common output pin LCD controller segment output pin June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 2 12 11 10 9 8 7 6 5 59 58 48 47 46 45 44 40 39 38 37 36 35 34 24 23 22 15 LQFP80 6 5 4 3 2 16 15 14 13 12 11 10 9 75 74 73 71 70 66 60 59 58 57 56 55 54 53 49 48 47 46 45 44 43 42 32 31 30 29 22 21 19 LQFP100 6 5 4 3 2 21 20 19 18 12 11 10 9 95 94 93 91 90 86 85 84 83 82 74 73 72 71 69 68 67 66 65 64 63 59 58 57 56 55 54 53 52 42 41 40 39 32 31 24 QFP100 84 83 82 81 80 99 98 97 96 90 89 88 87 73 72 71 69 68 64 63 62 61 60 52 51 50 49 47 46 45 44 43 42 41 37 36 35 34 33 32 31 30 20 19 18 17 10 9 2 31 D a t a S h e e t Pin function LCD Controller Real-time clock LowPower Consumption Mode Pin No Pin name SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 WKUP0 WKUP1 WKUP2 WKUP3 DAC HDMICEC/ Remote Control Reception 32 CONFIDENTIAL DA0 DA1 CEC0 CEC1 Function description LCD controller segment output pin Pulse output pin of Real-time clock Sub clock output pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin D/A converter ch.1 analog output pin HDMI-CEC/Remote Control Reception ch.0 input/output pin HDMI-CEC/Remote Control Reception ch.1 input/output pin LQFP64 14 13 8 7 6 5 57 37 10 57 37 10 LQFP80 18 17 8 7 12 11 10 9 72 45 14 72 45 14 LQFP100 23 22 8 7 12 11 10 9 92 55 19 92 55 19 QFP100 1 100 86 85 90 89 88 87 70 33 97 70 33 97 57 72 92 70 35 43 53 31 48 59 73 51 60 76 96 74 26 27 34 35 44 45 22 23 25 33 43 21 60 76 96 74 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin function Reset Pin No Pin name INITX Mode MD0 MD1 Power GND Clock Analog Power VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS X0 X0A X1 X1A CROUT_0 CROUT_1 AVCC AVRH Analog GND C pin AVSS C Function description External Reset Input Pin. A reset is valid when INITX = L. Mode 0 pin. During normal operation, MD0 = L must be input. During serial programming to Flash memory, MD0 = H must be input. Mode 1 pin. During normal operation, input is not needed. During serial programming to Flash memory, MD1 = L must be input. Power supply pin GND pin Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in High-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter and D/A converter GND pin Power supply stabilization capacity pin June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL LQFP64 LQFP80 LQFP100 QFP100 21 28 38 16 29 37 47 25 28 36 46 24 1 18 33 16 32 64 30 19 31 20 57 1 25 41 20 24 40 80 38 26 39 27 60 72 1 26 35 51 76 25 34 50 75 100 48 36 49 37 74 92 79 4 13 29 54 3 12 28 53 78 26 14 27 15 52 70 41 50 60 38 42 51 61 39 43 52 62 40 17 23 33 11 33 D a t a S h e e t I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function. When the main oscillation is selected. Oscillation feedback resistor : Approximately 1 MΩ With standby mode control Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R Pull-up resistor control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control CMOS level hysteresis input Pull-up resistor : Approximately 50 kΩ B Pull-up resistor Digital input 34 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Type Circuit Remarks C Digital input Open drain output CMOS level hysteresis input Digital output N-ch D It is possible to select the sub oscillation / GPIO function Pull-up resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control Digital input When the sub oscillation is selected. Oscillation feedback resistor : Approximately 5 MΩ With standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 35 D a t a S h e e t Type Circuit Remarks CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off E P-ch P-ch N-ch Digital output Digital output R Pull-up resistor control Digital input Standby mode control CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA F P-ch P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control 36 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Type Circuit Remarks G P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With standby mode control 5 V tolerant input IOH = -4 mA, IOL = 4 mA Available to control PZR registers. P0B, P0C, P4C, P60, P81, P82 only. When this pin is used as an I2C pin, the digital output P-ch transistor is always off R Digital input Standby mode control H CMOS level hysteresis input Mode input J P-ch P-ch N-ch R Digital output Digital output CMOS level output CMOS level hysteresis input With input control LCD segment output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control LCD output LCD control June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 37 D a t a S h e e t Type Circuit Remarks K P-ch P-ch N-ch CMOS level output CMOS level hysteresis input With input control LCD common output LCD segment output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Digital output Pull-up resistor control R Digital input Standby mode control LCD output LCD control LCD output LCD control L P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input With input control LCD common output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA Digital output Digital output Pull-up resistor control Digital input Standby mode control LCD output LCD control 38 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Type Circuit Remarks O P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control R Digital input Standby mode control Analog output Q P-ch P-ch N-ch R Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog input LCD segment output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog input Input control LCD output LCD control June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 39 D a t a S h e e t Type Circuit Remarks R P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input With input control LCD VV input/output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Digital output Pull-up resistor control Digital input Standby mode control LCD VV input/output LCD VV control 40 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 41 D a t a S h e e t Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. 42 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 43 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf 44 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pin. Example of Using an External Clock Device X0/PE2 (X0A/P46) Can be used as general-purpose I/O ports. X1/PE3 (X1A/P47) Set as general-purpose I/O ports. Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 45 D a t a S h e e t C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device Cs VSS GND Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC AVCC AVRH Turning off: AVRH AVCC VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. 46 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Block Diagram MB9AFAA1/AA2 ROM Table SWJ-DP Cortex-M3 Core @20MHz(Max) Flash I/F I Multi-layer AHB (Max 20MHz) TRSTX,TCK, TDI,TMS TDO D Sys AHB-APB Bridge: APB0 (Max 20MHz) NVIC Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) Security On-Chip Flash 64/128Kbyte SRAM1 12/16Kbyte CSV CLK X0 X1 X0A X1A Main Osc Sub Osc PLL Source Clock CR 4MHz CR 100kHz CROUT AVCC, AVSS,AVRH ANxx Deep Standby Ctrl WKUPx 12-bit A/D Converter Power On Reset Unit 0 LVD Ctrl ADTGx LVD Regulator TIOBx Base Timer 16-bit 8ch./ 32-bit 4ch. A/D Activation Compare 1ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x IGTRG AHB-APB Bridge : APB2 (Max 20MHz) TIOAx Multi-Function Timer ×1 VVx LCDC COMx, SEGxx HDMI-CEC/ Remote Receiver Control CECx RTCCO SUBOUT Real Time Clock External Interrupt Controller 16-pin + NMI INTxx NMIX MODE-Ctrl MD1, MD0 P0x, P1x, GPIO Waveform Generator 3ch. 16-bit PPG 3ch. C IRQ-Monitor 10-bit D/A Converter 2ch. AHB-APB Bridge : APB1 (Max 20MHz) DAx PIN-Function-Ctrl . . . Pxx Multi-Function Serial IF 8ch. HW flow control(ch.4)* SCKx SINx SOTx CTS4 RTS4 *: For the MB9AFAA1L and MB9AFAA2L, Multi-function Serial Interface does not support hardware flow control in these products. Memory Size See Memory size in Product Lineup to confirm the memory size. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 47 D a t a S h e e t Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved Reserved 0x4003_C000 0x4003_B000 0x4003_9000 0x4003_8000 0x4400_0000 0x4200_0000 32Mbytes Bit band alias 0x4003_6000 0x4003_5000 Peripherals 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 SRAM1 Reserved See " Memory Map (2)" for the memory size details. 0x0010_0008 0x0010_0000 0x4002_9000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 MFS Reserved LVD/DS mode HDMI-CEC/ Remote Control Receiver GPIO LCDC Int-Req.Read EXTI Reserved CR Trim Reserved D/AC A/DC Reserved Base Timer PPG Reserved 0x4002_1000 0x4002_0000 MFT unit0 Reserved 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 CONFIDENTIAL Reserved Security/CR Trim Flash 48 RTC SW WDT HW WDT Clock/Reset Reserved Flash I/F MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Memory Map (2) MB9AFAA2L/M/N MB9AFAA1L/M/N 0x2008_0000 0x2008_0000 Reserved Reserved 0x2000_4000 0x2000_3000 SRAM1 16 Kbytes 0x2000_0000 0x2000_0000 Reserved Reserved 0x0010_0008 0x0010_0004 0x0010_0000 SRAM1 12 Kbytes 0x0010_0008 CR trimming Security 0x0010_0004 0x0010_0000 CR trimming Security Reserved Reserved SA2 (60 KB) 0x0000_0000 SA1 (4 KB) 0x0001_0000 SA2 (60 KB) 0x0000_0000 Flash 64 Kbytes SA3 (64 KB) Flash 128 Kbytes 0x0002_0000 SA1 (4 KB) *: See MB9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 49 D a t a S h e e t Peripheral Address Map Start address End address Bus 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF AHB APB0 Peripherals Flash memory I/F register Reserved Software Watchdog timer Reserved 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF LCD Controller 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/ Remote Control Receiver 0x4003_5000 0x4003_50FF Low-Voltage Detector 0x4003_5100 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Base Timer APB1 APB2 Reserved Deep standby mode Controller Reserved 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x4006_1FFF 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved 50 CONFIDENTIAL Reserved AHB Reserved MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX = 0 This is the period when the INITX pin is the L level. INITX = 1 This is the period when the INITX pin is the H level. SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Trace output Indicates that the trace function can be used. GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 51 D a t a S h e e t Pin status type List of Pin Status Function group Main crystal oscillator input pin A External main clock input selected GPIO selected Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Input enabled Setting disabled Setting disabled Hi-Z / Main crystal Internal oscillator input fixed output pin at 0 Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 B C Input enabled Setting disabled Setting disabled Input enabled Maintain previous state Maintain previous state Timer mode, RTC mode, or Stop mode state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Input enabled Input enabled Input enabled Input enabled Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stops*1, output maintains previous state / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Input enabled Hi-Z / Input enabled / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous state / state / state / state / state / state / Hi-Z / When When When When When When Internal oscillation oscillation oscillation oscillation oscillation oscillation input fixed stops*1, Hi-Z stops*1, Hi-Z stops*1, Hi-Z stops*1, Hi-Z stops*1, Hi-Z stops*1, Hi-Z at 0 output / output / output / output / output / output / Internal Internal Internal Internal Internal Internal input fixed at input fixed at input fixed at input fixed at input fixed at input fixed at 0 0 0 0 0 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled 52 CONFIDENTIAL Power supply stable INITX = 1 - Power supply stable Hi-Z / Internal input fixed at 0 Maintain previous state Pull-up / Input enabled Pull-up / Input enabled MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 Pin status type D a t a S h e e t D Function group Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Mode input pin Input enabled Input enabled Input enabled JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled E F GPIO selected Setting disabled Setting disabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z GPIO selected G Hi-Z / Input enabled Hi-Z / Input enabled Input enabled Maintain previous state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP enabled Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Resource other than above selected Hi-Z GPIO selected Hi-Z / Input enabled June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Hi-Z / Input enabled Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 WKUP input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Power supply stable INITX = 1 Input enabled Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / WKUP input enabled GPIO selected GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state 53 Pin status type D a t a S h e e t Function group Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Resource selected H Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected NMIX selected I Resource other than above selected Setting disabled Hi-Z GPIO selected Analog input selected J Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected 54 CONFIDENTIAL Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 WKUP input enabled Power supply stable INITX = 1 - GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Resource other than above selected Setting disabled Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Hi-Z / WKUP input enabled Maintain previous state GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 Pin status type D a t a S h e e t Function group Analog input selected K Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Resource other than above selected Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled External interrupt enabled selected Maintain previous state Analog input selected L Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Resource other than above selected Setting disabled Setting disabled GPIO selected June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 55 Pin status type D a t a S h e e t Function group Sub crystal oscillator input pin External sub clock input selected Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Input enabled Setting disabled Input enabled Setting disabled Input enabled Setting disabled Input enabled Maintain previous state M GPIO selected Sub crystal oscillator output pin Setting disabled Hi-Z / Internal input fixed at 0 Setting disabled Hi-Z / Internal input fixed at 0 Setting disabled Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state N GPIO selected 56 CONFIDENTIAL Setting disabled Setting disabled Setting disabled Maintain previous state Timer mode, RTC mode, or Stop mode state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Input enabled Input enabled Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Input enabled Hi-Z / Input enabled / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Input enabled Power supply stable INITX = 1 Input enabled Maintain Hi-Z / Input previous enabled / state / When When oscillation Return from stops*2, Deep Hi-Z / Standby Internal STOP mode, input fixed GPIO at 0 is selected Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 Pin status type D a t a S h e e t Function group External interrupt enabled selected Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Setting disabled Setting disabled Q Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Setting disabled O P Timer mode, RTC mode, or Stop mode state Maintain previous state Maintain previous state Maintain previous state GPIO selected / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Power supply stable INITX = 1 - GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled Maintain previous state Hi-Z / Input enabled Maintain previous state CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled GPIO selected June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state 57 Pin status type D a t a S h e e t Function group CEC enabled Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Setting disabled Setting disabled Setting disabled Maintain previous state Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled WKUP enabled R External interrupt enabled selected Setting disabled Setting disabled GPIO selected External interrupt enabled selected Setting disabled Resource other than above selected Hi-Z GPIO selected 58 CONFIDENTIAL Maintain previous state Maintain previous state Resource other than above selected Hi-Z S Setting disabled Maintain previous state Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Power supply stable INITX = 1 Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 Pin status type D a t a S h e e t T Function group Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 WKUP enabled Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at "0" External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Resource other than above selected Hi-Z GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource selected U Hi-Z GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Resource selected V Hi-Z GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Maintain previous state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 GPIO selected Internal input fixed at "0" GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 59 Pin status type D a t a S h e e t Function group External interrupt enabled selected W Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 Setting disabled Resource other than above selected Hi-Z Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled X Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled GPIO selected 60 CONFIDENTIAL Setting disabled Setting disabled Maintain previous state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Analog input selected Setting disabled Timer mode, RTC mode, or Stop mode state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Power supply stable INITX = 1 - Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 Pin status type D a t a S h e e t Y Function group Power-on reset or Device Run mode INITX input low-voltage internal or Sleep state detection reset state mode state state Power Power supply Power supply stable supply unstable stable INITX = 0 INITX = 1 INITX = 1 - Analog output selected Setting disabled Setting disabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z GPIO selected Analog output selected Z Setting disabled Hi-Z / Input enabled Setting disabled Setting disabled Resource other than above selected Hi-Z GPIO selected Hi-Z / Input enabled Hi-Z / Input enabled Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state *3 Maintain previous state Power supply stable INITX = 1 - *4 Maintain previous state Maintain previous state Return Deep Standby RTC from Deep mode or Deep Standby Standby Stop mode state mode state Power supply stable *3 Maintain previous state Hi-Z / Input enabled Timer mode, RTC mode, or Stop mode state Hi-Z / Internal input fixed at 0 *4 Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state GPIO selected Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state *1: Oscillation is stopped at Sub Run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. *3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 61 D a t a S h e e t Electrical Characteristics 1. Absolute Maximum Ratings Parameter Symbol 1, 2 Power supply voltage* * Analog power supply voltage*1,*3 Analog reference voltage*1,*3 LCD input voltage*1,*3 Input voltage*1 VCC AVCC AVRH VV4 to VV0 VI Rating Max Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss + 6.5 Vss + 6.5 Vss + 6.5 V V V Vss - 0.5 Vss + 6.5 V Vss - 0.5 Vss - 0.5 Analog pin input voltage* 1 Output voltage*1 4 Unit Min VIA Vss - 0.5 VO Vss - 0.5 VCC + 0.5 (≤ 6.5 V) Vss + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) 10 4 100 50 -10 -4 -100 -50 400 + 150 Remarks V V 5 V tolerant V V L level maximum output current* IOL mA 5 L level average output current* IOLAV mA L level total maximum output current ∑IOL mA L level total average output current*6 ∑IOLAV mA H level maximum output current*4 IOH mA H level average output current*5 IOHAV mA H level total maximum output current ∑IOH mA H level total average output current*6 ∑IOHAV mA Power consumption PD mW Storage temperature TSTG - 55 C *1: These parameters are based on the condition that Vss = AVss = 0 V. *2: VCC must not drop below Vss - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 62 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 2. Recommended Operating Conditions (Vss = AVss = 0.0V) Parameter Symbol Conditions Power supply voltage VCC - LCD input voltage Analog power supply voltage VV4 AVCC - Analog reference voltage AVRH - CS - Smoothing capacitor Value Min Max 1.8 2.2 2.2 1.8 2.7 AVCC 1 FPT-64P-M38, FPT-64P-M39, Operating FPT-80P-M37, TA - 40 Temperature FPT-80P-M40, FPT-100P-M23, FPT-100P-M06 *1: When LCD is not used *2: When LCD is used *3: See ●C Pin in Handling Devices for the smoothing capacitor. 5.5 5.5 VCC 5.5 Unit V V V AVCC V 10 μF + 85 C Remarks *1 *2 AVCC = VCC AVCC ≥ 2.7 V AVCC < 2.7 V For built-in Regulator *3 <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 63 D a t a S h e e t 3. DC Characteristics (1) Current Rating (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name PLL Run mode High-speed CR Run mode ICC Power supply current VCC Sub Run mode Low-speed CR Run mode ICCS Value Unit Remarks Typ*3 Max*4 Conditions PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU: 20 MHz, Peripheral: clock stopped, NOP operation CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 19 24 mA *1, *5 9.5 12.5 mA *1, *5 4.5 5 mA *1 0.25 0.55 mA *1, *6 0.3 0.95 mA *1 Peripheral: 20 MHz 8 10.5 mA *1, *5 Peripheral: 4 MHz*2 2 2.5 mA *1 Peripheral: 32 kHz 0.2 0.45 mA *1, *6 Peripheral: 100 kHz 0.25 0.65 mA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) 64 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Parameter Symbol Pin name Conditions Main Timer mode ICCT Sub Timer mode ICCR Power supply current RTC mode VCC ICCH ICCRD ICCHD Stop mode Deep Standby RTC mode Deep Standby Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off Value Unit Remarks Typ*2 Max*3 0.9 3.3 mA *1, *4 1.5 3.5 mA *1, *4 7.5 60 μA *1, *5 16 150 μA *1, *5 1.5 6.5 μA *1, *5 6 79 μA *1, *5 0.6 5 μA *1 4.2 77 μA *1 1.3 4.5 μA *1, *5 3 22 μA *1, *5 0.4 3 μA *1 1.4 20 μA *1 *1: When all ports are fixed. *2: VCC=3.3 V *3: VCC=5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 65 D a t a S h e e t Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Low-voltage detection circuit (LVD) power supply current ICCLVD Value Typ* Max Pin name Conditions VCC For occurrence of reset or for occurrence of interrupt in normal mode operation For occurrence of reset and for occurrence of interrupt in normal mode operation For occurrence of interrupt in low-power mode operation 10 Unit Remarks μA 20 When not detected 14 30 μA 0.3 2 μA When not detected *: When VCC=3.3V Flash Memory Current (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Flash memory write/erase current ICCFLASH VCC Conditions At Write/Erase Value Typ Max Unit 10.8 mA 11.9 Remarks A/D Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Power supply current Reference power supply current Symbol Pin name ICCAD AVCC ICCAVRH AVRH Conditions At 1unit operation At stop At 1unit operation AVRH=5.5 V At stop Value Typ Max Unit 1.4 2.5 mA 0.1 0.35 μA 0.5 1.5 mA 0.1 0.3 μA Remarks D/A Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Power supply current Symbol IDDA Pin name Conditions AVCC At D/A 1ch. operation AVCC=3.3 V At D/A 1ch. operation AVCC=5.0 V At D/A stop IDSA *1: No-load *2: Generates the max current by the CODE about 0x200 66 CONFIDENTIAL Value Typ Max Unit Remarks 314 440 μA *1, *2 476 670 μA *1, *2 - 1.0 μA *1 MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t (2) Pin Characteristics (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions H level input voltage (hysteresis input) L level input voltage (hysteresis input) VIHS VILS MD0, MD1 PE0, PE2, PE3, P46, P47, P3A, P3B, P3C, P3D, P3E, P3F, INITX P0A, P0B, P0C, P4C, P60, P80, P81, P82 CMOS hysteresis input pins other than the above MD0, MD1 PE0, PE2, PE3, P46, P47, INITX CMOS hysteresis input pins other than the above H level output voltage VOH Pxx L level output voltage VOL Pxx - Input leak current IIL CEC0, CEC1 Pull-up resistor value RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Input capacitance June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Min Value Typ Max Unit - VCC× 0.8 - VCC+ 0.3 V - VCC× 0.7 - VSS+ 5.5 V - VCC× 0.7 - VCC+ 0.3 V - VSS0.3 - VCC× 0.2 V - VSS0.3 - VCC× 0.3 V VCC0.5 - VCC V VSS - 0.4 V -5 - +5 - - + 1.8 25 50 100 VCC 4.5 V 40 100 400 - - 5 15 VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 1 mA VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 2 mA VCC = AVCC = AVRH = VSS = AVSS = 0.0 V VCC ≥ 4.5 V Remarks 5V tolerant μA kΩ pF 67 D a t a S h e e t (3) LCD Characteristics (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter VV0 to VV3 Output voltage (1/4 bias) VV0 to VV3 Output voltage (1/3 bias) VV0 to VV3 Output voltage (1/2 bias) VV4 Active current (1/4 bias) VV4 Active current (1/3 bias) VV4 Active current (1/2 bias) VV4 Static current VV0 Output Voltage in using external resistor 68 CONFIDENTIAL Symbol Pin name VVV0 VV0 VVV1 VV1 VVV2 VV2 VVV3 VV3 VVV0 VV0 VVV1 VV1 VVV2 VV2 VVV3 VV3 VVV0 VV0 VVV1 VV1 VVV2 VV2 VVV3 VV3 IR100K VV4 IR10K VV4 IR100K VV4 IR10K VV4 IR100K VV4 IR10K VV4 Ioff_vv4 VV4 VVV0E VV0 Conditions When using internal dividing register Min Value Typ Max 0 - VVV4 × 5% VVV4 × 1/4 -10% VVV4 × 1/2 -10% VVV4 × 3/4 -10% 0 When using internal dividing register VVV4 × 1/3 -10% VVV4 × 2/3 -10% VVV4 × 2/3 -10% 0 When using internal dividing register When using 100 kΩ internal dividing register When using 10 kΩ internal dividing register When using 100 kΩ internal dividing register When using 10 kΩ internal dividing register When using 100 kΩ internal dividing register When using 10 kΩ internal dividing register VVV4 × 1/2 -10% VVV4 × 1/2 -10% VVV4 × 1/2 -10% - VVV4 × 1/4 +10% VVV4 × 1/2 +10% VVV4 × 3/4 +10% Unit Rem arks V VVV4 × 5% VVV4 × 1/3 +10% VVV4 × 2/3 +10% VVV4 × 2/3 +10% V VVV4 × 5% VVV4 × 1/2 +10% VVV4 × 1/2 +10% VVV4 × 1/2 +10% V - 15 35 μA - 130 250 μA - 18 45 μA - 170 350 μA - 27 75 μA - 250 500 μA When LCD stops - - 0.5 μA IOL=1mA - - 1.0 V MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 4. AC Characteristics (1) Main Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin Conditions name VCC ≥ 2.0 V VCC 2.0 V VCC ≥ 4.5 V VCC 4.5 V VCC ≥ 4.5 V VCC 4.5 V PWH/tCYLH, PWL/tCYLH Value Min Max Unit 4 4 4 4 50 62.5 MHz MHz MHz MHz ns ns 20 4 20 16 250 250 Remarks When crystal oscillator is connected Input frequency fCH When using external clock X0, When using external Input clock cycle tCYLH X1 clock Input clock pulse When using external 45 55 % width clock Input clock rising tCF, When using external 5 ns time and falling time tCR clock fCM 20 MHz Master clock Base clock fCC 20 MHz (HCLK/FCLK) fCP0 20 MHz APB0 bus clock*2 fCP1 20 MHz APB1 bus clock*2 fCP2 20 MHz APB2 bus clock*2 Base clock tCYCC 50 ns (HCLK/FCLK) Internal operating 1 tCYCP0 50 ns APB0 bus clock*2 clock* cycle time tCYCP1 50 ns APB1 bus clock*2 tCYCP2 50 ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 69 D a t a S h e e t (2) Sub Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input frequency Symbol Min Value Typ Max - - 32.768 - kHz - 32 - 100 kHz Pin Conditions name Unit fCL X0A, X1A Input clock cycle tCYLL - 10 - 31.25 μs Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock X0A (3) Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol TA = + 25C TA = - 40C to + 85C TA = - 40C to + 85C TA = + 25C TA = - 40C to + 85C TA = - 40C to + 85C VCC ≥ 2.2 V Clock frequency Value Unit Min Typ Max Conditions fCRH VCC 2.2 V 3.92 4 4.08 3.8 4 4.2 2.3 - 7.03 3.4 4 4.6 3.16 4 4.84 2.3 - 7.03 Remarks When trimming*1 MHz When not trimming When trimming*1 MHz When not trimming Frequency tCRWT 10 μs *2 stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Clock frequency 70 CONFIDENTIAL Symbol Conditions fCRL - Min Value Typ Max 50 100 150 Unit Remarks kHz MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 μs (LOCK UP time) PLL input clock frequency fPLLI 4 20 MHz PLL multiplication rate 1 5 multiplier PLL macro oscillation clock frequency fPLLO 10 20 MHz Main PLL clock frequency*2 fCLKPLL 20 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. (4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 200 μs (LOCK UP time) PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate 3 4 multiplier PLL macro oscillation clock frequency fPLLO 11.4 16.8 MHz Main PLL clock frequency*2 fCLKPLL 16.8 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 71 D a t a S h e e t (5) Reset Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Reset input time tINITX Pin Conditions name INITX - Value Unit Min Max 500 - ns 1.5 - ms 1.5 - ms Remarks When RTC mode or Stop mode When Deep Standby mode (6) Power-on Reset Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Power supply rising time Power supply shut down time Min Value Typ Max dV/dt 0.1 - - V/ms tOFF 1 - - ms 1.44 1.60 1.76 V When voltage rises 1.39 1.55 1.71 V When voltage drops tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs Symbol Reset release voltage VDETH Reset detection voltage Time until releasing Power-on reset Reset detection delay time VDETL Pin name VCC Unit Remarks VDETH VDETL VCC dV 0.2V dt 0.2V tOFF tPRT Internal reset CPU Operation 72 CONFIDENTIAL Reset active tOFFD Release Reset active start MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t (7) Base Timer Input Timing Timer input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - Input pulse width tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK TIN VIHS VIHS VILS VILS Trigger input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 73 D a t a S h e e t (8) CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Notes: 74 CONFIDENTIAL Symbol tSCYC tSLOVI tIVSHI tSHIXI VCC 2.7 V Min Max SCKx 4tCYCP - 4tCYCP -40 +40 75 0 SCKx, SOTx Master mode SCKx, SINx SCKx, SINx tSLSH SCKx tSHSL SCKx tSLOVE tIVSHE tSHIXE tF tR 2.7 V ≤ VCC 4.5 V Min Max Pin Conditions name SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK VIH VIH VIL tR SOT tSLSH tF VIL VIL tSHOVE VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 75 D a t a S h e e t CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Notes: 76 CONFIDENTIAL Symbol tSCYC tSHOVI tIVSLI tSLIXI VCC 2.7 V Min Max SCKx 4tCYCP - 4tCYCP -40 +40 75 0 SCKx, SOTx Master mode SCKx, SINx SCKx, SINx tSLSH SCKx tSHSL SCKx tSHOVE tIVSLE tSLIXE tF tR 2.7 V ≤ VCC 4.5 V Min Max Pin Conditions name SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK VIH VIH VIL tR SOT tSLSH tF VIL VIL tSHOVE VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 77 D a t a S h e e t CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time SOT SCK delay time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Notes: 78 CONFIDENTIAL Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI VCC 2.7 V Min Max SCKx 4tCYCP - 4tCYCP -40 +40 75 0 SCKx, SOTx SCKx, Master mode SINx SCKx, SINx SCKx, SOTx tSLSH SCKx tSHSL SCKx tSHOVE tIVSLE tSLIXE tF tR 2.7 V ≤ VCC 4.5 V Min Max Pin Conditions name SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 VCC ≥ 4.5 V Unit Min Max - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns - 0 - 0 - ns - ns - ns - ns - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t tSCYC VOH SCK VOL tSOVLI SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL Master mode tSLSH VIH SCK SOT VIL VIL tF * VOH VOL tR tIVSLE SIN tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 79 D a t a S h e e t CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin Conditions name VCC 2.7 V Min Max 2.7 V ≤ VCC 4.5 V Min Max VCC ≥ 4.5 V Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - 4tCYCP - ns SCK SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns 75 - 50 - 30 - ns 0 - 0 - 0 - ns - ns - ns - ns SIN SCK setup time SCK SIN hold time SOT SCK delay time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Notes: 80 CONFIDENTIAL tIVSHI tSHIXI tSOVHI SCKx, Master mode SINx SCKx, SINx SCKx, SOTx tSLSH SCKx tSHSL SCKx tSLOVE tIVSHE tSHIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL Master mode tR SCK tF tSHSL VIH VIH VIL tSLSH VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR CL = 50 pF Min Max tCYCP + 10 tCYCP + 10 - 5 5 Unit Remarks ns ns ns ns tF tR t t SHSL SCK V IL June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Value Symbol Conditions V IH SLSH V IH V IL VIL V IH 81 D a t a S h e e t (9) External Input Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Min Max ADTG - 2tCYCP*1 - ns ICxx DTTIxX IGTRG INTxx, NMIX *2 *3 2tCYCP*1 2tCYCP*1 2tCYCP + 100*1 500 - ns ns ns ns WKUPx *4 500 - ns FRCKx Input pulse width tINH, tINL Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform generator PPG IGBT mode External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, PPG, External interrupt, Deep Standby mode Controller are connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode. 82 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 2 (10) I C Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions Standard-mode Min Max Fast-mode Unit Remarks Min Max SCL clock frequency fSCL 0 100 0 400 kHz (Repeated) START condition hold time tHDSTA 4.0 0.6 μs SDA SCL SCL clock L width tLOW 4.7 1.3 μs SCL clock H width tHIGH 4.0 0.6 μs (Repeated) START condition setup time tSUSTA 4.7 0.6 μs CL = 50 pF, SCL SDA R= Data hold time 1 tHDDAT (VP/IOL)* 0 3.45*2 0 0.9*3 μs SCL SDA Data setup time tSUDAT 250 100 ns SDA SCL STOP condition setup time tSUSTO 4.0 0.6 μs SCL SDA Bus free time between STOP condition and tBUF 4.7 1.3 μs START condition Noise filter tSP 2 tCYCP*4 2 tCYCP*4 ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 83 D a t a S h e e t (11) JTAG Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions VCC ≥ 4.5 V VCC 4.5 V VCC ≥ 4.5 V tJTAGH VCC 4.5 V VCC ≥ 4.5 V TCK, TDO delay time tJTAGD 2.7 V ≤ VCC 4.5 V TDO VCC 2.7 V Note: When the external load capacitance CL = 50 pF. TMS,TDI setup time TMS,TDI hold time tJTAGS TCK, TMS, TDI TCK, TMS, TDI Value Min Max Unit 15 - ns 15 - ns - 30 45 60 ns Remarks TCK TMS/TDI TDO 84 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 5. 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Symbol Pin name - - Integral Nonlinearity INL - Differential Nonlinearity DNL - Zero transition voltage Full-scale transition voltage VZT VFST ANxx ANxx Conversion time*1 - - Sampling time*2 tS - tCCK - Parameter Resolution Compare clock cycle*3 Min 1.0 4.0 0.3 1.2 50 200 Value Typ Max 12 ± 2.5 ± 3.0 ± 3.5 ± 4.0 ± 1.8 ± 1.9 ± 2.7 ± 2.9 ±9 ± 20 AVRH ± 9 AVRH ± 20 Unit bit LSB LSB LSB LSB mV mV - - μs - 10 μs - 1000 ns Period of operation enable state transitions Analog input capacity tSTT - - - 1 μs CAIN - - - pF Analog input resistor RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 15 0.9 1.6 4.0 4 LSB - ANxx - - 0.3 μA - ANxx kΩ Remarks AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 4.5 V 2.7 V ≤ AVCC < 4.5 V AVCC < 2.7 V AVSS AVRH V 2.7 AVCC ≥ 2.7 V Reference voltage AVRH AVCC V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 85 D a t a S h e e t ANxx Analog input pin REXT Comparator RAIN Analog signal source CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: RAIN: CAIN: REXT: Sampling time Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: tCCK: 86 CONFIDENTIAL Compare time Compare clock cycle MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Definition of 12-bit A/D Converter Terms Resolution: Integral Nonlinearity: Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Actual conversion characteristics Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVSS Actual conversion characteristics AVRH AVSS Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST – VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL AVRH Analog input 87 D a t a S h e e t 6. 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Resolution Conversion time Integral Nonlinearity Differential Nonlinearity Output Voltage offset Analog output impedance Output undefined period *: No-load 88 CONFIDENTIAL Symbol Pin name tC20 tC100 INL DNL VOFF RO tR DAx Min Value Typ Max Unit Remarks 0.37 1.87 -4.0 0.53 2.67 - 10 0.69 3.47 +4.0 bit μs μs LSB Load 20 pF Load 100 pF * -0.9 - +0.9 LSB * -50.0 2.45 5.0 - 3.50 9.0 - 10.0 +5.5 4.55 250 mV mV kΩ MΩ ns Code is 0x000 Code is 0x3FF D/A operation D/A stop MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 7. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (TA = - 40C to + 85C) Parameter Symbol Detected voltage Released voltage Detected voltage Released voltage VDLR VDHR VDLR VDHR LVD stabilization wait time tLVDRW Conditions SVHR = 0001 SVHR = 0100 - Detection delay time tLVDRD dV/dt ≥ -4mV/μs *: tCYCP indicates the APB2 bus clock cycle time. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Min Value Unit Typ Max 1.43 1.53 1.80 1.90 1.53 1.63 1.93 2.03 1.63 1.73 2.06 2.16 V V V V - - 633 × tCYCP * μs - - 60 μs Remarks When voltage drops When voltage rises When voltage drops When voltage rises 89 D a t a S h e e t (2) Interrupt of Low-Voltage Detection Normal mode (TA = - 40C to + 85C) Parameter Symbol Conditions Min Value Typ Max 1.87 1.97 1.96 2.06 2.05 2.15 2.15 2.25 2.24 2.34 2.33 2.43 2.43 2.53 2.61 2.71 2.80 2.90 2.99 3.09 3.36 3.46 3.45 3.55 3.73 3.83 3.83 3.93 3.92 4.02 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 2.13 2.23 2.24 2.34 2.35 2.45 2.45 2.55 2.56 2.66 2.67 2.77 2.77 2.87 2.99 3.09 3.20 3.30 3.41 3.51 3.84 3.94 3.95 4.05 4.27 4.37 4.37 4.47 4.48 4.58 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI LVD stabilization wait time tLVDIW - - - 633 × tCYCP * μs Detection delay time tLVDID dV/dt ≥ - 4mV/μs - - 60 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. 90 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Low-power mode (TA = - 40C to + 85C) Parameter Symbol Conditions Min Value Typ Max 1.80 1.90 1.89 1.99 1.98 2.08 2.07 2.17 2.16 2.26 2.25 2.35 2.34 2.44 2.52 2.62 2.70 2.80 2.88 2.98 3.24 3.34 3.33 3.43 3.60 3.70 3.69 3.79 3.78 3.88 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 2.20 2.30 2.31 2.41 2.42 2.52 2.53 2.63 2.64 2.74 2.75 2.85 2.86 2.96 3.08 3.18 3.30 3.40 3.52 3.62 3.96 4.06 4.07 4.17 4.40 4.50 4.51 4.61 4.62 4.72 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Unit Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL VDLIL VDHIL LVD stabilization wait time tLVDILW - - - 8039 × tCYCP * μs Detection delay time tLVDILD dV/dt ≥ - 0.4mV/μs - - 800 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 91 D a t a S h e e t 8. Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 2.0V to 5.5V, TA = - 40C to + 85C) Parameter Large Sector Sector erase time Small Sector Half word (16-bit) write time Value Typ* Max* 1.6 0.4 7.5 2.1 Unit Remarks Includes write time prior to internal erase Not including system-level overhead 25 400 μs time. Includes write time prior to internal Chip erase time 4 19.2 s erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. s (2) Write cycles and data hold time Erase/write cycles (cycle) 1,000 10,000 100,000 *: At average + 85C 92 CONFIDENTIAL Data hold time (year) Remarks 20 * 10 * 5* MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 9. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Max* Low-speed CR Timer mode tICNT Unit 40 80 μs 630 1260 μs 630 1260 μs 2100 μs 2127 μs RTC mode, 1083 Stop mode Deep Standby RTC mode 1099 Deep Standby Stop mode *: The maximum value depends on the accuracy of built-in CR. Remarks μs tCYCC Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Sub Timer mode Typ Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 93 D a t a S h e e t Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: 94 CONFIDENTIAL The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Typ Max* 359 647 μs 359 647 μs 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs 2127 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Deep Standby RTC mode 1099 Deep Standby Stop mode *: The maximum value depends on the accuracy of built-in CR. Remarks Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Start 95 D a t a S h e e t Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. The internal resource reset means the watchdog reset and the CSV reset. 96 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t Ordering Information On-chip Flash memory On-chip SRAM MB9AFAA1LPMC1-G-SNE2 64 Kbyte 12 Kbyte MB9AFAA2LPMC1-G-SNE2 128 Kbyte 16 Kbyte MB9AFAA1LPMC-G-SNE2 64 Kbyte 12 Kbyte MB9AFAA2LPMC-G-SNE2 128 Kbyte 16 Kbyte MB9AFAA1MPMC-G-SNE2 64 Kbyte 12 Kbyte MB9AFAA2MPMC-G-SNE2 128 Kbyte 16 Kbyte MB9AFAA1MPMC1-G-SNE2 64 Kbyte 12 Kbyte MB9AFAA2MPMC1-G-SNE2 128 Kbyte 16 Kbyte MB9AFAA1NPMC-G-SNE2 64 Kbyte 12 Kbyte MB9AFAA2NPMC-G-SNE2 128 Kbyte 16 Kbyte MB9AFAA1NPF-G-SNE1 64 Kbyte 12 Kbyte MB9AFAA2NPF-G-SNE1 128 Kbyte 16 Kbyte Part number June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL Package Packing Plastic LQFP (0.5mm pitch), 64-pin (FPT-64P-M38) Plastic LQFP (0.65mm pitch), 64-pin (FPT-64P-M39) Plastic LQFP (0.5mm pitch), 80-pin (FPT-80P-M37) Plastic LQFP (0.65mm pitch), 80-pin (FPT-80P-M40) Tray Plastic LQFP (0.5mm pitch), 100-pin (FPT-100P-M23) Plastic QFP (0.65mm pitch), 100-pin (FPT-100P-M06) 97 D a t a S h e e t Package Dimensions 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145 ± 0.055 (.006 ± .002) 33 Details of "A" part 32 49 0.08(.003) +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° INDEX 1 0.22±0.05 (.009±.002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 98 CONFIDENTIAL 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) 17 64 M Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-64P-M39) 64-pin plastic LQFP (FPT-64P-M39) Note 1) Pins width and pins thickness include plating thickness. 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.006±.002) 33 Details of "A" part 32 49 +0.20 1.50 –0.10 +.008 .059 –.004 0.10(.004) INDEX 1 16 0.65(.026) C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 17 64 0.32±0.05 (.013±.002) CONFIDENTIAL 0.10±0.10 (.004±.004) 0.25(.010)BSC "A" 0.13(.005) M 2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E 0~8˚ Dimensions in mm (inches). Note: The values in parentheses are reference values. 99 D a t a S h e e t 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-80P-M37) 80-pin plastic LQFP (FPT-80P-M37) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00± 0.20(.551 ± .008)SQ *12.00± 0.10(.472 ± .004)SQ 60 0.145± 0.055 (.006 ± .002) 41 Details of "A" part 61 40 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° 0.08(.003) INDEX 80 0.50 ± 0.20 (.020 ± .008) 0.60 ± 0.15 (.024 ± .006) 0.10 ± 0.05 (.004 ± .002) (Stand off) 21 "A" 1 20 0.50(.020) 0.22± 0.05 (.009± .002) C 0.08(.003) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 100 CONFIDENTIAL M Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 80-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.60 mm Max. Code (Reference) P-LQFP80-14 × 14-0.65 (FPT-80P-M40) 80-pin plastic LQFP (FPT-80P-M40) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 60 0.145±0.055 (.006±.002) 41 Details of "A" part 40 61 1.50±0.10 (.059±.004) 0.25(.010) 0.10(.004) 0˚~7˚ INDEX 0.50±0.20 (.020±.008) 21 80 0.65(.026) C 0.60±0.15 (.024±.006) 20 1 0.32±0.06 (.013±.002) 0.13(.005) M 2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 0.10±0.05 (.004±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 101 D a t a S h e e t 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65 g (FPT-100P-M23) 100-pin plastic LQFP (FPT-100P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part 1.50 +0.20 - 0.10 (.059+.008 -.004) (Mounting height) INDEX 100 26 "A" 1 C 0.22±0.05 (.009±.002) 0.08(.003) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4 102 CONFIDENTIAL 0.60±0.15 (.024±.006) 25 0.50(.020) 0°~8° 0.50±0.20 (.020±.008) M 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0.145±0.055 (.006±.002) Dimensions in mm (inches). Note:The values in parentheses are reference values. MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 50 81 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7 June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 31 100 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. 103 D a t a S h e e t Major Changes Page Section Revision 0.1 Revision 1.0 ELECTRICAL CHARACTERISTICS 66,67 3.DC Characteristics (1) Current Rating Revision 2.0 Features 2 · On-chip Memories Packages 7 - 33 Pin Assignment List of Pin Functions Handling Devices 45 Crystal oscillator circuit Memory Map 49 · Memory map(2) 64 - 66 67 71 72 74 - 81 85 89 92 93 - 96 97 104 CONFIDENTIAL Electrical Characteristics 3. DC Characteristics (1) Current rating Electrical Characteristics 3. DC Characteristics (2) Pin Characteristics Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing Electrical Characteristics 5. 12bit A/D Converter Electrical Characteristics 7. Low-voltage Detection Characteristics Electrical Characteristics 8. Flash Memory Write/Erase Characteristics Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Ordering Information Change Results Initial release Changed from Preliminary to Full Producton Deleted a part of QFN Revised the values of “TBD” Changed the description of on-chip SRAM Deleted QFN package Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." Added the summary of Flash memory sector · Changed the table format · Added Main Timer mode current · Added Flash Memory Current · Moved A/D Converter Current · Moved D/A Converter Current Added the input leak current of CEC port at power off · Added the figure of Main PLL connection · Changed the figure of timing · Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVCC < 2.7 V Deleted the figure Change to the erase time of include write time prior to internal erase Added Return Time from Low-Power Consumption Mode Changed notation of part number MB9AAA0N_DS706-00067-2v0-E, June 30, 2015 D a t a S h e e t June 30, 2015, MB9AAA0N_DS706-00067-2v0-E CONFIDENTIAL 105 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2014-2015 Cypress Semiconductor Corp. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 106 CONFIDENTIAL MB9AAA0N_DS706-00067-2v0-E, June 30, 2015