STMicroelectronics L3GD20H Low power consumption Datasheet

L3GD20H
MEMS motion sensor:
three-axis digital output gyroscope
Datasheet - production data
Applications
• Gaming and virtual reality input devices
• Motion control with MMI (man-machine
interface)
• GPS navigation systems
• Appliances and robotics
LGA-16 (3x3x1 mm)
Description
Features
The L3GD20H is a low-power three-axis angular
rate sensor.
• Wide supply voltage, 2.2 V to 3.6 V
• Wide extended operating temperature range
(from -40 °C to 85 °C)
• Low voltage compatible IOs, 1.8 V
• Low power consumption
It includes a sensing element and an IC interface
able to provide the measured angular rate to the
external world through digital interface (I2C/SPI).
The sensing element is manufactured using a
dedicated micromachining process developed by
ST to produce inertial sensors and actuators on
silicon wafers.
• Embedded power-down
• Sleep mode
• Fast turn-on and wake-up
• Three selectable full scales up to 2000 dps
• 16 bit rate value data output
• 8 bit temperature data output
• I2C/SPI digital output interface
• 2 dedicated lines (1 interrupt, 1 data ready)
• User enable integrated high-pass filters
• Embedded temperature sensor
• Embedded 32 levels of 16 bit data output FIFO
• High shock survivability
The IC interface is manufactured using a CMOS
process that allows a high level of integration to
design a dedicated circuit which is trimmed to
better match the sensing element characteristics.
The L3GD20H has a full scale of
±245/±500/±2000 dps and is capable of
measuring rates with a user selectable
bandwidth.
The L3GD20H is available in a plastic land grid
array (LGA) package and can operate within a
temperature range from -40 °C to +85 °C.
• ECOPACK® RoHS and “Green” compliant
Table 1. Device summary
Order code
Temperature range (°C)
Package
Packing
L3GD20H
-40 to +85
LGA-16 (3x3x1)
Tray
L3GD20HTR
-40 to +85
LGA-16 (3x3x1)
Tape and reel
March 2013
This is information on a product in full production.
DocID023469 Rev 2
1/52
www.st.com
52
Contents
L3GD20H
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7
2.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.2
Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
2/52
4.2.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.3
Stream mode - dynamic stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.4
Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.5
Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.6
Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.7
Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.8
FIFO multiple read (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Level-sensitive/edge sensitive/impulse sensitive data enable . . . . . . . . . 25
4.3.1
Level sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2
Edge sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.3
Impulse sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID023469 Rev 2
L3GD20H
5
Contents
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.1
5.2
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2
CTRL1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3
CTRL2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4
CTRL3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5
CTRL4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6
CTRL5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.7
REFERENCE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.8
OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.9
STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.10
OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.11
OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.12
OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.13
FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.14
FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.15
IG_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.16
IG_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.17
IG_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.18
IG_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.19
IG_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.20
IG_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.21
IG_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.22
IG_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.23
IG_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DocID023469 Rev 2
3/52
Contents
L3GD20H
7.24
LOW_ODR (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4/52
DocID023469 Rev 2
L3GD20H
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trigger stamping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 29
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 29
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CTRL1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CTRL2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
High pass filter cut off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CTRL3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CTRL4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CTRL5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CTRL5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
OUT_TEMP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STATUS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FIFO_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FIFO_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IG_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IG_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IG_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IG_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IG_THS_XH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DocID023469 Rev 2
5/52
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
6/52
L3GD20H
IG_THS_XH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IG_THS_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IG_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IG_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IG_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IG_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IG_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LOW_ODR register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LOW_ODR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LGA 3x3x1.0 16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID023469 Rev 2
L3GD20H
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L3GD20H electrical connections and external components values . . . . . . . . . . . . . . . . . . 17
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Stream mode with threshold interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dynamic stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FIFO multiple read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IG_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LGA 3x3x1.0 16L mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DocID023469 Rev 2
7/52
Block diagram and pin description
1
L3GD20H
Block diagram and pin description
Figure 1. Block diagram
+Ω
x,y,z
X+
CHARGE
AMP
Y+
MIXER
LOW-PASS
FILTER
D
I
G
I
T
A
L
Z+
Z-
A
D
C
1
M
U
X
YX-
T
E
M
P
E
R
A
T
U
R
E
DRIVING MASS
Feedback loop
REFERENCE
TRIMMING
CIRCUITS
FIFO
S
E
N
S
O
R
F
I
L
T
E
R
I
N
G
I2C
SPI
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
A
D
C
2
CONTROL LOGIC
&
INTERRUPT GEN.
CLOCK
&
PHASE GENERATOR
INT1
DEN
DRDY/INT2
AM12689V1
The vibration of the structure is maintained by a drive circuitry in a feedback loop. The
sensing signal is filtered and appears as digital signal at the output.
1.1
Pin description
+Ω
14
Y
GND
GND
RES
RES
RES
X
(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATE
Vdd
Cap
+Ω
16
13
1
BOTTOM
VIEW
9
5
8
Vdd_IO
SCL/SPC
SDA/SDI/SDO
SDO/SA0
CS
6
DRDY/INT2
X
INT1
1
Z
DEN
+Ω
RES
Figure 2. Pin connection
AM12690V1
8/52
DocID023469 Rev 2
L3GD20H
Block diagram and pin description
Table 2. Pin description
Pin#
Name
Function
1
Vdd_IO(1)
2
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
3
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
4
SDO
SA0
SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
5
CS
6
DRDY/INT2
7
INT1
Programmable interrupt
8
DEN(2)
Gyroscope data enable
9
Reserved
Connect to GND
10
Reserved
Connect to GND
11
Reserved
Connect to GND or VDD
12
GND
0 V supply
13
GND
0 V supply
14
Cap
Connect to GND with ceramic capacitor(3)
15
Reserved
16
Vdd(4)
Power supply for I/O pins
I2C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I2C disabled)
Data ready/fifo interrupt (FIFO threshold/overrun/empty)
Connect to GND or VDD
Power supply
1. Recommended 100 nF filter capacitor.
2. Connected to GND if DEN is not used.
3. 10 nF (+/-10%), 25 V. 1 nF minimum value has to be guaranteed under 12 V bias condition.
4. Recommended 100 nF plus 10 μF capacitors.
DocID023469 Rev 2
9/52
Mechanical and electrical specifications
L3GD20H
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
@ Vdd = 3.0 V, T = 25 °C unless otherwise noted(a).
Table 3. Mechanical characteristics
Symbol
FS
So
Parameter
Measurement range
Test condition
Min.
User selectable
Sensitivity
Typ.(1)
Max.
Unit
±245
±500
±2000
dps
8.75
17.50
70.00
mdps/digit
SoDr
Sensitivity change vs.
temperature(2)
From -40 °C to +85 °C
Delta from T = 25 °C
±2
%
DVoff
Digital Zero-rate level
FS = 2000 dps
±25
dps
OffDr
Zero-rate level change
vs temperature(3)
FS = 2000 dps
±0.04
dps/°C
NL
Non linearity(3)
Best fit straight line
0.2
% FS
Rn
Rate noise density(3)
BW = 50 Hz
0.011
dps/ ( Hz )
ODR
Top
11.9/23.7/
47.3/94.7/
189.4/
378.8/
757.6
Digital output data
rate(3)
Operating temperature
range
-40
Hz
+85
°C
1. Typical specifications are not guaranteed.
2. Guaranteed by design.
3. The period (1/ODR), length of time between two consecutive sampling, must be derived by the reciprocal of the maximum.
and minimum ODR limits: for example for ODR = 189.4 Hz, sampling period range will be within [4591 μs, 6211 μs] (where
ODR minimum and maximum have been approximated at 162 Hz, 219 Hz respectively).
a. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 4.
10/52
DocID023469 Rev 2
L3GD20H
2.2
Mechanical and electrical specifications
Electrical characteristics
@ Vdd =3.0 V, T=25 °C unless otherwise noted(b).
Table 4. Electrical characteristics
Symbol
Vdd
Vdd_IO
Idd
Parameter
Test condition
Supply voltage
I/O pins supply voltage
(2)
Min.
Typ.(1)
Max.
Unit
2.2
3.0
3.6
V
Vdd+0.1
V
1.71
Supply current
5.0
mA
IddSL
Supply current
in sleep mode(3)
Selectable by digital
interface
2.5
mA
IddPdn
Supply current in powerdown mode
Selectable by digital
interface
1
μA
VIH
Digital high level input
voltage
VIL
Digital low level input
voltage
Ton
Turn-on time(4)
Top
Operating temperature
range
0.8*Vdd_I
O
V
0.2*Vdd_I
O
LPF2 disabled
ODR = 190 Hz
50
-40
V
ms
+85
°C
1. Typical specifications are not guaranteed.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
3. Sleep mode introduces a faster turn-on time related to power down mode.
4. Time to obtain stable sensitivity (within ±5% of final value) after exiting power-down mode. It is guaranteed by design.
b. The product is factory calibrated at 3.0 V.
DocID023469 Rev 2
11/52
Mechanical and electrical specifications
2.3
L3GD20H
Temperature sensor characteristics
@ Vdd =3.0 V, T=25 °C unless otherwise noted(c).
Table 5. Temperature sensor characteristics
Symbol
Parameter
TSDr
Temperature sensor output
change vs temperature
TODR
Temperature refresh rate
Test condition
Min.
Typ.(1)
Max.
Unit
-1
°C/digit
1
Hz
Top
Operating temperature range
-40
1. Typical specifications are not guaranteed.
c. The product is factory calibrated at 3.0 V.
12/52
DocID023469 Rev 2
+85
°C
L3GD20H
Mechanical and electrical specifications
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min.
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max.
100
ns
10
MHz
ns
50
5
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 3. SPI slave timing diagram(d)
CS
tc(SPC)
tsu(CS)
th(CS)
SPC
tsu(SI)
SDI
th(SI)
LSB IN
MSB IN
tv(SO)
SDO
MSB OUT
tdis(SO)
th(SO)
LSB OUT
d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port.
DocID023469 Rev 2
13/52
Mechanical and electrical specifications
L3GD20H
I2C - Inter IC control interface
2.4.2
Subject to general operating conditions for Vdd and Top.
Table 7. I2C slave timing values
I2C standard mode(1)
Symbol
I2C fast mode (1)
Parameter
f(SCL)
Unit
SCL clock frequency
Min.
Max.
Min.
Max.
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
kHz
μs
0
ns
3.45
0
0.9
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb (2)
300
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb (2)
300
μs
ns
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
μs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
Figure 4. I2C slave timing diagram(e)
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
th(SDA)
tsu(SP)
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
14/52
START
DocID023469 Rev 2
STOP
L3GD20H
2.5
Mechanical and electrical specifications
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8. Absolute maximum ratings
Symbol
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
10,000
g
2 (HBM)
kV
0.3 to Vdd_IO +0.3
V
Sg
ESD
Vin
Note:
Ratings
Acceleration g for 0.1 ms
Electrostatic discharge protection
Input voltage on any control pin
(including
CS,SCL/SPC,SDA/SDI/SDO,SDO/SA0,DEN)
Supply voltage on any pin should never exceed 4.8 V.
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part.
This is an ESD sensitive device, improper handling can cause permanent damage to
the part.
DocID023469 Rev 2
15/52
Mechanical and electrical specifications
2.6
Terminology
2.6.1
Sensitivity
L3GD20H
An angular rate gyroscope is a device that produces a positive-going analog output for
counterclockwise rotation around the sensitive axis considered. Sensitivity describes the
gain of the sensor and can be determined by applying a defined angular velocity to it. This
value changes very little over temperature and time.
2.6.2
Zero-rate level
Zero-rate level describes the actual output signal if there is no angular rate present. Zerorate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and
therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit
board or after exposing it to extensive mechanical stress.
2.7
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.
16/52
DocID023469 Rev 2
L3GD20H
Application hints
Figure 5. L3GD20H electrical connections and external components values
+Ω
1
Z
X
Vdd
+Ω
100nF
Y
10nF(25V)*
C1
GND
10µF
GND
+Ω
X
16
Vdd_IO
14
1
(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATES
13
SCL/SPC
SDA/SDI/SDO
TOP VIEW
SDO
CS
9
5
100nF
8
6
DEN
INT1
GND
DRDY/INT2
3
Application hints
GND
* C1 must guarantee 1nF value under 12V bias condition
Vdd I2C bus
Rpu
Rpu = 10kOhm
SCL/SPC
SDA_SDI_SDO
Pull-up to be added when I2C interface is used
GAMS080220130927FSR
Power supply decoupling capacitors (100 nF + 10 μF) should be placed as near as possible
to the device (common design practice).
If Vdd and Vdd_IO are not connected together, 100 nF and 10 μF decoupling capacitors
must be placed between Vdd and common ground while 100 nF between Vdd_IO and
common ground. Capacitors should be placed as near as possible to the device (common
design practice).
DocID023469 Rev 2
17/52
Digital main blocks
L3GD20H
4
Digital main blocks
4.1
Block diagram
Figure 6. Block diagram
Out_Sel
00
01
0
LPF2
ADC
LPF1
HPF
10
11
DataReg
FIFO
32x16x3
I2C
SPI
1
HPen
INT_Sel
10
11
01
Interrupt
generator
00
SCR REG
CONF REG
INT1
AM07230v1
4.2
FIFO
L3GD20H embeds 32 slots of 16-bit data FIFO for each of the three output channels: yaw,
pitch and roll. This allows consistent power saving for the system, since the host processor
does not need to continuously poll data from the sensor, but it can wakeup only when
needed and burst the significant data out from the FIFO. This buffer can work accordingly to
seven different modes: Bypass mode, FIFO-mode, Stream mode, Stream-to-FIFO mode,
Bypass-to-Stream, Dynamic-Stream, Bypass-to-FIFO. Each mode is selected by the FM2:0
bits in FIFO_CTRL register. Programmable FIFO threshold level, FIFO empty or FIFO
overrun events are available on FIFO_SRC register and can be set to generate dedicated
interrupts on DRDY/INT2 pin.
FIFO_SRC(EMPTY) is equal to '1' when no samples are available.
FIFO_SRC(FTH) goes to '1' if a new data arrives and FIFO_SRC(FSS4:0) is greater than or
equal to FIFO Threshold configured to FTH4:0 into FIFO_CTRL (2Eh). FIFO_SRC(FTH)
goes to '0' if reading Yaw, Pitch and Roll data slot from FIFO and FIFO_SRC(FSS4:0) is
minor than or equal to FIFO_CTRL(FTH4:0).
18/52
DocID023469 Rev 2
L3GD20H
Digital main blocks
FIFO_SRC(OVRN) is equal to '1' if a FIFO slot is overwritten.
FIFO feature is enabled writing to '1' CTRL5(FIFO_EN).
To guarantee the switching into and out of FIFO mode discard the first sample aquired.
4.2.1
Bypass mode
In bypass mode (FIFO_CTRL(FM2:0) = 000), the FIFO is not operational and it remains
empty.
Bypass mode is also used to reset the FIFO when in FIFO-mode.
As described in the next figure, for each channel only the first address is used. When a new
data is available the old one is overwritten.
Figure 7. Bypass mode
[L\L]L
HPSW\
[
\ L
]
[
\
]
[
\
]
[ \ ]
$0Y
4.2.2
FIFO mode
In FIFO mode (FIFO_CTRL(FM2:0) = 001) data from Yaw, Pitch and Roll channels are
stored into the FIFO until it is full.
To reset FIFO content Bypass mode should be written in FIFO_CTRL(FM2:0) '000' value.
After this reset command it is possible to restart FIFO mode writing FIFO_CTRL(FM2:0) the
value '001'.
FIFO buffer can memorize 32 Yaw, Pitch and Roll data, but the depth of the FIFO can be
reduced by means of CTRL5(StopOnFTH) bit setting to '1' StopOnFTH bit, FIFO depth is
limited to FIFO_CTRL(FTH4:0) - 1.
A FIFO Threshold interrupt can be enabled (INT2_ORun bit into CTRL3 (22h)) in order to be
raised when the FIFO is filled to the level specified into the FTH4:0 bits of FIFO_CTRL
(2Eh). When FIFO Threshold interrupt occurs, the first data has been overwritten and the
FIFO stops collecting data from the input channels.
DocID023469 Rev 2
19/52
Digital main blocks
L3GD20H
Figure 8. FIFO mode
[L\L]L
[
\ L
]
[
\
]
[
\
]
[ \ ]
$0Y
4.2.3
Stream mode - dynamic stream
Stream mode (FIFO_CTRL(FM2:0) = 010) provides continuous FIFO update: as new data
arrives the older is discarded.
An overrun interrupt can be enabled, CTRL3(INT2_ORun)= '1', in order to read the whole
FIFO content at once. If in the application no data can be lost and it is not possible to read at
least one sample for each axis within one ODR period, a FIFO Threshold interrupt can be
enabled in order to read partially the FIFO and let free memory slots for data incoming.
Setting the FIFO_CTRL(FTH4:0) to N value, the number of Yaw, Pitch and Roll data
samples that should be read at FIFO Threshold interrupt rising is up to (N+1).
20/52
DocID023469 Rev 2
L3GD20H
Digital main blocks
Figure 9. Stream mode
[L\L]L
[
\
]
[
\
]
[
\
]
[ \ ]
[ \ ]
$0Y
In the latter case reading all FIFO content before an overrun interrupt has occurred, the
first data read is equal to the last already read in previous burst, so the number of new data
available in FIFO depends on previous reading (see FIFO_SRC behavior depicted in next
figures).
Figure 10. Stream mode with threshold interrupt enable
GAMS310120131021FSR
In dynamic-stream mode (FIFO_CTRL(FM2:0) = 110) after emptying the FIFO the first new
sample that arrives becomes the first to be read in subsequent read burst. In this way in
DocID023469 Rev 2
21/52
Digital main blocks
L3GD20H
dynamic-stream mode (FIFO_CTRL(FM2:0) = 110) the number of new data available in
FIFO does not depend on previous reading.
In dynamic-stream mode FIFO_SRC(FSS4:0) + 1 is the number of new X, Y and Z samples
available in the FIFO buffer.
Stream mode is intended to be used reading all 32 samples of FIFO within an ODR after
receiving an overrun signal.
Dynamic-stream is intended to be used to read FIFO_SRC(FSS4:0) + 1 samples when it is
not possible to guarantee data reading within an ODR.
In dynamic-stream mode FIFO_CTRL(FTH4:0) setting should be between 1 and 30.
Also a FIFO Threshold interrupt CTRL3(INT2_FTH) can be enabled in order to read data
from the FIFO and let free memory slot for data incoming. Setting the FIFO_CTRL(FTH4:0)
to N value, the number of X, Y and Z data samples that should be read at FIFO Threshold
interrupt rising, in order to read the whole FIFO content, is N + 2.
Figure 11. Dynamic stream mode
GAMS310120131023FSR
4.2.4
Stream-to-FIFO mode
In stream-to-FIFO mode (FIFO_CTRL(FM2:0) = 011), FIFO behavior changes according to
IG_SRC(IA) bit. When IG_SRC(IA) bit is equal to '1' FIFO operates in FIFO-mode, when
IG_SRC(IA) bit is equal to '0' FIFO operates in Stream mode.
Interrupt generator should be set to the desired configuration by means of IG_CFG,
IG_THS_XH, IG_THS_XL, IG_THS_YH, IG_THS_YL, IG_THS_ZH and IG_THS_ZL.
IG_CFG(LIR) bit should be put to '1' in order to have latched interrupt.
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L3GD20H
Digital main blocks
Figure 12. Trigger stream mode
xi,yi,zi
Empty
x0
y 0i
z0
x1
y1
z1
x2
y2
z2
x 31
xi,yi,zi
x0
y0
z0
x1
y1
z1
x2
y2
z2
x 30
y 30
z30
x 31
y 31
z31
z31
y 31
Bypass mode
Stream mode
Trigger event
4.2.5
AM07235v1
Bypass-to-stream mode
In bypass-to-stream mode (FIFO_CTRL(FM2:0) = '100'), Yaw, Pitch and Roll measurement
storage inside FIFO operates in Stream mode when IG_SRC (IA) is equal to '1', otherwise
FIFO content is reset (bypass mode) .
Interrupt generator should be set to the desired configuration by means of IG_CFG,
IG_THS_XH, IG_THS_XL, IG_THS_YH, IG_THS_YL, IG_THS_ZH and IG_THS_ZL.
IG_CFG(LIR) bit should be put to '1' in order to have latched interrupt.
Figure 13. Bypass-to-stream mode
[L\L]L
(PSW\
[
\ L
]
[
\
]
[
\
]
[ \ [L\L]L
[
\
]
[
\
]
[
\
]
[ \ ]
[ \ ]
]
%\SDVVĆPRGH
6WUHDPĆPRGH
7ULJJHUĆHYHQW
DocID023469 Rev 2
$0Y
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Digital main blocks
4.2.6
L3GD20H
Bypass-to-FIFO mode
In bypass-to-FIFO mode (FIFO_CTRL(FM2:0) = '111', FIFO behavior changes according to
IG_SRC(IA) bit. When IG_SRC(IA) bit is equal to '1' FIFO operates in FIFO-mode, when
IG_SRC(IA) bit is equal to '0' FIFO operates in bypass mode (FIFO content reset). If a
latched interrupt is generated FIFO starts collecting data until the first data into the FIFObuffer is overwritten. Interrupt generator should be set to the desired configuration by
means of IG_CFG, IG_THS_XH, IG_THS_XL, IG_THS_YH, IG_THS_YL, IG_THS_ZH and
IG_THS_ZL.
IG_CFG (LIR) bit should be put to '1' in order to have latched interrupt.
4.2.7
Retrieve data from FIFO
FIFO data is read through OUT_X_L and OUT_X_H (Addr reg 28h and 29h), OUT_Y_L
OUT_Y_H (Addr reg 2Ah and 2Bh) and OUT_Z_L and OUT_Z_H (Addr reg 2Ch and 2Dh)
registers. A read operation by means of serial interface of OUT_X, OUT_Y or OUT_Z output
registers provides the data stored into the FIFO. Each time data is read from the FIFO, the
oldest X, Y and Z data are placed into the OUT_X, OUT_Y and OUT_Z registers and both
single read and read_burst operations can be used.
4.2.8
FIFO multiple read (burst)
Starting from the Addr 28h multiple read can be performed. Once the reading reaches the
Addr 2Dh the system automatically restarts from the Addr. 28h.
Figure 14. FIFO multiple read
Read #1
Read #n
x,y,z
OUT_X
(28-29)
OUT_Y
(2A-2B)
OUT_Z
(2C-2D)
OUT_X
(28-29)
OUT_Y
(2A-2B)
OUT_Z
(2C-2D)
x,y,z
GAMS290120131638FSR
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DocID023469 Rev 2
L3GD20H
4.3
Digital main blocks
Level-sensitive/edge sensitive/impulse sensitive data enable
L3GD20H allows external trigger level recognition through enabling EXTRen and LVLen bits
into CTRL2 (21h) and IMPen bit into CTRL4 (23h). Three different modes can be used:
level, edge or impulse sensitive trigger.
Table 9. Trigger stamping mode
LVLen
EXTRen
IMPen
Trigger stamping mode
1
0
0
Level sensitive trigger
0
1
0
Edge sensitive trigger
1
0
1
Impulse sensitive trigger
Figure 15. Trigger stamping
Level-sensitive
Trigger enabled
on X-Axis
d
Xen=1,Yen=Zen=0
xi,yi,zi
xi(15-1)
xi-N+1
(15-1)
Level-sensitive
Trigger enabled
on Y-axis
Yen=1, Xen=Zen=0
Level-sensitive
Trigger enabled
on Z-axis
Zen=1, Xen=Yen=0
xi,yi,zi
xi,yi,zi
D
E
N
yi(15-0)
Zi(15-0)
D
E
N
yi-N+1
(15-0)
zi-N+1
(15-0)
yi(15-1)
D
E
N
Zi(15-0)
xi-N+1
(15-0)
yi-N+1
(15-1)
D
E
N
Zi-N+1
(15-0)
xi(15-0)
yi(15-0)
xi(15-0)
xi-N+1
yi-N+1
(15-0)
(15-0)
Zi(15-1)
D
E
N
zi-N+1
(15-1)
D
E
N
GAMS290120131645FSR
4.3.1
Level sensitive trigger stamping
Level sensitive trigger can be enabled by setting to ‘1’ the LVLen bit into CTRL2 (21h) while
EXTRen bit into CTRL2 (21h) and IMPen bit into CTRL4 (23h) have to be set to ‘0’.
Once enabled, DEN level replaces the LSB of X, Y or Z axes configurable through Xen, Yen,
Zen bits into CTRL1 (20h). Data is stored inside the FIFO with the internal selected ODR.
4.3.2
Edge sensitive trigger
Edge sensitive trigger can be enabled by setting to ‘1’ the EXTRen bit into CTRL2 (21h)
while LVLen bit into CTRL2 (21h) and IMPen bit into CTRL4 (23h) have to be set to ‘0’.
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Digital main blocks
L3GD20H
Once enabled, FIFO is filled with the Pitch, Roll and Yaw data on the rising edge of DEN
input signal. When ODR selected is 800 Hz, maximum DEN sample frequency is
fDEN =1/TDEN = 400 Hz.
Figure 16. Edge-sensitive trigger
GAMS310120131026FSR
4.3.3
Impulse sensitive trigger
Impulse sensitive trigger can be enabled by setting to ‘1’ LVLen bit into CTRL2 (21h) and
IMPen bit into CTRL4 (23h) while the EXTRen bit into CTRL2 (21h) has to be set to ‘0’.
If the duration of the DEN pulse is shorter than the selected ODR, the Impulse sensitive
trigger functionality has to be enabled.
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DocID023469 Rev 2
L3GD20H
5
Digital interfaces
Digital interfaces
The registers embedded inside the L3GD20H may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
Table 10. Serial interface pin description
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
5.1
Pin description
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I2C less significant bit of the device address
I2C serial interface
The L3GD20H I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 11. I2C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
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Digital interfaces
5.1.1
L3GD20H
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the L3GD20H is 110101xb. SDO/SA0 pin can be
used to modify less significant bit of the device address. If SDO/SA0 pin is connected to
voltage supply LSb is ‘1’ (address 1101011b) else if SDO/SA0 pin is connected to ground
LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two
different gyroscopes to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the L3GD20H behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged. Table 12 explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 12. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SDO
R/W
SAD+R/W
Read
110101
0
1
11010101 (D5h)
Write
110101
0
0
11010100 (D4h)
Read
110101
1
1
11010111 (D7h)
Write
110101
1
0
11010110 (D6h)
Table 13. Transfer when Master is writing one byte to slave
Master
Slave
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ST
SAD + W
SUB
SAK
DocID023469 Rev 2
DATA
SAK
SP
SAK
L3GD20H
Digital interfaces
Table 14. Transfer when Master is writing multiple bytes to slave
Master
ST
SAD + W
Slave
SUB
SAK
DATA
DATA
SAK
SAK
SP
SAK
Table 15. Transfer when Master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
Slave
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Table 16. Transfer when Master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave
SUB
SAK
SR SAD+R
SAK
MAK
SAK DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
In order to disable the I2C block it is needed to write '1' in bit 3 of register located in address
39h.
5.2
SPI bus interface
The SPI is a bus slave. The SPI allows to write and read the registers of the device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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Digital interfaces
L3GD20H
Figure 17. Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AM10129V1
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
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L3GD20H
5.2.1
Digital interfaces
SPI read
Figure 18. SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AM10130V1
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
Figure 19. Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
M S A D5 A D4 AD 3 A D2 A D1 A D0
SD O
DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 DO 15 DO 14 DO 13 DO 12 DO 11 DO 10 D O9 D O8
AM10131V1
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Digital interfaces
5.2.2
L3GD20H
SPI write
Figure 20. SPI write protocol
CS
SPC
SDI
D I7 D I6 D I5 D I4 DI3 DI2 DI1 DI0
RW
MS AD5 AD 4 AD 3 AD2 AD 1 AD0
AM10132V1
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 21. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 D I6 DI5 D I4 DI3 DI2 DI1 DI0 DI15 D I1 4DI13 D I1 2DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD 0
AM10133V1
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L3GD20H
5.2.3
Digital interfaces
SPI read in 3-wires mode
Figure 22. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
D O7 D O6 D O5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD 4 AD 3 AD2 AD1 AD 0
AM10134V1
The SPI Read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
Multiple read command is also available in 3-wires mode.
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Output register mapping
6
L3GD20H
Output register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related addresses:
Table 17. Register address map
Register address
Name
34/52
Type
Default
Hex
Binary
Reserved
-
00-0E
-
-
WHO_AM_I
r
0F
000 1111
11010111
Reserved
-
10-1F
-
-
CTRL1
rw
20
010 0000
00000111
CTRL2
rw
21
010 0001
00000000
CTRL3
rw
22
010 0010
00000000
CTRL4
rw
23
010 0011
00000000
CTRL5
rw
24
010 0100
00000000
REFERENCE
rw
25
010 0101
00000000
OUT_TEMP
r
26
010 0110
Output
STATUS
r
27
010 0111
Output
OUT_X_L
r
28
010 1000
Output
OUT_X_H
r
29
010 1001
Output
OUT_Y_L
r
2A
010 1010
Output
OUT_Y_H
r
2B
010 1011
Output
OUT_Z_L
r
2C
010 1100
Output
OUT_Z_H
r
2D
010 1101
Output
FIFO_CTRL
rw
2E
010 1110
00000000
FIFO_SRC
r
2F
010 1111
Output
IG_CFG
rw
30
011 0000
00000000
IG_SRC
r
31
011 0001
Output
IG_THS_XH
rw
32
011 0010
00000000
IG_THS_XL
rw
33
011 0011
00000000
IG_THS_YH
rw
34
011 0100
00000000
IG_THS_YL
rw
35
011 0101
00000000
IG_THS_ZH
rw
36
011 0110
00000000
IG_THS_ZL
rw
37
011 0111
00000000
IG_DURATION
rw
38
011 1000
00000000
LOW_ODR
rw
39
011 1001
00000000
DocID023469 Rev 2
L3GD20H
Output register mapping
Registers marked as Reserved must not be changed. The writing to those registers may
cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered-up.
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Register description
7
L3GD20H
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
angular rate data. The registers address, made of 7 bits, is used to identify them and to write
the data through serial interface.
7.1
WHO_AM_I (0Fh)
Table 18. WHO_AM_I register
1
1
0
1
0
1
1
1
Zen
Xen
Yen
Device identification register.
7.2
CTRL1 (20h)
Table 19. CTRL1 register(1)
DR1
DR0
BW1
BW0
PD
1. Xen, Yen, Zen enable X, Yor Z register in level sensitive trigger mode. Once LVLen bit = 1, DEN level
replaces the LSB of X, Y or Z axes and all axis are available for reading.
Table 20. CTRL1 description
DR1-DR0
Output data rate selection. Refer to Table 21
BW1-BW0
Bandwidth selection. Refer to Table 21
Power mode. Default value: 0. Refer to Table
0= Power Down
PD
1= Normal Mode
(For Sleep Mode set {PD:Zen:Yen:Xen} to {1000})
Zen
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
Xen
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
DR<1:0> is used to set ODR selection. BW <1:0> is used to set bandwidth selection.
In the following table are reported all frequency resulting in combination of DR / BW bits.
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DocID023469 Rev 2
L3GD20H
Register description
Table 21. DR and BW configuration setting
Low_ODR
(1)
DR <1:0>
BW <1:0>
Cut-Off [Hz](2)
ODR [Hz]
1
00
00
12.5
n.a.
1
00
01
12.5
n.a.
1
00
10
12.5
n.a.
1
00
11
12.5
n.a.
1
01
00
25
n.a.
1
01
01
25
n.a.
1
01
10
25
n.a.
1
01
11
25
n.a.
1
1X
00
50
16.6
1
1X
01
50
16.6
1
1X
10
50
16.6
1
1X
11
50
16.6
0
00
00
100
12.5
0
00
01
100
25
0
00
10
100
25
0
00
11
100
25
0
01
00
200
12.5
0
01
01
200
-
0
01
10
200
-
0
01
11
200
70
0
10
00
400
20
0
10
01
400
25
0
10
10
400
50
0
10
11
400
110
0
11
00
800
30
0
11
01
800
35
0
11
10
800
-
0
11
11
800
100
1. this bit is described in register LOW_ODR (39h register).
2. values in the table are indicative and they can vary proportionally with the specific ODR value.
Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down /
normal / sleep mode) according with the following table.
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Register description
L3GD20H
Table 22. Power mode selection configuration
Mode
7.3
PD
Zen
Yen
Xen
Power down
0
-
-
-
Normal
1
-
-
-
Sleep
1
0
0
0
CTRL2 (21h)
Table 23. CTRL2 register
EXTRen
LVLen
HPM1
HPM0
HPCF3
HPCF2
HPCF1
HPCF0
Table 24. CTRL2 description
EXTRen
Edge sensitive trigger Enable: Default value: 0
(0: external trigger disabled; 1: External trigger enabled)
LVLen
Level sensitive trigger Enable: Default value: 0
(0: level sensitive trigger disabled; 1: level sensitive trigger enabled)
HPM1HPM0
High Pass filter Mode Selection. Default value: 00
Refer to Table 25
HPCF3HPCF0
High Pass filter Cut Off frequency selection. Default value: 0000
Refer to Table 26
Table 25. High pass filter mode configuration
HPM1
HPM0
High pass filter mode
0
0
Normal mode (reset reading REFERENCE 25h register)
0
1
Reference signal for filtering
1
0
Normal mode
1
1
Autoreset on interrupt event
Table 26. High pass filter cut off frequency configuration [Hz](1)
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HPCF3-0
ODR=12.5 ODR=25
Hz
Hz
ODR=50
Hz
ODR =100 ODR =200 ODR =400 ODR =800
Hz
Hz
Hz
Hz
0000
1
2
4
8
15
30
56
0001
0.5
1
2
4
8
15
30
0010
0.2
0.5
1
2
4
8
15
0011
0.1
0.2
0.5
1
2
4
8
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Register description
Table 26. High pass filter cut off frequency configuration [Hz](1) (continued)
HPCF3-0
ODR=12.5 ODR=25
Hz
Hz
ODR=50
Hz
ODR =100 ODR =200 ODR =400 ODR =800
Hz
Hz
Hz
Hz
0100
0.05
0.1
0.2
0.5
1
2
4
0101
0.02
0.05
0.1
0.2
0.5
1
2
0110
0.01
0.02
0.05
0.1
0.2
0.5
1
0111
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1000
0.002
0.005
0.01
0.02
0.05
0.1
0.2
1001
0.001
0.002
0.005
0.01
0.02
0.05
0.1
1. values in the table are indicative and they can vary proportionally with the specific ODR value
7.4
CTRL3 (22h)
Table 27. CTRL3 register
INT1_IG INT1_Boot H_Lactive PP_OD INT2_DRDY INT2_FTH INT2_ORun
INT2_Empty
Table 28. CTRL3 description
INT1_IG
Interrupt enable on INT1 pin. Default value 0. (0: disable; 1: enable)
INT1_Boot
Boot status available on INT1 pin. Default value 0. (0: disable; 1: enable)
H_Lactive
Interrupt active configuration on INT. Default value 0. (0: high; 1:low)
PP_OD
Push- Pull / Open drain. Default value: 0. (0: push-pull; 1: open drain)
INT2_DRDY Date Ready on DRDY/INT2 pin. Default value 0. (0: disable; 1: enable)
INT2_FTH
FIFO Threshold interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)
INT2_ORun FIFO Overrun interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)
INT2_Empty FIFO Empty interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)
7.5
CTRL4 (23h)
Table 29. CTRL4 register
BDU
BLE
FS1
FS0
IMPen
ST2
ST1
SIM
Table 30. CTRL4 description
BDU
Block data update. Default value: 0
(0: continuos update; 1: output registers not updated until MSB and LSB reading)
BLE
Big/little endian data selection. Default value 0.
(0: Data LSB @ lower address; 1: Data MSB @ lower address)
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Register description
L3GD20H
Table 30. CTRL4 description (continued)
FS1-FS0
Full scale selection. Default value: 00
(00: 245 dps; 01: 500 dps; 1x: 2000 dps)
IMPen
Level sensitive latched enable. Default value: 0
(0: level sensitive latched disabled; 1: level sensitive latched enabled)
ST2-ST1
Self-test enable. Default value: 00
00 = normal mode (default)
01 = self-test 0 (+)
10 = unused
11 = self-test 1(-)
SIM
7.6
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
CTRL5 (24h)
Table 31. CTRL5 register
BOOT
FIFO_EN
StopOnFTH
HPen
IG_Sel1
IG_Sel0
Out_Sel1
Out_Sel0
Table 32. CTRL5 description
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content(1))
FIFO_EN
FIFO enable. Default value: 0
(0: FIFO disable; 1: FIFO Enable)
StopOnFTH
Sensing chain FIFO stop values memorization at FIFO Threshold.
Default value: 0
0 = FIFO depth is not limited (32 digital words per axis)
1 = FIFO depth is limited to FIFO Threshold which is defined in
FIFO_CTRL (2Eh Register)
HPen
High Pass filter Enable. Default value: 0
(0: HPF disabled; 1: HPF enabled see Figure 23.)
IG_Sel1-IG_Sel0
INT Generator selection configuration. Default value: 00
(See Figure 23.)
Out_Sel1-Out_Sel0
Out selection configuration. Default value: 00
(See Figure 23.)
1. Boot request is executed as soon as internal oscillator is turned-on. It is possibile to set bit while in Powerdown mode, in this case it will be served at the next normal mode or sleep mode.
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Register description
Figure 23. IG_Sel and Out_Sel configuration block diagram
Out_Sel <1:0>
00
01
DataReg
0
LPF2
ADC
LPF1
HPF
FIFO
32x16x3
10
11
1
INT1_Sel <1:0>
HPen
10
11
01
Interrupt
generator
00
AM08592V1
7.7
REFERENCE (25h)
Table 33. REFERENCE register
Ref7
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Table 34. REFERENCE register description
Ref 7-Ref0
7.8
Digital high pass filter reference value. Default value: 0
OUT_TEMP (26h)
Table 35. OUT_TEMP register
Temp7
Temp6
Temp5
Temp4
Temp3
Temp2
Temp1
Temp0
Table 36. OUT_TEMP register description
Temp7-Temp0
Temperature data (-1LSB/deg with 8 bit resolution). The value is expressed
as two’s complement.
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Register description
7.9
L3GD20H
STATUS (27h)
Table 37. STATUS register
ZYXOR
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
Table 38. STATUS description
X, Y, Z -axis data overrun. Default value: 0
ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous one before it was
read)
ZOR
Z axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one)
YOR
Y axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one)
XOR
X axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one)
ZYXDA X, Y, Z -axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
7.10
ZDA
Z axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)
YDA
Y axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available;1: a new data for the Y-axis is available)
XDA
X axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
OUT_X_L (28h), OUT_X_H (29h)
X-axis angular rate data. The value is expressed as two’s complement.
7.11
OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y-axis angular rate data. The value is expressed as two’s complement.
7.12
OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis angular rate data. The value is expressed as two’s complement.
7.13
FIFO_CTRL (2Eh)
Table 39. FIFO_CTRL register
FM2
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FM1
FM0
FTH4
FTH3
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FTH2
FTH1
FTH0
L3GD20H
Register description
Table 40. FIFO_CTRL register description
FM2-FM0
FIFO mode selection. Default value: 000 (see Table 41)
FTH4-FTH0
FIFO threshold setting. Default value: 0
Table 41. FIFO mode configuration
FM2
7.14
FM1
FM0
FIFO mode
0
0
0
Bypass mode
0
0
1
FIFO mode
0
1
0
Stream mode
0
1
1
Stream-to-FIFO mode
1
0
0
Bypass-to-stream mode
1
1
0
Dynamic stream mode
1
1
1
Bypass-to-FIFO mode
FIFO_SRC (2Fh)
Table 42. FIFO_SRC register
FTH
OVRN
EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
Table 43. FIFO_SRC register description
7.15
FTH
FIFO threshold status. (0: FIFO filling is lower than FTH level; 1: FIFO filling is
equal or higher than FTH level)
OVRN
Overrun bit status.
(0: FIFO is not completely filled; 1:FIFO is completely filled)
EMPTY
FIFO empty bit.
( 0: FIFO not empty; 1: FIFO empty)
FSS4-FSS0
FIFO stored data level of the unread samples
IG_CFG (30h)
Table 44. IG_CFG register
AND/OR
LIR
ZHIE
ZLIE
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YHIE
YLIE
XHIE
XLIE
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Register description
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Table 45. IG_CFG description
AND/OR
AND/OR combination of Interrupt events. Default value: 0
(0: OR combination of interrupt events 1: AND combination of interrupt events
Latch Interrupt Request. Default value: 0
LIR
(0: interrupt request not latched; 1: interrupt request latched)
Cleared by reading IG_SRC reg.
ZHIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value higher than preset threshold)
ZLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value lower than preset threshold)
YHIE
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value higher than preset threshold)
YLIE
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value lower than preset threshold)
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured angular rate
value lower than preset threshold)
Configuration register for Interrupt source.
7.16
IG_SRC (31h)
Table 46. IG_SRC register
0
IA
ZH
ZL
YH
YL
XH
XL
Table 47. IG_SRC description
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IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred)
ZL
Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred)
YH
Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred)
YL
Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred)
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Register description
Table 47. IG_SRC description
XH
X high. Default value: 0 (0: no interrupt, 1: X High event has occurred)
XL
X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred)
Interrupt source register. Read only register.
Reading at this address clears IG_SRC IA bit (and eventually the interrupt signal on INT1
pin) and allows the refresh of data in the IG_SRC register if the latched option was chosen.
7.17
IG_THS_XH (32h)
Table 48. IG_THS_XH register
DCRM
THSX14
THSX13
THSX12
THSX11
THSX10
THSX9
THSX8
Table 49. IG_THS_XH description
Interrupt generation counter mode selection. Default value: 0
DCRM
0 = Reset
1 = Decrement
THSX14 - THSX8
7.18
Interrupt threshold on X axis. Default value: 000 0000
IG_THS_XL (33h)
Table 50. IG_THS_XL register
THSX7
THSX6
THSX5
THSX4
THSX3
THSX2
THSX1
THSX0
THSY9
THSY8
Table 51. IG_THS_XL description
THSX7 - THSX0
7.19
Interrupt threshold on X axis. Default value: 0000 0000
IG_THS_YH (34h)
Table 52. IG_THS_YH register
-
THSY14
THSY13
THSY12
THSY11
THSY10
Table 53. IG_THS_YH description
THSY14 - THSY8
Interrupt threshold on Y axis. Default value: 000 0000
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Register description
7.20
L3GD20H
IG_THS_YL (35h)
Table 54. IG_THS_YL register
THSY7
THSY6
THSY5
THSY4
THSY3
THSY2
THSY1
THSY0
THSZ9
THSZ8
THSZ1
THSZ0
D1
D0
Table 55. IG_THS_YL description
THSY7 - THSY0
7.21
Interrupt threshold on Y axis. Default value: 0000 0000
IG_THS_ZH (36h)
Table 56. IG_THS_ZH register
-
THSZ14
THSZ13
THSZ12
THSZ11
THSZ10
Table 57. IG_THS_ZH description
THSZ14 - THSZ8
7.22
Interrupt threshold on Z axis. Default value: 000 0000
IG_THS_ZL (37h)
Table 58. IG_THS_ZL register
THSZ7
THSZ6
THSZ5
THSZ4
THSZ3
THSZ2
Table 59. IG_THS_ZL description
THSZ7 - THSZ0
7.23
Interrupt threshold on Z axis. Default value: 0000 0000
IG_DURATION (38h)
Table 60. IG_DURATION register
WAIT
D6
D5
D4
D3
D2
Table 61. IG_DURATION description
WAIT
WAIT enable. Default value: 0 (0: disable; 1: enable)
D6 - D0
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
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Register description
WAIT bit has the following meaning:
Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold
Wait =’1’: if signal crosses the selected threshold, the interrupt falls after a number of
samples equal to the duration counter register value.
Figure 24. Wait disabled
Figure 25. Wait enabled
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Register description
7.24
L3GD20H
LOW_ODR (39h)
Table 62. LOW_ODR register
--
--
DRDY_HL
0(1)
I2C_dis
SW_RES
0(1)
Low_ODR
1. These bits must be set to ‘0’ for proper working of the device.
Table 63. LOW_ODR description
DRDY/INT2 pin active level. Default value: 0
DRDY_HL
0 = DRDY active high
1 = DRDY active low
0 = both the I2C and SPI interfaces enabled (default)
I2C_dis
1 = SPI only
Software reset. Default value: 0
SW_RES
0 = Normal Mode
1 = Reset Device (this bit is cleared by hardware after next flash boot)
Low speed ODR. Default value: 0
Low_ODR
Refer to Table 21 DR and BW configuration setting: for ODR and
Bandwidth configuration on CTRL1 register
0 = Low Speed ODR disabled
1 = Low Speed ODR enabled
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8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 64. LGA 3x3x1.0 16L mechanical data
mm
Dim.
Min.
Typ.
A1
Max.
1
A2
0.785
A3
0.200
D1
2.850
3.000
3.150
E1
2.850
3.000
3.150
L1
1.000
1.060
L2
2.000
2.060
N1
0.500
N2
1.000
M
0.040
0.100
P1
0.875
P2
1.275
T1
0.290
0.350
0.410
T2
0.190
0.250
0.310
d
0.150
k
0.050
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Package information
L3GD20H
Figure 26. LGA 3x3x1.0 16L mechanical drawing
7983231_M
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9
Revision history
Revision history
Table 65. Document revision history
Date
Revision
Changes
20-Jul-2012
1
Initial release.
05-Mar-2013
2
Added Chapter 3: Application hints, Chapter 6: Output register
mapping and Chapter 7: Register description
Updated Chapter 4.2: FIFO.
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L3GD20H
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