OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 High Voltage, Rail-to-Rail Input/Output, Precision Operational Amplifiers, e-trim™ Series Check for Samples: OPA192, OPA2192, OPA4192 FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • 1 23456 Low Offset Voltage: ±5 µV Low Offset Voltage Drift: ±0.2µV/°C Low Noise: 5.5 nV/√Hz at 1 kHz Wide Bandwidth: 10 MHz GBW (G = 100) High Slew Rate : 20 V/µs Low Quiescent Current: 1 mA per Amplifier Rail-to-Rail Input and Output Wide Supply: ±2.25 V to ±18 V, +4.5 V to +36 V EMI/RFI Filtered Inputs High Common-Mode Rejection: 140 dB Low Bias Current: ±5 pA Differential Input Voltage Range to Supply Rail High Capacitive Load Drive Capability: 1 nF Industry standard packages: – Single in SO-8, MSOP-8 and SOT23-5 – Dual in SO-8 and MSOP-8 – Quad in SO-14 and TSSOP-14 High-Resolution ADC Driver Amplifiers Multiplexed Data-Acquisition Systems SAR ADC Reference Buffers Programmable Logic Controllers Test and Measurement Equipment High-Side and Low-Side Current Sensing High Precision Comparator DESCRIPTION The OPA192 family (1) (OPA192, OPA2192, and OPA4192) is a new generation of 36-V, e-trim operational amplifiers. These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ), and 10MHz bandwidth. Unique features such as differential inputvoltage range to the supply rail, high output current and high capacitive load drive of up to 1 nF, and high slew rate make the OPA192 a robust, highperformance operational amplifier for high-voltage industrial applications. The OPA192 family of op amps is available in standard packages and is specified from –40°C to +125°C. (1) OPA192 SO-8 package is production data. All other devices are product preview. OPA192 IN A HIGH-VOLTAGE, MULTIPLEXED, DATA-ACQUISITION SYSTEM Analog Inputs REF3240 RC Filter OPA192 RC Filter Reference Driver Bridge Sensor OPA192 Gain Network Gain Network + 4:2 HV MUX Thermocouple REF + Current Sensing Photo LED Detect Optical Sensor High Voltage Multiplexed Input VINP OPA192 Gain Network + Gain Network OPA192 High Voltage Level Translation Anti-Aliasing Filter ADS8864 VIN M VCM 1 2 3 4 5 6 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. e-trim is a trademark of Texas Instruments. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage Signal input terminals VALUE UNIT ±20 (+40, single supply) V (V–) – 0.5 to (V+) + 0.5 V Common-mode Voltage Differential Current (V+) - (V-) + 0.2 V ±10 mA Output short circuit (2) Continuous Operating temperature –55 to +150 °C Storage temperature –65 to +150 °C Junction temperature +150 °C Human body model (HBM) 4 kV Charged device model (CDM) 1 kV Electrostatic discharge (ESD) ratings (1) (2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to ground, one amplifier per package. ELECTRICAL CHARACTERISTICS: VS= ±4 V to ±18 V (VS= +8 V to +36 V) At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. OPA192 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±5 ±25 µV OFFSET VOLTAGE VOS Input offset voltage dVOS/dT Input offset voltage drift TA = –40°C to +125°C PSRR Power-supply rejection ratio TA = –40°C to +125°C TA = –40°C to +125°C (V–) – 0.1 V < VCM < (V+) – 3 V ±75 µV ±0.2 ±0.5 µV/°C ±0.3 ±1.0 µV/V ±5 ±20 pA ±5 nA ±20 pA ±2 nA INPUT BIAS CURRENT IB IOS Input bias current Input offset current TA = –40°C to +125°C ±2 TA = –40°C to +125°C NOISE En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3V f = 0.1 Hz to 10 Hz 1.30 µVPP (V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4 µVPP (V–) – 0.1 V < VCM < (V+) – 3 V en in 2 Input voltage noise density (V+) – 1.5 V < VCM < (V+) + 0.1 V Input current noise density Submit Documentation Feedback f = 100 Hz f = 1 kHz f = 100 Hz 10.5 nV/√Hz 5.5 nV/√Hz 32 nV/√Hz f = 1 kHz 12.5 nV/√Hz f = 1kHz 1.5 fA/√Hz Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS: VS= ±4 V to ±18 V (VS= +8 V to +36 V) (continued) At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. OPA192 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (V+) + 0.1 V INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V (V+) – 3 V < VCM < (V+) - 1.5 V CMRR Common-mode rejection ratio TA = –40°C to +125°C 120 140 dB See Typical Characteristics (V+) – 1.5 V < VCM < (V+) + 0.1 V 100 120 dB (V–) – 0.1 V < VCM < (V+) – 3 V 114 126 dB (V+) – 1.5 V < VCM < (V+) + 0.1 V 86 100 dB INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 MΩ || pF 1013Ω || pF 1 || 6.4 OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V RLOAD = 2 kΩ 120 134 dB (V–) + 0.6 V < VO < (V+) – 0.6 V TA = –40°C to +125°C RLOAD = 2 kΩ 114 126 dB (V–) + 0.3 V < VO < (V+) – 0.3 V RLOAD = 10 kΩ 126 140 dB (V–) + 0.3 V < VO < (V+) – 0.3 V TA = –40°C to +125°C RLOAD = 10 kΩ 120 134 dB 10 MHz 20 V/µs VS = ±18 V, G = 1, 10-V step 1.4 µs VS = ±18 V, G = 1, 5-V step 0.9 µs VS = ±18 V, G = 1, 10-V step 2.1 µs VS = ±18 V, G = 1, 5-V step 1.8 µs 200 ns 0.00008 % FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 10-V step To 0.01% ts Settling time To 0.001% tOR Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS OUTPUT No load Positive rail VO Voltage output swing from rail Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 10 mV 95 110 mV RLOAD = 2 kΩ 430 500 mV 5 10 mV RLOAD = 10 kΩ 95 110 mV RLOAD = 2 kΩ 430 500 mV No load Negative rail ISC 5 RLOAD = 10 kΩ ±65 See Typical Characteristics f = 1 MHz, IO = 0 A, See Figure 23 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 375 Submit Documentation Feedback mA pF Ω 3 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS: VS= ±2.25 V to ±4 V (VS= +4.5 V to +8 V) At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. OPA192 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±5 ±25 µV OFFSET VOLTAGE VCM = (V+) – 3 V VOS Input offset voltage See Common-Mode Voltage Range section VCM = VS / 2 VCM = (V+) – 1.5 V ±10 TA = –40°C to +125°C, VCM = (V+) – 3 V dVOS/dT PSRR Input offset voltage drift Power-supply rejection ratio TA = –40°C to +125°C µV ±25 µV ±75 µV (V–) – 0.1 V < VCM < (V+) – 1.5 V ±0.2 ±0.5 µV/°C (V+) – 1.5 V < VCM < (V+) + 0.1 V ±0.5 ±3 µV/°C VCM = (V-) TA = –40°C to +125°C ±0.5 µV/V ±1 µV/V INPUT BIAS CURRENT IB IOS Input bias current Input offset current ±5 TA = –40°C to +125°C ±2 TA = –40°C to +125°C ±20 pA ±5 nA ±20 pA ±2 nA NOISE En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz (V–) – 0.1 V < VCM < (V+) – 3 V en Input voltage noise density (V+) – 1.5 V < VCM < (V+) + 0.1 V in 1.30 (V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz Input current noise density µVPP 4 f = 100 Hz µVPP 10.5 nV/√Hz f = 1 kHz 5.5 nV/√Hz f = 100 Hz 32 nV/√Hz f = 1 kHz 12.5 nV/√Hz f = 1kHz 1.5 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V CMRR 94 (V+) – 3 V < VCM < (V+) – 1.5 V Common-mode rejection ratio 110 See Typical Characteristics (V+) – 1.5V < VCM < (V+) + 0.1 V TA = –40°C to +125°C (V+) + 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V V dB dB 100 120 dB 90 104 dB INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 1 || 6.4 MΩ || pF 1013Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.6 V < VO < (V+) – 0.6 V RLOAD = 2 kΩ 110 120 dB (V–) + 0.6 V < VO < (V+) – 0.6 V TA = –40 °C to +125 °C RLOAD = 2 kΩ 100 114 dB (V–) + 0.3 V < VO < (V+) – 0.3 V RLOAD = 10 kΩ 110 126 dB (V–) + 0.3 V < VO < (V+) – 0.3 V TA = –40°C to +125°C RLOAD = 10 kΩ 110 120 dB 10 MHz 20 V/µs 1 µs 200 ns FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 10-V step ts Settling time To 0.01% tOR Overload recovery time VIN× G = VS 4 Submit Documentation Feedback VS = ±3 V, G = 1, 5-V step Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VS Specified voltage range IQ +4.5 Quiescent current per amplifier IO = 0 A 1 TA = –40°C to +125°C, IO = 0 A +36 V 1.2 mA 1.5 mA TEMPERATURE Specified range –40 +125 °C Operating range –55 +150 °C Thermal protection +140 °C THERMAL INFORMATION: OPA192 OPA192 THERMAL METRIC (1) D (SO) DBV (SOT23) DGK (MSOP) 8 PINS 5 PINS 8 PINS θJA Junction-to-ambient thermal resistance 115.8 TBD TBD θJC(top) Junction-to-case(top) thermal resistance 60.1 TBD TBD θJB Junction-to-board thermal resistance 56.4 TBD TBD ψJT Junction-to-top characterization parameter 12.8 TBD TBD ψJB Junction-to-board characterization parameter 55.9 TBD TBD θJC(bottom) Junction-to-case(bottom) thermal resistance N/A TBD TBD (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 5 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com PIN CONFIGURATIONS DBV PACKAGE: OPA192 SOT23-5 (TOP VIEW) OUT 1 V- 2 +IN 3 D AND DGK PACKAGES: OPA2192 SO-8 AND MSOP-8 (TOP VIEW) V+ 5 4 -IN DCK PACKAGE: OPA192 SC-70 (TOP VIEW) IN+ 1 V- 2 IN- 3 NC 5 V+ 4 OUT (1) 1 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B D AND PW PACKAGES: OPA4192 SO-14 AND TSSOP-14 (TOP VIEW) D AND DGK PACKAGES: OPA192 SO-8 AND MSOP-8 (TOP VIEW) (1) OUT A 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C NC = No internal connection. NOTE: OPA192 SO-8 package is production data. All other packages are product preview. 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: Table of Graphs Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4, Figure 5, Figure 6 Offset Voltage vs Power Supply Figure 7 Open-Loop Gain and Phase vs Frequency Figure 8 Closed-Loop Gain and Phase vs Frequency Figure 9 Input Bias Current vs Common-Mode Voltage Figure 10 Input Bias Current vs Temperature Figure 11 Output Voltage Swing vs Output Current (maximum supply) Figure 12 CMRR and PSRR vs Frequency Figure 13 CMRR vs Temperature Figure 14 PSRR vs Temperature Figure 15 0.1-Hz to 10-Hz Noise Figure 16 Input Voltage Noise Spectral Density vs Frequency Figure 17 THD+N Ratio vs Frequency Figure 18 THD+N vs Output Amplitude Figure 19 Quiescent Current vs Supply Voltage Figure 20 Quiescent Current vs Temperature Figure 21 Open Loop Gain vs Temperature Figure 22 Open Loop Output Impedance vs Frequency Figure 23 Small Signal Overshoot vs Capacitive Load (100-mV output step) Figure 24, Figure 25 No Phase Reversal Figure 26 Positive Overload Recovery Figure 27 Negative Overload Recovery Figure 28 Small-Signal Step Response (100 mV) Figure 29, Figure 30 Large-Signal Step Response Figure 31 Settling Time Figure 32, Figure 33, Figure 34, Figure 35 Short-Circuit Current vs Temperature Figure 36 Maximum Output Voltage vs Frequency Figure 37 Propagation Delay Rising Edge Figure 38 Propagation Delay Falling Edge Figure 39 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 7 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 35 22 Distribution Taken From 66 Amplifiers Distribution Taken From 4715 Amplifiers Percentage of Amplifiers (%) Percentage of Amplifiers (%) 20 18 16 14 12 10 8 6 4 Temperature = -40C to 125C 30 25 20 15 10 5 Offset Voltage (V) 0.95 0.85 0.75 0.65 0.50 0.40 0.30 0.20 0.10 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 0.00 2 Offset Voltage Drift (µV/C) C032 C013 Figure 1. OFFSET VOLTAGE PRODUCTION DISTRIBUTION Figure 2. OFFSET VOLTAGE DRIFT DISTRIBUTION 100 50 66 Typical Units Shown 5 Typical Units Shown 75 25 25 VOS (V) VOS (V) 50 0 ±25 0 VCM = -18.1V ±50 ±25 ±75 ±100 ±75 ±50 ±50 ±25 0 25 50 75 100 125 150 Temperature (C) ±20 Figure 3. OFFSET VOLTAGE vs TEMPERATURE ±5 0 5 10 15 20 C001 Figure 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 200 5 Typical Units Shown 150 75 VCM = +18.1V VCM = -18.1V VOS (V) 25 0 ±25 50 0 ±50 P-Channel N-Channel ±100 ±50 VCM =+2.35V VCM = -2.35 V ±150 ±75 ±100 12.5 5 Typical Units Shown VS = ±2.25 V 100 50 VOS (V) ±10 VCM (V) 100 Transition 13.5 14.5 15.5 VCM (V) 16.5 17.5 18.5 Submit Documentation Feedback Transition P-Channel ±200 ±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5 VCM (V) C001 Figure 5. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 8 ±15 C001 N-Channel 1.0 1.5 2.0 2.5 C001 Figure 6. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 50 CLOAD = 15 pF 120.0 100.0 10 80.0 Gain (dB) 20 0 ±10 ±20 ±40 0.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 VSUPPLY (V) 1 10 100 1k 10k 100k Frequency (Hz) C001 60.0 1M 0 10M 100M C004 Figure 8. OPEN-LOOP GAIN AND PHASE vs FREQUENCY 20 G = -100 G = +1 G = -1 G = -10 15 Input Bias Current (pA) 40.0 90 45 ±20.0 Figure 7. OFFSET VOLTAGE vs POWER SUPPLY Gain (dB) Phase 40.0 20.0 2.0 135 60.0 ±30 ±50 Open-loop Gain Phase () VOS (V) 30 0.0 180 140.0 10 Typical Units Shown VS = ±2.25V to 18V 40 20.0 0.0 IB- 10 5 0 IB+ ±5 ±10 ±15 ±20.0 1000 10k 100k 1M ±20 ±18.0 10M Frequency (Hz) IB+ IB Ios Output Voltage (V) Input Bias Current (pA) 4000 3000 2000 1000 Ios ±1000 ±75 ±50 ±25 0 25 50 75 100 Temperature (C) 125 150 18.0 C001 Figure 10. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 6000 0 9.0 VCM (V) Figure 9. CLOSED-LOOP GAIN AND PHASE vs FREQUENCY 5000 0.0 ±9.0 C003 175 (V+) +1 (V+) (V+) -1 (V+) -2 (V+) -3 (V+) -4 (V+) -5 (V-) +5 (V-) +4 (V-) +3 (V-) +2 (V-) +1 (V-) (V-) -1 25C ±40C 85C 125C 125C 85C ±40C 25C 0 10 Figure 11. INPUT BIAS CURRENT vs TEMPERATURE 20 30 40 50 60 70 Output Current (mA) C001 80 C018 Figure 12. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 9 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. Common-Mode Rejection Ratio (µV/V) Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 160.0 140.0 120.0 100.0 80.0 60.0 +PSRR 40.0 CMRR 20.0 -PSRR 10 8 6 4 VS = ±2.25 V, VCM = V+ - 3V 2 0 ±2 VS = ±18 V, VCM = 0 V ±4 ±6 ±8 ±10 0.0 1 10 100 1k 10k 100k Frequency (Hz) ±75 1M ±50 ±25 0 25 50 75 100 125 Temperature (C) C012 Figure 13. CMRR AND PSRR vs FREQUENCY 150 C001 Figure 14. CMRR vs TEMPERATURE 0.6 0.4 400 nV/div Power-Supply Rejection Ratio (µV/V) 1 0.8 0.2 0 -0.2 -0.4 -0.6 -0.8 Peak-to-Peak Noise = VRMS × 6.6 = 1.30 Vpp -1 ±75 ±50 ±25 0 25 50 75 100 125 Temperature (C) Time (1 s/div) 150 C001 C001 Figure 15. PSRR vs TEMPERATURE Figure 16. 0.1-Hz to 10-Hz NOISE Total Harmonic Distortion + Noise (%) 9ROWDJH1RLVH'HQVLW\ Q9¥+] VCM = V+ - 100 mV N-Channel Input 100 10 VCM = 0 V P-Channel Input G = +1 V/V, RL = 2 k G = -1 V/V, RL = 10 k 0.01 -80 G = -1 V/V, RL = 2 k 0.001 -100 0.0001 -120 VOUT = 3.5 VRMS BW = 80 kHz 0.00001 1 0.1 1 10 100 1k Frequency (Hz) 10k 100k Submit Documentation Feedback -140 10 100 1k 10k Frequency (Hz) C002 Figure 17. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 10 -60 G = +1 V/V, RL = 10 k Total Harmonic Distortion + Noise (dB) 0.1 1000 C007 Figure 18. THD+N RATIO vs FREQUENCY Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 0.01 -80 0.001 -100 0.0001 -120 G = +1 V/V, RL = 10 k G = +1 V/V, RL = 2 k G = -1 V/V, RL = 10 k G = -1 V/V, RL = 2 k 0.00001 0.01 0.1 1.2 1.1 IQ (mA) Total Harmonic Distortion + Noise (%) -60 f = 1 kHz BW = 80 kHz Total Harmonic Distortion + Noise (dB) 0.1 0.9 -140 1 1.0 0.8 10 0 Output Amplitude (VRMS) 4 8 12 16 20 24 28 32 36 Supply Voltage (V) C008 Figure 19. THD+N vs OUTPUT AMPLITUDE C001 Figure 20. QUIESCENT CURRENT vs SUPPLY VOLTAGE 3.0 1.2 Vs = 4.5V Vs = 36V 2.0 1.1 AOL (µV/V) IQ (mA) 1.0 Vs = ±18V 1 Vs = ±2.25V 0.0 ±1.0 0.9 ±2.0 ±3.0 0.8 ±75 ±50 ±25 0 25 50 75 100 125 ±75 150 Temperature (C) RL = 10k ±50 ±25 0 25 50 75 100 125 150 Temperature (C) C001 Figure 21. QUIESCENT CURRENT vs TEMPERATURE C001 Figure 22. OPEN-LOOP GAIN vs TEMPERATURE 10k 50 RII =N 1 kO R RFF =N 1 kO 45 G = -1 40 1k Overshoot (%) Output Impedance ( ) + 18 V 100 35 ± + + VIN ± 30 RISO OPA192 CL ± 18 V 25 20 RISO = 00 15 RISO = 2525 10 RISO = 50 50 5 10 0 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 23. OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10p 100p 1n Capacitive Load (F) C016 C013 Figure 24. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 11 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 50 ± 40 35 OPA192 + VIN RL CL + + ± 37 VPP ± 18 V Sine Wave (±18.5V) ± 18 V ± 5 V/div 30 VIN + 18 V ± RISO OPA192 + Overshoot (%) G = +1 + 18 V 45 25 20 VOUT 15 VOUT RISO = 0 0 RISO = 25 25 RISO = 50 50 10 5 0 10p 100p Time (200 s/div) 1n Capacitive Load (F) C011 C013 Figure 25. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) Figure 26. NO PHASE REVERSAL 1 kO RRI I =N 1 kO RRI = N I ± + 10 kO RRF = N F OPA192 OPA192 G = -10 VOUT + ± VOUT ± 18 V 5 V/div 5 V/div ± ± + VOUT + VIN + 18 V VIN 10 kO RRFF = N + 18 V VOUT ± 18 V G = -10 VIN VIN Time (200 ns/div) Time (200 ns/div) C009 C010 Figure 27. POSITIVE OVERLOAD RECOVERY Figure 28. NEGATIVE OVERLOAD RECOVERY 1 kO RII = N kO RFF = 1N G = -1 + 18 V + 20 mV/div 20 mV/div ± G = +1 + 18 V ± ± OPA192 + VIN CL ± 18 V OPA192 + VIN + ± 18 V RL CL ± RL N CL = 10 pF CL = 10 pF Time (100 ns/div) Time (120 ns/div) C015 Figure 29. SMALL-SIGNAL STEP RESPONSE (100 mV) 12 Submit Documentation Feedback C006 Figure 30. SMALL-SIGNAL STEP RESPONSE (100 mV) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 4 1 kO RRI I =N Output Delta from Final Value (mV) 2 V/div RL N CL = 10 pF G = -1 RRFF =N 1 kO + 18 V ± + OPA192 + VIN ± CL ± 18 V G = +1 3 2 1 0 -1 0.01% Settling = ±1 mV -2 -3 Step Applied at t = 0 -4 Time (300 ns/div) 0 0.25 0.5 0.75 Figure 31. LARGE-SIGNAL STEP RESPONSE 1.5 1.75 2 C034 4 G = +1 Output Delta from Final Value (mV) Output Delta from Final Value (mV) 1.25 Figure 32. SETTLING TIME (10-V Positive Step) 4 3 2 1 0 0.01% Settling = ±500 V -1 -2 -3 Step Applied at t = 0 -4 G = +1 3 2 1 0 -1 0.01% Settling = ±1 mV -2 -3 Step Applied at t = 0 -4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Time (s) 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Time (s) C034 Figure 33. SETTLING TIME (5-V Positive Step) 2 C034 Figure 34. SETTLING TIME (10-V Negative Step) 80 4 G = +1 3 ISC, Source ISC, Sink 60 2 1 ISC (mA) Output Delta from Final Value (mV) 1 Time (s) C005 0 0.01% Settling = ±500 V -1 -2 40 20 -3 Step Applied at t = 0 0 -4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Time (s) 1.8 ±75 ±50 ±25 Figure 35. SETTLING TIME (5-V Negative Step) 0 25 50 75 100 125 Temperature (C) C034 150 C001 Figure 36. SHORT-CIRCUIT CURRENT vs TEMPERATURE Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 13 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. 30 Maximum output voltage without slew-rate induced distortion. VS = ±15 V Overdrive = 100 mV Output Voltage (5 V/div) Output Voltage (VPP) 25 20 15 VS = ±5 V 10 VS = ±2.25 V 5 tpLH = 0.97 s VOUT Voltage 0 10k 100k 1M Time (200 ns/div) 10M Frequency (Hz) C033 C025 Output Voltage (1 V/div) Figure 37. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Figure 38. PROPAGATION DELAY RISING EDGE VOUT Voltage tpLH = 1.1 s Overdrive = 100 mV Time (200 ns/div) C026 Figure 39. PROPAGATION DELAY FALLING EDGE 14 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 DETAILED DESCRIPTION OVERVIEW The OPA192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. Figure 40 shows the simplified diagram of OPA192 with e-trim. OPA192 NCH Input Stage IN+ 36-V Differential Front End Slew Boost High Capacitive Load Compensation IN Output Stage VOUT PCH Input Stage e-Trim Package Level Trim Figure 40. Simplified Schematic Unlike previous e-trim op amps, the OPA192 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 25 µV (max) and low voltage offset drift of 0.5 µV/°C (max) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial sensors, filters, and high-voltage data acquisition. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-μF capacitors are adequate. OPERATING VOLTAGE The OPA192 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings. In addition, key parameters are assured over the specified temperature of TA = –40°C to +125°C. Parameters that vary significantly with operating voltage or temperature are shown in the Typical Characteristics. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 15 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com EMI REJECTION The OPA192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPA192 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 41 shows the results of this testing on the OPA192. Table 2 shows the EMIRR IN+ values for the OPA192 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com. 160.0 140.0 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V EMIRR IN+ (dB) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 10M 100M 1G 10G Frequency (Hz) C017 Figure 41. EMIRR Testing Table 2. OPA192 EMIRR IN+ for Frequencies of Interest 16 FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 44.1 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 52.8 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz) 69.5 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB 5.0 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 105.5 dB Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 42 for an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS + ± RF +VS VDD R1 IN- 100 RS IN+ 100 OPA192 Power-Supply ESD Cell ID VIN RL + ± VSS + ± -VS TVS Figure 42. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before it is soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. While this behavior is necessary for out-of-circuit protection, it causes excessive current and damage if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 17 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com COMMON-MODE VOLTAGE RANGE The OPA192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 43. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V to (V+) – 1.5 V) in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded compared to operation outside this region. +Vsupply IS1 VINPCH1 PCH2 NCH4 NCH3 VIN+ e-TrimTM FUSE BANK VOS TRIM VOS DRIFT TRIM -Vsupply Figure 43. Rail-to-Rail Input Stage To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPA192 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in Figure 44. P-Channel Region Transition Region N-Channel Region P-Channel Region 100 0 -100 OPA192 e-Trim Input Offset Voltage vs Vcm -200 -300 -15.0 N-Channel Region 200 Input Offset Voltage (uV) Input Offset Voltage (uV) 200 Transition Region -14.0 Y11.0 12.0 13.0 Common Mode Voltage 14.0 15.0 100 0 -100 -200 -300 -15.0 Input Offset Voltage vs Vcm without e-Trim Input -14.0 Y11.0 12.0 13.0 Common Mode Voltage 14.0 15.0 Figure 44. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers 18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 INPUT PROTECTION CIRCUITRY The OPA192 uses a unique input architecture to eliminate the need for input protection diodes but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 45 can be activated by fast transient step responses and can introduce signal distortion and settling time delays due to alternate current paths, as shown in Figure 46. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes causing an increase in input current and resulting in extended settling time, as seen in Figure 47. V+ V+ VIN+ VIN+ VOUT VOUT OPA192 36 V ~0.7 V VIN VIN OPA192 Provides Full 36-V Differential Input Range Conventional Input Protection Limits Differential Input Range V V Figure 45. OPA192 Input Protection Does Not Limit Differential Input Capability Vn=+10V RFILT +10V Ron_mux Sn CFILT 1 D CS 1 2 +10V ~-9.3V CD Vin- Vn+1=- R FILT 10V -10V Sn+ Ron_mux 2 ~0.7V Vout 1 CS CFILT Idiode_transient -10V Vin+ Buffer Amplifier Simplified Mux Model Input Low Pass Filter Figure 46. Back-to-Back Diodes Create Settling Issues Output Delta From Final Value (mV) 100 Standard Input Diode Structure Extends Settling Time 80 60 40 0.1% Settling = ±10 mV 20 0 ±20 OPA192 Input Structure Offers Fast Settling ±40 ±60 ±80 ±100 0 5 10 15 20 25 30 35 40 45 50 55 Time (s) 60 C040 Figure 47. OPA192 Protection Circuit Maintains Fast-Settling Transient Response Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 19 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com The OPA192 family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making it an optimal op amp for multichannel, high-switched, input applications. The OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting terminal of the op amp) of up to 36 V, making it suitable for use as a comparator or in applications with fast-ramping input signals, such as multiplexed data-acquisition systems, as shown in Figure 55. PHASE REVERSAL PROTECTION The OPA192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPA192 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 48. VIN + 18 V ± 5 V/div OPA192 + + ± 37 VPP ± 18 V Sine Wave (±18.5V) VOUT VOUT Time (200 s/div) C011 Figure 48. No Phase Reversal THERMAL PROTECTION Vout The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPA192 is +150°C. Exceeding this temperature causes damage to the device. The OPA192 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above +140°C. Figure 49 shows an application example for the OPA192 that will have significant self heating (+159°C) because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of +65°C the device junction temperature should reach +187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 49 depicts how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above +140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. + + - Vin 3V dc OPA192 3V Normal Operation Output High-Z 0V 150º C Iout = 30mA + 3V - Temperature - Ta= 65C Pd = 0.81W ja = 116º C/W Tj = 116º C/W x 0.81W + 65º C Tj = 159º C (expected) RL 100 +30V 140º C Figure 49. Thermal Protection 20 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 OVERLOAD RECOVERY Overload recovery is defined as the time it takes for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx192 is approximately 200 ns. GENERAL LAYOUT GUIDELINES For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to singlesupply applications. • In order to reduce parasitic coupling, run the input traces as far away from the supply lines as possible. • A ground plane helps distribute heat and reduces EMI noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. CAPACITIVE LOAD AND STABILITY The OPA192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, can directly drive up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads, as shown in Figure 50 and Figure 51. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation. 50 50 RII =N 1 kO R RFF =N 1 kO 45 G = -1 35 + ± ± + VIN ± 30 40 RISO CL ± 18 V 25 35 + VIN RL 25 RISO = 00 15 RISO = 2525 15 10 RISO = 50 50 10 20 RISO = 0 0 RISO = 25 25 RISO = 50 50 5 0 0 10p 100p 1n Capacitive Load (F) 10p 100p 1n Capacitive Load (F) C013 Figure 50. Small-Signal Overshoot vs Capacitive Load (100-mV output step) CL ± 18 V ± 30 20 5 RISO OPA192 + OPA192 Overshoot (%) Overshoot (%) 40 G = +1 + 18 V 45 + 18 V C013 Figure 51. Small-Signal Overshoot vs Capacitive Load (100-mV output step) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 21 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com For additional drive capability in unity-gain configurations, capacitive load drive can be improved by inserting a small (10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 52. This resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 52 uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results. +Vs Vout Riso + Vin Cload + ± -Vs Figure 52. Extending Capacitive Load Drive with the OPA192 Table 3. OPA192 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and Measured Results Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60° RISO (Ω) 47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7 Measured Overshoot (%) 23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6 Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2° For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU032 - Capacitive Load Drive Solution using an Isolation Resistor 22 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 APPLICATION INFORMATION TI PRECISION DESIGNS The OPA192 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. SLEW RATE LIMIT FOR INPUT PROTECTION In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages can ramp up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate) one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPA192 make it an optimal amplifier to achieve slew rate control for both dual- and single-supply systems. Figure 53 shows the OPA192 in a slew-rate limit design. Op Amp Gain Stage Slew Rate Limiter C1 470 nF R1 1.69 k VEE + VIN VEE R2 1.6 M OPA192 V+ OPA192 V+ VOUT VCC RL 10 k VCC Figure 53. Slew Rate Limiter Uses One Op Amp For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU026 - Slew Rate Limiter Uses One Op Amp Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 23 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com PRECISION REFERENCE BUFFER The OPA192 features high output current drive capability and low input offset voltage, making it an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 54, RISO, a 37.4-Ω isolation resistor, provides separation of two feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output, VOUT. Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz, while still providing a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components: RF, RFx, CF, and RISO. RF 1 k RFx 10 k CF 39 nF RISO 37.4 OPA192 V+ VOUT VREF 2.5 V CL 10 µF VCC Figure 54. Precision Reference Buffer 24 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 OPA192 OPA2192 OPA4192 www.ti.com SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 16-BIT PRECISION MULTIPLEXED DATA-ACQUISITION SYSTEM Figure 55 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. 1 2 Very Low Output Impedance Input-Filter Bandwidth ±20-V, 10-kHz Sine Wave 3 High-Impedance Inputs No Differential Input Clamps Fast Settling-Time Requirements Attenuate High-Voltage Input Signal Fast-Settling Time Requirements Stability of the Input Driver Attenuate ADC Kickback Noise VREF Output: Value and Accuracy Low Temp and Long-Term Drift Voltage Reference CH0+ OPA192 + 4 RC Filter Buffer RC Filter Reference Driver + OPA192 CH0- Gain Network OPA192 Gain Network + 4:2 Mux REFP + OPA192 + CH3+ OPA192 VINP + Antialiasing Filter SAR ADC + VINM OPA192 CH3- CONV Gain Network ±20-V, 10-kHz Sine Wave OPA140 Gain Network n 16 Bits 400 kSPS High-Voltage Level Translation VCM High-Voltage Multiplexed Input REF3240 Voltage Divider OPA350 VCM Generation Circuit Counter n Shmidtt Trigger Delay Digital Counter For Multiplexer 5 Fast logic transition Figure 55. OPA192 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage Inputs with Lowest Distortion For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU181 - 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest Distortion TINA-TI™ (Free Download Software) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 Submit Documentation Feedback 25 OPA192 OPA2192 OPA4192 SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2013) to Revision A Page • Changed first paragraph of 16-BIT PRECISION MULTIPLEXED DATA-ACQUISITION SYSTEM section ....................... 25 • Changed Figure 55 and title ............................................................................................................................................... 25 • Changed TIDU181 reference design title ........................................................................................................................... 25 26 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA192 OPA2192 OPA4192 PACKAGE OPTION ADDENDUM www.ti.com 10-Jan-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA192ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192IDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 OPA192IDBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 OPA192IDGKR PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 OPA192IDGKT PREVIEW VSSOP DGK 8 80 TBD Call TI Call TI -40 to 125 OPA192IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192 OPA192 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jan-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA192IDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA192IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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