ON NLSX5011AMUTBG 1-bit 100 mb/s configurable dual-supply level translator Datasheet

NLSX5011
1-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
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MARKING
DIAGRAMS
ULLGA6, 1.2x1.0
BMX1 SUFFIX
CASE 613AE
E
M
E
M
P
M
1
ULLGA6, 1.45x1.0
AMX1 SUFFIX
CASE 613AF
1
UDFN6, 1.2 x 1.0
MU SUFFIX
CASE 517AA
UDFN6, 1.45 x 1.0
AMU SUFFIX
CASE 517AQ
D
The NLSX5011 is a 1-bit configurable dual-supply autosensing
bidirectional level translator that does not require a direction control
pin. The I/O VCC- and I/O VL-ports are designed to track two
different power supply rails, VCC and VL respectively. Both the VCC
and the VL supply rails are configurable from 0.9 V to 4.5 V. This
allows a logic signal on the VL side to be translated to either a higher
or a lower logic signal voltage on the VCC side, and vice-versa.
The NLSX5011 offers the feature that the values of the VCC and VL
supplies are independent. Design flexibility is maximized because
VL can be set to a value either greater than or less than the VCC
supply. In contrast, the majority of competitive auto sense translators
have a restriction that the value of the VL supply must be equal to less
than (VCC - 0.4) V.
The NLSX5011 has high output current capability, which allows
the translator to drive high capacitive loads such as most high
frequency EMI filters. Another feature of the NLSX5011 is that each
I/O_VLn and I/O_VCCn channel can function as either an input or an
output.
An Output Enable (EN) input is available to reduce the power
consumption. The EN pin can be used to disable both I/O ports by
putting them in 3-state which significantly reduces the supply current
from both VCC and VL. The EN signal is referenced to the VL supply.
M
1
1
Features
• Wide VCC, VL Operating Range: 0.9 V to 4.5 V
• VL and VCC are independent
E, P, D = Specific Device Code
M = Date Code
− VL may be greater than, equal to, or less than VCC
• High 100 pF Capacitive Drive Capability
• High−Speed with 140 Mb/s Guaranteed Date Rate
•
•
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 2 of this data sheet.
for VCC, VL > 1.8 V
Low Bit−to−Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non−preferential Power−Up Sequencing
Power−Off Protection
Small packaging: ULLGA6 & UDFN6 Packages
These are Pb−Free Devices
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
Important Information
• ESD Protection for All Pins:
♦
HBM (Human Body Model) > 8000 V
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 6
1
Publication Order Number:
NLSX5011/D
NLSX5011
P
One−Shot
VL
+1.8V
R1
+3.6V
VL
+1.8 V System
I/O VL1
I/O1
I/On
GND OE
N
One−Shot
VCC
NLSX5011
VCC
+3.6 V System
I/O VCC1
I/O1
I/O VLn I/O VCCn
EN
GND
I/On
I/O VL
I/O VCC
P
One−Shot
R2
GND
N
One−Shot
Figure 1. Typical Application Circuit
2.5 V
mC
VL
VCC
Figure 2. Simplified Functional Diagram (1 I/O Line)
3.0 V
2.5 V
Peripheral
mC
1.8 V
VL
NLSX5011
GPIO
I/O VL1
ANO
EN
I/O VCC1
VCC
Peripheral
NLSX5011
GPIO
EN
GND
ANO
Figure 3. Application Example for VL < VCC
I/O VL1
EN
I/O VCC1
EN
GND
Figure 4. Application Example for VL > VCC
ORDERING INFORMATION
Device
NLSX5011AMUTBG
NLSX5011AMUTCG
NLSX5011MUTCG
Package
Shipping†
UDFN6, 1.45x1.0, 0.5P
(Pb−Free)
UDFN6, 1.2x1.0, 0.4P
(Pb−Free)
NLSX5011AMX1TCG
ULLGA6, 1.45x1.0, 0.5P
(Pb−Free)
NLSX5011BMX1TCG
ULLGA6, 1.2x1.0, 0.4P
(Pb−Free)
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2
3000 / Tape & Reel
NLSX5011
VL
EN
VCC GND
I/O VL
VL
1
6
VCC
GND
2
5
EN
I/O VL
3
4
I/O VCC
I/O VCC
ULLGA6/UDFN6
(Top View)
Figure 5. Logic Diagram
Figure 6. Pin Assignments
PIN ASSIGNMENT
Pins
FUNCTION TABLE
Description
EN
Operating Mode
VCC
VCC Input Voltage
L
Hi−Z
VL
VL Input Voltage
H
I/O Buses Connected
GND
Ground
EN
Output Enable
I/O VCCn
I/O Port, Referenced to VCC
I/O VLn
I/O Port, Referenced to VL
MAXIMUM RATINGS
Symbol
Parameter
Value
Condition
Unit
VCC
High−side DC Supply Voltage
−0.5 to +5.5
V
VL
Low−side DC Supply Voltage
−0.5 to +5.5
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.5 to +5.5
V
VI
Enable Control Pin DC Input Voltage
−0.5 to +5.5
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
ICC
DC Supply Current Through VCC
$100
mA
IL
DC Supply Current Through VL
$100
mA
IGND
DC Ground Current Through Ground Pin
$100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
High−side Positive DC Supply Voltage
0.9
4.5
V
VL
Low−side Positive DC Supply Voltage
0.9
4.5
V
VI
Enable Control Pin Voltage
GND
4.5
V
VIO
Bus Input/Output Voltage
GND
GND
4.5
4.5
V
TA
Operating Temperature Range
−55
+125
°C
0
10
ns
Dt/DV
I/O VCC
I/O VL
Input Transition Rise or Rate
VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
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NLSX5011
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
−555C to +1255C
Typ
(Note 4)
Max
Min
Max
Unit
2/3 *
VCC
−
−
2/3 *
VCC
−
V
0.9 – 4.5
−
−
1/3 *
VCC
−
1/3 *
VCC
V
0.9 – 4.5
0.9 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
TA = +25°C
0.9 – 4.5
0.9 – 4.5
2/3 *
VL
−
−
2/3 * VL
−
V
Control Pin Input LOW Voltage
TA = +25°C
0.9 – 4.5
0.9 – 4.5
−
−
1/3 *
VL
−
1/3 * VL
V
VOHC
I/O VCC Output HIGH Voltage
I/O VCC source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VCC
−
−
0.9 *
VCC
−
V
VOLC
I/O VCC Output LOW Voltage
I/O VCC sink
current = 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
VOHL
I/O VL Output HIGH Voltage
I/O VL source
current = 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 *
VL
−
−
0.9 * VL
−
V
VOLL
I/O VL Output LOW Voltage
I/O VL sink current
= 20 mA
0.9 – 4.5
0.9 – 4.5
−
−
0.2
−
0.2
V
IQVCC
VCC Supply Current
EN = VL, IO = 0 A,
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
0.9 – 4.5
0.9 – 4.5
−
−
1
−
2.5
mA
TA = +25°C,
EN = 0 V
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
0.9 – 4.5
0.9 – 4.5
−
−
0.5
−
1.5
mA
0.9 – 4.5
0.9 – 4.5
−
−
0.5
−
1.5
mA
VCC (V)
(Note 2)
VL (V)
(Note 3)
I/O VCC Input HIGH Voltage
0.9 – 4.5
0.9 – 4.5
VILC
I/O VCC Input LOW Voltage
0.9 – 4.5
VIHL
I/O VL Input HIGH Voltage
VILL
I/O VL Input LOW Voltage
VIH
Control Pin Input HIGH Voltage
VIL
Symbol
Parameter
VIHC
IQVL
ITS−VCC
VL Supply Current
VCC Tristate Output Mode
Supply Current
Test Conditions
(Note 1)
Min
ITS−VL
VL Tristate Output Mode
Supply Current
IOZ
I/O Tristate Output Mode
Leakage Current
TA = +25°C,
EN = 0V
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1.5
mA
II
Control Pin Input Current
TA = +25°C
0.9 – 4.5
0.9 – 4.5
−
−
±1
−
±1
mA
I/O VCC = 0 to 4.5V,
0
0
−
−
1
−
1.5
mA
I/O VL = 0 to 4.5 V
0.9 – 4.5
0
−
−
1
−
1.5
0
0.9 – 4.5
−
−
1
−
1.5
IOFF
Power Off Leakage Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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NLSX5011
TIMING CHARACTERISTICS
−555C to +1255C
Symbol
tR−VCC
tF−VCC
tR−VL
tF−VL
ZOVCC
ZOVL
Parameter
I/O VCC Rise Time
I/O VCC Fall Time
I/O VL Rise Time
I/O VL Fall Time
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
Min
Typ
(Note 8)
Max
Unit
CIOVCC = 15 pF
0.9 – 4.5
0.9 – 4.5
−
−
8.5
nS
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
0.9 – 4.5
0.9 – 4.5
−
−
8.5
1.8 – 4.5
1.8 – 4.5
−
−
3.5
CIOVCC = 15 pF
CIOVL = 15 pF
CIOVL = 15 pF
nS
nS
nS
I/O VCC One−Shot
Output Impedance
(Note 9)
0.9
1.8
4.5
0.9 – 4.5
−
−
−
37
20
6.0
−
−
−
W
I/O VL One−Shot Output Impedance
(Note 9)
0.9
1.8
4.5
0.9 – 4.5
−
−
−
37
20
6.0
−
−
−
W
CIOVCC = 15 pF
0.9 – 4.5
0.9 – 4.5
−
−
35
nS
1.8 – 4.5
1.8 – 4.5
−
−
10
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
1.0 – 4.5
1.0 – 4.5
−
−
37
1.8 – 4.5
1.8 – 4.5
−
−
11
1.2 – 4.5
1.2 – 4.5
−
−
40
1.8 – 4.5
1.8 – 4.5
−
−
13
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
0.9 – 4.5
0.9 – 4.5
−
−
35
1.8 – 4.5
1.8 – 4.5
−
−
10
1.0 – 4.5
1.0 – 4.5
−
−
37
1.8 – 4.5
1.8 – 4.5
−
−
11
1.2 – 4.5
1.2 – 4.5
−
−
40
1.8 – 4.5
1.8 – 4.5
−
−
13
tPD_VL−VCC Propagation Delay
(Driving I/O VCC)
CIOVCC = 30 pF
CIOVCC = 50 pF
CIOVCC = 100 pF
tPD_VCC−VL Propagation Delay
(Driving I/O VL)
CIOVL = 15 pF
CIOVL = 30 pF
CIOVL = 50 pF
CIOVL = 100 pF
nS
tSK
Channel−to−Channel
Skew
CIOVCC = 15 pF, CIOVL = 15 pF
(Note 9)
0.9 – 4.5
0.9 – 4.5
−
−
0.15
nS
IIN_PEAK
Input Driver Maximum
Peak Current
EN = VL;
I/O_VCC = 1 MHz Square Wave,
Amplitude = VCC, or
I/O_VL = 1 MHz Square Wave,
Amplitude = VL (Note 9)
0.9 – 4.5
0.9 – 4.5
−
−
5.0
mA
Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
9. Guaranteed by design.
5.
6.
7.
8.
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5
NLSX5011
TIMING CHARACTERISTICS (continued)
−555C to +1255C
Symbol
tEN−VCC
tEN−VL
I/O_VCC Output Enable Time
I/O_VL Output Enable Time
tDIS−VCC I/O_VCC Output Disable Time
tDIS−VL
MDR
Test Conditions
(Note 10)
VCC (V)
(Note 11)
VL (V)
(Note 12)
Min
Typ
(Note 13)
Max
Unit
tPZH
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
160
nS
tPZL
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPZH
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
160
tPZL
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
130
tPHZ
CIOVCC = 15 pF,
I/O_VL = VL
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVCC = 15 pF,
I/O_VL = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
tPHZ
CIOVL = 15 pF,
I/O_VCC = VCC
0.9 – 4.5
0.9 – 4.5
−
−
210
tPLZ
CIOVL = 15 pF,
I/O_VCC = 0 V
0.9 – 4.5
0.9 – 4.5
−
−
175
CIO = 15 pF
0.9 – 4.5
0.9 – 4.5
50
−
−
1.8 – 4.5
1.8 – 4.5
140
−
−
0.9 – 4.5
0.9 – 4.5
40
−
−
1.8 – 4.5
1.8 – 4.5
120
−
−
1.0 – 4.5
1.0 – 4.5
30
−
−
1.8 – 4.5
1.8 – 4.5
100
−
−
1.2 – 4.5
1.2 – 4.5
20
−
−
1.8 – 4.5
1.8 – 4.5
60
−
−
Parameter
I/O_VL Output Disable Time
Maximum Data Rate
CIO = 30 pF
CIO = 50 pF
CIO = 100 pF
nS
nS
nS
mbps
10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
13. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
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NLSX5011
DYNAMIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
CPD_VCC
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
Test Conditions
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
CLoad = 0, f = 1 MHz,
EN = VL (outputs enabled)
VCC (V)
(Note 14)
VL (V)
(Note 15)
Typ
(Note 16)
Unit
0.9
4.5
39
pF
1.5
1.8
20
1.8
1.5
17
1.8
1.8
14
1.8
2.8
13
2.5
2.5
14
2.8
1.8
13
4.5
0.9
19
0.9
4.5
37
1.5
1.8
30
1.8
1.5
29
1.8
1.8
29
1.8
2.8
29
2.5
2.5
30
2.8
1.8
29
4.5
0.9
19
0.9
4.5
29
1.5
1.8
29
1.8
1.5
29
1.8
1.8
29
1.8
2.8
29
2.5
2.5
30
2.8
1.8
29
4.5
0.9
35
0.9
4.5
21
1.5
1.8
18
1.8
1.5
18
1.8
1.8
14
1.8
2.8
13
2.5
2.5
14
2.8
1.8
13
4.5
0.9
30
pF
pF
pF
14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
16. Typical values are at TA = +25°C.
17. CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the
VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC
+ ICC VL and NSW = total number of outputs switching.
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NLSX5011
STATIC POWER CONSUMPTION (TA = +25°C)
Symbol
Parameter
CPD_VL
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
CPD_VCC
VL = Input port,
VCC = Output Port
VCC = Input port,
VL = Output Port
Test Conditions
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
CLoad = 0, f = 1 MHz,
EN = GND (outputs disabled)
VCC (V)
(Note 18)
VL (V)
(Note 19)
Typ
(Note 20)
Unit
0.9
4.5
0.01
pF
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
0.9
4.5
0.01
1.5
1.8
0.01
1.8
1.5
0.01
1.8
1.8
0.01
1.8
2.8
0.01
2.5
2.5
0.01
2.8
1.8
0.01
4.5
0.9
0.01
18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
20. Typical values are at TA = +25°C
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pF
pF
pF
NLSX5011
NLSX5011
VL
VCC
NLSX5011
VL
EN
VCC
EN
I/O VL
I/O VL
I/O VCC
Source
I/O VCC
CIOVL
CIOVCC
Source
tRISE/FALL v
3 ns
I/O VL
90%
50%
10%
tRISE/FALL v 3 ns
I/O VCC
90%
50%
10%
tPD_VL−VCC
I/O VCC
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 7. Driving I/O VL Test Circuit and Timing
tR−VL
Figure 8. Driving I/O VCC Test Circuit and Timing
VCC
2xVCC
OPEN
R1
PULSE
GENERATOR
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 9. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
EN
VCC
90%
50%
10%
GND
GND
tPZL
tPHL
90%
50%
10%
tR
VL
50%
Output
Output
HIGH
IMPEDANCE
50%
tPZH
tF
tPLZ
tPHZ
10%
VOL
90%
VOH
50%
Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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9
HIGH
IMPEDANCE
NLSX5011
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
VL pins to a high impedance state. Normal translation
operation occurs when the EN pin is equal to a logic high
signal. The EN pin is referenced to the VL supply and has
Over−Voltage Tolerant (OVT) protection.
The NLSX5011 auto−sense translator provides
bi−directional logic voltage level shifting to transfer data
in multiple supply voltage systems. These level translators
have two supply voltages, VL and VCC, which set the logic
levels on the input and output sides of the translator. When
used to transfer data from the I/O VL to the I/O VCC ports,
input signals referenced to the VL supply are translated to
output signals with a logic level matched to VCC. In a
similar manner, the I/O VCC to I/O VL translation shifts
input signals with a logic level compatible to VCC to an
output signal matched to VL.
The NLSX5011 translator consists of bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. One−shot
circuits are used to detect the rising or falling input signals.
In addition, the one−shots decrease the rise and fall times
of the output signal for high−to−low and low−to−high
transitions.
Uni−Directional versus Bi−Directional Translation
The NLSX5011 translator can function as a
non−inverting uni−directional translator. One advantage of
using the translator as a uni−directional device is that each
I/O pin can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
The values of the VL and VCC supplies can be set to
anywhere between 0.9 and 4.5 V. Design flexibility is
maximized because VL may be either greater than or less
than the VCC supply. In contrast, the majority of the
competitive auto sense translators has a restriction that the
value of the VL supply must be equal to less than (VCC −
0.4) V.
The sequencing of the power supplies will not damage
the device during power−up operation. In addition, the I/O
VCC and I/O VL pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 to 0.1 mF decoupling capacitors should
be used on the VL and VCC power supply pins. Ceramic
capacitors are a good design choice to filter and bypass any
noise signals on the voltage lines to the ground plane of the
PCB. The noise immunity will be maximized by placing
the capacitors as close as possible to the supply and ground
pins, along with minimizing the PCB connection traces.
The NLSX5011 translators have a power down feature
that provides design flexibility. The output ports are
disabled when either power supply is off (VL or VCC = 0 V).
This feature causes all of the I/O pins to be in the power
saving high impedance state.
Input Driver Requirements
Auto−sense translators such as the NLSX5011 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent in the opposite direction. For
proper operation, the input driver to the auto−sense
translator should be capable of driving 2 mA of peak output
current. The bi−directional configuration of the translator
results in both input stages being active for a very short time
period. Although the peak current from the input signal
circuit is relatively large, the average current is small and
consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5011 translator has an Enable pin (EN) that
provides tri−state operation at the I/O pins. Driving the
Enable pin to a low logic level minimizes the power
consumption of the device and drives the I/O VCC and I/O
www.onsemi.com
10
NLSX5011
PACKAGE DIMENSIONS
UDFN6 1.2 x 1.0, 0.4P
CASE 517AA
ISSUE D
EDGE OF PACKAGE
PIN ONE
REFERENCE
2X
0.10 C
ÏÏ
ÏÏ
ÏÏ
L1
E
DETAIL A
Bottom View
(Optional)
TOP VIEW
2X
EXPOSED Cu
0.10 C
(A3)
0.10 C
A1
A
10X
0.08 C
ÏÏÏ
ÏÏÏ
A3
DETAIL B
Side View
(Optional)
5X
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.20 BSC
1.00 BSC
0.40 BSC
0.30
0.40
0.00
0.15
0.40
0.50
MOUNTING FOOTPRINT*
6X
C
A1
DIM
A
A1
A3
b
D
E
e
L
L1
L2
MOLD CMPD
SEATING
PLANE
SIDE VIEW
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
D
6X
0.42
0.22
L
3
L2
6X
b
0.10 C A B
0.05 C
6
4
0.40
PITCH
e
NOTE 3
1.07
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
NLSX5011
PACKAGE DIMENSIONS
UDFN6 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
A
B
D
L
L
L1
PIN ONE
REFERENCE
0.10 C
ÏÏÏ
ÏÏÏ
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
DETAIL B
MOLD CMPD
DETAIL B
0.05 C
6X
DIM
A
A1
A2
b
D
E
e
L
L1
ÏÏ
ÏÏ
EXPOSED Cu
TOP VIEW
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
OPTIONAL
CONSTRUCTIONS
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.07 REF
0.20
0.30
1.45 BSC
1.00 BSC
0.50 BSC
0.30
0.40
−−−
0.15
MOUNTING FOOTPRINT
0.05 C
A1
A2
SIDE VIEW
C
SEATING
PLANE
6X
0.30
PACKAGE
OUTLINE
e
6X
L
1.24
3
1
DETAIL A
6X
0.53
6
4
BOTTOM VIEW
6X
0.50
PITCH
DIMENSIONS: MILLIMETERS
b
0.10 C A B
0.05 C
1
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
12
NLSX5011
PACKAGE DIMENSIONS
ULLGA6 1.2 x 1.0, 0.4P
CASE 613AE
ISSUE A
PIN ONE
REFERENCE
0.10 C
ÏÏÏ
ÏÏÏ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
A
B
D
E
DIM
A
A1
b
D
E
e
L
L1
TOP VIEW
0.05 C
A
6X
0.05 C
SEATING
PLANE
SIDE VIEW
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
C
A1
MILLIMETERS
MIN
MAX
−−−
0.40
0.00
0.05
0.15
0.25
1.20 BSC
1.00 BSC
0.40 BSC
0.25
0.35
0.35
0.45
5X
0.49
e
5X
L
6X
0.26
NOTE 4
3
1
1.24
L1
6
4
0.53
6X
b
0.10 C A B
BOTTOM VIEW
0.05 C
1
PKG
OUTLINE
0.40
PITCH
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
NLSX5011
PACKAGE DIMENSIONS
ULLGA6 1.45 x 1.0, 0.5P
CASE 613AF
ISSUE A
PIN ONE
REFERENCE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
A
B
D
ÏÏÏ
ÏÏÏ
ÏÏÏ
E
DIM
A
A1
b
D
E
e
L
L1
TOP VIEW
0.10 C
0.05 C
MILLIMETERS
MIN
MAX
−−−
0.40
0.00
0.05
0.15
0.25
1.45 BSC
1.00 BSC
0.50 BSC
0.25
0.35
0.30
0.40
A
6X
0.05 C
SEATING
PLANE
SIDE VIEW
A1
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
C
5X
0.49
e
5X
L
6X
0.30
NOTE 4
3
1
L1
1.24
6
4
6X
BOTTOM VIEW
0.53
b
0.10 C A B
0.05 C
1
PKG
OUTLINE
0.50
PITCH
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NLSX5011/D