REJ09B0050-0500
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2368 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2300 Series
H8S/2368F
H8S/2367F
H8S/2365
H8S/2364F
H8S/2363
H8S/2362F
H8S/2361F
H8S/2360F
Rev. 5.00
Revision Date: Aug 02, 2006
HD64F2368
HD64F2367
HD6432365
HD64F2364
HD6412363
HD64F2362
HD64F2361
HD64F2360
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 5.00 Aug 02, 2006 page ii of liv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 5.00 Aug 02, 2006 page iii of liv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Main Revisions in this Edition
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
5. Contents
6. Overview
7. Description of Functional Modules
•
•
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
11. Index
Rev. 5.00 Aug 02, 2006 page iv of liv
Preface
The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing
Renesas Technology’s original architecture as their cores, and the peripheral functions required to
configure a system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with direct memory access controller (DMAC) and data transfer controller
(DTC) bus masters, ROM and RAM, a 16-bit timer pulse unit (TPU), a programmable pulse
generator (PPG), 8-bit timers (TMR), a watchdog timer (WDT), serial communication interfaces
(SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip
peripheral modules required for system configuration. I2C bus interface 2 (IIC2) can also be
included as an optional interface.
A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM
and other kinds of memory.
A single-power flash memory (F-ZTAT) version is available for this LSI's ROM. This provides
flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of
mass production to full-scale mass production. This is particularly applicable to application
devices with specifications that will most probably change.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2368 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2368 Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed
description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 5.00 Aug 02, 2006 page v of liv
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
For the execution state of each instruction in this LSI, see appendix D, Bus State during
Execution of Instructions.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 24,
List of Registers.
Examples:
Related Manuals:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation:
Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx
Signal notation:
An overbar is added to a low-active signal: xxxx
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8S/2368 Group manuals:
Document Title
Document No.
H8S/2368 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Software Manual
REJ09B0139
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage
Editor User's Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger User's Manual
REJ10B0211
H8S, H8/300 Series High-performance Embedded Workshop, Tutorial
ADE-702-231
High-performance Embedded Workshop User's Manual
REJ10J0886
Rev. 5.00 Aug 02, 2006 page vi of liv
Main Revisions in This Edition
Item
Page
Revision (See Manual for Details)
All
HD64F2364, HD64F2361, and HD64F2360 added
HD64F2366 (H8S/2366F) deleted
1.1 Features
2
Table amended
ROM Type
Model
Flash memory version HD64F2368F
RAM
Remarks
32 kbytes
H8S/2368
0.18 µm F-ZTAT Grou
HD64F2367F
384 kbytes
24 kbytes
HD64F2364
384 kbytes
32 kbytes
H8S/2368
0.18 µm F-ZTAT Grou
HD64F2362F
256 kbytes
32 kbytes
H8S/2368
0.18 µm F-ZTAT Grou
HD64F2361
256 kbytes
24 kbytes
H8S/2368
0.18 µm F-ZTAT Grou
HD64F2360
256 kbytes
16 kbytes
H8S/2368
0.18 µm F-ZTAT Grou
Masked ROM version HD6432365
256 kbytes
16 kbytes
ROMless version
2
ROM
512 kbytes
•
HD6412363
16 kbytes
Compact package
Note 2 amended
Note: 2. Not supported by the H8S/2368 0.18 µm F-ZTAT
Group.
1.2 Block Diagram
4
Figure title amended
6
Figure title amended
Figure 1.2 Internal Block
Diagram of H8S/2368 0.18
µm F-ZTAT Group
1.3.1 Pin Arrangement
Figure 1.4 Pin
Arrangement of H8S/2368
0.18 µm F-ZTAT Group
Figure 1.5 Pin
7
Arrangement of H8S/2367,
H8S/2365, and H8S/2363
Note amended
1.3.2 Pin Arrangement
in Each Operating Mode
Notes 1 and 2 amended
Table 1.1 Pin
Arrangement in Each
Operating Mode
13
Note: FP-128B is not supported by the H8S/2368 0.18 µm FZTAT Group.
Notes: 1. Not supported by the H8S/2368 0.18 µm F-ZTAT
Group.
2. Used as the VCL pin in the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page vii of liv
Item
Page
Revision (See Manual for Details)
1.3.3 Pin Functions
14
Table 1.2 amended
Table 1.2 Pin Functions
... The pin 33 of TFP-120, which is used as the VCL pin in the
H8S/2368 0.18 µm F-ZTAT Group, should not be connected to
the power supply. ...
20
Note * amended
Note: * Not supported by the H8S/2368 0.18 µm F-ZTAT
Group.
3.1 Operating Mode
Selection
57
Description amended
... Modes 1 to 5 and 7 are available in the H8S/2368 0.18 µm FZTAT Group flash memory version. …
Table 3.1 MCU
57
Operating Mode Selection
Note * amended
3.2.2 System Control
Register (SYSCR)
59
Note * deleted from EXPE description
3.3.5 Mode 5
61
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
(Before) ... In mode 3* and 7 ... → (After) ... In mode 3 and 7 ...
Description amended
... Mode 5 is only available in the H8S/2368 0.18 µm F-ZTAT
Group.
3.3.7 Pin Functions
62
Note: 3. Mode 5 is available only in the H8S/2368 0.18 µm FZTAT Group.
Table 3.2 Pin Functions
in Each Operating Mode
3.4 Memory Map in
Each Operating Mode
Note 3 amended
63
Figure 3.1 amended
4
Reserved area*
Figure 3.1 H8S/2368F
Memory Map (2)
Figure 3.6 H8S/2364F
Memory Map (2)
68
Figure 3.8 added
Figure 3.9 H8S/2361F
Memory Map (1)
71
Figure 3.11 added
Figure 3.10 H8S/2361F
Memory Map (2)
72
Figure 3.12 added
Figure 3.11 H8S/2360F
Memory Map (1)
73
Figure 3.13 added
Figure 3.12 H8S/2360F
Memory Map (2)
74
Figure 3.14 added
Rev. 5.00 Aug 02, 2006 page viii of liv
Item
Page
Revision (See Manual for Details)
8.2.7 DTC Enable
Registers A to G
(DTCERA to DTCERG)
299
Table amended
… These bits are not automatically cleared when the DISEL bit
is 0 …
• When 0 is written to the DTCE bit after reading DTCE=1.
14.3.9 Bit Rate Register 565,
(BRR)
566
Table 14.3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
Table 14.3 amended
Operating Frequency
8
Bit Rate
(bit/s)
n
Error
(%)
N
(MHz)
9.8304
n
10
Error
(%)
N
n
N
n
N
Error
(%)
0.16
9600
0
25
0.16
0
31
0.00
0
32
–1.38
0
38
19200
0
12
0.16
0
15
0.00
0
15
1.70
0
19
–2.40
31250
0
7
0.00
0
9
–1.73
0
9
0.00
0
11
0.00
38400
—
—
—
0
7
0.00
0
7
1.70
0
9
–2.40
Operating Frequency
12.288
Bit Rate
(bit/s)
n
14
N
Error
(%)
n
(MHz)
14.7456
N
Error
(%)
n
16
N
Error
(%)
n
N
Error
(%)
0.03
110
2
217
0.08
2
248
–0.17
3
64
0.69
3
70
9600
0
39
0.00
0
45
–0.94
0
47
0.00
0
51
0.16
19200
0
19
0.00
0
22
–0.94
0
23
0.00
0
25
0.16
31250
0
11
2.34
0
13
0.00
0
14
–1.73
0
15
0.00
Operating Frequency
17.2032
18
N
Error
(%)
n
0
27
0.00
0
16
1.20
0
13
0.00
Bit Rate
(bit/s)
n
19200
31250
38400
n
110
150
300
20
N
n
N
Error
(%)
0
28
1.01
0
31
0.00
0
32
–1.38
0
17
0.00
0
19
–1.73
0
19
0.00
0
14
–2.40
0
15
0.00
0
15
1.70
Operating Frequency
Bit Rate
(bit/s)
(MHz)
19.6608
Error
(%)
25
566
12
Error
(%)
N
Error
(%)
n
N
Error
(%)
3
145
0.33
3
150
–0.05
3
106
0.39
3
110
–0.29
2
214
–0.07
2
220
0.16
N
n
3
132
0.13
3
97
–0.35
2
194
0.16
n
3
110
–0.02
3
80
0.47
2
162
–0.15
Error
(%)
34*
33
Error
(%)
N
N
(MHz)
30
Error
(%)
n
600
2
80
0.47
2
97
–0.35
2
106
0.39
2
110
–0.29
1200
1
162
–0.15
1
194
0.16
1
214
–0.07
1
220
0.16
2400
1
80
0.47
1
97
–0.35
1
106
0.39
1
110
–0.29
4800
0
162
–0.15
0
194
0.16
0
214
–0.07
0
220
0.16
–0.29
9600
0
80
0.47
0
97
–0.35
0
106
0.39
0
110
19200
0
40
–0.76
0
48
–0.35
0
53
–0.54
0
54
0.61
31250
0
24
0.00
0
29
0
0
32
0
0
33
0.00
38400
0
19
1.70
0
23
1.70
0
26
–0.54
0
27
–1.20
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page ix of liv
Item
Page
14.3.9 Bit Rate Register 567
(BRR)
Table 14.4 Maximum Bit
Rate for Each Frequency
(Asynchronous Mode)
Revision (See Manual for Details)
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Table 14.5 Maximum Bit 568
Rate for Each Frequency
(Asynchronous Mode)
Note * amended
Table 14.6 BRR Settings 569
for Various Bit Rates
(Clocked Synchronous
Mode)
Note 1 amended
Table 14.7 Maximum Bit 570
Rate with External Clock
Input (Clocked
Synchronous Mode)
Note * amended
Table 14.8 Examples of 571
Bit Rate for Various BRR
Settings (Smart Card
Interface Mode) (when n =
0 and S = 372)
Note * amended
Table 14.9 Maximum Bit 572
Rate at Various
Frequencies (Smart Card
Interface Mode) (when S =
372)
Note * amended
14.8 IrDA Operation
Note * amended
618
2
Table 15.2 Transfer Rate
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Table 14.12 Settings of
Bits IrCKS2 to IrCKS0
15.3.1 I C Bus Control
Register A (ICCRA)
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
634
Note 1 amended
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page x of liv
Item
Page
Revision (See Manual for Details)
19.1 Features
689
Description of "• Flash and memory emulation by RAM" deleted
Figure 19.1 amended
Module bus
Figure 19.1 Block
690
Diagram of Flash Memory
FLMCR1
FLMCR2
EBR1
EBR2
SYSCR
19.2 Mode Transitions
692
Table19.1 Differences
between Boot Mode and
User Program Mode
19.5 Register
Descriptions
Table19.1 amended
Boot Mode
Programming control program*
User Program Mode
Program/program-verify Erase/erase-verify/program/
program-verify
697
"• RAM emulation register (RAMER)" deleted
"RAM Emulation Register (RAMER)" description deleted
"Flash Memory Emulation in RAM" description deleted
19.8.2 Software
Protection
710
Description amended
19.11 Usage Notes
712
… SWE bit in FLMCR 1 to 0. When protection is in effect …
Description amended
… on-board programming mode, and programmer mode …
4. … during programming, erasing, or verifying.
5. Do not use ...
Rev. 5.00 Aug 02, 2006 page xi of liv
Item
Page
Revision (See Manual for Details)
20.1 Features
717
Table amended
Product Classification
ROM Size
ROM Address
H8S/2368F
HD64F2368
512 kbytes
H'000000 to H'07FFFF
(Modes 3 to 5 and 7)
H8S/2364F
HD64F2364
384 kbytes
H'000000 to H'05FFFF
(Modes 3 to 5 and 7)
H8S/2362F
HD64F2362
256 kbytes
H8S/2361F
HD64F2361
H'000000 to H'03FFFF
(Modes 3 to 5 and 7)
H8S/2360F
HD64F2360
Description amended
•
The flash-memory MATs according to LSI initiation mode
The user memory MAT ... in user mode: 512 kbytes
(H8S/2368F), 384 kbytes (H8S/2364F), 256 kbytes
(H8S/2362F, H8S/2361F, H8S/2360F) …
Figure 20.1 Block
719
Diagram of Flash Memory
Figure 20.1 amended
User MAT: 512 kbytes*
Note * added
Note: * 384 kbytes, 256 kbytes
20.1.3 Flash MAT
Configuration
722
Description amended
Figure 20.3 Flash
Memory Configuration
722
Figure 20.3 replaced
20.1.3 Block Division
723
Figure 20.4 replaced
739
(2) Programming/Erasing Initialization
This LSI’s flash memory is configured by the 256-kbyte/384kbyte/512-kbyte user MAT ...
Figure 20.4 Block
Division of User MAT
20.3.2
Programming/Erasing
Interface Parameter
(b) Flash user branch address setting parameter (FUBRA:
general register ER1 of CPU)
UA31 to UA0 description amended
Likewise, ... programming/erase interface register during user
branched processing. ...
Rev. 5.00 Aug 02, 2006 page xii of liv
Item
Page
Revision (See Manual for Details)
20.3.2
Programming/Erasing
Interface Parameter
744
(4) Erasure Execution
(a) Flash erase block select parameter (FEBS: general register
ER0 of CPU)
EBN7 to 0 description amended
Note: * For the H8S/2362F, H8S/2361F, and H8S/2360F
choose a setting value within the range from H'00 to H'0B.
For the H8S/2364F, choose a setting value within the range
from H'00 to H'0D.
20.4.2 User Program
Mode
754
Figure 20.10 amended
Address RAMTOP (H'FF4000/ H'FF6000/ H'FF8000)
Figure 20.10 RAM Map
when
Programming/Erasing Is
Executed
758
(2) Programming Procedure in User Program Mode
Description amended
6. … FPEFEQ parameter is 8 MHz to 8 MHz to 34 MHz. When
...
20.8 Serial
790
Communication Interface
Specification for Boot
Mode
(4) Inquiry and Selection States
(e) Multiplication Ratio Inquiry
Description amended
•
Multiplication ratio (one byte): The value ...
Division ratio: Not supported by the H8S/2368F 0.18 µmFZTAT Group.
20.9 Usage Notes
810
Usage note added
6. User Branch Processing Start Intervals
22.2.1 Connecting a
Crystal Oscillator
816
Note: * In the H8S/2368 0.18 µm F-ZTAT Group, CL1 = CL2 = 10
pF.
Figure 22.2 Connection
of Crystal Oscillator
(Example)
22.5.1 Notes on Clock
Pulse Generator
819
23.2.3 Software Standby 832
Mode
Table 23.2 Oscillation
Stabilization Time Settings
Note * amended
Note * amended
Note: * 34 MHz for the H8S/2368 0.18 µm F-ZTAT Group
Note 2 amended
Note: 2. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page xiii of liv
Item
Page
Revision (See Manual for Details)
23.2.4 Hardware Standby 835
Mode
Description amended
24.1 Register Addresses 843
(Address Order)
849
RAMER description deleted from table
Hardware Standby Mode Timing when Power Is Supplied (Only
H8S/2368 0.18 µm F-ZTAT Group):
Notes 3 and 4 amended
Notes: 3. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
4. Cannot be accessed by other than H8S/2368 0.18 µm FZTAT Group.
24.2 Register Bits
855
RAMER description deleted from table
862
Note 7 amended
Note: 7. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
24.3 Register States in
Each Operating Mode
866
RAMER description deleted from table
872
Note * amended
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
25.3.6 Flash Memory
Characteristics
Table 25.38 Flash
Memory Characteristics
(0.18-µm F-ZTAT Version)
939
Table 25.38 amended
Item
Min.
Typ.
Max.
Unit
1 2 4
Programming time* * *
1
10
ms/
128 bytes
1 2 4
Erase time* * *
250
1500
ms/
4 kbytes
500
4000
ms/
32 kbytes
750
6500
ms/
64 kbytes
2
6
s/256 kbytes
3
9
s/384 kbytes
4
12
s/512 kbytes
1 2 4
Erase time (total)* * *
7
20
s/All blocks
Programming and erase time
1 2 4
(total)* * *
9
26
s/256 kbytes
10
29
s/384 kbytes
11
32
s/512 kbytes
1 2 4
Programming time (total)* * *
Rev. 5.00 Aug 02, 2006 page xiv of liv
Item
Page
Revision (See Manual for Details)
B. Product Lineup
949
Table replaced
Note 1 amended
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT
Group.
Rev. 5.00 Aug 02, 2006 page xv of liv
Rev. 5.00 Aug 02, 2006 page xvi of liv
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Features ............................................................................................................................. 1
Block Diagram .................................................................................................................. 3
Pin Description.................................................................................................................. 5
1.3.1 Pin Arrangement .................................................................................................. 5
1.3.2 Pin Arrangement in Each Operating Mode .......................................................... 8
1.3.3 Pin Functions ....................................................................................................... 14
Section 2 CPU ...................................................................................................................... 21
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features .............................................................................................................................
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................
2.1.2 Differences from H8/300 CPU ............................................................................
2.1.3 Differences from H8/300H CPU..........................................................................
CPU Operating Modes ......................................................................................................
2.2.1 Normal Mode .......................................................................................................
2.2.2 Advanced Mode ...................................................................................................
Address Space ...................................................................................................................
Register Configuration ......................................................................................................
2.4.1 General Registers .................................................................................................
2.4.2 Program Counter (PC) .........................................................................................
2.4.3 Extended Control Register (EXR) .......................................................................
2.4.4 Condition-Code Register (CCR) ..........................................................................
2.4.5 Initial Register Values..........................................................................................
Data Formats .....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Table of Instructions Classified by Function .......................................................
2.6.2 Basic Instruction Formats ....................................................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Register Direct—Rn.............................................................................................
2.7.2 Register Indirect—@ERn ....................................................................................
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)..............
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn ..
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 .................................................................
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................
21
22
23
23
24
24
26
28
29
30
31
31
32
34
34
34
36
37
38
47
49
49
49
50
50
50
51
51
Rev. 5.00 Aug 02, 2006 page xvii of liv
2.8
2.9
2.7.8 Memory Indirect—@@aa:8 ................................................................................
2.7.9 Effective Address Calculation .............................................................................
Processing States...............................................................................................................
Usage Note........................................................................................................................
2.9.1 Note on Bit Manipulation Instructions.................................................................
51
52
55
56
56
Section 3 MCU Operating Modes .................................................................................. 57
3.1
3.2
3.3
3.4
Operating Mode Selection.................................................................................................
Register Descriptions ........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR) ......................................................................
Operating Mode Descriptions ...........................................................................................
3.3.1 Mode 1 .................................................................................................................
3.3.2 Mode 2 .................................................................................................................
3.3.3 Mode 3 .................................................................................................................
3.3.4 Mode 4 .................................................................................................................
3.3.5 Mode 5 .................................................................................................................
3.3.6 Mode 7 .................................................................................................................
3.3.7 Pin Functions .......................................................................................................
Memory Map in Each Operating Mode ............................................................................
57
58
58
58
60
60
60
60
60
61
61
62
63
Section 4 Exception Handling ......................................................................................... 79
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Exception Handling Types and Priority ............................................................................
Exception Sources and Exception Vector Table ...............................................................
Reset .................................................................................................................................
4.3.1 Reset Exception Handling....................................................................................
4.3.2 Interrupts after Reset............................................................................................
4.3.3 On-Chip Peripheral Functions after Reset Release ..............................................
Traces................................................................................................................................
Interrupts ...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Usage Notes ......................................................................................................................
79
79
81
81
83
83
84
84
85
86
87
Section 5 Interrupt Controller .......................................................................................... 89
5.1
5.2
5.3
Features .............................................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
5.3.1 Interrupt Control Register (INTCR) ....................................................................
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................
Rev. 5.00 Aug 02, 2006 page xviii of liv
89
91
91
92
93
5.4
5.6
5.7
5.3.3 IRQ Enable Register (IER) ..................................................................................
5.3.4 IRQ Sense Control Register L (ISCRL)...............................................................
5.3.5 IRQ Status Register (ISR)....................................................................................
5.3.6 IRQ Pin Select Register (ITSR) ...........................................................................
5.3.7 Software Standby Release IRQ Enable Register (SSIER) ...................................
Interrupt Sources ...............................................................................................................
5.4.1 External Interrupts................................................................................................
5.4.2 Internal Interrupts.................................................................................................
Interrupt Control Modes and Interrupt Operation .............................................................
5.6.1 Interrupt Control Mode 0 .....................................................................................
5.6.2 Interrupt Control Mode 2 .....................................................................................
5.6.3 Interrupt Exception Handling Sequence ..............................................................
5.6.4 Interrupt Response Times ....................................................................................
5.6.5 DTC and DMAC Activation by Interrupt ............................................................
Usage Notes ......................................................................................................................
5.7.1 Contention between Interrupt Generation and Disabling.....................................
5.7.2 Instructions that Disable Interrupts ......................................................................
5.7.3 Times when Interrupts are Disabled ....................................................................
5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................
5.7.6 Note on IRQ Status Register (ISR) ......................................................................
95
96
99
100
101
101
101
102
108
108
110
112
114
115
116
116
117
117
117
117
118
Section 6 Bus Controller (BSC) ...................................................................................... 119
6.1
6.2
6.3
Features ............................................................................................................................. 119
Input/Output Pins .............................................................................................................. 121
Register Descriptions ........................................................................................................ 122
6.3.1 Bus Width Control Register (ABWCR)............................................................... 123
6.3.2 Access State Control Register (ASTCR) .............................................................123
6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,
WTCRBH, and WTCRBL).................................................................................. 124
6.3.4 Read Strobe Timing Control Register (RDNCR)................................................. 129
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 130
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1
Burst ROM Interface Control Register (BROMCRL) ......................................... 132
6.3.7 Bus Control Register (BCR) ................................................................................ 133
6.3.8 DRAM Control Register (DRAMCR) ................................................................. 135
6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 140
6.3.10 Refresh Control Register (REFCR) ..................................................................... 141
6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 144
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 144
Rev. 5.00 Aug 02, 2006 page xix of liv
6.4
Operation ..........................................................................................................................
6.4.1 Area Division.......................................................................................................
6.4.2 Bus Specifications................................................................................................
6.4.3 Memory Interfaces ...............................................................................................
6.4.4 Chip Select Signals ..............................................................................................
6.5 Basic Bus Interface ...........................................................................................................
6.5.1 Data Size and Data Alignment.............................................................................
6.5.2 Valid Strobes........................................................................................................
6.5.3 Basic Timing........................................................................................................
6.5.4 Wait Control ........................................................................................................
6.5.5 Read Strobe (RD) Timing ....................................................................................
6.5.6 Extension of Chip Select (CS) Assertion Period..................................................
6.6 DRAM Interface ...............................................................................................................
6.6.1 Setting DRAM Space...........................................................................................
6.6.2 Address Multiplexing...........................................................................................
6.6.3 Data Bus...............................................................................................................
6.6.4 Pins Used for DRAM Interface............................................................................
6.6.5 Basic Timing........................................................................................................
6.6.6 Column Address Output Cycle Control ...............................................................
6.6.7 Row Address Output State Control......................................................................
6.6.8 Precharge State Control .......................................................................................
6.6.9 Wait Control ........................................................................................................
6.6.10 Byte Access Control ............................................................................................
6.6.11 Burst Operation....................................................................................................
6.6.12 Refresh Control....................................................................................................
6.6.13 DMAC Single Address Transfer Mode and DRAM Interface.............................
6.7 Burst ROM Interface.........................................................................................................
6.7.1 Basic Timing........................................................................................................
6.7.2 Wait Control ........................................................................................................
6.7.3 Write Access ........................................................................................................
6.8 Idle Cycle ..........................................................................................................................
6.8.1 Operation .............................................................................................................
6.8.2 Pin States in Idle Cycle ........................................................................................
6.9 Write Data Buffer Function ..............................................................................................
6.10 Bus Release.......................................................................................................................
6.10.1 Operation .............................................................................................................
6.10.2 Pin States in External Bus Released State............................................................
6.10.3 Transition Timing ................................................................................................
6.11 Bus Arbitration..................................................................................................................
6.11.1 Operation .............................................................................................................
Rev. 5.00 Aug 02, 2006 page xx of liv
144
144
146
148
149
150
150
152
153
161
162
163
165
165
165
166
167
168
169
170
172
173
176
177
182
187
190
190
192
192
193
193
204
204
206
206
207
208
209
209
6.11.2 Bus Transfer Timing ............................................................................................
6.12 Bus Controller Operation in Reset ....................................................................................
6.13 Usage Notes ......................................................................................................................
6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............
6.13.2 External Bus Release Function and Software Standby ........................................
6.13.3 External Bus Release Function and CBR Refreshing ..........................................
6.13.4 BREQO Output Timing .......................................................................................
210
211
211
211
211
211
212
Section 7 DMA Controller (DMAC) ............................................................................. 213
7.1
7.2
7.3
7.4
7.5
Features .............................................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
7.3.1 Memory Address Registers (MARA and MARB) ...............................................
7.3.2 I/O Address Registers (IOARA and IOARB) ......................................................
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)...................................
7.3.4 DMA Control Registers (DMACRA and DMACRB) .........................................
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............
7.3.6 DMA Write Enable Register (DMAWER) ..........................................................
7.3.7 DMA Terminal Control Register (DMATCR).....................................................
Activation Sources ............................................................................................................
7.4.1 Activation by Internal Interrupt Request..............................................................
7.4.2 Activation by External Request ...........................................................................
7.4.3 Activation by Auto-Request.................................................................................
Operation...........................................................................................................................
7.5.1 Transfer Modes ....................................................................................................
7.5.2 Sequential Mode ..................................................................................................
7.5.3 Idle Mode.............................................................................................................
7.5.4 Repeat Mode ........................................................................................................
7.5.5 Single Address Mode ...........................................................................................
7.5.6 Normal Mode .......................................................................................................
7.5.7 Block Transfer Mode ...........................................................................................
7.5.8 Basic Bus Cycles..................................................................................................
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles ...............................................
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles.............................................
7.5.11 Write Data Buffer Function .................................................................................
7.5.12 Multi-Channel Operation .....................................................................................
7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles .........
7.5.14 DMAC and NMI Interrupts..................................................................................
7.5.15 Forced Termination of DMAC Operation............................................................
7.5.16 Clearing Full Address Mode ................................................................................
213
215
215
217
217
218
219
226
238
240
241
242
242
243
244
244
246
249
252
256
259
262
267
267
275
281
282
283
284
285
286
Rev. 5.00 Aug 02, 2006 page xxi of liv
7.6
7.7
Interrupt Sources ...............................................................................................................
Usage Notes ......................................................................................................................
7.7.1 DMAC Register Access during Operation...........................................................
7.7.2 Module Stop.........................................................................................................
7.7.3 Write Data Buffer Function .................................................................................
7.7.4 TEND Output.......................................................................................................
7.7.5 Activation by Falling Edge on DREQ Pin ...........................................................
7.7.6 Activation Source Acceptance .............................................................................
7.7.7 Internal Interrupt after End of Transfer................................................................
7.7.8 Channel Re-Setting ..............................................................................................
287
288
288
289
289
290
291
291
292
292
Section 8 Data Transfer Controller (DTC) ................................................................... 293
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Features .............................................................................................................................
Register Descriptions ........................................................................................................
8.2.1 DTC Mode Register A (MRA) ............................................................................
8.2.2 DTC Mode Register B (MRB).............................................................................
8.2.3 DTC Source Address Register (SAR)..................................................................
8.2.4 DTC Destination Address Register (DAR)..........................................................
8.2.5 DTC Transfer Count Register A (CRA) ..............................................................
8.2.6 DTC Transfer Count Register B (CRB)...............................................................
8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) .....................................
8.2.8 DTC Vector Register (DTVECR)........................................................................
Activation Sources ............................................................................................................
Location of Register Information and DTC Vector Table ................................................
Operation ..........................................................................................................................
8.5.1 Normal Mode.......................................................................................................
8.5.2 Repeat Mode ........................................................................................................
8.5.3 Block Transfer Mode ...........................................................................................
8.5.4 Chain Transfer .....................................................................................................
8.5.5 Interrupts..............................................................................................................
8.5.6 Operation Timing.................................................................................................
8.5.7 Number of DTC Execution States........................................................................
Procedures for Using DTC................................................................................................
8.6.1 Activation by Interrupt.........................................................................................
8.6.2 Activation by Software ........................................................................................
Examples of Use of the DTC ............................................................................................
8.7.1 Normal Mode.......................................................................................................
8.7.2 Chain Transfer .....................................................................................................
8.7.3 Chain Transfer when Counter = 0........................................................................
8.7.4 Software Activation .............................................................................................
Rev. 5.00 Aug 02, 2006 page xxii of liv
293
295
295
297
297
297
298
298
299
300
301
302
306
308
309
310
311
312
313
314
316
316
316
317
317
317
318
320
8.8
Usage Notes ......................................................................................................................
8.8.1 Module Stop Mode Setting ..................................................................................
8.8.2 On-Chip RAM .....................................................................................................
8.8.3 DTCE Bit Setting .................................................................................................
8.8.4 DMAC Transfer End Interrupt.............................................................................
8.8.5 Chain Transfer .....................................................................................................
321
321
321
321
321
321
Section 9 I/O Ports .............................................................................................................. 323
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Port 1.................................................................................................................................
9.1.1 Port 1 Data Direction Register (P1DDR).............................................................
9.1.2 Port 1 Data Register (P1DR)................................................................................
9.1.3 Port 1 Register (PORT1)......................................................................................
9.1.4 Pin Functions .......................................................................................................
Port 2.................................................................................................................................
9.2.1 Port 2 Data Direction Register (P2DDR).............................................................
9.2.2 Port 2 Data Register (P2DR)................................................................................
9.2.3 Port 2 Register (PORT2)......................................................................................
9.2.4 Pin Functions .......................................................................................................
Port 3.................................................................................................................................
9.3.1 Port 3 Data Direction Register (P3DDR).............................................................
9.3.2 Port 3 Data Register (P3DR)................................................................................
9.3.3 Port 3 Register (PORT3)......................................................................................
9.3.4 Port 3 Open Drain Control Register (P3ODR).....................................................
9.3.5 Port Function Control Register 2 (PFCR2) ..........................................................
9.3.6 Pin Functions .......................................................................................................
Port 4.................................................................................................................................
9.4.1 Port 4 Register (PORT4)......................................................................................
9.4.2 Pin Functions .......................................................................................................
Port 5.................................................................................................................................
9.5.1 Port 5 Data Direction Register (P5DDR).............................................................
9.5.2 Port 5 Data Register (P5DR)................................................................................
9.5.3 Port 5 Register (PORT5)......................................................................................
9.5.4 Pin Functions .......................................................................................................
Port 8.................................................................................................................................
9.6.1 Port 8 Data Direction Register (P8DDR).............................................................
9.6.2 Port 8 Data Register (P8DR)................................................................................
9.6.3 Port 8 Register (PORT8)......................................................................................
9.6.4 Pin Functions .......................................................................................................
Port 9.................................................................................................................................
9.7.1 Port 9 Register (PORT9)......................................................................................
327
327
328
328
329
337
337
338
338
339
347
347
348
348
349
350
351
354
354
355
357
357
357
358
358
360
360
361
361
362
363
363
Rev. 5.00 Aug 02, 2006 page xxiii of liv
9.8
9.9
9.10
9.11
9.12
9.13
9.7.2 Pin Functions .......................................................................................................
Port A................................................................................................................................
9.8.1 Port A Data Direction Register (PADDR) ...........................................................
9.8.2 Port A Data Register (PADR)..............................................................................
9.8.3 Port A Register (PORTA) ....................................................................................
9.8.4 Port A MOS Pull-Up Control Register (PAPCR) ................................................
9.8.5 Port A Open Drain Control Register (PAODR)...................................................
9.8.6 Port Function Control Register 0 (PFCR0) ..........................................................
9.8.7 Port Function Control Register 1 (PFCR1) ..........................................................
9.8.8 Pin Functions .......................................................................................................
9.8.9 Port A MOS Input Pull-Up States........................................................................
Port B ................................................................................................................................
9.9.1 Port B Data Direction Register (PBDDR) ...........................................................
9.9.2 Port B Data Register (PBDR) ..............................................................................
9.9.3 Port B Register (PORTB) ....................................................................................
9.9.4 Port B MOS Pull-Up Control Register (PBPCR) ................................................
9.9.5 Pin Functions .......................................................................................................
9.9.6 Port B MOS Input Pull-Up States ........................................................................
Port C ................................................................................................................................
9.10.1 Port C Data Direction Register (PCDDR) ...........................................................
9.10.2 Port C Data Register (PCDR) ..............................................................................
9.10.3 Port C Register (PORTC) ....................................................................................
9.10.4 Port C MOS Pull-Up Control Register (PCPCR).................................................
9.10.5 Pin Functions .......................................................................................................
9.10.6 Port C MOS Input Pull-Up States ........................................................................
Port D................................................................................................................................
9.11.1 Port D Data Direction Register (PDDDR) ...........................................................
9.11.2 Port D Data Register (PDDR)..............................................................................
9.11.3 Port D Register (PORTD)....................................................................................
9.11.4 Port D Pull-up Control Register (PDPCR)...........................................................
9.11.5 Pin Functions .......................................................................................................
9.11.6 Port D MOS Input Pull-Up States........................................................................
Port E ................................................................................................................................
9.12.1 Port E Data Direction Register (PEDDR) ............................................................
9.12.2 Port E Data Register (PEDR)...............................................................................
9.12.3 Port E Register (PORTE).....................................................................................
9.12.4 Port E Pull-up Control Register (PEPCR) ...........................................................
9.12.5 Pin Functions .......................................................................................................
9.12.6 Port E MOS Input Pull-Up States ........................................................................
Port F ................................................................................................................................
Rev. 5.00 Aug 02, 2006 page xxiv of liv
363
364
365
366
366
367
367
368
369
370
372
373
373
374
374
375
375
376
377
377
378
378
379
379
380
381
381
382
382
383
383
384
385
385
386
386
387
387
388
388
9.13.1 Port F Data Direction Register (PFDDR) ............................................................
9.13.2 Port F Data Register (PFDR) ...............................................................................
9.13.3 Port F Register (PORTF) .....................................................................................
9.13.4 Pin Functions .......................................................................................................
9.14 Port G................................................................................................................................
9.14.1 Port G Data Direction Register (PGDDR) ...........................................................
9.14.2 Port G Data Register (PGDR) ..............................................................................
9.14.3 Port G Register (PORTG) ....................................................................................
9.14.4 Pin Functions .......................................................................................................
389
390
390
391
395
395
396
396
397
Section 10 16-Bit Timer Pulse Unit (TPU) .................................................................. 401
10.1 Features .............................................................................................................................
10.2 Input/Output Pins ..............................................................................................................
10.3 Register Descriptions ........................................................................................................
10.3.1 Timer Control Register (TCR) .............................................................................
10.3.2 Timer Mode Register (TMDR) ............................................................................
10.3.3 Timer I/O Control Register (TIOR) .....................................................................
10.3.4 Timer Interrupt Enable Register (TIER) ..............................................................
10.3.5 Timer Status Register (TSR)................................................................................
10.3.6 Timer Counter (TCNT)........................................................................................
10.3.7 Timer General Register (TGR) ............................................................................
10.3.8 Timer Start Register (TSTR)................................................................................
10.3.9 Timer Synchronous Register (TSYR) ..................................................................
10.4 Operation...........................................................................................................................
10.4.1 Basic Functions....................................................................................................
10.4.2 Synchronous Operation........................................................................................
10.4.3 Buffer Operation ..................................................................................................
10.4.4 Cascaded Operation .............................................................................................
10.4.5 PWM Modes ........................................................................................................
10.4.6 Phase Counting Mode ..........................................................................................
10.5 Interrupts ...........................................................................................................................
10.6 DTC Activation.................................................................................................................
10.7 DMAC Activation.............................................................................................................
10.8 A/D Converter Activation .................................................................................................
10.9 Operation Timing ..............................................................................................................
10.9.1 Input/Output Timing ............................................................................................
10.9.2 Interrupt Signal Timing........................................................................................
10.10 Usage Notes ......................................................................................................................
10.10.1 Module Stop Mode Setting ..................................................................................
10.10.2 Input Clock Restrictions.......................................................................................
401
405
406
408
413
414
432
434
437
437
437
438
439
439
445
447
452
454
459
466
468
468
468
469
469
473
477
477
477
Rev. 5.00 Aug 02, 2006 page xxv of liv
10.10.3 Caution on Cycle Setting .....................................................................................
10.10.4 Contention between TCNT Write and Clear Operations .....................................
10.10.5 Contention between TCNT Write and Increment Operations..............................
10.10.6 Contention between TGR Write and Compare Match .........................................
10.10.7 Contention between Buffer Register Write and Compare Match ........................
10.10.8 Contention between TGR Read and Input Capture..............................................
10.10.9 Contention between TGR Write and Input Capture.............................................
10.10.10 Contention between Buffer Register Write and Input Capture ........................
10.10.11 Contention between Overflow/Underflow and Counter Clearing....................
10.10.12 Contention between TCNT Write and Overflow/Underflow...........................
10.10.13 Multiplexing of I/O Pins ..................................................................................
10.10.14 Interrupts and Module Stop Mode ...................................................................
478
478
479
479
480
481
482
482
483
484
484
484
Section 11 Programmable Pulse Generator (PPG) .................................................... 485
11.1 Features .............................................................................................................................
11.2 Input/Output Pins ..............................................................................................................
11.3 Register Descriptions ........................................................................................................
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL).........................................
11.3.2 Output Data Registers H, L (PODRH, PODRL)..................................................
11.3.3 Next Data Registers H, L (NDRH, NDRL) .........................................................
11.3.4 PPG Output Control Register (PCR) ...................................................................
11.3.5 PPG Output Mode Register (PMR) .....................................................................
11.4 Operation ..........................................................................................................................
11.4.1 Output Timing......................................................................................................
11.4.2 Sample Setup Procedure for Normal Pulse Output..............................................
11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)..........
11.4.4 Non-Overlapping Pulse Output............................................................................
11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ..............................
11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output) .........................................................
11.4.7 Inverted Pulse Output ..........................................................................................
11.4.8 Pulse Output Triggered by Input Capture ............................................................
11.5 Usage Notes ......................................................................................................................
11.5.1 Module Stop Mode Setting ..................................................................................
11.5.2 Operation of Pulse Output Pins............................................................................
485
487
487
488
489
490
492
493
495
496
497
498
499
501
Section 12 8-Bit Timers (TMR) ......................................................................................
12.1 Features .............................................................................................................................
12.2 Input/Output Pins ..............................................................................................................
12.3 Register Descriptions ........................................................................................................
507
507
509
509
Rev. 5.00 Aug 02, 2006 page xxvi of liv
502
504
505
505
505
505
12.4
12.5
12.6
12.7
12.8
12.3.1 Timer Counter (TCNT)........................................................................................
12.3.2 Time Constant Register A (TCORA)...................................................................
12.3.3 Time Constant Register B (TCORB) ...................................................................
12.3.4 Timer Control Register (TCR) ............................................................................
12.3.5 Timer Control/Status Register (TCSR) ................................................................
Operation...........................................................................................................................
12.4.1 Pulse Output.........................................................................................................
Operation Timing ..............................................................................................................
12.5.1 TCNT Incrementation Timing .............................................................................
12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................
12.5.3 Timing of Timer Output when Compare-Match Occurs......................................
12.5.4 Timing of Compare Match Clear .........................................................................
12.5.5 Timing of TCNT External Reset..........................................................................
12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................
Operation with Cascaded Connection ...............................................................................
12.6.1 16-Bit Counter Mode ...........................................................................................
12.6.2 Compare Match Count Mode...............................................................................
Interrupts ...........................................................................................................................
12.7.1 Interrupt Sources and DTC Activation.................................................................
12.7.2 A/D Converter Activation ....................................................................................
Usage Notes ......................................................................................................................
12.8.1 Contention between TCNT Write and Clear........................................................
12.8.2 Contention between TCNT Write and Increment ................................................
12.8.3 Contention between TCOR Write and Compare Match.......................................
12.8.4 Contention between Compare Matches A and B .................................................
12.8.5 Switching of Internal Clocks and TCNT Operation.............................................
12.8.6 Mode Setting with Cascaded Connection ............................................................
12.8.7 Interrupts in Module Stop Mode ..........................................................................
509
510
510
510
512
515
515
516
516
517
518
518
519
519
520
520
520
521
521
521
522
522
523
524
525
525
527
527
Section 13 Watchdog Timer ............................................................................................. 529
13.1 Features .............................................................................................................................
13.2 Input/Output Pin................................................................................................................
13.3 Register Descriptions ........................................................................................................
13.3.1 Timer Counter (TCNT)........................................................................................
13.3.2 Timer Control/Status Register (TCSR) ................................................................
13.3.3 Reset Control/Status Register (RSTCSR) ............................................................
13.4 Operation...........................................................................................................................
13.4.1 Watchdog Timer Mode ........................................................................................
13.4.2 Interval Timer Mode ............................................................................................
13.5 Interrupts ...........................................................................................................................
529
530
531
531
531
533
534
534
535
536
Rev. 5.00 Aug 02, 2006 page xxvii of liv
13.6 Usage Notes ......................................................................................................................
13.6.1 Notes on Register Access.....................................................................................
13.6.2 Contention between Timer Counter (TCNT) Write and Increment .....................
13.6.3 Changing Value of CKS2 to CKS0......................................................................
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................
13.6.5 Internal Reset in Watchdog Timer Mode.............................................................
13.6.6 System Reset by WDTOVF Signal......................................................................
536
536
538
538
538
539
539
Section 14 Serial Communication Interface (SCI, IrDA) ........................................ 541
14.1 Features .............................................................................................................................
14.2 Input/Output Pins ..............................................................................................................
14.3 Register Descriptions ........................................................................................................
14.3.1 Receive Shift Register (RSR) ..............................................................................
14.3.2 Receive Data Register (RDR) ..............................................................................
14.3.3 Transmit Data Register (TDR).............................................................................
14.3.4 Transmit Shift Register (TSR) .............................................................................
14.3.5 Serial Mode Register (SMR)................................................................................
14.3.6 Serial Control Register (SCR)..............................................................................
14.3.7 Serial Status Register (SSR) ................................................................................
14.3.8 Smart Card Mode Register (SCMR) ....................................................................
14.3.9 Bit Rate Register (BRR) ......................................................................................
14.3.10 IrDA Control Register (IrCR) ..............................................................................
14.3.11 Serial Extension Mode Register (SEMR) ............................................................
14.4 Operation in Asynchronous Mode ....................................................................................
14.4.1 Data Transfer Format...........................................................................................
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
14.4.3 Clock....................................................................................................................
14.4.4 SCI Initialization (Asynchronous Mode) .............................................................
14.4.5 Data Transmission (Asynchronous Mode)...........................................................
14.4.6 Serial Data Reception (Asynchronous Mode)......................................................
14.5 Multiprocessor Communication Function.........................................................................
14.5.1 Multiprocessor Serial Data Transmission ............................................................
14.5.2 Multiprocessor Serial Data Reception .................................................................
14.6 Operation in Clocked Synchronous Mode ........................................................................
14.6.1 Clock....................................................................................................................
14.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) ....................................
14.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................
14.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................
Rev. 5.00 Aug 02, 2006 page xxviii of liv
541
544
545
546
546
546
547
547
551
556
563
564
573
574
576
576
578
579
580
581
584
588
589
591
595
595
596
597
600
602
14.7 Operation in Smart Card Interface Mode ..........................................................................
14.7.1 Pin Connection Example......................................................................................
14.7.2 Data Format (Except for Block Transfer Mode) ..................................................
14.7.3 Block Transfer Mode ...........................................................................................
14.7.4 Receive Data Sampling Timing and Reception Margin.......................................
14.7.5 Initialization .........................................................................................................
14.7.6 Data Transmission (Except for Block Transfer Mode) ........................................
14.7.7 Serial Data Reception (Except for Block Transfer Mode) ...................................
14.7.8 Clock Output Control...........................................................................................
14.8 IrDA Operation .................................................................................................................
14.9 SCI Interrupts....................................................................................................................
14.9.1 Interrupts in Normal Serial Communication Interface Mode...............................
14.9.2 Interrupts in Smart Card Interface Mode .............................................................
14.10 Usage Notes ......................................................................................................................
14.10.1 Module Stop Mode Setting ..................................................................................
14.10.2 Break Detection and Processing...........................................................................
14.10.3 Mark State and Break Sending.............................................................................
14.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).....................................................................
14.10.5 Relation between Writes to TDR and the TDRE Flag .........................................
14.10.6 Restrictions on Use of DMAC or DTC................................................................
14.10.7 Operation in Case of Mode Transition.................................................................
604
604
605
606
606
608
608
612
613
616
619
619
621
622
622
622
622
623
623
623
624
Section 15 I2C Bus Interface2 (IIC2) (Option) ........................................................... 629
15.1 Features .............................................................................................................................
15.2 Input/Output Pins ..............................................................................................................
15.3 Register Descriptions ........................................................................................................
15.3.1 I2C Bus Control Register A (ICCRA) ..................................................................
15.3.2 I2C Bus Control Register B (ICCRB) ..................................................................
15.3.3 I2C Bus Mode Register (ICMR)...........................................................................
15.3.4 I2C Bus Interrupt Enable Register (ICIER)..........................................................
15.3.5 I2C Bus Status Register (ICSR)............................................................................
15.3.6 Slave Address Register (SAR) .............................................................................
15.3.7 I2C Bus Transmit Data Register (ICDRT) ...........................................................
15.3.8 I2C Bus Receive Data Register (ICDRR).............................................................
15.3.9 I2C Bus Shift Register (ICDRS)...........................................................................
15.4 Operation...........................................................................................................................
15.4.1 I2C Bus Format ....................................................................................................
15.4.2 Master Transmit Operation ..................................................................................
15.4.3 Master Receive Operation....................................................................................
629
631
632
633
635
636
637
639
641
642
642
642
643
643
644
646
Rev. 5.00 Aug 02, 2006 page xxix of liv
15.4.4 Slave Transmit Operation ....................................................................................
15.4.5 Slave Receive Operation......................................................................................
15.4.6 Noise Canceler .....................................................................................................
15.4.7 Example of Use....................................................................................................
15.5 Interrupt Request...............................................................................................................
15.6 Bit Synchronous Circuit....................................................................................................
15.7 Usage Notes ......................................................................................................................
648
650
653
653
658
658
659
Section 16 A/D Converter .................................................................................................
16.1 Features .............................................................................................................................
16.2 Input/Output Pins ..............................................................................................................
16.3 Register Descriptions ........................................................................................................
16.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................
16.3.2 A/D Control/Status Register (ADCSR) ...............................................................
16.3.3 A/D Control Register (ADCR) ............................................................................
16.4 Operation ..........................................................................................................................
16.4.1 Single Mode.........................................................................................................
16.4.2 Scan Mode ...........................................................................................................
16.4.3 Input Sampling and A/D Conversion Time .........................................................
16.4.4 External Trigger Input Timing.............................................................................
16.5 Interrupts ...........................................................................................................................
16.6 A/D Conversion Precision Definitions..............................................................................
16.7 Usage Notes ......................................................................................................................
16.7.1 Module Stop Mode Setting ..................................................................................
16.7.2 Permissible Signal Source Impedance .................................................................
16.7.3 Influences on Absolute Precision.........................................................................
16.7.4 Setting Range of Analog Power Supply and Other Pins ......................................
16.7.5 Notes on Board Design ........................................................................................
16.7.6 Notes on Noise Countermeasures ........................................................................
661
661
663
664
664
666
668
669
669
669
670
673
673
674
676
676
676
677
677
677
678
Section 17 D/A Converter .................................................................................................
17.1 Features .............................................................................................................................
17.2 Input/Output Pins ..............................................................................................................
17.3 Register Descriptions ........................................................................................................
17.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)............................................
17.3.2 D/A Control Register 23 (DACR23) ...................................................................
17.4 Operation ..........................................................................................................................
17.5 Usage Notes ......................................................................................................................
17.5.1 Setting for Module Stop Mode ............................................................................
17.5.2 D/A Output Hold Function in Software Standby Mode.......................................
681
681
683
683
683
684
685
686
686
686
Rev. 5.00 Aug 02, 2006 page xxx of liv
Section 18 RAM .................................................................................................................. 687
Section 19 Flash Memory (0.35-µm F-ZTAT Version) ........................................... 689
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
Features .............................................................................................................................
Mode Transitions ..............................................................................................................
Block Configuration..........................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
19.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................
19.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................
19.5.3 Erase Block Register 1 (EBR1) ...........................................................................
19.5.4 Erase Block Register 2 (EBR2) ...........................................................................
On-Board Programming Modes ........................................................................................
19.6.1 Boot Mode ...........................................................................................................
19.6.2 User Program Mode .............................................................................................
Flash Memory Programming/Erasing ...............................................................................
19.7.1 Program/Program-Verify .....................................................................................
19.7.2 Erase/Erase-Verify ...............................................................................................
19.7.3 Interrupt Handling when Programming/Erasing Flash Memory..........................
Program/Erase Protection..................................................................................................
19.8.1 Hardware Protection ............................................................................................
19.8.2 Software Protection..............................................................................................
19.8.3 Error Protection....................................................................................................
Programmer Mode ............................................................................................................
Power-Down States for Flash Memory .............................................................................
Usage Notes ......................................................................................................................
689
691
695
697
697
698
699
700
700
702
702
705
706
706
708
708
710
710
710
710
711
711
712
Section 20 Flash Memory (0.18-µm F-ZTAT Version) ........................................... 717
20.1 Features .............................................................................................................................
20.1.1 Operating Mode ...................................................................................................
20.1.2 Mode Comparison................................................................................................
20.1.3 Flash MAT Configuration....................................................................................
20.1.4 Block Division .....................................................................................................
20.1.5 Programming/Erasing Interface ...........................................................................
20.2 Input/Output Pins ..............................................................................................................
20.3 Register Descriptions ........................................................................................................
20.3.1 Programming/Erasing Interface Register .............................................................
20.3.2 Programming/Erasing Interface Parameter ..........................................................
20.3.3 Flash Vector Address Control Register (FVACR)...............................................
20.4 On-Board Programming Mode..........................................................................................
717
720
721
722
723
724
726
726
728
735
747
748
Rev. 5.00 Aug 02, 2006 page xxxi of liv
20.5
20.6
20.7
20.8
20.9
20.4.1 Boot Mode ...........................................................................................................
20.4.2 User Program Mode.............................................................................................
20.4.3 User Boot Mode...................................................................................................
20.4.4 Procedure Program and Storable Area for Programming Data ............................
Protection ..........................................................................................................................
20.5.1 Hardware Protection ............................................................................................
20.5.2 Software Protection..............................................................................................
20.5.3 Error Protection....................................................................................................
Switching between User MAT and User Boot MAT ........................................................
Programmer Mode ............................................................................................................
Serial Communication Interface Specification for Boot Mode.........................................
Usage Notes ......................................................................................................................
748
753
764
768
778
778
779
779
781
782
782
810
Section 21 Mask ROM....................................................................................................... 811
Section 22 Clock Pulse Generator .................................................................................. 813
22.1 Register Descriptions ........................................................................................................
22.1.1 System Clock Control Register (SCKCR) ...........................................................
22.1.2 PLL Control Register (PLLCR) ...........................................................................
22.2 Oscillator...........................................................................................................................
22.2.1 Connecting a Crystal Oscillator ...........................................................................
22.2.2 External Clock Input ............................................................................................
22.3 PLL Circuit .......................................................................................................................
22.4 Frequency Divider ............................................................................................................
22.5 Usage Notes ......................................................................................................................
22.5.1 Notes on Clock Pulse Generator ..........................................................................
22.5.2 Notes on Oscillator ..............................................................................................
22.5.3 Notes on Board Design ........................................................................................
813
814
815
816
816
817
818
819
819
819
820
820
Section 23 Power-Down Modes ...................................................................................... 823
23.1 Register Descriptions ........................................................................................................
23.1.1 Standby Control Register (SBYCR) ....................................................................
23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)....................
23.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) .........................................................................
23.2 Operation ..........................................................................................................................
23.2.1 Clock Division Mode...........................................................................................
23.2.2 Sleep Mode ..........................................................................................................
23.2.3 Software Standby Mode.......................................................................................
23.2.4 Hardware Standby Mode .....................................................................................
Rev. 5.00 Aug 02, 2006 page xxxii of liv
826
826
828
829
830
830
830
831
834
23.2.5 Module Stop Mode ..............................................................................................
23.2.6 All-Module-Clocks-Stop Mode ...........................................................................
23.3 φ Clock Output Control.....................................................................................................
23.4 Usage Notes ......................................................................................................................
23.4.1 I/O Port Status......................................................................................................
23.4.2 Current Dissipation during Oscillation Stabilization Standby Period ..................
23.4.3 DMAC/DTC Module Stop...................................................................................
23.4.4 On-Chip Peripheral Module Interrupts ................................................................
23.4.5 Writing to MSTPCR, EXMSTPCR .....................................................................
23.4.6 Notes on Clock Division Mode............................................................................
835
836
836
837
837
837
837
837
837
838
Section 24 List of Registers .............................................................................................. 839
24.1 Register Addresses (Address Order) ................................................................................. 840
24.2 Register Bits...................................................................................................................... 850
24.3 Register States in Each Operating Mode........................................................................... 863
Section 25 Electrical Characteristics..............................................................................
25.1 Electrical Characteristics of Masked ROM and ROMless Versions .................................
25.1.1 Absolute Maximum Ratings ................................................................................
25.1.2 DC Characteristics ...............................................................................................
25.1.3 AC Characteristics ...............................................................................................
25.1.4 A/D Conversion Characteristics...........................................................................
25.1.5 D/A Conversion Characteristics...........................................................................
25.2 Electrical Characteristics of 0.35 µm F-ZTAT Version....................................................
25.2.1 Absolute Maximum Ratings ................................................................................
25.2.2 DC Characteristics ...............................................................................................
25.2.3 A/D Conversion Characteristics...........................................................................
25.2.4 D/A Conversion Characteristics...........................................................................
25.2.5 Flash Memory Characteristics..............................................................................
25.3 Electrical Characteristics for 0.18 µm F-ZTAT Version...................................................
25.3.1 Absolute Maximum Ratings ................................................................................
25.3.2 DC Characteristics ...............................................................................................
25.3.3 AC Characteristics ...............................................................................................
25.3.4 A/D Conversion Characteristics...........................................................................
25.3.5 D/A Conversion Characteristics...........................................................................
25.3.6 Flash Memory Characteristics..............................................................................
25.4 Usage Note........................................................................................................................
873
873
873
874
877
910
910
911
911
912
923
923
924
926
926
927
930
938
938
939
940
Appendix
A.
............................................................................................................................. 941
I/O Port States in Each Pin State....................................................................................... 941
Rev. 5.00 Aug 02, 2006 page xxxiii of liv
B.
C.
D.
Product Lineup.................................................................................................................. 949
Package Dimensions ......................................................................................................... 950
Bus State during Execution of Instructions....................................................................... 952
Index
............................................................................................................................. 975
Rev. 5.00 Aug 02, 2006 page xxxiv of liv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8S/2367F, H8S/2365, and H8S/2363 .......................
Figure 1.2 Internal Block Diagram of H8S/2368 0.18 µm F-ZTAT Group.............................
Figure 1.3 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363 ..................................
Figure 1.4 Pin Arrangement of H8S/2368 0.18 µm F-ZTAT Group .......................................
Figure 1.5 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363 ..................................
3
4
5
6
7
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)................................................................
Figure 2.2 Stack Structure in Normal Mode............................................................................
Figure 2.3 Exception Vector Table (Advanced Mode)............................................................
Figure 2.4 Stack Structure in Advanced Mode ........................................................................
Figure 2.5 Memory Map..........................................................................................................
Figure 2.6 CPU Internal Registers ...........................................................................................
Figure 2.7 Usage of General Registers ....................................................................................
Figure 2.8 Stack .......................................................................................................................
Figure 2.9 General Register Data Formats (1).........................................................................
Figure 2.9 General Register Data Formats (2).........................................................................
Figure 2.10 Memory Data Formats............................................................................................
Figure 2.11 Instruction Formats (Examples) .............................................................................
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................
Figure 2.13 State Transitions .....................................................................................................
25
25
26
27
28
29
30
31
34
35
36
48
52
56
Section 3 MCU Operating Modes
Figure 3.1 H8S/2368F Memory Map (1).................................................................................
Figure 3.2 H8S/2368F Memory Map (2).................................................................................
Figure 3.3 H8S/2367F Memory Map (1).................................................................................
Figure 3.4 H8S/2367F Memory Map (2).................................................................................
Figure 3.5 H8S/2364F Memory Map (1).................................................................................
Figure 3.6 H8S/2364F Memory Map (2).................................................................................
Figure 3.7 H8S/2362F Memory Map (1).................................................................................
Figure 3.8 H8S/2362F Memory Map (2).................................................................................
Figure 3.9 H8S/2361F Memory Map (1).................................................................................
Figure 3.10 H8S/2361F Memory Map (2).................................................................................
Figure 3.11 H8S/2360F Memory Map (1).................................................................................
Figure 3.12 H8S/2360F Memory Map (2).................................................................................
Figure 3.13 H8S/2365 Memory Map (1) ...................................................................................
63
64
65
66
67
68
69
70
71
72
73
74
75
Rev. 5.00 Aug 02, 2006 page xxxv of liv
Figure 3.14 H8S/2365 Memory Map (2) ................................................................................... 76
Figure 3.15 H8S/2363 Memory Map......................................................................................... 77
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)..........................
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled).........................
Figure 4.3 Stack Status after Exception Handling ...................................................................
Figure 4.4 Operation when SP Value Is Odd...........................................................................
82
83
86
87
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller...................................................................
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0.........................................................
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2
Figure 5.5 Interrupt Exception Handling .................................................................................
Figure 5.6 Contention between Interrupt Generation and Disabling .......................................
90
102
109
111
113
116
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller...........................................................................
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) .......................
Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0) .......................................................................................................
Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................
Figure 6.5 Area Divisions........................................................................................................
Figure 6.6 CSn Signal Output Timing (n = 0 to 7) ..................................................................
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space) ..........................
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space) .........................
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space ..........................................................
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space ..........................................................
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)..........
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) ...........
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ...............................
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)..........
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ...........
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ...............................
Figure 6.17 Example of Wait State Insertion Timing................................................................
Figure 6.18 Example of Read Strobe Timing ............................................................................
Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended ....................
Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)...........................................
Rev. 5.00 Aug 02, 2006 page xxxvi of liv
120
129
131
139
145
150
151
151
153
154
155
156
157
158
159
160
162
163
164
168
Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0).............................................................................................................
Figure 6.22 Example of Access Timing when RAS Signal Goes Low from Beginning
of Tr State (CAST = 0) ...........................................................................................
Figure 6.23 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0) ..........................................................................................
Figure 6.24 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)......
Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output) ........
Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output) .........
Figure 6.27 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0).........
Figure 6.28 Example of 2-CAS DRAM Connection .................................................................
Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) ..............................
Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) ..............................
Figure 6.31 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)........
Figure 6.32 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).............
Figure 6.33 RTCNT Operation..................................................................................................
Figure 6.34 Compare Match Timing .........................................................................................
Figure 6.35 CBR Refresh Timing..............................................................................................
Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)................
Figure 6.37 Example of CBR Refresh Timing (CBRM = 1) .....................................................
Figure 6.38 Self-Refresh Timing ...............................................................................................
Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States ..............................................................................................................
Figure 6.40 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) .........
Figure 6.41 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1) .........
Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) ............
Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) ............
Figure 6.44 xample of Idle Cycle Operation (Consecutive Reads in Different Areas)..............
Figure 6.45 Example of Idle Cycle Operation (Write after Read) .............................................
Figure 6.46 Example of Idle Cycle Operation (Read after Write) .............................................
Figure 6.47 Relationship between Chip Select (CS) and Read (RD).........................................
Figure 6.48 Example of DRAM Full Access after External Read (CAST = 0) .........................
Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads
in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)..........................................
Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0) .........................................................................
Figure 6.51 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in
Different Areas) (IDLC = 0, RAST = 0, CAST = 0) ...................................................................
Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0) .........................................................................
169
170
171
172
174
175
176
177
178
179
180
181
182
183
183
184
185
186
187
188
189
191
192
193
194
195
196
196
197
198
199
199
Rev. 5.00 Aug 02, 2006 page xxxvii of liv
Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0,
ICIS1 = 0, RAST = 0, CAST = 0) ..........................................................................
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode ...................................
Figure 6.55 Example of Timing when Write Data Buffer Function is Used .............................
Figure 6.56 Bus Released State Transition Timing ...................................................................
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ......................................................................................
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) ............................................
Figure 7.3 Operation in Sequential Mode................................................................................
Figure 7.4 Example of Sequential Mode Setting Procedure....................................................
Figure 7.5 Operation in Idle Mode ..........................................................................................
Figure 7.6 Example of Idle Mode Setting Procedure ..............................................................
Figure 7.7 Operation in Repeat mode......................................................................................
Figure 7.8 Example of Repeat Mode Setting Procedure..........................................................
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)............
Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential
Mode is Specified) .................................................................................................
Figure 7.11 Operation in Normal Mode ....................................................................................
Figure 7.12 Example of Normal Mode Setting Procedure.........................................................
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ................................................
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ................................................
Figure 7.15 Operation Flow in Block Transfer Mode ...............................................................
Figure 7.16 Example of Block Transfer Mode Setting Procedure.............................................
Figure 7.17 Example of DMA Transfer Bus Timing.................................................................
Figure 7.18 Example of Short Address Mode Transfer .............................................................
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) .........................................
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode).........................................
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) .........................
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer....
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer...................
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer.......
Figure 7.26 Example of Single Address Mode Transfer (Byte Read) .......................................
Figure 7.27 Example of Single Address Mode (Word Read) Transfer......................................
Figure 7.28 Example of Single Address Mode Transfer (Byte Write) ......................................
Figure 7.29 Example of Single Address Mode Transfer (Word Write).....................................
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer....
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer.......
Rev. 5.00 Aug 02, 2006 page xxxviii of liv
200
203
205
208
214
239
247
248
249
251
254
255
257
258
260
261
263
264
265
266
267
268
269
270
271
272
273
274
275
276
276
277
278
279
280
Figure 7.32
Figure 7.33
Figure 7.34
Figure 7.35
Figure 7.36
Figure 7.37
Figure 7.38
Figure 7.39
Figure 7.40
Figure 7.41
Example of Dual Address Transfer Using Write Data Buffer Function.................
Example of Single Address Transfer Using Write Data Buffer Function ..............
Example of Multi-Channel Transfer.......................................................................
Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt ....................................................................................................
Example of Procedure for Forcibly Terminating DMAC Operation......................
Example of Procedure for Clearing Full Address Mode ........................................
Block Diagram of Transfer End/Transfer Break Interrupt .....................................
DMAC Register Update Timing.............................................................................
Contention between DMAC Register Update and CPU Read................................
Example in which Low Level is Not Output at TEND Pin ....................................
281
282
283
284
285
286
287
288
289
291
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ..........................................................................................
Figure 8.2 Block Diagram of DTC Activation Source Control ...............................................
Figure 8.3 Correspondence between DTC Vector Address and Register Information ............
Figure 8.4 Correspondence between DTC Vector Address and Register Information ............
Figure 8.5 Flowchart of DTC Operation..................................................................................
Figure 8.6 Memory Mapping in Normal Mode .......................................................................
Figure 8.7 Memory Mapping in Repeat Mode ........................................................................
Figure 8.8 Memory Mapping in Block Transfer Mode ...........................................................
Figure 8.9 Operation of Chain Transfer...................................................................................
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)..............................................................................................
Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ...........................................
Figure 8.13 Chain Transfer when Counter = 0 ..........................................................................
313
314
319
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU...........................................................................................
Figure 10.2 Example of Counter Operation Setting Procedure .................................................
Figure 10.3 Free-Running Counter Operation ...........................................................................
Figure 10.4 Periodic Counter Operation....................................................................................
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............
Figure 10.6 Example of 0 Output/1 Output Operation ..............................................................
Figure 10.7 Example of Toggle Output Operation ....................................................................
Figure 10.8 Example of Setting Procedure for Input Capture Operation...................................
Figure 10.9 Example of Input Capture Operation......................................................................
Figure 10.10 Example of Synchronous Operation Setting Procedure .........................................
Figure 10.11 Example of Synchronous Operation.......................................................................
404
439
440
441
442
443
443
444
445
446
447
294
302
303
303
307
309
310
311
312
313
Rev. 5.00 Aug 02, 2006 page xxxix of liv
Figure 10.12 Compare Match Buffer Operation..........................................................................
Figure 10.13 Input Capture Buffer Operation..............................................................................
Figure 10.14 Example of Buffer Operation Setting Procedure....................................................
Figure 10.15 Example of Buffer Operation (1) ...........................................................................
Figure 10.16 Example of Buffer Operation (2) ...........................................................................
Figure 10.17 Cascaded Operation Setting Procedure ..................................................................
Figure 10.18 Example of Cascaded Operation (1).......................................................................
Figure 10.19 Example of Cascaded Operation (2).......................................................................
Figure 10.20 Example of PWM Mode Setting Procedure ...........................................................
Figure 10.21 Example of PWM Mode Operation (1) ..................................................................
Figure 10.22 Example of PWM Mode Operation (2) ..................................................................
Figure 10.23 Example of PWM Mode Operation (3) ..................................................................
Figure 10.24 Example of Phase Counting Mode Setting Procedure............................................
Figure 10.25 Example of Phase Counting Mode 1 Operation .....................................................
Figure 10.26 Example of Phase Counting Mode 2 Operation .....................................................
Figure 10.27 Example of Phase Counting Mode 3 Operation .....................................................
Figure 10.28 Example of Phase Counting Mode 4 Operation .....................................................
Figure 10.29 Phase Counting Mode Application Example..........................................................
Figure 10.30 Count Timing in Internal Clock Operation.............................................................
Figure 10.31 Count Timing in External Clock Operation ...........................................................
Figure 10.32 Output Compare Output Timing ............................................................................
Figure 10.33 Input Capture Input Signal Timing.........................................................................
Figure 10.34 Counter Clear Timing (Compare Match) ...............................................................
Figure 10.35 Counter Clear Timing (Input Capture) ...................................................................
Figure 10.36 Buffer Operation Timing (Compare Match) ..........................................................
Figure 10.37 Buffer Operation Timing (Input Capture) ..............................................................
Figure 10.38 TGI Interrupt Timing (Compare Match) ................................................................
Figure 10.39 TGI Interrupt Timing (Input Capture) ....................................................................
Figure 10.40 TCIV Interrupt Setting Timing...............................................................................
Figure 10.41 TCIU Interrupt Setting Timing...............................................................................
Figure 10.42 Timing for Status Flag Clearing by CPU ...............................................................
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation ................................
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................
Figure 10.45 Contention between TCNT Write and Clear Operations........................................
Figure 10.46 Contention between TCNT Write and Increment Operations ................................
Figure 10.47 Contention between TGR Write and Compare Match ...........................................
Figure 10.48 Contention between Buffer Register Write and Compare Match...........................
Figure 10.49 Contention between TGR Read and Input Capture ................................................
Figure 10.50 Contention between TGR Write and Input Capture ...............................................
Figure 10.51 Contention between Buffer Register Write and Input Capture...............................
Rev. 5.00 Aug 02, 2006 page xl of liv
448
448
449
450
451
452
453
453
456
457
457
458
460
461
462
463
464
465
469
469
470
470
471
471
472
472
473
474
475
475
476
476
477
478
479
480
480
481
482
483
Figure 10.52 Contention between Overflow and Counter Clearing............................................. 483
Figure 10.53 Contention between TCNT Write and Overflow.................................................... 484
Section 11 Programmable Pulse Generator (PPG)
Figure 11.1 Block Diagram of PPG...........................................................................................
Figure 11.2 Overview Diagram of PPG.....................................................................................
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................
Figure 11.4 Setup Procedure for Normal Pulse Output (Example)............................................
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) ....................................
Figure 11.6 Non-Overlapping Pulse Output ..............................................................................
Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................
Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)...............
Figure 11.10 Inverted Pulse Output (Example) ...........................................................................
Figure 11.11 Pulse Output Triggered by Input Capture (Example).............................................
486
495
496
497
498
499
500
501
502
504
505
Section 12 8-Bit Timers (TMR)
Figure 12.1 Block Diagram of 8-Bit Timer Module..................................................................
Figure 12.2 Example of Pulse Output........................................................................................
Figure 12.3 Count Timing for Internal Clock Input...................................................................
Figure 12.4 Count Timing for External Clock Input .................................................................
Figure 12.5 Timing of CMF Setting ..........................................................................................
Figure 12.6 Timing of Timer Output .........................................................................................
Figure 12.7 Timing of Compare Match Clear............................................................................
Figure 12.8 Timing of Clearance by External Reset..................................................................
Figure 12.9 Timing of OVF Setting...........................................................................................
Figure 12.10 Contention between TCNT Write and Clear ..........................................................
Figure 12.11 Contention between TCNT Write and Increment...................................................
Figure 12.12 Contention between TCOR Write and Compare Match.........................................
508
516
516
517
517
518
518
519
519
522
523
524
Section 13
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
530
535
536
537
538
539
Watchdog Timer
Block Diagram of WDT .........................................................................................
Operation in Watchdog Timer Mode......................................................................
Operation in Interval Timer Mode .........................................................................
Writing to TCNT, TCSR, and RSTCSR................................................................
Contention between TCNT Write and Increment...................................................
Circuit for System Reset by WDTOVF Signal (Example).....................................
Section 14 Serial Communication Interface (SCI, IrDA)
Figure 14.1 Block Diagram of SCI ............................................................................................ 543
Rev. 5.00 Aug 02, 2006 page xli of liv
Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits) ............................................................................................
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode .......................................
Figure 14.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode)
Figure 14.5 Sample SCI Initialization Flowchart ......................................................................
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................
Figure 14.7 Sample Serial Transmission Flowchart ..................................................................
Figure 14.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
One Stop Bit)..........................................................................................................
Figure 14.9 Sample Serial Reception Data Flowchart (1) .........................................................
Figure 14.9 Sample Serial Reception Data Flowchart (2) .........................................................
Figure 14.10 Example of Communication Using Multiprocessor Format (Transmission
of Data H'AA to Receiving Station A) ...................................................................
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart .........................................
Figure 14.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)..........................................................................
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1).........................................
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2).........................................
Figure 14.14 Data Format in Clocked Synchronous Communication (For LSB-First) ...............
Figure 14.15 Sample SCI Initialization Flowchart ......................................................................
Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ...................
Figure 14.17 Sample Serial Transmission Flowchart ..................................................................
Figure 14.18 Example of SCI Operation in Reception ................................................................
Figure 14.19 Sample Serial Reception Flowchart .......................................................................
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations .......
Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections...............................
Figure 14.22 Normal Smart Card Interface Data Format ............................................................
Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0) .......................................................
Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1) .....................................................
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of
372 Times the Bit Rate)..........................................................................................
Figure 14.26 Retransfer Operation in SCI Transmit Mode .........................................................
Figure 14.27 TEND Flag Generation Timing in Transmission Operation ..................................
Figure 14.28 Example of Transmission Processing Flow............................................................
Figure 14.29 Retransfer Operation in SCI Receive Mode ...........................................................
Figure 14.30 Example of Reception Processing Flow.................................................................
Figure 14.31 Timing for Fixing Clock Output Level ..................................................................
Figure 14.32 Clock Halt and Restart Procedure ..........................................................................
Figure 14.33 Block Diagram of IrDA..........................................................................................
Rev. 5.00 Aug 02, 2006 page xlii of liv
576
578
579
580
582
583
584
586
587
589
590
592
593
594
595
596
598
599
600
601
603
604
605
605
606
607
609
610
611
612
613
614
615
616
Figure 14.34 IrDA Transmit/Receive Operations........................................................................
Figure 14.35 Example of Synchronous Transmission Using DTC..............................................
Figure 14.36 Sample Flowchart for Mode Transition during Transmission................................
Figure 14.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous
Transmission) ..............................................................................................................................
Figure 14.38 Port Pin States during Mode Transition (Internal Clock,
Synchronous Transmission) ...................................................................................
Figure 14.39 Sample Flowchart for Mode Transition during Reception .....................................
617
623
625
626
626
627
Section 15 I2C Bus Interface2 (IIC2) (Option)
Figure 15.1 Block Diagram of I2C Bus Interface2.....................................................................
Figure 15.2 External Circuit Connections of I/O Pins ...............................................................
Figure 15.3 I2C Bus Formats .....................................................................................................
Figure 15.4 I2C Bus Timing.......................................................................................................
Figure 15.5 Master Transmit Mode Operation Timing 1...........................................................
Figure 15.6 Master Transmit Mode Operation Timing 2...........................................................
Figure 15.7 Master Receive Mode Operation Timing 1 ............................................................
Figure 15.8 Master Receive Mode Operation Timing 2 ............................................................
Figure 15.9 Slave Transmit Mode Operation Timing 1.............................................................
Figure 15.10 Slave Transmit Mode Operation Timing 2.............................................................
Figure 15.11 Slave Receive Mode Operation Timing 1 ..............................................................
Figure 15.12 Slave Receive Mode Operation Timing 2 ..............................................................
Figure 15.13 Block Diagram of Noise Canceler..........................................................................
Figure 15.14 Sample Flowchart for Master Transmit Mode........................................................
Figure 15.15 Sample Flowchart for Master Receive Mode .........................................................
Figure 15.16 Sample Flowchart for Slave Transmit Mode..........................................................
Figure 15.17 Sample Flowchart for Slave Receive Mode ...........................................................
Figure 15.18 Timing of the Bit Synchronous Circuit ..................................................................
630
631
643
643
645
646
647
648
649
650
651
652
653
654
655
656
657
659
Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
Figure 16.7
662
671
673
675
675
676
678
A/D Converter
Block Diagram of A/D Converter ..........................................................................
A/D Conversion Timing .........................................................................................
External Trigger Input Timing ...............................................................................
A/D Conversion Precision Definitions ...................................................................
A/D Conversion Precision Definitions ...................................................................
Example of Analog Input Circuit ...........................................................................
Example of Analog Input Protection Circuit ..........................................................
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter .......................................................................... 682
Rev. 5.00 Aug 02, 2006 page xliii of liv
Figure 17.2 Example of D/A Converter Operation.................................................................... 686
Section 19
Figure 19.1
Figure 19.2
Figure 19.3
Figure 19.4
Figure 19.5
Figure 19.6
Figure 19.7
Figure 19.8
Figure 19.9
Figure 19.0
Flash Memory (0.35-µ
µm F-ZTAT Version)
Block Diagram of Flash Memory..........................................................................
Flash Memory State Transitions.............................................................................
Boot Mode..............................................................................................................
User Program Mode ...............................................................................................
384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) .....................
Programming/Erasing Flowchart Example in User Program Mode.......................
Program/Program-Verify Flowchart ......................................................................
Erase/Erase-Verify Flowchart ................................................................................
Power-On/Off Timing ............................................................................................
Mode Transition Timing (Example: Boot Mode → User Mode ↔
User Program Mode) ..............................................................................................
Section 20 Flash Memory (0.18-µ
µm F-ZTAT Version)
Figure 20.1 Block Diagram of Flash Memory...........................................................................
Figure 20.2 Mode Transition of Flash Memory.........................................................................
Figure 20.3 Flash Memory Configuration .................................................................................
Figure 20.4 Block Division of User MAT .................................................................................
Figure 20.5 Overview of User Procedure Program ...................................................................
Figure 20.6 System Configuration in Boot Mode......................................................................
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................
Figure 20.8 Overview of Boot Mode State Transition Diagram................................................
Figure 20.9 Programming/Erasing Overview Flow...................................................................
Figure 20.10 RAM Map when Programming/Erasing Is Executed .............................................
Figure 20.11 Programming Procedure.........................................................................................
Figure 20.12 Erasing Procedure ..................................................................................................
Figure 20.13 Procedure for Programming User MAT in User Boot Mode .................................
Figure 20.14 Procedure for Erasing User MAT in User Boot Mode...........................................
Figure 20.15 Transitions to Error-Protection State......................................................................
Figure 20.16 Switching between the User MAT and User Boot MAT .......................................
Figure 20.17 Boot Program States...............................................................................................
Figure 20.18 Bit-Rate-Adjustment Sequence ..............................................................................
Figure 20.19 Communication Protocol Format ...........................................................................
Figure 20.20 New Bit-Rate Selection Sequence..........................................................................
Figure 20.21 Programming Sequence..........................................................................................
Figure 20.22 Erasure Sequence ...................................................................................................
Rev. 5.00 Aug 02, 2006 page xliv of liv
690
691
693
694
696
705
707
709
714
715
719
720
722
723
724
749
749
752
753
754
755
762
765
767
780
781
783
784
785
796
801
804
Section 21 Mask ROM
Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365)....................................... 811
Section 22
Figure 22.1
Figure 22.2
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Clock Pulse Generator
Block Diagram of Clock Pulse Generator ..............................................................
Connection of Crystal Oscillator (Example) ..........................................................
Crystal Oscillator Equivalent Circuit .....................................................................
External Clock Input (Examples) ...........................................................................
External Clock Input Timing..................................................................................
Note on Oscillator Board Design............................................................................
Recommended External Circuitry for PLL Circuit.................................................
813
816
816
817
818
820
821
Section 23
Figure 23.1
Figure 23.2
Figure 23.3
Figure 23.4
Power-Down Modes
Mode Transitions....................................................................................................
Software Standby Mode Application Example ......................................................
Hardware Standby Mode Timing ...........................................................................
Hardware Standby Mode Timing when Power Is Supplied ...................................
825
833
834
835
Section 25 Electrical Characteristics
Figure 25.1 Output Load Circuit................................................................................................
Figure 25.2 System Clock Timing.............................................................................................
Figure 25.3 Oscillation Stabilization Timing (1) .......................................................................
Figure 25.3 Oscillation Stabilization Timing (2) .......................................................................
Figure 25.4 Reset Input Timing.................................................................................................
Figure 25.5 Interrupt Input Timing............................................................................................
Figure 25.6 Basic Bus Timing: Two-State Access ....................................................................
Figure 25.7 Basic Bus Timing: Three-State Access ..................................................................
Figure 25.8 Basic Bus Timing: Three-State Access, One Wait .................................................
Figure 25.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ................
Figure 25.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ..............
Figure 25.11 Burst ROM Access Timing: One-State Burst Access ............................................
Figure 25.12 Burst ROM Access Timing: Two-State Burst Access............................................
Figure 25.13 DRAM Access Timing: Two-State Access ............................................................
Figure 25.14 DRAM Access Timing: Two-State Access, One Wait...........................................
Figure 25.15 DRAM Access Timing: Two-State Burst Access ..................................................
Figure 25.16 DRAM Access Timing: Three-State Access (RAST = 1) ......................................
Figure 25.17 DRAM Access Timing: Three-State Burst Access.................................................
Figure 25.18 CAS-Before-RAS Refresh Timing.........................................................................
Figure 25.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ............................
877
878
879
879
880
881
886
887
888
889
890
891
892
893
894
895
896
897
898
898
Rev. 5.00 Aug 02, 2006 page xlv of liv
Figure 25.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)..............
Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)..............
Figure 25.22 External Bus Release Timing .................................................................................
Figure 25.23 External Bus Request Output Timing.....................................................................
Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access.................................
Figure 25.25 DMAC Single Address Transfer Timing: Three-State Access...............................
Figure 25.26 DMAC TEND Output Timing ...............................................................................
Figure 25.27 DMAC DREQ Input Timing..................................................................................
Figure 25.28 I/O Port Input/Output Timing.................................................................................
Figure 25.29 PPG Output Timing................................................................................................
Figure 25.30 TPU Input/Output Timing ......................................................................................
Figure 25.31 TPU Clock Input Timing........................................................................................
Figure 25.32 8-Bit Timer Output Timing ....................................................................................
Figure 25.33 8-Bit Timer Clock Input Timing ............................................................................
Figure 25.34 8-Bit Timer Reset Input Timing .............................................................................
Figure 25.35 WDT Output Timing ..............................................................................................
Figure 25.36 SCK Clock Input Timing .......................................................................................
Figure 25.37 SCI Input/Output Timing: Synchronous Mode ......................................................
Figure 25.38 A/D Converter External Trigger Input Timing.......................................................
Figure 25.39 I2C Bus Interface Input/Output Timing (Option) ...................................................
Appendix
Figure C.1
Figure C.2
Figure D.1
899
899
900
900
902
903
903
904
906
906
906
907
907
907
907
908
908
908
908
909
Package Dimensions (TFP-120)............................................................................. 950
Package Dimensions (FP-128B) ............................................................................ 951
Timing of Address Bus, RD, HWR, and LWR (8-bit bus, 3-state access,
no wait)................................................................................................................... 953
Rev. 5.00 Aug 02, 2006 page xlvi of liv
Tables
Section 1 Overview
Table 1.1
Pin Arrangement in Each Operating Mode ............................................................ 8
Table 1.2
Pin Functions.......................................................................................................... 14
Section 2 CPU
Table 2.1
Instruction Classification........................................................................................
Table 2.2
Operation Notation .................................................................................................
Table 2.3
Data Transfer Instructions ......................................................................................
Table 2.4
Arithmetic Operations Instructions ........................................................................
Table 2.5
Logic Operations Instructions ................................................................................
Table 2.6
Shift Instructions ....................................................................................................
Table 2.7
Bit Manipulation Instructions.................................................................................
Table 2.8
Branch Instructions.................................................................................................
Table 2.9
System Control Instructions ...................................................................................
Table 2.10 Block Data Transfer Instructions............................................................................
Table 2.11 Addressing Modes..................................................................................................
Table 2.12 Absolute Address Access Ranges...........................................................................
Table 2.13 Effective Address Calculation ................................................................................
37
38
39
40
42
42
43
45
46
47
49
51
53
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection............................................................................ 57
Table 3.2
Pin Functions in Each Operating Mode.................................................................. 62
Section 4 Exception Handling
Table 4.1
Exception Types and Priority .................................................................................
Table 4.2
Exception Handling Vector Table ..........................................................................
Table 4.3
Status of CCR and EXR after Trace Exception Handling ......................................
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling .....................
79
80
84
85
Section 5 Interrupt Controller
Table 5.1
Pin Configuration ................................................................................................... 91
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 103
Table 5.3
Interrupt Control Modes ......................................................................................... 108
Table 5.4
Interrupt Response Times....................................................................................... 114
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses..................... 115
Rev. 5.00 Aug 02, 2006 page xlvii of liv
Section 6 Bus Controller (BSC)
Table 6.1
Pin Configuration ................................................................................................... 121
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface) ........................................ 147
Table 6.3
Data Buses Used and Valid Strobes ....................................................................... 152
Table 6.4
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 165
Table 6.5
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... 166
Table 6.6
DRAM Interface Pins............................................................................................. 167
Table 6.7
Idle Cycles in Mixed Accesses to Normal Space and DRAM ............................... 201
Table 6.8
Pin States in Idle Cycle .......................................................................................... 204
Table 6.9
Pin States in Bus Released State ............................................................................ 207
Section 7 DMA Controller (DMAC)
Table 7.1
Pin Configuration ...................................................................................................
Table 7.3
DMAC Activation Sources ....................................................................................
Table 7.4
DMAC Transfer Modes..........................................................................................
Table 7.5
Register Functions in Sequential Mode..................................................................
Table 7.6
Register Functions in Idle Mode ............................................................................
Table 7.7
Register Functions in Repeat Mode .......................................................................
Table 7.8
Register Functions in Single Address Mode ..........................................................
Table 7.9
Register Functions in Normal Mode ......................................................................
Table 7.10 Register Functions in Block Transfer Mode...........................................................
Table 7.11 DMAC Channel Priority Order ..............................................................................
Table 7.12 Interrupt Sources and Priority Order ......................................................................
215
241
244
246
249
252
256
259
262
282
287
Section 8 Data Transfer Controller (DTC)
Table 8.1
Relationship between Activation Sources and DTCER Clearing...........................
Table 8.2
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................
Table 8.3
Chain Transfer Conditions .....................................................................................
Table 8.4
Register Function in Normal Mode........................................................................
Table 8.5
Register Function in Repeat Mode .........................................................................
Table 8.6
Register Function in Block Transfer Mode ............................................................
Table 8.7
DTC Execution Status ............................................................................................
Table 8.8
Number of States Required for Each Execution Status ..........................................
301
304
308
308
309
310
314
315
Section 9 I/O Ports
Table 9.1
Port Functions ........................................................................................................
Table 9.2
MOS Input Pull-Up States (Port A)........................................................................
Table 9.3
MOS Input Pull-Up States (Port B)........................................................................
Table 9.4
MOS Input Pull-Up States (Port C)........................................................................
324
372
376
380
Rev. 5.00 Aug 02, 2006 page xlviii of liv
Table 9.5
Table 9.6
MOS Input Pull-Up States (Port D)........................................................................ 384
MOS Input Pull-Up States (Port E) ........................................................................ 388
Section 10
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
Table 10.12
Table 10.13
Table 10.14
Table 10.15
Table 10.16
Table 10.17
Table 10.18
Table 10.19
Table 10.20
Table 10.21
Table 10.22
Table 10.23
Table 10.24
Table 10.25
Table 10.26
Table 10.27
Table 10.28
Table 10.29
Table 10.30
Table 10.31
Table 10.32
Table 10.33
Table 10.34
Table 10.35
Table 10.36
16-Bit Timer Pulse Unit (TPU)
TPU Functions........................................................................................................
Pin Configuration ...................................................................................................
CCLR2 to CCLR0 (Channels 0 and 3)...................................................................
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ..........................................................
TPSC2 to TPSC0 (Channel 0)................................................................................
TPSC2 to TPSC0 (Channel 1)................................................................................
TPSC2 to TPSC0 (Channel 2)................................................................................
TPSC2 to TPSC0 (Channel 3)................................................................................
TPSC2 to TPSC0 (Channel 4)................................................................................
TPSC2 to TPSC0 (Channel 5)................................................................................
MD3 to MD0..........................................................................................................
TIORH_0 ..............................................................................................................
TIORL_0 ..............................................................................................................
TIOR_1 ..............................................................................................................
TIOR_2 ..............................................................................................................
TIORH_3 ..............................................................................................................
TIORL_3 ..............................................................................................................
TIOR_4 ..............................................................................................................
TIOR_5 ..............................................................................................................
TIORH_0 ..............................................................................................................
TIORL_0 ..............................................................................................................
TIOR_1 ..............................................................................................................
TIOR_2 ..............................................................................................................
TIORH_3 ..............................................................................................................
TIORL_3 ..............................................................................................................
TIOR_4 ..............................................................................................................
TIOR_5 ..............................................................................................................
Register Combinations in Buffer Operation ...........................................................
Cascaded Combinations .........................................................................................
PWM Output Registers and Output Pins ................................................................
Clock Input Pins in Phase Counting Mode.............................................................
Up/Down-Count Conditions in Phase Counting Mode 1 .......................................
Up/Down-Count Conditions in Phase Counting Mode 2 .......................................
Up/Down-Count Conditions in Phase Counting Mode 3 .......................................
Up/Down-Count Conditions in Phase Counting Mode 4 .......................................
TPU Interrupts........................................................................................................
402
405
409
409
410
410
411
411
412
412
414
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
448
452
455
459
461
462
463
464
467
Rev. 5.00 Aug 02, 2006 page xlix of liv
Section 11 Programmable Pulse Generator (PPG)
Table 11.1 Pin Configuration ................................................................................................... 487
Section 12 8-Bit Timers (TMR)
Table 12.1 Pin Configuration ...................................................................................................
Table 12.2 Clock Input to TCNT and Count Condition ...........................................................
Table 12.3 8-Bit Timer Interrupt Sources ................................................................................
Table 12.4 Timer Output Priorities ..........................................................................................
Table 12.5 Switching of Internal Clock and TCNT Operation ................................................
509
512
521
525
526
Section 13 Watchdog Timer
Table 13.1 Pin Configuration ................................................................................................... 530
Table 13.2 WDT Interrupt Source............................................................................................ 536
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.1 Pin Configuration ...................................................................................................
Table 14.2 Relationships between N Setting in BRR and Bit Rate B ......................................
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) ..................................
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)..................
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ......................
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)......
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372) .......................................................................................
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372) .......................................................................................................
Table 14.10 Serial Transfer Formats (Asynchronous Mode) .....................................................
Table 14.11 SSR Status Flags and Receive Data Handling........................................................
Table 14.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................
Table 14.13 SCI Interrupt Sources .............................................................................................
Table 14.14 Interrupt Sources ....................................................................................................
544
564
565
567
568
569
570
571
572
577
585
618
620
621
Section 15 I2C Bus Interface2 (IIC2) (Option)
Table 15.1 Pin Configuration ................................................................................................... 631
Table 15.2 Transfer Rate .......................................................................................................... 634
Table 15.3 Interrupt Requests .................................................................................................. 658
Table 15.4 Time for monitoring SCL....................................................................................... 659
Section 16 A/D Converter
Table 16.1 Pin Configuration ................................................................................................... 663
Rev. 5.00 Aug 02, 2006 page l of liv
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Analog Input Channels and Corresponding ADDR Registers................................
A/D Conversion Time (Single Mode) ....................................................................
A/D Conversion Time (Scan Mode).......................................................................
A/D Converter Interrupt Source .............................................................................
Analog Pin Specifications ......................................................................................
665
672
672
673
679
Section 17 D/A Converter
Table 17.1 Pin Configuration ................................................................................................... 683
Table 17.2 Control of D/A Conversion .................................................................................... 685
Section 19 Flash Memory (0.35-µ
µm F-ZTAT Version)
Table 19.1 Differences between Boot Mode and User Program Mode.................................... 692
Table 19.2 Pin Configuration ................................................................................................... 697
Table 19.3 Erase Blocks........................................................................................................... 701
Table 19.4 Setting On-Board Programming Mode................................................................... 702
Table 19.5 Boot Mode Operation............................................................................................. 704
Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
is Possible............................................................................................................... 705
Table 19.7 Flash Memory Operating States ............................................................................. 711
Section 20 Flash Memory (0.18-µ
µm F-ZTAT Version)
Table 20.1 Comparison of Programming Modes .....................................................................
Table 20.2 Pin Configuration ...................................................................................................
Table 20.3 Register/Parameter and Target Mode .....................................................................
Table 20.4 Parameters and Target Modes ................................................................................
Table 20.5 Setting On-Board Programming Mode...................................................................
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI ..........
Table 20.7 Executable MAT ....................................................................................................
Table 20.8 (1) Useable Area for Programming in User Program Mode ......................................
Table 20.8 (2) Useable Area for Erasure in User Program Mode................................................
Table 20.8 (3) Useable Area for Programming in User Boot Mode ............................................
Table 20.8 (4) Useable Area for Erasure in User Boot Mode......................................................
Table 20.9 Hardware Protection...............................................................................................
Table 20.10 Software Protection ................................................................................................
Table 20.11 Inquiry and Selection Commands...........................................................................
Table 20.12 Programming/Erasing Command ...........................................................................
Table 20.13 Status Code.............................................................................................................
Table 20.14 Error Code..............................................................................................................
Table 20.15 User Branch Processing Start Intervals ..................................................................
721
726
727
736
748
750
769
770
772
774
776
778
779
786
799
808
809
810
Rev. 5.00 Aug 02, 2006 page li of liv
Section 22 Clock Pulse Generator
Table 22.1 Damping Resistance Value .................................................................................... 816
Table 22.2 Crystal Oscillator Characteristics ........................................................................... 817
Table 22.3 External Clock Input Conditions ............................................................................ 818
Section 23 Power-Down Modes
Table 23.1 Operating Modes and Internal States of the LSI .................................................... 824
Table 23.2 Oscillation Stabilization Time Settings .................................................................. 832
Table 23.3 φ Pin State in Each Processing State ...................................................................... 836
Section 25
Table 25.1
Table 25.2
Table 25.3
Table 25.4
Table 25.5
Table 25.6
Table 25.7
Table 25.8
Table 25.9
Table 25.10
Table 25.11
Table 25.12
Table 25.13
Table 25.14
Table 25.15
Table 25.16
Table 25.17
Table 25.18
Table 25.19
Table 25.20
Table 25.21
Table 25.22
Table 25.23
Table 25.24
Table 25.25
Table 25.26
Table 25.27
Table 25.28
Table 25.29
Electrical Characteristics
Absolute Maximum Ratings...................................................................................
DC Characteristics (1) ............................................................................................
DC Characteristics (2) ............................................................................................
Permissible Output Currents ..................................................................................
Clock Timing..........................................................................................................
Control Signal Timing............................................................................................
Bus Timing (1) .......................................................................................................
Bus Timing (2) .......................................................................................................
DMAC Timing .......................................................................................................
Timing of On-Chip Peripheral Modules.................................................................
A/D Conversion Characteristics .............................................................................
D/A Conversion Characteristics .............................................................................
Absolute Maximum Ratings...................................................................................
DC Characteristics (1) ............................................................................................
DC Characteristics (2) ............................................................................................
Permissible Output Currents ..................................................................................
Clock Timing..........................................................................................................
Control Signal Timing............................................................................................
Bus Timing (1) .......................................................................................................
Bus Timing (2) .......................................................................................................
DMAC Timing .......................................................................................................
Timing of On-Chip Peripheral Modules.................................................................
A/D Conversion Characteristics .............................................................................
D/A Conversion Characteristics .............................................................................
Flash Memory Characteristics................................................................................
Absolute Maximum Ratings...................................................................................
DC Characteristics..................................................................................................
DC Characteristics..................................................................................................
Permissible Output Currents ..................................................................................
Rev. 5.00 Aug 02, 2006 page lii of liv
873
874
875
876
878
880
882
884
901
904
910
910
911
912
913
914
915
916
917
919
920
921
923
923
924
926
927
928
929
Table 25.30
Table 25.31
Table 25.32
Table 25.33
Table 25.34
Table 25.35
Table 25.36
Table 25.37
Table 25.38
Clock Timing..........................................................................................................
Control Signal Timing............................................................................................
Bus Timing (1) .......................................................................................................
Bus Timing (2) .......................................................................................................
DMAC Timing .......................................................................................................
Timing of On-Chip Peripheral Modules.................................................................
A/D Conversion Characteristics .............................................................................
D/A Conversion Characteristics .............................................................................
Flash Memory Characteristics (0.18-µm F-ZTAT Version) ..................................
930
931
932
934
935
936
938
938
939
Appendix
Table D.1
Execution State of Instructions............................................................................... 954
Rev. 5.00 Aug 02, 2006 page liii of liv
Rev. 5.00 Aug 02, 2006 page liv of liv
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
DMA controller (DMAC)
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
I2C bus interface 2 (IIC2)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
Rev. 5.00 Aug 02, 2006 page 1 of 980
REJ09B0050-0500
Section 1 Overview
• On-chip memory
ROM Type
Model
ROM
RAM
Remarks
Flash memory version HD64F2368F
512 kbytes
32 kbytes
H8S/2368
0.18 µm F-ZTAT Group
HD64F2367F
384 kbytes
24 kbytes
HD64F2364
384 kbytes
32 kbytes
H8S/2368
0.18 µm F-ZTAT Group
HD64F2362F
256 kbytes
32 kbytes
H8S/2368
0.18 µm F-ZTAT Group
HD64F2361
256 kbytes
24 kbytes
H8S/2368
0.18 µm F-ZTAT Group
HD64F2360
256 kbytes
16 kbytes
H8S/2368
0.18 µm F-ZTAT Group
Masked ROM version HD6432365
256 kbytes
16 kbytes
ROMless version
16 kbytes
HD6412363
• General I/O ports
I/O pins: 83
Input-only pins: 11
• Supports various power-down states
• Compact package
Package
Code
Body Size
Pin Pitch
TFP-120
1
TFP-120 (TFP-120V* )
14.0 × 14.0 mm
0.4 mm
2
QFP-128*
1
FP-128B (FP-128BV* )
14.0 × 20.0 mm
Notes: 1. Pb free version
2. Not supported by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 2 of 980
REJ09B0050-0500
0.5 mm
Section 1 Overview
1.2
Block Diagram
Port 8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
RAM
SCI × 5 channels
I2C bus interface 2 (option)
P85/SCK3
P83/RxD3
P81/TxD3
Port A
DMAC
ROM *
(Flash memory
Mask ROM)
Port B
Port F
DTC
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
PG6/BREQ
PG5/BACK
PG4/CS4/BREQO
PG3/CS3/RAS3
PG2/CS2/RAS2
PG1/CS1
PG0/CS0
Interrupt controller
Port G
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1/CS5/UCAS
PF0/WAIT/OE
PA7/A23/CS7/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
Port 3
H8S/2000 CPU
Clock
pulse
generator
Bus controller
Internal data bus
PLL
Peripheral address bus
Port E
Peripheral data bus
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Port D
Internal address bus
MD2
MD1
MD0
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
VCC
VCC
VCC
VCC
VCC
PLLVCC
PLLVSS
VSS
VSS
VSS
VSS
VSS
VSS
Figures 1.1 and 1.2 show the internal block diagrams of this LSI.
TPU × 6 channels
8-bit D/A converter
Port 5
10-bit A/D converter
PPG
P53/ADTRG//IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port 9
P95/AN13/DA3
P94/AN12/DA2
P20/PO0/TIOCA3/TMRI0
P21/PO1/TIOCB3/TMRI1
P22/PO2/TIOCC3/TMCI0
P23/PO3/TIOCD3/TxD4/TMCI1
P24/PO4/TIOCA4/RxD4/TMO0
P25/PO5/TIOCB4/TMO1
P26/PO6/TIOCA5
P27/PO7/TIOCB5
Port 4
P47/AN7/(IRQ7)
P46/AN6/(IRQ6)
P45/AN5/(IRQ5)
P44/AN4/(IRQ4)
P43/AN3/(IRQ3)
P42/AN2/(IRQ2)
P41/AN1/(IRQ1)
P40/AN0/(IRQ0)
Port 2
Vref
AVCC
AVSS
Port 1
P10/PO8/TIOCA0/DREQ0
P11/PO9/TIOCB0/DREQ1
P12/PO10/TIOCC0/TCLKA/TEND0
P13/PO11/TIOCD0/TCLKB/TEND1
P14/PO12/TIOCA1/DACK0
P15/PO13/TIOCB1/TCLKC/DACK1
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
TMR × 2 channels
Note: * The ROMless version has no on-chip ROM.
Figure 1.1 Internal Block Diagram of H8S/2367F, H8S/2365, and H8S/2363
Rev. 5.00 Aug 02, 2006 page 3 of 980
REJ09B0050-0500
Port 8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
RAM
SCI × 5 channels
I2C bus interface 2 (option)
P85/SCK3
P83/RxD3
P81/TxD3
Port A
DMAC
ROM
(Flash memory)
Port B
Port F
DTC
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
Port C
PG6/BREQ
PG5/BACK
PG4/CS4/BREQO
PG3/CS3/RAS3
PG2/CS2/RAS2
PG1/CS1
PG0/CS0
Interrupt controller
Port G
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1/CS5/UCAS
PF0/WAIT/OE
PA7/A23/CS7/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
Port 3
H8S/2000 CPU
Clock
pulse
generator
Bus controller
Internal data bus
PLL
Peripheral address bus
Port E
Peripheral data bus
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Port D
Internal address bus
MD2
MD1
MD0
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
VCC
VCC
VCC
VCC
PLLVCC
PLLVSS
VSS
VSS
VSS
VSS
VSS
VSS
VCL
Section 1 Overview
TPU × 6 channels
8-bit D/A converter
Port 5
10-bit A/D converter
PPG
P53/ADTRG//IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port 9
P95/AN13/DA3
P94/AN12/DA2
P20/PO0/TIOCA3/TMRI0
P21/PO1/TIOCB3/TMRI1
P22/PO2/TIOCC3/TMCI0
P23/PO3/TIOCD3/TxD4/TMCI1
P24/PO4/TIOCA4/RxD4/TMO0
P25/PO5/TIOCB4/TMO1
P26/PO6/TIOCA5
P27/PO7/TIOCB5
Port 4
P47/AN7/(IRQ7)
P46/AN6/(IRQ6)
P45/AN5/(IRQ5)
P44/AN4/(IRQ4)
P43/AN3/(IRQ3)
P42/AN2/(IRQ2)
P41/AN1/(IRQ1)
P40/AN0/(IRQ0)
Port 2
Vref
AVCC
AVSS
Port 1
P10/PO8/TIOCA0/DREQ0
P11/PO9/TIOCB0/DREQ1
P12/PO10/TIOCC0/TCLKA/TEND0
P13/PO11/TIOCD0/TCLKB/TEND1
P14/PO12/TIOCA1/DACK0
P15/PO13/TIOCB1/TCLKC/DACK1
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
TMR × 2 channels
Figure 1.2 Internal Block Diagram of H8S/2368 0.18 µm F-ZTAT Group
Rev. 5.00 Aug 02, 2006 page 4 of 980
REJ09B0050-0500
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Arrangement
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PG1/CS1
PG0/CS0
STBY
VSS
P81/TxD3
P83/RxD3
VCC
VCC
EXTAL
XTAL
VSS
PF7/φ
PLLVSS
RES
PLLVCC
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1/CS5/UCAS
PF0/WAIT/OE
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Figures 1.3 to 1.5 show the pin arrangements of this LSI.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
TFP-120
(Top view)
VCC
PE7/D7
VSS
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P85/SCK3
P27/PO7/TIOCB5
P26/PO6/TIOCA5
P25/PO5/TIOCB4/TMO1
P24/PO4/TIOCA4/TMO0/RxD4
P23/PO3/TIOCD3/TMCI1/TxD4
P22/PO2/TIOCC3/TMCI0
P21/PO1/TIOCB3/TMRI1
P20/PO0/TIOCA3/TMRI0
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC/DACK1
P14/PO12/TIOCA1/DACK0
P13/PO11/TIOCD0/TCLKB/TEND1
P12/PO10/TIOCC0/TCLKA/TEND0
P11/PO9/TIOCB0/DREQ1
P10/PO8/TIOCA0/DREQ0
VCC
NMI
WDTOVF
MD2
VCC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
VSS
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
VSS
PB5/A13
PB6/A14
PB7/A15
PA0/A16
VSS
PA1/A17
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/CS7/IRQ7
EMLE*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PG2/CS2/RAS2
PG3/CS3/RAS3
AVCC
Vref
P40/AN0/(IRQ0)
P41/AN1/(IRQ1)
P42/AN2/(IRQ2)
P43/AN3/(IRQ3)
P44/AN4/(IRQ4)
P45/AN5/(IRQ5)
P46/AN6/(IRQ6)
P47/AN7/(IRQ7)
P94/AN12/DA2
P95/AN13/DA3
AVSS
PG4/CS4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
Note: * This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version,
the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.
Figure 1.3 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363
Rev. 5.00 Aug 02, 2006 page 5 of 980
REJ09B0050-0500
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PG1/CS1
PG0/CS0
STBY
VSS
P81/TxD3
P83/RxD3
VCC
VCC
EXTAL
XTAL
VSS
PF7/φ
PLLVSS
RES
PLLVCC
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1/CS5/UCAS
PF0/WAIT/OE
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Section 1 Overview
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
TFP-120
(Top view)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC
PE7/D7
VSS
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P85/SCK3
P27/PO7/TIOCB5
P26/PO6/TIOCA5
P25/PO5/TIOCB4/TMO1
P24/PO4/TIOCA4/TMO0/RxD4
P23/PO3/TIOCD3/TMCI1/TxD4
P22/PO2/TIOCC3/TMCI0
P21/PO1/TIOCB3/TMRI1
P20/PO0/TIOCA3/TMRI0
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC/DACK1
P14/PO12/TIOCA1/DACK0
P13/PO11/TIOCD0/TCLKB/TEND1
P12/PO10/TIOCC0/TCLKA/TEND0
P11/PO9/TIOCB0/DREQ1
P10/PO8/TIOCA0/DREQ0
VCL*2
NMI
WDTOVF
MD2
VCC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
VSS
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
VSS
PB5/A13
PB6/A14
PB7/A15
PA0/A16
VSS
PA1/A17
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/CS7/IRQ7
EMLE*1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PG2/CS2/RAS2
PG3/CS3/RAS3
AVCC
Vref
P40/AN0/(IRQ0)
P41/AN1/(IRQ1)
P42/AN2/(IRQ2)
P43/AN3/(IRQ3)
P44/AN4/(IRQ4)
P45/AN5/(IRQ5)
P46/AN6/(IRQ6)
P47/AN7/(IRQ7)
P94/AN12/DA2
P95/AN13/DA3
AVSS
PG4/CS4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
Notes: 1. This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version,
the on-chip emulator function is enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.
2. A capacitor should be externally connected to the VCL pin.
33
0.1 µF (Recommended value)
Figure 1.4 Pin Arrangement of H8S/2368 0.18 µm F-ZTAT Group
Rev. 5.00 Aug 02, 2006 page 6 of 980
REJ09B0050-0500
FP-128B
(Top view)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VSS
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P85/SCK3
P27/PO7/TIOCB5
P26/PO6/TIOCA5
P25/PO5/TIOCB4/TMO1
P24/PO4/TIOCA4/TMO0/RxD4
P23/PO3/TIOCD3/TMCI1/TxD4
P22/PO2/TIOCC3/TMCI0
P21/PO1/TIOCB3/TMRI1
P20/PO0/TIOCA3/TMRI0
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC/DACK1
P14/PO12/TIOCA1/DACK0
P13/PO11/TIOCD0/TCLKB/TEND1
P12/PO10/TIOCC0/TCLKA/TEND0
P11/PO9/TIOCB0/DREQ1
P10/PO8/TIOCA0/DREQ0
VCC
MD0
MD1
VSS
VSS
MD2
VCC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
VSS
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
VSS
PB5/A13
PB6/A14
PB7/A15
PA0/A16
VSS
PA1/A17
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/CS7/IRQ7
EMLE*2
VSS
VSS
WDTOVF
NMI
AVCC
Vref
P40/AN0/(IRQ0)
P41/AN1/(IRQ1)
P42/AN2/(IRQ2)
P43/AN3/(IRQ3)
P44/AN4/(IRQ4)
P45/AN5/(IRQ5)
P46/AN6/(IRQ6)
P47/AN7/(IRQ7)
P94/AN12/DA2
P95/AN13/DA3
AVSS
PG4/CS4/BREQO
PG5/BACK
PG6/BREQ
P50/TxD2/IRQ0
P51/RxD2/IRQ1
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PG3/CS3/RAS3
PG2/CS2/RAS2
VSS
VSS
PG1/CS1
PG0/CS0
STBY
VSS
P81/TxD3
P83/RxD3
VCC
VCC
EXTAL
XTAL
VSS
PF7/φ
PLLVSS
RES
PLLVCC
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1/CS5/UCAS
PF0/WAIT/OE
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
VSS
NC*1
VCC
PE7/D7
Section 1 Overview
Notes: FP-128B is not supported by the H8S/2368 0.18 µm F-ZTAT Group.
1. The NC pin should be fixed to Vss or should be open.
2. This is an emulator enable pin. Normally, this pin should be set to low. If this pin goes high in the flash memory version, the on-chip emulator function is
enabled. At this time, pins P53, PG4, PG5, PG6, and WDTOVF function only for the on-chip emulator.
Figure 1.5 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363
Rev. 5.00 Aug 02, 2006 page 7 of 980
REJ09B0050-0500
Section 1 Overview
1.3.2
Pin Arrangement in Each Operating Mode
Table 1.1
Pin Arrangement in Each Operating Mode
Pin No.
Pin Name
TFP-120
QFP-128* Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
1
5
MD2
MD2
MD2
MD2
MD2
Vss
2
6
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
3
7
A0
A0
PC0/A0
PC0/A0
PC0
A0
4
8
A1
A1
PC1/A1
PC1/A1
PC1
A1
5
9
A2
A2
PC2/A2
PC2/A2
PC2
A2
6
10
A3
A3
PC3/A3
PC3/A3
PC3
A3
7
11
A4
A4
PC4/A4
PC4/A4
PC4
A4
8
12
Vss
Vss
Vss
Vss
Vss
Vss
9
13
A5
A5
PC5/A5
PC5/A5
PC5
A5
10
14
A6
A6
PC6/A6
PC6/A6
PC6
A6
11
15
A7
A7
PC7/A7
PC7/A7
PC7
A7
12
16
A8
A8
PB0/A8
PB0/A8
PB0
A8
13
17
A9
A9
PB1/A9
PB1/A9
PB1
A9
14
18
A10
A10
PB2/A10
PB2/A10
PB2
A10
15
19
A11
A11
PB3/A11
PB3/A11
PB3
A11
16
20
A12
A12
PB4/A12
PB4/A12
PB4
A12
17
21
Vss
Vss
Vss
Vss
Vss
Vss
18
22
A13
A13
PB5/A13
PB5/A13
PB5
A13
19
23
A14
A14
PB6/A14
PB6/A14
PB6
A14
20
24
A15
A15
PB7/A15
PB7/A15
PB7
A15
21
25
A16
A16
PA0/A16
PA0/A16
PA0
A16
22
26
Vss
Vss
Vss
Vss
Vss
Vss
23
27
A17
A17
PA1/A17
PA1/A17
PA1
A17
24
28
A18
A18
PA2/A18
PA2/A18
PA2
A18
25
29
A19
A19
PA3/A19
PA3/A19
PA3
NC
26
30
A20/IRQ4
A20/IRQ4
PA4/A20/IRQ4
PA4/A20/IRQ4
PA4/IRQ4
NC
27
31
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/A21/IRQ5
PA5/IRQ5
PA5/IRQ5
NC
28
32
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/A22/IRQ6
PA6/IRQ6
PA6/IRQ6
NC
Mode 7
1
Rev. 5.00 Aug 02, 2006 page 8 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Pin Name
Mode 7
TFP-120
QFP-128*1 Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
29
33
PA7/IRQ7
NC
PA7/A23/CS7/
PA7/A23/CS7/
PA7/A23/CS7/
PA7/CS7/
IRQ7
IRQ7
IRQ7
IRQ7
30
34
EMLE
EMLE
EMLE
EMLE
EMLE
EMLE
35
Vss
Vss
Vss
Vss
Vss
Vss
36
Vss
Vss
Vss
Vss
Vss
Vss
31
37
WDTOVF
WDTOVF
WDTOVF
WDTOVF
WDTOVF
NC
32
38
NMI
NMI
NMI
NMI
NMI
Vcc
33
39
2
VCC (VCL* )
2
VCC (VCL* )
2
VCC (VCL* )
2
VCC (VCL* )
2
VCC (VCL* )
VCC (VCL* )
34
40
P10/PO8/
P10/PO8/
P10/PO8/
P10/PO8/
P10/PO8/
NC
TIOCA0/
TIOCA0/
TIOCA0/
TIOCA0/
TIOCA0/
DREQ0
DREQ0
DREQ0
DREQ0
DREQ0
P11/PO9/
P11/PO9/
P11/PO9/
P11/PO9/
P11/PO9/
TIOCB0/
TIOCB0/
TIOCB0/
TIOCB0/
TIOCB0/
DREQ1
DREQ1
DREQ1
DREQ1
DREQ1
P12/PO10/
P12/PO10/
P12/PO10/
P12/PO10/
P12/PO10/
35
36
41
42
2
NC
NC
TIOCC0/TCLKA/ TIOCC0/TCLKA/ TIOCC0/TCLKA/ TIOCC0/TCLKA/ TIOCC0/TCLKA/
37
43
TEND0
TEND0
TEND0
TEND0
TEND0
P13/PO11/
P13/PO11/
P13/PO11/
P13/PO11/
P13/PO11/
NC
TIOCD0/TCLKB/ TIOCD0/TCLKB/ TIOCD0/TCLKB/ TIOCD0/TCLKB/ TIOCD0/TCLKB/
38
39
44
45
TEND1
TEND1
TEND1
TEND1
TEND1
P14/PO12/
P14/PO12/
P14/PO12/
P14/PO12/
P14/PO12/
TIOCA1/
TIOCA1/
TIOCA1/
TIOCA1/
TIOCA1/
DACK0
DACK0
DACK0
DACK0
DACK0
P15/PO13/
P15/PO13/
P15/PO13/
P15/PO13/
P15/PO13/
NC
NC
TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/ TIOCB1/TCLKC/
40
41
46
47
DACK1
DACK1
DACK1
DACK1
DACK1
P16/PO14/
P16/PO14/
P16/PO14/
P16/PO14/
P16/PO14/
TIOCA2
TIOCA2
TIOCA2
TIOCA2
TIOCA2
P17/PO15/
P17/PO15/
P17/PO15/
P17/PO15/
P17/PO15/
NC
NC
TIOCB2/TCLKD TIOCB2/TCLKD TIOCB2/TCLKD TIOCB2/TCLKD TIOCB2/TCLKD
42
48
P20/PO0/
P20/PO0/
P20/PO0/
P20/PO0/
P20/PO0/
NC
TIOCA3/TMRI0 TIOCA3/(TMRI0) TIOCA3/(TMRI0) TIOCA3/(TMRI0) TIOCA3/(TMRI0)
43
49
P21/PO1/
P21/PO1/
P21/PO1/
P21/PO1/
P21/PO1/
NC
TIOCB3/TMRI1 TIOCB3/TMRI1 TIOCB3/TMRI1 TIOCB3/TMRI1 TIOCB3/TMRI1
44
50
P22/PO2/
P22/PO2/
P22/PO2/
P22/PO2/
P22/PO2/
OE
TIOCC3/TMCI0 TIOCC3/TMCI0 TIOCC3/TMCI0 TIOCC3/TMCI0 TIOCC3/TMCI0
Rev. 5.00 Aug 02, 2006 page 9 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Pin Name
Mode 7
TFP-120
QFP-128*1 Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
45
51
P23/PO3/
P23/PO3/
P23/PO3/
P23/PO3/
CE
P23/PO3/
TIOCD3/TMCI1/ TIOCD3/TMCI1/ TIOCD3/TMCI1/ TIOCD3/TMCI1/ TIOCD3/TMCI1/
46
52
TxD4
TxD4
TxD4
TxD4
TxD4
P24/PO4/
P24/PO4/
P24/PO4/
P24/PO4/
P24/PO4/
WE
TIOCA4/TMO0/ TIOCA4/TMO0/ TIOCA4/TMO0/ TIOCA4/TMO0/ TIOCA4/TMO0/
47
48
49
53
54
55
RxD4
RxD4
RxD4
RxD4
RxD4
P25/PO5/
P25/PO5/
P25/PO5/
P25/PO5/
P25/PO5/
TIOCB4/TMO1
TIOCB4/TMO1
TIOCB4/TMO1
TIOCB4/TMO1
TIOCB4/TMO1
P26/PO6/
P26/PO6/
P26/PO6/
P26/PO6/
P26/PO6/
TIOCA5
TIOCA5
TIOCA5
TIOCA5
TIOCA5
P27/PO7/
P27/PO7/
P27/PO7/
P27/PO7/
P27/PO7/
TIOCB5
TIOCB5
TIOCB5
TIOCB5
TIOCB5
Vss
NC
NC
50
56
P85/SCK3
P85/SCK3
P85/SCK3
P85/SCK3
P85/SCK3
NC
51
57
D0
PE0/D0
PE0/D0
PE0/D0
PE0
NC
52
58
D1
PE1/D1
PE1/D1
PE1/D1
PE1
NC
53
59
D2
PE2/D2
PE2/D2
PE2/D2
PE2
NC
54
60
D3
PE3/D3
PE3/D3
PE3/D3
PE3
NC
55
61
D4
PE4/D4
PE4/D4
PE4/D4
PE4
NC
56
62
D5
PE5/D5
PE5/D5
PE5/D5
PE5
NC
57
63
D6
PE6/D6
PE6/D6
PE6/D6
PE6
NC
58
64
Vss
Vss
Vss
Vss
Vss
Vss
59
65
D7
PE7/D7
PE7/D7
PE7/D7
PE7
NC
60
66
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
67
NC
NC
NC
NC
NC
NC
68
Vss
Vss
Vss
Vss
Vss
Vss
61
69
D8
D8
D8
D8
PD0
I/O0
62
70
D9
D9
D9
D9
PD1
I/O1
63
71
D10
D10
D10
D10
PD2
I/O2
64
72
D11
D11
D11
D11
PD3
I/O3
65
73
D12
D12
D12
D12
PD4
I/O4
66
74
D13
D13
D13
D13
PD5
I/O5
67
75
D14
D14
D14
D14
PD6
I/O6
Rev. 5.00 Aug 02, 2006 page 10 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Pin Name
Mode 7
TFP-120
QFP-128*1 Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
68
76
D15
D15
D15
D15
PD7
I/O7
69
77
PF0/WAIT/OE
PF0/WAIT/OE
PF0/WAIT/OE
PF0/WAIT/OE
PF0
NC
70
78
PF1/CS5/
PF1/CS5/
PF1/CS5/
PF1/CS5/
PF1
NC
UCAS
UCAS
UCAS
UCAS
PF2
NC
71
79
PF2/CS6/
PF2/CS6/
PF2/CS6/
PF2/CS6/
LCAS
LCAS
LCAS
LCAS
PF3/LWR
PF3/LWR
PF3/LWR
PF3
NC
72
80
PF3/LWR
73
81
HWR
HWR
HWR
HWR
PF4
NC
74
82
RD
RD
RD
RD
PF5
NC
75
83
PF6/AS
PF6/AS
PF6/AS
PF6/AS
PF6
NC
76
84
PLLVcc
PLLVcc
PLLVcc
PLLVcc
PLLVcc
Vcc
77
85
RES
RES
RES
RES
RES
RES
78
86
PLLVss
PLLVss
PLLVss
PLLVss
PLLVss
Vss
79
87
PF7/φ
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
80
88
Vss
Vss
Vss
Vss
Vss
Vss
81
89
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
82
90
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
83
91
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
84
92
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
85
93
P83/RxD3
P83/RxD3
P83/RxD3
P83/RxD3
P83/RxD3
NC
86
94
P81/TxD3
P81/TxD3
P81/TxD3
P81/TxD3
P81/TxD3
NC
87
95
Vss
Vss
Vss
Vss
Vss
Vss
88
96
STBY
STBY
STBY
STBY
STBY
Vcc
89
97
PG0/CS0
PG0/CS0
PG0/CS0
PG0/CS0
PG0
NC
90
98
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1
NC
99
Vss
Vss
Vss
Vss
Vss
Vss
100
Vss
Vss
Vss
Vss
Vss
Vss
91
101
PG2/CS2/
PG2/CS2/
PG2/CS2/
PG2/CS2/
PG2
NC
RAS2
RAS2
RAS2
RAS2
PG3/CS3/
PG3/CS3/
PG3/CS3/
PG3/CS3/
PG3
NC
RAS3
RAS3
RAS3
RAS3
AVcc
AVcc
AVcc
AVcc
AVcc
Vcc
92
93
102
103
Rev. 5.00 Aug 02, 2006 page 11 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Pin Name
Mode 7
TFP-120
QFP-128*1 Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
94
104
Vref
Vref
Vref
Vref
Vref
NC
95
105
P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) NC
96
106
P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) NC
97
107
P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) NC
98
108
P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) P43/AN3/(IRQ3) NC
99
109
P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) P44/AN4/(IRQ4) NC
100
110
P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) P45/AN5/(IRQ5) NC
101
111
P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) P46/AN6/(IRQ6) NC
102
112
P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) P47/AN7/(IRQ7) NC
103
113
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
P94/AN12/DA2
NC
104
114
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
P95/AN13/DA3
NC
105
115
AVss
AVss
AVss
AVss
AVss
Vss
106
116
PG4/CS4/
BREQO
PG4/CS4/
BREQO
PG4/CS4/
BREQO
PG4/CS4/
BREQO
PG4
NC
107
117
PG5/BACK
PG5/BACK
PG5/BACK
PG5/BACK
PG5
NC
108
118
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6
NC
109
119
P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0
P50/TxD2/IRQ0
Vss
110
120
P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1
P51/RxD2/IRQ1
Vss
111
121
P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2
P52/SCK2/IRQ2
Vcc
112
122
P53/ADTRG/
P53/ADTRG/
P53/ADTRG/
P53/ADTRG/
P53/ADTRG/
NC
IRQ3
IRQ3
IRQ3
IRQ3
IRQ3
P35/SCK1/SCL0 NC
113
114
123
124
115
125
116
126
P35/SCK1/
P35/SCK1/
P35/SCK1/
P35/SCK1/
SCL0/(OE)
SCL0/(OE)
SCL0/(OE)
SCL0/(OE)
P34/SCK0/
P34/SCK0/
P34/SCK0/
P34/SCK0/
P34/SCK0/
SCK4/SDA0
SCK4/SDA0
SCK4/SDA0
SCK4/SDA0
SCK4/SDA0
NC
P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC
P32/RxD0/
P32/RxD0/
P32/RxD0/
P32/RxD0/
P32/RxD0/
IrRxD/SDA1
IrRxD/SDA1
IrRxD/SDA1
IrRxD/SDA1
IrRxD/SDA1
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
Vcc
117
127
P31/TxD1
118
128
P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC
119
1
MD0
MD0
MD0
MD0
MD0
Vss
120
2
MD1
MD1
MD1
MD1
MD1
Vss
Rev. 5.00 Aug 02, 2006 page 12 of 980
REJ09B0050-0500
NC
Section 1 Overview
Pin No.
Pin Name
Mode 7
TFP-120
QFP-128*1 Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
3
Vss
Vss
Vss
Vss
Vss
Vss
4
Vss
Vss
Vss
Vss
Vss
Vss
Notes: 1. Not supported by the H8S/2368 0.18 µm F-ZTAT Group.
2. Used as the VCL pin in the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 13 of 980
REJ09B0050-0500
Section 1 Overview
1.3.3
Pin Functions
Table 1.2
Pin Functions
Pin No.
TFP-120
QFP-128*
I/O
Function
Power Supply Vcc
2,33,60,
83,84
6,39,66,
91,92
Input
Power supply pins. VCC pins should
be connected to the system power
supply. The pin 33 of TFP-120,
which is used as the VCL pin in the
H8S/2368 0.18 µm F-ZTAT Group,
should not be connected to the
power supply. The pin should be
connected to VSS via 0.1-µF
(recommended value) capacitor
(placed close to the pins).
Vss
8,17,22,
58,80,87
3,4,12,21,
26,35,36,
64,68,88,
95,99,100
Input
Ground pins. VSS pins should be
connected to the system power
supply (0 V).
PLLVCC
76
84
Input
Power supply pin for the on-chip PLL
oscillator.
PLLVSS
78
86
Input
Ground pin for the on-chip PLL
oscillator.
XTAL
81
89
Input
For connection to a crystal oscillator.
See section 22, Clock Pulse
Generator for typical connection
diagrams for a crystal oscillator and
external clock input.
EXTAL
82
90
Input
For connection to a crystal oscillator.
The EXTAL pin can also input an
external clock. See section 22, Clock
Pulse Generator for typical
connection diagrams for a crystal
oscillator and external clock input.
0
79
87
Output Supplies the system clock to external
devices.
MD2
MD1
MD0
1,
120,
119
5,
2,
1
Input
Type
Clock
Operating
mode control
Symbol
Rev. 5.00 Aug 02, 2006 page 14 of 980
REJ09B0050-0500
These pins set the operating mode.
These pins should not be changed
while the MCU is operating.
Section 1 Overview
Pin No.
TFP-120
QFP-128*
I/O
Function
77
85
Input
Reset pin. When this pin is driven
low, the chip is reset.
STBY
88
96
Input
When this pin is driven low, a
transition is made to hardware
standby mode.
EMLE
30
34
Input
Enables emulator. This pin should
be connected to the power supply
(0 V).
Address bus
A23 to
A0
29 to 23,
21 to 18,
16 to 9,
7 to 3
33 to 27,
25 to 22,
20 to 13,
11 to 7
Output Address output pins.
Data bus
D15 to
D0
68 to 61,
59,
57 to 51
76 to 69,
65,
63 to 57
Input/
output
Bus control
CS7 to
CS0
29,71,70,
106,
92 to 89
33,79,78,
116,102,
101,98,97
Output Signals that select division areas 7
to 0 in the external address space.
AS
75
83
Output When this pin is low, it indicates
that address output on the address
bus is valid.
RD
74
82
Output When this pin is low, it indicates
that the external address space is
being read.
HWR
73
81
Output Strobe signal indicating that
external address space is to be
written, and the upper half (D15 to
D8) of the data bus is enabled.
Type
Symbol
System control RES
These pins constitute a bidirectional
data bus.
Write enable signal for accessing
the DRAM space.
LWR
72
80
Output Strobe signal indicating that
external address space is to be
written, and the lower half (D7 to
D0) of the data bus is enabled.
BREQ
108
118
Input
The external bus master requests
the bus to this LSI.
BREQO
106
116
Input
External bus request signal when
the internal bus master accesses
the external space in external bus
release state.
Rev. 5.00 Aug 02, 2006 page 15 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Type
Symbol
TFP-120
QFP-128*
I/O
Bus control
BACK
107
117
Output Indicates the bus is released to the
external bus master.
UCAS
70
78
Output Upper column address strobe
signal for accessing the 16-bit
DRAM space.
Function
Column address strobe signal for
accessing the 8-bit DRAM space.
LCAS
71
79
Output Lower column address strobe
signal for accessing the 16-bit
DRAM space.
RAS2
RAS3
91
92
101
102
Output Row address strobe signal for the
DRAM interface.
WAIT
69
77
Input
OE
(OE)
69,
113
77,
123
Output Output enable signal for accessing
the DRAM space.
Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
The output pins of OE and (OE) are
selected by the port function control
register 2 (PFCR2) of port 3.
Interrupt
signals
NMI
32
38
Input
33 to 30,
Input
IRQ7 to 29 to 26,
112 to 109, 122 to 119,
IRQ0
112 to 105
(IRQ7) to 102 to 95
(IRQ0)
Nonmaskable interrupt request pin.
Fix high when not used.
These pins request a maskable
interrupt.
The input pins of IRQn and (IRQn)
are selected by the IRQ pin select
register (ITSR) of the interrupt
controller. (n = 0 to 7)
DMA controller DREQ1
(DMAC)
DREQ0
35,
34
41,
40
Input
TEND1,
TEND0
37,
36
43,
42
Output These signals indicate the end of
DMAC data transfer.
DACK1,
DACK0
39,
38
45,
44
Output DMAC single address transfer
acknowledge signals.
Rev. 5.00 Aug 02, 2006 page 16 of 980
REJ09B0050-0500
These signals request DMAC
activation.
Section 1 Overview
Pin No.
TFP-120
QFP-128*
I/O
Function
41,
39,
37,
36
47,
45,
43,
42
Input
External clock input pins for the
timer.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
34,
35,
36,
37
40,
41,
42,
43
Input/
output
TGRA_0 to TGRD_0 input capture
input/output compare output/PWM
output pins.
TIOCA1
TIOCB1
38,
39
44,
45
Input/
output
TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
TIOCA2
TIOCB2
40,
41
46,
47
Input/
output
TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
TIOCA3
TIOCB3
TIOCC3
TIOCD3
42,
43,
44,
45
48,
49,
50,
51
Input/
output
TGRA_3 to TGRD_3 input capture
input/output compare output/PWM
output pins.
TIOCA4
TIOCB4
46,
47
52,
53
Input/
output
TGRA_4 and TGRB_4 input
capture input/output compare
output/PWM output pins.
TIOCA5
TIOCB5
48,
49
54,
55
Input/
output
TGRA_5 and TGRB_5 input
capture input/output compare
output/PWM output pins.
Programmable PO15 to
pulse generator PO0
(PPG)
41 to 34,
49 to42
47 to 40,
55 to 48
Output Pulse output pins.
8-bit timer
(TMR)
TMO0
TMO1
46,
47
52,
53
Output Waveform output pins with output
compare function.
TMCI0
TMCI1
44,
45
50,
51
Input
External event input pins.
TMRI0
TMRI1
42,
43
48,
49
Input
Counter reset input pins.
WDTOVF 31
37
Output Counter overflow signal output pin
in watchdog timer mode.
Type
Symbol
16-bit timer
TCLKD
pulse unit (TPU) TCLKC
TCLKB
TCLKA
Watchdog
Timer (WDT)
Rev. 5.00 Aug 02, 2006 page 17 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
TFP-120
QFP-128*
I/O
45,
86,
109,
117,
118
51,
94,
119,
127,
128
Output Data output pins.
46,
85,
110,
115,
116
52,
93,
120
125,
126
Input
Data input pins.
SCK4
SCK3
SCK2
SCK1
SCK0
114,
50,
111,
113,
114
124,
56,
121,
123,
124
Input/
output
Clock input/output pins.
IIC bus
SCL1
interface2 (IIC2) SCL0
115,
113
125,
123
Input/
output
IIC clock input/output pins.
SDA1
SDA0
116,
114
126,
124
Input/
output
IIC data input/output pins.
AN13,
AN12,
AN7 to
AN0
104 to 95
114 to 105
Input
Analog input pins.
ADTRG
112
122
Input
Pin for input of an external trigger to
start A/D conversion.
D/A converter
DA3,
DA2
104,
103
114,
113
Output Analog output pins.
A/D converter,
D/A converter
AVcc
93
103
Input
Type
Symbol
Serial
TxD4
communication TxD3
interface(SCI)/ TxD2
smart card
TxD1
interface (SCI_0 TxD0/
with IrDA
IrTxD
function)
RxD4
RxD3
RxD2
RxD1
RxD0/
IrRxD
A/D converter
Function
The analog power-supply pin for
the A/D converter and D/A
converter.
When the A/D converter and D/A
converter are not used, this pin
should be connected to the system
power supply (+3 V).
AVss
105
115
Input
The ground pin for the A/D
converter and D/A converter.
This pin should be connected to the
system power supply (0 V).
Rev. 5.00 Aug 02, 2006 page 18 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
Type
Symbol
TFP-120
QFP-128*
I/O
Function
A/D converter,
D/A converter
Vref
94
104
Input
The reference voltage input pin for
the A/D converter and D/A
converter.
When the A/D converter and D/A
converter are not used, this pin
should be connected to the system
power supply (+3 V).
I/O ports
P17 to
P10
41 to 34
47 to 40
Input/
output
Eight-bit input/output pins.
P27 to
P20
49 to 42
55 to 48
Input/
output
Eight-bit input/output pins.
P35 to
P30
113 to 118
123 to 128
Input/
output
Six-bit input/output pins.
P47 to
P40
102 to 95
112 to 105
Input
Eight-bit input pins.
P53 to
P50
112 to 109
122 to 119
Input/
output
Four-bit input/output pins.
P85,
P83,
P81
50,
85,
86
56,
93,
94
Input/
output
Three-bit input/output pins.
P95,
P94
104,
103
114,
113
Input
Two-bit input pins.
PA7 to
PA0
29 to 23,
21
33 to 27,
25
Input/
Eight-bit input/output pins.
PB7 to
PB0
20 to 18,
16 to 12
24 to 22,
20 to 16
Input/
PC7 to
PC0
11 to 9,
7 to 3
15 to 13,
11 to 7
Input/
PD7 to
PD0
68 to 61
76 to 69
Input/
PE7 to
PE0
59,
57 to 51
65,
63 to 57
Input/
PF7 to
PF0
79,
75 to 69
87,
83 to 77
Input/
output
Eight-bit input/output pins.
output
Eight-bit input/output pins.
output
Eight-bit input/output pins.
output
Eight-bit input/output pins.
output
Eight-bit input/output pins.
output
Rev. 5.00 Aug 02, 2006 page 19 of 980
REJ09B0050-0500
Section 1 Overview
Pin No.
QFP-128*
Type
Symbol
TFP-120
I/O ports
PG6 to
PG0
108 to 106, 118 to 116, Input/
92 to 89
102,101,
output
98,97
Note:
*
I/O
Function
Seven-bit input/output pins.
Not supported by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 20 of 980
REJ09B0050-0500
Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
• Upward-compatibility with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H CPU object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed operation
All frequently-used instructions are executed in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
CPUS211A_000020020100
Rev. 5.00 Aug 02, 2006 page 21 of 980
REJ09B0050-0500
Section 2 CPU
16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
Normal mode*
Advanced mode
Note: * For this LSI, normal mode is not available.
• Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
MULXS
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 5.00 Aug 02, 2006 page 22 of 980
REJ09B0050-0500
Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
Rev. 5.00 Aug 02, 2006 page 23 of 980
REJ09B0050-0500
Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space.
The mode is selected by the LSI's mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
• Address space
Linear access to a maximum address space of 64 kbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
• Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.
Rev. 5.00 Aug 02, 2006 page 24 of 980
REJ09B0050-0500
Section 2 CPU
Note: For this LSI, normal mode is not available.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
(SP
*2
Reserved*1*3
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
Rev. 5.00 Aug 02, 2006 page 25 of 980
REJ09B0050-0500
Section 2 CPU
2.2.2
Advanced Mode
• Address space
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
H'0000000B
H'0000000C
H'00000010
(Reserved for system use)
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 5.00 Aug 02, 2006 page 26 of 980
REJ09B0050-0500
Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
• Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.
EXR*1
SP
SP
Reserved*1*3
Reserved
PC
(24 bits)
(SP
*2
)
CCR
PC
(24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
Rev. 5.00 Aug 02, 2006 page 27 of 980
REJ09B0050-0500
Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'00000000
64 kbyte
16 Mbyte
H'FFFF
Program area
H'00FFFFFF
Data area
Not available
in this LSI
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * For this LSI, normal mode is not available.
Figure 2.5 Memory Map
Rev. 5.00 Aug 02, 2006 page 28 of 980
REJ09B0050-0500
Section 2 CPU
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Note: * For this LSI, the interrupt mask bit is not available.
Figure 2.6 CPU Internal Registers
Rev. 5.00 Aug 02, 2006 page 29 of 980
REJ09B0050-0500
Section 2 CPU
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
Rev. 5.00 Aug 02, 2006 page 30 of 980
REJ09B0050-0500
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit
Bit Name
Initial Value R/W
Description
7
T
0
Trace Bit
R/W
When this bit is set to 1, trace exception processing
starts every when an instruction is executed. When
this bit is cleared to 0, instructions are consecutively
executed.
6 to
–
1
–
3
Reserved
These bits are always read as 1.
2 to 0 I2
I1
I0
1
R/W
Interrupt Mask Bits 2 to 0
Specify interrupt request mask levels (0 to 7). For
details, see section 5, Interrupt Controller.
Rev. 5.00 Aug 02, 2006 page 31 of 980
REJ09B0050-0500
Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev. 5.00 Aug 02, 2006 page 32 of 980
REJ09B0050-0500
Section 2 CPU
Bit
Bit Name
Initial Value
R/W Description
7
I
1
R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
refer to section 5, Interrupt Controller.
6
UI
Undefined
R/W User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
For this LSI, Interrupt Mask Bit is not available.
5
H
Undefined
R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
4
U
Undefined
R/W User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined
R/W Negative Flag
Stores the value of the most significant bit of data as a sign
bit.
2
Z
Undefined
R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
1
V
Undefined
R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and cleared to
0 otherwise.
0
C
Undefined
R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0 otherwise.
Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Rev. 5.00 Aug 02, 2006 page 33 of 980
REJ09B0050-0500
Section 2 CPU
2.4.5
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Don't care
MSB
Figure 2.9 General Register Data Formats (1)
Rev. 5.00 Aug 02, 2006 page 34 of 980
REJ09B0050-0500
0
Lower
LSB
Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
Legend:
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Figure 2.9 General Register Data Formats (2)
Rev. 5.00 Aug 02, 2006 page 35 of 980
REJ09B0050-0500
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Address
Data Format
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
7
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.10 Memory Data Formats
Rev. 5.00 Aug 02, 2006 page 36 of 980
REJ09B0050-0500
LSB
Section 2 CPU
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
B/W/L
5
LDM, STM
3
3
MOVFPE* , MOVTPE*
L
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
4
TAS*
W/L
B
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
BIAND, BOR, BIOR, BXOR, BIXOR
2
BCC* , JMP, BSR, JSR, RTS
–
14
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
–
9
–
1
Arithmetic
operations
Branch
System control
Block data transfer EEPMOV
W/L
B
19
5
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. BCC is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 5.00 Aug 02, 2006 page 37 of 980
REJ09B0050-0500
Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
Note:
*
8-, 16-, 24-, or 32-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 5.00 Aug 02, 2006 page 38 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn → @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM
L
STM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Note:
* Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 5.00 Aug 02, 2006 page 39 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.4
Arithmetic Operations Instructions
Instruction
Size*
Function
ADD
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
1
SUB
ADDX
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
B
SUBX
INC
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
B/W/L
DEC
ADDS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B
DAS
MULXU
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)
SUBS
DAA
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Rev. 5.00 Aug 02, 2006 page 40 of 980
REJ09B0050-0500
Section 2 CPU
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
1
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets the CCR bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS*
2
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 5.00 Aug 02, 2006 page 41 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ Rd → Rd
Takes the one's complement (logical complement) of data in a general
register.
Note:
* Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
SHAL
B/W/L
SHAR
SHLL
B/W/L
ROTXR
Note:
Rd (shift) → Rd
Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.
B/W/L
ROTR
ROTXL
Rd (shift) → Rd
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
SHLR
ROTL
Function
Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
B/W/L
Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
* Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 5.00 Aug 02, 2006 page 42 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.7
Bit Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR
B
C ∨ (∼ <bit-No.> of <EAd>) → C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
Rev. 5.00 Aug 02, 2006 page 43 of 980
REJ09B0050-0500
Section 2 CPU
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ∼ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag. The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag. The bit number is specified by 3-bit immediate
data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
∼ C → (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand. The bit number is specified by 3bit immediate data.
Note:
* Size refers to the operand size.
B: Byte
Rev. 5.00 Aug 02, 2006 page 44 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
–
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
C=0
(high or same)
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
–
Branches unconditionally to a specified address.
BSR
–
Branches to a subroutine at a specified address.
JSR
–
Branches to a subroutine at a specified address.
RTS
–
Returns from a subroutine.
Rev. 5.00 Aug 02, 2006 page 45 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
–
Starts trap-instruction exception handling.
RTE
–
Returns from an exception-handling routine.
SLEEP
–
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate
data.
NOP
–
PC + 2 → PC
Only increments the program counter.
Note:
* Size refers to the operand size.
B: Byte
W: Word
Rev. 5.00 Aug 02, 2006 page 46 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
–
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
EEPMOV.W
–
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
• Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
Rev. 5.00 Aug 02, 2006 page 47 of 980
REJ09B0050-0500
Section 2 CPU
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
Rev. 5.00 Aug 02, 2006 page 48 of 980
REJ09B0050-0500
Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
Rev. 5.00 Aug 02, 2006 page 49 of 980
REJ09B0050-0500
Section 2 CPU
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Rev. 5.00 Aug 02, 2006 page 50 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
2.7.6
H'000000 to H'FFFFFF
24 bits (@aa:24)
Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
2.7.8
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00).
Rev. 5.00 Aug 02, 2006 page 51 of 980
REJ09B0050-0500
Section 2 CPU
Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * For this LSI, normal mode is not available.
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Rev. 5.00 Aug 02, 2006 page 52 of 980
REJ09B0050-0500
Section 2 CPU
Table 2.13 Effective Address Calculation
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
disp
0
31
31
24 23
0
Don't care
General register contents
r
•Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
1, 2, or 4
0
31
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
Rev. 5.00 Aug 02, 2006 page 53 of 980
REJ09B0050-0500
Section 2 CPU
Addressing Mode and Instruction Format
No
5
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
•*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
•
8 7
31
op
abs
H'000000
31
0
Memory contents
Note:
*
For this LSI, normal mode is not available.
Rev. 5.00 Aug 02, 2006 page 54 of 980
REJ09B0050-0500
0
abs
31
24 23
Don't care
0
Section 2 CPU
2.8
Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
In a product which has a DMA controller and a data transfer controller (DTC), the bus-released
state occurs when the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 23, Power-Down Modes.
Rev. 5.00 Aug 02, 2006 page 55 of 980
REJ09B0050-0500
Section 2 CPU
End of bus request
Bus request
g
nd
lin
lin
g
ha
nd
ha
re
ex
fo
of
st
d
ue
upt
rr
Inte
Re
q
En
xc
ce
pt
ep
t
ion
ion
d
En
=0
BY
SS EEP tion
SL truc
ins
Exception
handling state
n
Bus-released state
io
= 1 ruct
BY nst
SS EP i
E
SL
of
bu
s
re
Bu
qu
sr
es
eq
t
ue
st
Program execution state
Sleep mode
est
u
req
External interrupt request
Software standby
mode
RES = High
Reset
STBY = High,
RES = Low
state*1
Reset state
Hardware standby
mode*2
Power down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 23, Power-Down Modes.
Figure 2.13 State Transitions
2.9
Usage Note
2.9.1
Note on Bit Manipulation Instructions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.
Rev. 5.00 Aug 02, 2006 page 56 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
This LSI has six operating modes (modes 1 to 5 and 7). Modes 1 to 5 and 7 are available in the
H8S/2368 0.18 µm F-ZTAT Group flash memory version. Modes 1 to 4 and 7 are available in the
H8S/2367F. Modes 1, 2, 4, and 7 are available in the masked ROM version. Modes 1 and 2 are
available in the ROMless version. The operating mode is selected by the setting of mode pins
(MD2 to MD0).
Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external
memory and peripheral devices. In the externally expanded mode, each area can be switched to 8bit or 16-bit address space by the bus controller. If any one of the areas is set to 16-bit address
space, the bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits.
Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to
access an external memory and peripheral devices at the beginning of a program execution.
Modes 3 and 5 are a boot mode/user boot mode in which the flash memory can be programmed or
erased. For details on the boot mode/user boot mode, refer to section 19, Flash Memory (0.35-µm
F-ZTAT Version), or section 20, Flash Memory (0.18-µm F-ZTAT Version).
Do not change the MD2 to MD0 pin settings during operation.
Table 3.1
MCU Operating Mode Selection
MCU
CPU
Operating
Operating
Mode
MD2 MD1 MD0 Mode
External Data Bus
Initial
On-Chip ROM Width
Description
Max.
Value
1
0
0
1
Advanced
Expanded mode with on- Disabled
chip ROM disabled
16 bits
16 bits
2
0
1
0
Advanced
Expanded mode with on- Disabled
chip ROM disabled
8 bits
16 bits
3
0
1
1
Advanced
Boot mode
—
16 bits
4
1
0
0
Advanced
Expanded mode with on- Enabled
chip ROM enabled
8 bits
16 bits
5*
1
0
1
Advanced
User boot mode
Enabled
—
16 bits
7
1
1
1
Advanced
Single-chip mode
Enabled
—
16 bits
Note:
*
Enabled
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 57 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
MDCR monitors the current operating mode of this LSI.
Bit
Bit Name
Initial Value
R/W
Descriptions
7
6
5
4
3
−
−
−
−
−
0
0
0
0
0
−
−
−
−
−
Reserved
These bits are always read as 0 and cannot be
modified.
2
1
0
MDS2
MDS1
MDS0
R
R
R
Mode Select 2 to 0
These bits indicate the input levels at pins MD2 to
MD0 (the current operating mode). Bits MDS2 to
MDS0 correspond to MD2 to MD0. MDS2 to MDS0
are read-only bits and they cannot be written to. The
mode pin (MD2 to MD0) input levels are latched into
these bits when MDCR is read. These latches are
canceled by a reset.
Note:
3.2.2
*
−*
−*
−*
Determined by pins MD2 to MD0.
System Control Register (SYSCR)
SYSCR controls CPU access to the flash memory control registers, sets external bus mode, and
enables or disables on-chip RAM.
Rev. 5.00 Aug 02, 2006 page 58 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
Bit
Bit Name
Initial Value
R/W
Descriptions
7
6
1
1
R/W
R/W
Reserved
The initial value should not be modified.
0
R/W
4
−
−
−
−
0
R/W
Reserved
The initial value should not be modified.
3
FLSHE
0
R/W
5
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read/written to. If this bit is cleared to 0, the
flash memory control registers are not selected. At
this time, the contents of the flash memory control
registers are maintained. This bit should be written
to 0 in other than flash memory version.
0: Flash memory control registers are not selected
for area H'FFFFC8 to H'FFFFCB
1: Flash memory control registers are selected for
area H'FFFFC8 to H'FFFFCB
2
−
0
−
Reserved
This bit is always read as 0 and cannot be modified.
1
EXPE
−
R/W
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4, this bit is fixed at 1 and cannot
be modified. In mode 3 and 7, this bit has an initial
value of 0, and can be read and written.
Writing of 0 to EXPE when its value is 1 should only
be carried out when an external bus cycle is not
being executed.
0: External bus disabled
1: External bus enabled
0
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. The RAME
bit is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 5.00 Aug 02, 2006 page 59 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, and G, carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.
3.3.2
Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, and G carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and
port E functions as a data bus.
3.3.3
Mode 3
This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the
programming and erasure on the flash memory. Mode 3 is only available in the H8S/2368 Group
flash memory version.
3.3.4
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A, B, and C function as input ports immediately after a reset, but can be set to function as an
address bus. Ports D and E function as a data bus, and parts of ports F, and G, carry bus control
signals. For details, see section 9, I/O Ports.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.
Rev. 5.00 Aug 02, 2006 page 60 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to
1.
3.3.5
Mode 5
This mode is a user boot mode of the flash memory. This mode is the same as mode 7, except for
the programming and erasure on the flash memory. Mode 5 is only available in the H8S/2368 0.18
µm F-ZTAT Group.
3.3.6
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the chip starts up in single-chip mode. External address space cannot be used in single-chip
mode.
The initial mode after a reset is single-chip mode, with all I/O ports available for use as
input/output ports. However, the mode can be switched to externally expanded mode by setting 1
to the EXPE bit of SYSCR and then the external address space is enabled. When externally
expanded mode is selected, all areas are initially designated as 16-bit access space. The functions
of pins in ports A to G are the same as in externally expanded mode with on-chip ROM enabled.
In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to
1.
Rev. 5.00 Aug 02, 2006 page 61 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
3.3.7
Pin Functions
Table 3.2 shows the pin functions in each operating mode.
Table 3.2
Pin Functions in Each Operating Mode
Port
Port A
PA7 to PA5
PA4 to PA0
Port B
Mode 1
Mode 2
Mode 3*2
Mode 4*2
Mode 5*2*3
Mode 7*2
P*1/A
P*1/A
P*1/A
P*1/A
P*1/A
P*1/A
A
A
A
A
P*1/A
P*1/A
P*1/A
P*1/A
A
*1
*1
*1
Port C
A
Port D
D
Port G
P /A
P /A
P*1/A
P*1/D
D
P*1/D
P*1/D
*1
P/D
*1
P /D
*1
P /D
*1
P /D
*1
P /D
P*1/D
PF7, PF6
P/C*1
P*1/C
P*1/C
P/C*1
P*1/C
P*1/C
PF5, PF4
C
C
C
PF3
P/C*1
P/C*1
P/C*1
PF2 to PF0
P*1/C
P*1/C
P*1/C
PG6 to PG1
P*1/C
P*1/C
P*1/C
P*1/C
*1
*1
Port E
Port F
D
P /A
PG0
P/C
P/C
P*1/C
P*1/C
*1
P /C
Legend:
P: I/O port
A: Address bus output
D: Data bus input/output
C: Control signals, clock input/output
Notes: 1. After reset
2. Setting not allowed on ROMless versions.
3. Mode 5 is available only in the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 62 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
3.4
Memory Map in Each Operating Mode
Figures 3.1 to 3.15 show memory maps for each product.
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
ROM: 512 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
H'000000
On-chip ROM
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space
H'FFFF00
External address space/
reserved area*2*4
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.1 H8S/2368F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 63 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 512 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 512 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'060000
H'060000
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
External address
space/
reserved area*2*4
H'FF4000
On-chip RAM/
external address
space *3
On-chip RAM *5
H'FFC000
Reserved area*4
H'FFD000 External address space
H'FFFF20
H'FFFFFF
On-chip ROM
External address
space/
reserved area*2*4
External address
space
H'FFFF00
H'000000
On-chip ROM
H'060000
H'FFFC00
ROM: 512 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
Internal I/O registers
External address space
Internal I/O registers
H'FFC000
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.2 H8S/2368F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 64 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 24 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 384 kbytes
RAM: 24 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
External address
space
H'060000
External address
space/
reserved area*2*4
H'FF4000
H'FF6000
H'FFC000
H'FF4000
H'FF6000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFC800
External address space
H'FFC800
External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
H'FFFF20
H'FFFFFF
Notes: 1.
2.
3.
4.
Reserved area*4
On-chip RAM/
external address
space*1
Reserved area*4
External address space
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
When EXPE = 1, external address space; when EXPE = 0, reserved area.
On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.
Do not access a reserved area.
Figure 3.3 H8S/2367F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 65 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 384 kbytes
RAM: 24 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
ROM: 384 kbytes
RAM: 24 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'060000
On-chip ROM
H'060000
External address
space/
reserved area*2*4
External address
space
H'FF4000
H'FF6000
H'FFC000
Reserved area
On-chip RAM/
external address
space*1
Reserved area
H'FF4000
H'FF6000
H'FFC000
Reserved area*4
On-chip RAM/
external address
space *3
Reserved area*4
H'FFC800 External address space
H'FFC800 External address space/
reserved area*2*4
H'FFFC00
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O registers
External address space
Internal I/O registers
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. Do not access a reserved area.
Figure 3.4 H8S/2367F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 66 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 384 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'060000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
External address space/
reserved area*2*4
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.5 H8S/2364F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 67 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 384 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 384 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'060000
Reserved area*4
H'060000
H'080000
Reserved area*4
H'080000
External address
space/
reserved area*2*4
External address
space
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
External address
space/
reserved area*2*4
H'FF4000
On-chip RAM/
external address
space*3
On-chip RAM *5
H'FFC000
Reserved area*4
H'FFD000 External address space
H'FFFF20
H'FFFFFF
On-chip ROM
Reserved area*4
H'080000
H'FFFF00
H'000000
On-chip ROM
H'060000
H'FFFC00
ROM: 384 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
Internal I/O registers
External address space
Internal I/O registers
H'FFC000
H'FFC000
Reserved area *4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.6 H8S/2364F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 68 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFD000
External address space
H'FFD000
External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
H'FFFF20
H'FFFFFF
External address space
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.7 H8S/2362F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 69 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'040000
Reserved area*4
H'040000
H'060000
Reserved area*4
H'060000
External address
space/
reserved area*2*4
External address
space
H'FF4000
H'FF4000
On-chip RAM/
external address
space*1
External address
space/
reserved area*2*4
H'FF4000
On-chip RAM/
external address
space *3
On-chip RAM *5
H'FFC000
Reserved area
H'FFD000 External address space
H'FFFF20
H'FFFFFF
On-chip ROM
Reserved area*4
H'060000
H'FFFF00
H'000000
On-chip ROM
H'040000
H'FFFC00
ROM: 256 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
Internal I/O registers
External address space
Internal I/O registers
H'FFC000
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.8 H8S/2362F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 70 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 24 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 24 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space/
reserved area*2*4
H'FF4000
Reserved area*4
H'FF6000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
H'FF6000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFD000
External address space
H'FFD000
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
H'FFFF20
H'FFFFFF
External address space/
reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.9 H8S/2361F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 71 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 24 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 24 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'040000
Reserved area*4
H'080000
Reserved area*4
Reserved area*4
H'FFD000 External address space
H'FFFF20
H'FFFFFF
H'080000
H'FF4000
Reserved area*4
H'FF6000
H'FFC000
Internal I/O registers
External address space
Internal I/O registers
Reserved area*4
External address
space/
reserved area*2*4
On-chip RAM/
external address
space*1
H'FFFF00
H'040000
H'080000
H'FF6000
On-chip ROM
Reserved area*4
External address
space
H'FFFC00
H'000000
On-chip ROM
H'040000
H'FF4000
ROM: 256 kbytes
RAM: 24 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
External address
space/
reserved area*2*4
H'FF4000
Reserved area*4
H'FF6000
On-chip RAM/
external address
space*3
On-chip RAM *5
H'FFC000
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.10 H8S/2361F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 72 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 16 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
ROM: 256 kbytes
RAM: 16 kbytes
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'040000
Reserved area*4
External address
space
H'080000
External address
space
H'FF4000
Reserved area*4
H'FF8000
H'FF4000
On-chip RAM/
external address
space*1
H'FFC000
Reserved area*4
H'FF8000
Reserved area*4
On-chip RAM*3
H'FFC000
Reserved area*4
H'FFD000
External address space
H'FFD000
External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFC00
Internal I/O registers
H'FFFF00
External address space/
reserved area*2*4
H'FFFF00
H'FFFF20
H'FFFFFF
External address space
Internal I/O registers
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Figure 3.11 H8S/2360F Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 73 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 16 kbytes
Mode 5
(User boot mode)
ROM: 256 kbytes
RAM: 16 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'040000
Reserved area*4
H'080000
Reserved area*4
Reserved area*4
H'FFD000 External address space
H'FFFF20
H'FFFFFF
H'080000
H'FF4000
Reserved area*4
H'FF8000
H'FFC000
Internal I/O registers
External address space
Internal I/O registers
Reserved area*4
External address
space/
reserved area*2*4
On-chip RAM/
external address
space*1
H'FFFF00
H'040000
H'080000
H'FF8000
On-chip ROM
Reserved area*4
External address
space
H'FFFC00
H'000000
On-chip ROM
H'040000
H'FF4000
ROM: 256 kbytes
RAM: 16 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
External address
space/
reserved area*2*4
H'FF4000
Reserved area*4
H'FF8000
On-chip RAM/
external address
space*3
On-chip RAM *5
H'FFC000
H'FFC000
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
Reserved area*4
H'FFD000 External address space/
reserved area*2*4
H'FFFC00
Internal I/O registers
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00 External address space/
reserved area*2*4
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
4. A reserved area should not be accessed.
5. The on-chip RAM is used to program the flash memory. The RAME bit in SYSCR should not be cleared to 0.
Figure 3.12 H8S/2360F Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 74 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 256 kbytes
RAM: 16 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
RAM: 16 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
H'000000
On-chip ROM
H'040000
External address
space
Reserved area*2
H'060000
External address
space
H'FF4000
H'FF8000
H'FFC000
Reserved area*2
On-chip RAM/
external address
space*1
Reserved area*2
H'FF4000
H'FF8000
H'FFC000
Reserved area*2
On-chip RAM/
external address
space*1
Reserved area*2
H'FFC800
External address space
H'FFC800 External address space
H'FFFC00
Internal I/O registers
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
External address space
Internal I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Internal I/O registers
External address space
Internal I/O registers
Notes: 1. This area is specified as external address space by clearing the RAME bit in SYSCR to 0.
2. Do not access a reserved area.
Figure 3.13 H8S/2365 Memory Map (1)
Rev. 5.00 Aug 02, 2006 page 75 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
ROM: 258 kbytes
RAM: 16 kbytes
Mode 7
(Single-chip activation expanded mode,
with on-chip ROM enabled)
H'000000
On-chip ROM
H'040000
Reserved area*3
H'060000
External address
space/
reserved area*1*3
H'FF4000
H'FF8000
Reserved area*3
On-chip RAM/
external address
space*2
H'FFC000
H'FFC800
Reserved area*3
External address space/
reserved area*1*3
H'FFFC00 Internal I/O registers
H'FFFF00 External address space/
reserved area*1*3
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area.
2. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1.
When EXPE = 0, on-chip RAM.
3. Do not access a reserved area.
Figure 3.14 H8S/2365 Memory Map (2)
Rev. 5.00 Aug 02, 2006 page 76 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
RAM: 16 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
External address
space
H'FF8000
H'FFC000
On-chip RAM/
external address
space*1
Reserved area*2
H'FFC800
External address space
H'FFFC00
Internal I/O registers
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. Do not access a reserved area.
Figure 3.15 H8S/2363 Memory Map
Rev. 5.00 Aug 02, 2006 page 77 of 980
REJ09B0050-0500
Section 3 MCU Operating Modes
Rev. 5.00 Aug 02, 2006 page 78 of 980
REJ09B0050-0500
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Trace*
1
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Direct transition*
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Interrupt
Starts when execution of the current instruction or exception
3
handling ends, if an interrupt request has been issued.*
2
Low
Trap instruction*
4
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
4. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Rev. 5.00 Aug 02, 2006 page 79 of 980
REJ09B0050-0500
Section 4 Exception Handling
Table 4.2
Exception Handling Vector Table
Vector Address*
1
Exception Source
Vector Number
Normal Mode*
Advanced Mode
Power-on reset
3
Manual reset*
0
H'0000 to H'0001
H'0000 to H'0003
1
H'0002 to H'0003
H'0004 to H'0007
Reserved for system use
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
4
H'0008 to H'0019
H'0010 to H'0013
Trace
2
5
H'000A to H'000B
H'0014 to H'0017
Interrupt (direct transition)*
6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
Trap instruction (#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
IRQ6
22
H'002C to H'002D
H'0058 to H'005B
IRQ7
23
H'002E to H'002F
H'005C to H'005F
Reserved for system use
24
H'0030 to H'0031
H'0060 to H'0063
25
H'0032 to H'0033
H'0064 to H'0067
26
H'0034 to H'0035
H'0068 to H'006B
27
H'0036 to H'0037
H'006C to H'006F
28
H'0038 to H'0039
H'0070 to H'0073
29
H'003A to H'003B
H'0074 to H'0077
3
Reserved for system use
External interrupt
Rev. 5.00 Aug 02, 2006 page 80 of 980
REJ09B0050-0500
Section 4 Exception Handling
Vector Address*
1
Exception Source
Vector Number
Normal Mode*
Advanced Mode
Reserved for system use
30
H'003C to H'003D
H'0078 to H'007B
31
H'003E to H'003F
H'007C to H'007F
32
118
H'0040 to H'0041
H'00EC to H'00ED
H'0080 to H'0083
H'01D8 to H'01DB
4
Internal interrupt*
Notes: 1.
2.
3.
4.
4.3
2
Lower 16 bits of the address.
Not available in this LSI.
Not available in this LSI. It is reserved for system use.
For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 13,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
Rev. 5.00 Aug 02, 2006 page 81 of 980
REJ09B0050-0500
Section 4 Exception Handling
Vector fetch
Prefetch of first
Internal
processing program instruction
(1)
(3)
φ
Internal
address bus
(5)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
Rev. 5.00 Aug 02, 2006 page 82 of 980
REJ09B0050-0500
Section 4 Exception Handling
Internal
processing
Vector fetch
*
Address bus
*
(1)
*
(3)
(5)
High
,
D15 to D0
Prefetch of first
program instruction
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Seven program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Functions after Reset Release
After reset release, MSTPCR is initialized to H'0FFF and EXMSTPCR is to H'FFFD, all modules
except the DMAC and the DTC enter module stop mode.
Rev. 5.00 Aug 02, 2006 page 83 of 980
REJ09B0050-0500
Section 4 Exception Handling
Consequently, on-chip peripheral module registers cannot be read from or written to. Register
reading and writing is enabled when module stop mode is exited.
4.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3
Status of CCR and EXR after Trace Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
0
Trace exception handling cannot be used.
2
1
—
I2 to I0
—
T
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
4.5
Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
Rev. 5.00 Aug 02, 2006 page 84 of 980
REJ09B0050-0500
Section 4 Exception Handling
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
4.6
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
—
—
—
2
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
Rev. 5.00 Aug 02, 2006 page 85 of 980
REJ09B0050-0500
Section 4 Exception Handling
4.7
Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
(a) Normal Modes*2
SP
EXR
Reserved*1
SP
CCR
CCR
CCR*1
CCR*1
PC (16 bits)
PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR
Reserved*1
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Notes: 1. Ignored on return.
2. Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
Rev. 5.00 Aug 02, 2006 page 86 of 980
REJ09B0050-0500
Section 4 Exception Handling
4.8
Usage Notes
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation
when the SP value is odd.
Address
CCR
R1L
SP
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
TRAP instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7
Data saved above SP
Contents of CCR lost
[Legend]
CCR :
PC :
R1L :
SP :
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
Rev. 5.00 Aug 02, 2006 page 87 of 980
REJ09B0050-0500
Section 4 Exception Handling
Rev. 5.00 Aug 02, 2006 page 88 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing,
can be selected for IRQ7 to IRQ0.
• DTC and DMAC control
DTC and DMAC activations are performed by means of interrupts.
Rev. 5.00 Aug 02, 2006 page 89 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
INTCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
SSIER ITSR ISCRL
Interrupt
request
Vector
number
IER
Priority
determination
Internal
interrupt
sources
SWDTEND
to IICI1
I
I2 to I0
IPR
Interrupt controller
Legend:
ISCRL: IRQ sense control register
IER:
IRQ enable register
ISR:
IRQ status register
IPR:
Interrupt priority register
INTCR: Interrupt control register
ITSR: IRQ pin select register
SSIER: Software standby release IRQ enable register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 5.00 Aug 02, 2006 page 90 of 980
REJ09B0050-0500
CCR
EXR
Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising or falling edge can be selected.
IRQ7 to IRQ0
Input
Maskable external interrupts
Rising edge, falling edge, both edges, or level sensing, can be
selected.
5.3
Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• IRQ pin select register (ITSR)
• Software standby release IRQ enable register (SSIER)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)
Rev. 5.00 Aug 02, 2006 page 91 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
Bit Name
Initial Value
R/W
Description
7
6
−
−
0
0
−
Reserved
5
4
INTM1
INTM0
0
0
R/W
R/W
These bits are always read as 0 and cannot be
modified.
Interrupt Control Select Mode 1 and 0
These bits select either of two interrupt control
modes for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0, and
IPR.
11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of
NMI input
1: Interrupt request generated at rising edge of
NMI input
2 to
0
−
0
−
Rev. 5.00 Aug 02, 2006 page 92 of 980
REJ09B0050-0500
Reserved
These bits are always read as 0 and cannot be
modified.
Section 5 Interrupt Controller
5.3.2
Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0
sets the priority of the corresponding interrupt. IPR should be read in word size.
Bit
Bit Name
Initial Value
R/W
Description
15
−
0
−
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
IPR14
IPR13
IPR12
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
11
−
0
−
Reserved
This bit is always read as 0 and cannot be
modified.
10
9
8
IPR10
IPR9
IPR8
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
7
−
0
−
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 93 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3
−
0
−
Reserved
This bit is always read as 0 and cannot be
modified.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Rev. 5.00 Aug 02, 2006 page 94 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.3
IRQ Enable Register (IER)
IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15 to
8
−
0
R/W
Reserved
7
IRQ7E
The write value should always be 0.
0
R/W
IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
6
IRQ6E
0
R/W
IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
5
IRQ5E
0
R/W
IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this
bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this
bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this
bit is 1.
Rev. 5.00 Aug 02, 2006 page 95 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Register L (ISCRL)
ISCRL select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15
14
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
IRQ7 Sense Control B
IRQ7 Sense Control A
00: Interrupt request generated at IRQ7 input
low level
01: Interrupt request generated at falling edge of
IRQ7 input
10: Interrupt request generated at rising edge of
IRQ7 input
11: Interrupt request generated at both falling
and rising edges of IRQ7 input
13
12
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
IRQ6 Sense Control B
IRQ6 Sense Control A
00: Interrupt request generated at IRQ6 input
low level
01: Interrupt request generated at falling edge of
IRQ6 input
10: Interrupt request generated at rising edge of
IRQ6 input
11: Interrupt request generated at both falling
and rising edges of IRQ6 input
11
10
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
IRQ5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input
low level
01: Interrupt request generated at falling edge of
IRQ5 input
10: Interrupt request generated at rising edge of
IRQ5 input
11: Interrupt request generated at both falling
and rising edges of IRQ5 input
Rev. 5.00 Aug 02, 2006 page 96 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
8
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input
low level
01: Interrupt request generated at falling edge of
IRQ4 input
10: Interrupt request generated at rising edge of
IRQ4 input
11: Interrupt request generated at both falling
and rising edges of IRQ4 input
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
IRQ3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input
low level
01: Interrupt request generated at falling edge of
IRQ3 input
10: Interrupt request generated at rising edge of
IRQ3 input
11: Interrupt request generated at both falling
and rising edges of IRQ3 input
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input
low level
01: Interrupt request generated at falling edge of
IRQ2 input
10: Interrupt request generated at rising edge of
IRQ2 input
11: Interrupt request generated at both falling
and rising edges of IRQ2 input
Rev. 5.00 Aug 02, 2006 page 97 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input
low level
01: Interrupt request generated at falling edge of
IRQ1 input
10: Interrupt request generated at rising edge of
IRQ1 input
11: Interrupt request generated at both falling
and rising edges of IRQ1 input
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input
low level
01: Interrupt request generated at falling edge of
IRQ0 input
10: Interrupt request generated at rising edge of
IRQ0 input
11: Interrupt request generated at both falling
and rising edges of IRQ0 input
Rev. 5.00 Aug 02, 2006 page 98 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.5
IRQ Status Register (ISR)
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Bit
Bit
Name
Initial Value
R/W
Description
15 to 8
−
0
R/W
Reserved
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
The write value should always be 0.
7
6
5
4
3
2
1
0
Note:
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
*
[Setting condition]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
•
Cleared by reading IRQnF flag when
IRQnF = 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
Only 0 can be written, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 99 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.6
IRQ Pin Select Register (ITSR)
ITSR selects input pins IRQ7 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15 to 8
−
0
R/W
Reserved
The write value should always be 0.
7
ITS7
0
R/W
Selects IRQ7 input pin.
0: PA7
1: P47
6
ITS6
0
R/W
Selects IRQ6 input pin.
0: PA6
1: P46
5
ITS5
0
R/W
Selects IRQ5 input pin.
0: PA5
1: P45
4
ITS4
0
R/W
Selects IRQ4 input pin.
0: PA4
1: P44
3
ITS3
0
R/W
Selects IRQ3 input pin.
0: P53
1: P43
2
ITS2
0
R/W
Selects IRQ2 input pin.
0: P52
1: P42
1
ITS1
0
R/W
Selects IRQ1 input pin.
0: P51
1: P41
0
ITS0
0
R/W
Selects IRQ0 input pin.
0: P50
1: P40
Rev. 5.00 Aug 02, 2006 page 100 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ pins used to recover from the software standby state.
Bit
Bit Name
Initial Value
R/W
Description
15 to 8
—
0
R/W
Reserved
The write value should always be 0.
7
6
5
4
3
2
1
0
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
0
0
0
0
0
0
0
0
5.4
Interrupt Sources
5.4.1
External Interrupts
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Software Standby Release IRQ Setting
These bits select the IRQn pins used to
recover from the software standby state.
0: IRQn requests are not sampled in the
software standby state (Initial value when n
= 7 to 3)
1: When an IRQn request occurs in the
software standby state, the chip recovers
from the software standby state after the
elapse of the oscillation settling time (Initial
value when n = 2 to 0)
There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore
the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCRL, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
Rev. 5.00 Aug 02, 2006 page 101 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should
be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in
the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not
be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnE
IRQnSCB, IRQnSCA
IRQnF
Edge/
level detection
circuit
S
Q
IRQn interrupt
request
R
input
Clear signal
Note: n = 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.
Rev. 5.00 Aug 02, 2006 page 102 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Table 5.2
Interrupt
Source
External
pin
—
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address*
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
NMI
7
H'001C
—
High
—
—
IRQ0
16
H'0040
IPRA14 to IPRA12
O
—
IRQ1
17
H'0044
IPRA10 to IPRA8
O
—
IRQ2
18
H'0048
IPRA6 to IPRA4
O
—
IRQ3
19
H'004C
IPRA2 to IPRA0
O
—
IRQ4
20
H'0050
IPRB14 to IPRB12
O
—
IRQ5
21
H'0054
IPRB10 to IPRB8
O
—
IRQ6
22
H'0058
IPRB6 to IPRB4
O
—
IRQ7
23
H'005C
IPRB2 to IPRB0
O
—
Reserved for
system use
24
H'0060
IPRC14 to IPRC12
—
—
25
H'0064
IPRC10 to IPRC8
—
—
26
H'0068
IPRC6 to IPRC4
—
—
27
H'006C
IPRC2 to IPRC0
—
—
28
H'0070
IPRD14 to IPRD12
—
—
29
H'0074
IPRD10 to IPRD8
—
—
30
H'0078
IPRD6 to IPRD4
—
—
31
H'007C
IPRD2 to IPRD0
—
—
DTC
SWDTEND
32
H'0080
IPRE14 to IPRE12
O
—
WDT
WOVI
33
H'0084
IPRE10 to IPRE8
—
—
—
Reserved for
system use
34
H'0088
IPRE6 to IPRE4
—
—
Low
Rev. 5.00 Aug 02, 2006 page 103 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Vector
Address*
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
Refresh
controller
CMI
35
H'008C
IPRE2 to IPRE0
High
—
—
—
Reserved for
system use
36
H'0090
IPRF14 to IPRF12
—
—
37
H'0094
—
—
O
O
—
—
O
O
Interrupt
Source
A/D
ADI
38
H'0098
—
Reserved for
system use
39
H'009C
TPU_0
TGI0A
40
H'00A0
TGI0B
41
H'00A4
O
—
TGI0C
42
H'00A8
O
—
TGI0D
43
H'00AC
O
—
TCI0V
44
H'00B0
—
—
Reserved for
system use
45
H'00B4
—
—
—
TPU_1
TPU_2
—
IPRF6 to IPRF4
IPRF6 to IPRF4
46
H'00B8
—
—
47
H'00BC
—
—
TGI1A
48
H'00C0
O
O
TGI1B
49
H'00C4
O
—
TCI1V
50
H'00C8
—
—
TCI1U
51
H'00CC
—
—
TGI2A
52
H'00D0
O
O
O
—
TGI2B
TPU_3
IPRF10 to IPRF8
53
IPRF2 to IPRF0
IPRG14 to IPRG12
H'00D4
TCI2V
54
H'00D8
—
—
TCI2U
55
H'00DC
—
—
TGI3A
56
H'00E0
O
O
TGI3B
57
H'00E4
O
—
TGI3C
58
H'00E8
O
—
TGI3D
59
H'00EC
O
—
TCI3V
60
H'00F0
—
—
61
H'00F4
—
—
62
H'00F8
—
—
63
H'00FC
—
—
Reserved for
system use
Rev. 5.00 Aug 02, 2006 page 104 of 980
REJ09B0050-0500
IPRG10 to IPRG8
Low
Section 5 Interrupt Controller
Vector
Address*
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
TPU_4
TGI4A
64
H'0100
IPRG6 to IPRG4
High
O
O
TGI4B
65
H'0104
O
—
TCI4V
66
H'0108
—
—
TCI4U
67
H'010C
—
—
TGI5A
68
H'0110
O
O
TGI5B
69
H'0114
O
—
—
TPU_5
IPRG2 to IPRG0
TCI5V
70
H'0118
—
TCI5U
71
H'011C
—
—
CMIA0
72
H'0120
O
—
CMIB0
73
H'0124
O
—
OVI0
74
H'0128
—
—
—
Reserved for
system use
75
H'012C
IPRH14 to IPRH12
—
—
TMR_1
CMIA1
76
H'0130
IPRH10 to IPRH8
TMR_0
IPRH14 to IPRH12
O
—
—
CMIB1
77
H'0134
O
OVI1
78
H'0138
—
—
—
Reserved for
system use
79
H'013C
—
—
DMAC
DMTEND0A
80
H'0140
O
—
DMTEND0B
81
H'0144
DMTEND1A
SCI_0
82
IPRH6 to IPRH4
O
—
H'0148
O
—
O
—
DMTEND1B
83
H'014C
Reserved for
system use
84
H'0150
IPRH0 to IPRH0
—
—
85
H'0154
IPRI14 to IPRI12
—
—
86
H'0158
IPRI10 to IPRI8
—
—
87
H'015C
IPRI6 to IPRI4
—
—
ERI0
88
H'0160
IPRI2 to IPRI0
—
—
RXI0
89
H'0164
O
O
O
O
—
—
TXI0
90
H'0168
TEI0
91
H'016C
Low
Rev. 5.00 Aug 02, 2006 page 105 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Vector
Address*
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
SCI_1
ERI1
92
H'0170
IPRJ14 to IPRJ12
High
—
—
RXI1
93
H'0174
O
O
TXI1
94
H'0178
O
O
TEI1
95
H'017C
—
—
ERI2
96
H'0180
—
—
RXI2
97
H'0184
O
—
—
SCI_2
SCI_3
SCI_4
—
—
IIC2
IPRJ10 to IPRJ8
TXI2
98
H'0188
O
TEI2
99
H'018C
—
—
ERI3
100
H'0190
—
—
RXI3
101
H'0194
—
—
TXI3
102
H'0198
—
—
TEI3
103
H'019C
—
—
ERI4
104
H'01A0
—
—
RXI4
105
H'01A4
O
—
TXI4
106
H'01A8
O
—
—
—
—
—
IPRJ6 to IPRJ4
IPRJ2 to IPRJ0
TEI4
107
H'01AC
Reserved for
system use
108
H'01B0
109
H'01B4
—
—
110
H'01B8
—
—
111
H'01BC
—
—
112
H'01C0
—
—
113
H'01C4
—
—
114
H'01C8
—
—
115
H'01CC
—
—
IICI0
116
H'01D0
—
—
Reserved for
system use
117
H'01D4
—
—
IICI1
118
H'01D8
—
—
Reserved for
system use
119
H'01DC
—
—
Reserved for
system use
Rev. 5.00 Aug 02, 2006 page 106 of 980
REJ09B0050-0500
IPRK14 to IPRK12
IPRK10 to IPRK8
IPRK6 to IPRK4
Low
Section 5 Interrupt Controller
Interrupt
Source
—
Origin of
Interrupt
Source
Reserved for
system use
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
DTC
DMAC
Activation Activation
120
H'01E0
IPRK2 to IPRK0
High
—
—
121
H'01E4
—
—
122
H'01E8
—
—
123
H'01EC
—
—
124
H'01F0
—
—
125
H'01F4
—
—
126
H'01F8
—
—
—
—
127
Note:
*
H'01EC
Low
Lower 16 bits of the start address.
Rev. 5.00 Aug 02, 2006 page 107 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt
Interrupt Control Modes
Priority Setting
Interrupt
Control Mode Registers
Mask Bits Description
0
Default
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2
IPR
I2 to I0
8 priority levels except for NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Rev. 5.00 Aug 02, 2006 page 108 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Hold
pending
Yes
No
IRQ0
Yes
No
IRQ1
Yes
IICI1
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev. 5.00 Aug 02, 2006 page 109 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 5.00 Aug 02, 2006 page 110 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Yes
No
Level 6 interrupt?
No
Yes
Level 1 interrupt?
No
Mask level 5
or below?
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold
pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
Rev. 5.00 Aug 02, 2006 page 111 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 5.00 Aug 02, 2006 page 112 of 980
REJ09B0050-0500
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address)
(2) (4) Instruction code (Not executed)
(3)
Instruction prefetch address (Not executed)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
Vector fetch
(12)
(11)
(14)
(13)
Interrupt handling
routine instruction
prefetch
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
stack
Internal
operation
Section 5 Interrupt Controller
Figure 5.5 Interrupt Exception Handling
Rev. 5.00 Aug 02, 2006 page 113 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4
Interrupt Response Times
Normal Mode*
Advanced Mode
Interrupt
control
mode 0
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
3
3
3
3
5
No.
Execution Status
1
Interrupt priority determination*
2
Number of wait states until executing 1 to 19 +2·SI 1 to 19+2·SI
2
instruction ends*
1 to 19+2·SI 1 to 19+2·SI
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
5
Instruction fetch*
2·SI
2·SI
2·SI
2·SI
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
6
1
3
Internal processing
*4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in this LSI.
Rev. 5.00 Aug 02, 2006 page 114 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6+2m
2
3+m
Branch address read SJ
Stack manipulation SK
Legend:
m: Number of wait states in an external device access.
5.6.5
DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and
section 8, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).
Rev. 5.00 Aug 02, 2006 page 115 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.7
Usage Notes
5.7.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
TIER_0 write cycle by CPU
TCIV exception handling
φ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.6 Contention between Interrupt Generation and Disabling
Rev. 5.00 Aug 02, 2006 page 116 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
5.7.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
Change of IRQ Pin Select Register (ITSR) Setting
When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 7) of ISR
may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 7) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.
Rev. 5.00 Aug 02, 2006 page 117 of 980
REJ09B0050-0500
Section 5 Interrupt Controller
5.7.6
Note on IRQ Status Register (ISR)
Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from
ISR after a reset and then write 0 to clear the IRQnF flags.
Rev. 5.00 Aug 02, 2006 page 118 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight
areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
masters—the CPU, DMA controller (DMAC) and data transfer controller (DTC).
6.1
Features
• Manages external space in area units
Manages the external space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, or DRAM, interface can be set
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
• DRAM interface
DRAM interface can be set for areas 2 to 5
• Bus arbitration function
Includes a bus arbiter that arbitrates bus right between the CPU, DMAC, and DTC
BSCS201A_000020020100
Rev. 5.00 Aug 02, 2006 page 119 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
A block diagram of the bus controller is shown in figure 6.1.
Internal address bus
CS7 to CS0
Area decoder
WAIT
BREQ
BACK
BREQO
External bus controller
Internal bus master bus request signal
Internal bus master bus acknowledge signal
External bus
arbiter
External bus
control signals
Internal bus control signals
Internal bus controller
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Internal bus
arbiter
Control registers
Internal data bus
ABWCR
ASTCR
WTCRAH WTCRAL
DRAMCR
DRACCR
WTCRBH WTCRBL
RDNCR
CSACRH
REFCR
RTCNT
RTCOR
CSACRL
BROMCRH BROMCRL
BCR
Legend:
ABWCR:
ASTCR:
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL:
RDNCR:
CSACRH and CSACRL:
BROMCRH:
Bus width control register
Access state control register
BROMCRL:
BCR:
DRAMCR:
Wait control registers AH, AL, BH, and BL
DRACCR:
Read strobe timing control register
REFCR:
CS assertion period control registers H and L RTCNT:
Area 0 burst ROM interface control register
RTCOR:
Area 1 burst ROM interface control register
Bus control register
DRAM control register
DRAM access control register
Refresh control register
Refresh timer counter
Refresh time constant register
Figure 6.1 Block Diagram of Bus Controller
Rev. 5.00 Aug 02, 2006 page 120 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Read
RD
Output
Strobe signal indicating that normal space
is being read.
High write
HWR
Output
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Low write
LWR
Output
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0
CS0
Output
Strobe signal indicating that area 0 is
selected.
Chip select 1
CS1
Output
Strobe signal indicating that area 1 is
selected
Chip select 2/row address
strobe 2
CS2/
RAS2
Output
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space.
Chip select 3/row address
strobe 3
CS3/
RAS3
Output
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space.
Chip select 4
CS4
Output
Strobe signal indicating that area 4 is
selected.
Chip select 5
CS5
Output
Strobe signal indicating that area 5 is
selected.
Chip select 6
CS6
Output
Strobe signal indicating that area 6 is
selected.
Chip select 7
CS7
Output
Strobe signal indicating that area 7 is
selected.
Upper column address strobe
UCAS
Output
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal.
Rev. 5.00 Aug 02, 2006 page 121 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Name
Symbol
I/O
Function
Lower column address strobe
LCAS
Output
16-bit DRAM space lower column address
strobe signal.
Output enable
OE
Output
Output enable signal for the DRAM space.
Wait
WAIT
Input
Wait request signal when accessing
external address space.
Bus request
BREQ
Input
Request signal for release of bus to
external bus master.
Bus request acknowledge
BACK
Output
Acknowledge signal indicating that bus has
been released to external bus master.
Bus request output
BREQO
Output
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
Data transfer acknowledge
1 (DMAC)
DACK1
Output
Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge
0 (DMAC)
DACK0
Output
Data transfer acknowledge signal for single
address transfer by DMAC channel 0.
6.3
Register Descriptions
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)
• DRAM access control register (DRACCR)
Rev. 5.00 Aug 02, 2006 page 122 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
• Refresh control register (REFCR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
6.3.1
Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
Bit Name
Initial Value*
R/W
Description
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Bus Width Control
Note:
6.3.2
*
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized to
0.
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
Wait state insertion in area n access is
disabled
1: Area n is designated as 3-state access space
Wait state insertion in area n access is
enabled
(n = 7 to 0)
Rev. 5.00 Aug 02, 2006 page 123 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.3
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
• WTCRAH
Bit
Bit Name
Initial Value
R/W
Description
15
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W72
W71
W70
1
1
1
R/W
R/W
R/W
Area 7 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 124 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
W62
W61
W60
1
1
1
R/W
R/W
R/W
Area 6 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 6 while AST6 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
• WTARAL
Bit
Bit Name
Initial Value
R/W
Description
7
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
5
4
W52
W51
W50
1
1
1
R/W
R/W
R/W
Area 5 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 5 while AST5 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
Rev. 5.00 Aug 02, 2006 page 125 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
3
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
1
0
W42
W41
W40
1
1
1
R/W
R/W
R/W
Area 4 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 4 while AST4 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
Rev. 5.00 Aug 02, 2006 page 126 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
• WTCRBH
Bit
Bit Name
Initial Value
R/W
Description
15
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W32
W31
W30
1
1
1
R/W
R/W
R/W
Area 3 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 3 while AST3 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
10
9
8
W22
W21
W20
1
1
1
R/W
R/W
R/W
Area 2 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
Rev. 5.00 Aug 02, 2006 page 127 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
• WTCRBL
Bit
Bit Name
Initial Value
R/W
Description
7
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
5
4
W12
W11
W10
1
1
1
R/W
R/W
R/W
Area 1 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 1 while AST1 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
−
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
1
0
W02
W01
W00
1
1
1
R/W
R/W
R/W
Area 0 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 0 while AST0 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
Rev. 5.00 Aug 02, 2006 page 128 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.4
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is
negated one half-state earlier than that for an
area for which the RDNn bit is cleared to 0. The
read data setup and hold time specifications are
also one half-state earlier.
0: In an area n read access, the RD is negated
at the end of the read cycle
1: In an area n read access, the RD is negated
one half-state before the end of the read cycle
(n = 7 to 0)
Bus cycle
T1
T2
T3
φ
RD
RDNn = 0
Data
RD
RDNn = 1
Data
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
Rev. 5.00 Aug 02, 2006 page 129 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.5
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control
1
These bits specify whether or not the Th cycle is
to be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state Th cycle, in which only the CSn and
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Th) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Th) is extended
(n = 7 to 0)
• CSACRL
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control
2
These bits specify whether or not the Tt cycle
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state Tt cycle, in which only the
CSn and address signals are asserted, is
inserted after the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Tt) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Tt) is extended
(n = 7 to 0)
Rev. 5.00 Aug 02, 2006 page 130 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
φ
Address
CS
RD
Read
Data
HWR, LWR
Write
Data
Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0)
Rev. 5.00 Aug 02, 2006 page 131 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.6
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)
BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1
burst ROM interface settings can be made independently in BROMCRH and BROMCRL,
respectively.
Bit
Bit Name
Initial Value
R/W
7
BSRMn
0
R/W
Description
Burst ROM Interface Select
Selects the basic bus interface or burst ROM
interface.
0: Basic bus interface space
1: Burst ROM interface space
6
5
4
BSTSn2
BSTSn1
BSTSn0
0
0
0
R/W
R/W
R/W
Burst Cycle Select
These bits select the number of burst cycle
states.
000: 1 state
001: 2 states
010: 3 states
011: 4 states
100: 5 states
101: 6 states
110: 7 states
111: 8 states
3
and
2
−
1
0
BSWDn1
BSWDn0
0
R/W
Reserved
Though these bits can be read from or written to,
the write value should always be 0.
0
0
R/W
R/W
Burst Word Number Select
These bits select the number of words that can
be burst-accessed on the burst ROM interface.
00: Maximum 4 words
01: Maximum 8 words
10: Maximum 16 words
11: Maximum 32 words
(n = 1 or 0)
Rev. 5.00 Aug 02, 2006 page 132 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.7
Bus Control Register (BCR)
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
Bit Name
Initial Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used
as I/O ports
1: External bus release enabled
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13
−
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
12
IDLC
1
R/W
Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
11
ICIS1
1
R/W
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
Rev. 5.00 Aug 02, 2006 page 133 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
ICIS0
1
R/W
Idle Cycle Insert 0
When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
9
WDBE
0
R/W
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle or DMAC single address
transfer cycle.
0: Write data buffer function not used
1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable
Selects enabling or disabling of wait input by the
WAIT pin.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
7 to 3
−
0
R/W
Reserved
Though these bits can be read from or written to,
the write value should always be 0.
2
ICIS2
0
R/W
Idle Cycle Insert 2
When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
1 and 0
−
0
R/W
Reserved
Though these bits can be read from or written to,
the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 134 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.8
DRAM Control Register (DRAMCR)
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Bit
Bit Name
Initial Value
R/W
Description
15
OEE
0
R/W
OE Output Enable
The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The OE signal is common to all
areas designated as DRAM space.
0: OE signal output disabled
(OE) pin can be used as I/O port
1: OE signal output enabled
14
RAST
0
R/W
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS
signal is asserted from the start of the Tr cycle
(rising edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in Tr
cycle
1: RAS is asserted from start of Tr cycle
13
−
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
12
CAST
0
R/W
Column Address Output Cycle Number Select
Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all
areas designated as DRAM space.
0: 2-state column address output cycle
1: 3-state column address output cycle
11
−
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 135 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
RMTS2
RMTS1
RMTS0
0
0
0
R/W
R/W
R/W
DRAM Space Select
These bits designate DRAM space for areas 2
to 5.
When continuous DRAM space is set, it is
possible to connect large-capacity DRAM
exceeding 2 Mbytes per area. In this case, the
RAS signal is output from the CS2 pin.
000: Normal space
001: Normal space in areas 3 to 5
DRAM space in area 2
010: Normal space in areas 4 and 5
DRAM space in areas 2 and 3
011: Reserved (setting prohibited)
100: Reserved (setting prohibited)
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Continuous DRAM space in areas 2 to 5
7
BE
0
R/W
Burst Access Enable
Selects enabling or disabling of burst access to
areas designated as DRAM space. DRAM
space burst access is performed in fast page
mode. When using EDO page mode DRAM, the
OE signal must be connected.
0: Full access
1: Access in fast page mode
Rev. 5.00 Aug 02, 2006 page 136 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
6
RCDM
0
R/W
RAS Down Mode
When access to DRAM space is interrupted by
an access to normal space, an access to an
internal I/O register, etc., this bit selects whether
the RAS signal is held low while waiting for the
next DRAM access (RAS down mode), or is
driven high again (RAS up mode). The setting
of this bit is valid only when the BE bit is set to
1.
If this bit is cleared to 0 when set to 1 in the
RAS down state, the RAS down state is cleared
at that point, and RAS goes high.
0: RAS up mode selected for DRAM space
access
1: RAS down mode selected for DRAM space
access
5
DDS
0
R/W
DMAC Single Address Transfer Option
Selects whether full access is always performed
or burst access is enabled when DMAC single
address transfer is performed on the DRAM
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM burst access, DMAC single
address transfer is performed in full access
mode regardless of the setting of this bit.
This bit has no effect on other bus master
external accesses or DMAC dual address
transfers.
0: Full access is always executed
1: Burst access is enabled
4 and
3
−
0
R/W
Reserved
Though these bits can be read from or written
to, the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 137 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM interface, these bits also
select the row address bits to be used for
comparison.
For details, refer to section 6.6.2, Address
Multiplexing.
000: 8-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
011: 11-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
1××: Setting prohibited
Legend:
×: Don't care
Rev. 5.00 Aug 02, 2006 page 138 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
Tp
Tr
Tc1
Tc2
φ
Row address
Address
RAST = 0
RAS
RAST = 1
RAS
Column address
UCAS, LCAS
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)
Rev. 5.00 Aug 02, 2006 page 139 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.9
DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM interface bus specifications.
Bit
Bit Name
Initial Value
R/W
Description
7
DRMI
0
R/W
Idle Cycle Insertion
An idle cycle can be inserted after a DRAM
access cycle when a continuous normal space
access cycle follows a DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
6
−
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
5
4
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1-state RAS precharge cycle
01: 2-state RAS precharge cycle
10: 3-state RAS precharge cycle
11: 4-state RAS precharge cycle
3
2
—
1
0
RCD1
RCD0
0
R/W
Reserved
Though these bits can be read from or written to,
the write value should always be 0.
0
0
R/W
R/W
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
Rev. 5.00 Aug 02, 2006 page 140 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.10
Refresh Control Register (REFCR)
REFCR specifies DRAM interface refresh control.
Bit
15
Bit Name
CMF
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
When 0 is written to CMF after reading CMF
= 1 while the RFSHE bit is cleared to 0
•
When CBR refreshing is executed while the
RFSHE bit is set to 1
[Setting condition]
When RTCOR = RTCNT
14
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
13
12
RCW1
RCW0
0
0
R/W
R/W
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
11
−
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Note:
*
Only 0 can be written, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 141 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
9
8
RTCK2
RTCK1
RTCK0
0
0
0
R/W
R/W
R/W
Refresh Counter Clock Select
These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0,
the refresh counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
7
RFSHE
0
R/W
Refresh Control
Refresh control can be performed. When
refresh control is not performed, the refresh
timer can be used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
6
CBRM
0
R/W
CBR Refresh Control Mode
Selects CBR refreshing performed in parallel
with other external accesses, or execution of
CBR refreshing alone.
0: External access during CAS-before-RAS
refreshing is enabled
1: External access during CAS-before-RAS
refreshing is disabled
5
4
RLW1
RLW0
0
0
R/W
R/W
Refresh Cycle Wait Control
These bits select the number of wait states to
be inserted in a DRAM interface CAS-beforeRAS refresh cycle. This setting applies to all
areas designated as DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Rev. 5.00 Aug 02, 2006 page 142 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
3
SLFRF
0
R/W
Self-Refresh Enable
If this bit is set to 1, DRAM self-refresh mode is
selected when a transition is made to the
software standby state. This bit is valid when
the RFSHE bit is set to 1, enabling refresh
operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
2
1
0
TPCS2
TPCS1
TPCS0
0
0
0
R/W
R/W
R/W
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after selfrefreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to
the number of states set by bits TPC1 and
TPC0 in DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
Rev. 5.00 Aug 02, 2006 page 143 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.3.11
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock
selected by bits RTCK2 to RTCK0 in REFCR.
When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and
RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is
started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match
interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.3.12
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that sets the period for compare match operations
with RTCNT.
The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in
REFCR is set to 1 and RTCNT is cleared to H'00.
RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.4
Operation
6.4.1
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Chip select signals (CS0 to CS7)
can be output for each area. Figure 6.5 shows an outline of the memory map.
Rev. 5.00 Aug 02, 2006 page 144 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
H'000000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
Figure 6.5 Area Divisions
Rev. 5.00 Aug 02, 2006 page 145 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.4.2
Bus Specifications
The external space bus specifications consist of five elements: bus width, number of access states,
number of program wait states, read strobe timing, and chip select (CS) assertion period extension
states. The bus width and number of access states for on-chip memory and internal I/O registers
are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space. With the DRAM interface and burst ROM
interface, the number of access states may be determined without regard to the setting of ASTCR.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus
width, and number of access states and program wait states) for each basic bus interface area.
Rev. 5.00 Aug 02, 2006 page 146 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
ABWn
ASTn
Wn2
Wn1
Wn0
Bus Width
Access
States
Program Wait
States
0
0
—
—
—
16
2
0
1
0
0
0
3
0
WTCRA, WTCRB
1
1
0
1
1
Bus Specifications (Basic Bus Interface)
1
1
0
2
1
3
0
4
1
5
0
6
1
7
0
—
—
—
1
0
0
0
1
1
1
0
2
1
3
0
4
1
5
0
6
1
7
1
0
1
8
2
0
3
0
(n = 0 to 7)
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS
CS)
CS Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
Rev. 5.00 Aug 02, 2006 page 147 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.4.3
Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on a synchronous DRAM interface that allows direct connection of
synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and an area for which the
burst ROM interface is designated functions as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external space, and in expanded mode with on-chip ROM
disabled, all of area 0 is external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Area 1: In externally expanded mode, all of area 1 is external space.
When area 1 external space is accessed, the CS1 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 1.
Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface, or DRAM interface can be selected for areas 2 to 5. With the DRAM
interface, signals CS2 and CS3 are used as RAS signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Rev. 5.00 Aug 02, 2006 page 148 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Only the basic bus interface can be used for area 6.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded
mode, the space excluding the on-chip RAM and internal I/O registers is external space. The onchip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external space.
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.6 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to
CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 is used as RAS signals.
Rev. 5.00 Aug 02, 2006 page 149 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T1
Address bus
T2
T3
Area n external address
Figure 6.6 CSn Signal Output Timing (n = 0 to 7)
6.5
Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 6.7 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
Rev. 5.00 Aug 02, 2006 page 150 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Upper data bus
D15
Lower data bus
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword
size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure 6.8 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
D15
Byte size
• Even address
Byte size
• Odd address
Lower data bus
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space)
Rev. 5.00 Aug 02, 2006 page 151 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.5.2
Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3
Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data Bus
(D15 to D8)
(D7 to D0)
8-bit access
space
Byte
Read
—
RD
Valid
Write
—
HWR
16-bit access
space
Byte
Read
Even
RD
Area
Odd
Hi-Z
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
—
RD
Valid
Valid
Write
—
HWR, LWR
Valid
Valid
Write
Word
Invalid
Notes: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
Rev. 5.00 Aug 02, 2006 page 152 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.5.3
Basic Timing
8-Bit, 2-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space
Rev. 5.00 Aug 02, 2006 page 153 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
High
LWR
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space
Rev. 5.00 Aug 02, 2006 page 154 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
16-Bit, 2-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)
Rev. 5.00 Aug 02, 2006 page 155 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
High impedance
D15 to D8
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)
Rev. 5.00 Aug 02, 2006 page 156 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
Rev. 5.00 Aug 02, 2006 page 157 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
16-Bit, 3-State Access Space: Figures 6.14 to 6.16 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)
Rev. 5.00 Aug 02, 2006 page 158 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)
Rev. 5.00 Aug 02, 2006 page 159 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
Rev. 5.00 Aug 02, 2006 page 160 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.5.4
Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in 3-state access space, according to the settings in
WTCRA and WTCRB.
Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the
WAIT pin. When external space is accessed in this state, a program wait is first inserted in
accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge
of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states
are inserted until it goes high. This is useful when inserting seven or more Tw states, or when
changing the number of Tw states to be inserted for different external devices. The WAITE bit
setting applies to all areas. Figure 6.17 shows an example of wait state insertion timing.
The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input
disabled.
Rev. 5.00 Aug 02, 2006 page 161 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Notes: 1. Downward arrows indicate the timing of WAIT pin sampling.
2. When RDN = 0
Figure 6.17 Example of Wait State Insertion Timing
6.5.5
Read Strobe (RD
RD)
RD Timing
The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to
1 in RDNCR. Figure 6.18 shows an example of the timing when the read strobe timing is changed
in basic bus 3-state access space.
When the DMAC is used in single address mode, note that if the RD timing is changed by setting
RDNn to 1, the RD timing will change relative to the rise of DACK.
Rev. 5.00 Aug 02, 2006 page 162 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
T3
φ
Address bus
CSn
AS
RD
RDNn = 0
Data bus
RD
RDNn = 1
Data bus
DACK
Figure 6.18 Example of Read Strobe Timing
6.5.6
Extension of Chip Select (CS
CS)
CS Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.19 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Rev. 5.00 Aug 02, 2006 page 163 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
φ
Address bus
CSn
AS
Read
(when
RDNn = 0)
RD
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended
Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0).
Rev. 5.00 Aug 02, 2006 page 164 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6
DRAM Interface
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.6.1
Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and continuous
area (areas 2 to 5).
Table 6.4
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
1
Normal space
Normal space
Normal space
DRAM space
1
0
Normal space
Normal space
DRAM space
DRAM space
1
0
1
1
Reserved (setting prohibited)
0
Reserved (setting prohibited)
1
Reserved (setting prohibited)
0
Reserved (setting prohibited)
1
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.6.2
Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
Rev. 5.00 Aug 02, 2006 page 165 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Table 6.5
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
Address Pins
A23
to
MXC2 MXC1 MXC0 Shift Size A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Row
0
0
0
8 bits
address
A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
to
A16
1
9 bits
A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
to
A16
1
0
10 bits
A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
to
A16
1
11 bits
A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
to
A16
1
×
×
Column 0
×
×
address
Reserved (setting prohibited)
—
A23 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6
A5 A4 A3 A2 A1 A0
to
A16
×
1
×
Reserved (setting prohibited)
Legend:
×: Don’t care.
6.6.3
Data Bus
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
Rev. 5.00 Aug 02, 2006 page 166 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.4
Pins Used for DRAM Interface
Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2, CS5 pins
are in the input state after a reset, set the corresponding DDR to 1 when RAS2, RAS5 signals are
output.
Table 6.6
DRAM Interface Pins
Pin
With DRAM
Setting
Name
I/O
Function
HWR
WE
Write enable
Output
Write enable for DRAM space
access
CS2
RAS2
Row address strobe 2/
row address strobe
Output
Row address strobe when area
2 is designated as DRAM space
or row address strobe when
areas 2 to 5 are designated as
continuous DRAM space
CS3
RAS3
Row address strobe 3
Output
Row address strobe when area
3 is designated as DRAM space
UCAS
UCAS
Upper column address
strobe
Output
Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
LCAS
LCAS
Lower column address
strobe
Output
Lower column address strobe
signal for 16-bit DRAM space
access
RD, OE
OE
Output enable
Output
Output enable signal for DRAM
space access
WAIT
WAIT
Wait
Input
Wait request signal
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
Rev. 5.00 Aug 02, 2006 page 167 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.5
Basic Timing
Figure 6.20 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address
output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM
space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output
Rev. 5.00 Aug 02, 2006 page 168 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
6.6.6
Column Address Output Cycle Control
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.21
shows an example of the timing when a 3-state column address output cycle is selected.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0)
Rev. 5.00 Aug 02, 2006 page 169 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.7
Row Address Output State Control
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.22 shows an example of the timing when the RAS signal goes low
from the beginning of the Tr state.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.22 Example of Access Timing when RAS Signal Goes Low from Beginning
of Tr State (CAST = 0)
Rev. 5.00 Aug 02, 2006 page 170 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three Trw states, in which row address output is
maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the falling edge of the RAS signal according to the DRAM connected
and the operating frequency of this LSI. Figure 6.23 shows an example of the timing when one Trw
state is set.
Tp
Tr
Trw
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.23 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 171 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.8
Precharge State Control
When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is
always inserted when DRAM space is accessed. From one to four Tp states can be selected by
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the
DRAM connected and the operating frequency of this LSI. Figure 6.24 shows the timing when
two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh
cycles.
Tp2
Tp1
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.24 Example of Timing with Two-State Precharge Cycle
(RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 172 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.9
Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM
space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2
state, according to the WTCR setting.
Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait
input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a
program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or
Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it
goes high.
Figures 6.25 and 6.26 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles.
Rev. 5.00 Aug 02, 2006 page 173 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
By program wait
Tp
Tr
Tc1
Tw
By WAIT pin
Tw
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Notes: Downward arrows indicate the timing of WAIT pin sampling.
n = 2, 3
Figure 6.25 Example of Wait State Insertion Timing
(2-State Column Address Output)
Rev. 5.00 Aug 02, 2006 page 174 of 980
REJ09B0050-0500
Tc2
Section 6 Bus Controller (BSC)
Tp
Tr
By program wait
By WAIT pin
Tc1
Tw
Tw
Tc2
Tc3
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Notes: Downward arrows indicate the timing of WAIT pin sampling.
n = 2, 3
Figure 6.26 Example of Wait State Insertion Timing
(3-State Column Address Output)
Rev. 5.00 Aug 02, 2006 page 175 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.10
Byte Access Control
When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access. Figure 6.27 shows the control timing for 2-CAS access,
and figure 6.28 shows an example of 2-CAS DRAM connection.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS
LCAS
High
WE (HWR)
OE (RD)
High
Upper data bus
Write data
High impedance
Lower data bus
Note: n = 2, 3
Figure 6.27 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 176 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
This LSI
(Address shift size
set to 10 bits)
2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
RASn (CSn)
RAS
UCAS
UCAS
LCAS
LCAS
HWR (WE)
RD (OE)
A10
WE
OE
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
Row address input:
A9 to A0
Column address input:
A9 to A0
D15 to D0
Figure 6.28 Example of 2-CAS DRAM Connection
6.6.11
Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.29 and 6.30 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
Rev. 5.00 Aug 02, 2006 page 177 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc1
Tc2
φ
Address bus
Row address
Column address 1 Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.29 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 178 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc3
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address 1
Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2, 3
Figure 6.30 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 1)
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.6.9, Wait Control.
RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that
access to DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the RAS signal is held low during the access to the other space, burst operation can be
resumed when the same row address in DRAM space is accessed again.
• RAS Down Mode
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the RAS signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.31 shows an example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if:
a refresh operation is initiated in the RAS down state
self-refreshing is performed
Rev. 5.00 Aug 02, 2006 page 179 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
the chip enters software standby mode
the external bus is released
the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
DRAM space read
Tp
Tr
Tc1
Tc2
Normal space
read
DRAM space
read
T1
Tc1
T2
Tc2
φ
Row address
Address bus
Column address 1
External address Column address 2
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2, 3
Figure 6.31 Example of Operation Timing in RAS Down Mode
(RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 180 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.32 shows an example of
the timing in RAS up mode.
DRAM space read
Tp
Tr
Tc1
Tc2
DRAM space
read
Normal space
read
Tc1
T1
Tc2
T2
φ
Address bus
Row address
Column address 1 Column address 2
External address
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2, 3
Figure 6.32 Example of Operation Timing in RAS Up Mode
(RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 181 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.6.12
Refresh Control
This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing
is used. In addition, self-refreshing can be executed when the chip enters the software standby
state.
Refresh control is enabled when any area is designated as DRAM space in accordance with the
setting of bits RMTS2 to RMTS0 in DRAMCR.
CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in
REFCR.
With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the DRAM used.
When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR
settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is
shown in figure 6.33, compare match timing in figure 6.34, and CBR refresh timing in figure 6.35.
When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is
performed in parallel during the CBR refresh period.
RTCNT
RTCOR
H'00
Refresh request
Figure 6.33 RTCNT Operation
Rev. 5.00 Aug 02, 2006 page 182 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
RTCNT
N
H'00
RTCOR
N
Refresh request
signal and CMF bit
setting signal
Figure 6.34 Compare Match Timing
TRp
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, LCAS
Note: n = 2, 3
Figure 6.35 CBR Refresh Timing
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.36 shows the timing when bits RCW1 and RCW0 are set.
Rev. 5.00 Aug 02, 2006 page 183 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
TRp
TRrw
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, LCAS
Note: n = 2, 3
Figure 6.36 CBR Refresh Timing
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.37 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
Rev. 5.00 Aug 02, 2006 page 184 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Normal space access request
φ
A23 to A0
CS
AS
RD
HWR (WE)
Refresh period
RAS
CAS
Figure 6.37 Example of CBR Refresh Timing (CBRM = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP
instruction is executed to enter software standby mode, the CAS and RAS signals are output and
DRAM enters self-refresh mode, as shown in figure 6.38.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically. If a CBR refresh request occurs when making a transition to software
standby mode, CBR refreshing is executed, and then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
Rev. 5.00 Aug 02, 2006 page 185 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
TRp
Software
standby
TRr
TRc3
φ
CSn (RASn)
UCAS, LCAS
HWR (WE)
High
Note: n = 2, 3
Figure 6.38 Self-Refresh Timing
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.39 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.
Rev. 5.00 Aug 02, 2006 page 186 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Software
standby
DRAM space write
Trc3
Trp1
Trp2
Tp
Tr
Tc1
Tc2
φ
Address bus
RASn (CSn)
UCAS, LCAS
OE (RD)
HWR (WE)
Data bus
Note: n = 2, 3
Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR
refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in
sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH.
6.6.13
DMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the DACK output timing can be selected
with the DDS bit in DRAMCR. When DRAM space is accessed in DMAC single address mode at
the same time, these bits select whether or not burst access is to be performed.
Rev. 5.00 Aug 02, 2006 page 187 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
When DDS = 1 : Burst access is performed by determining the address only, irrespective of the
bus master. With the DRAM interface, the DACK output goes low from the Tc1 state.
Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK
Note: n = 2, 3
Figure 6.40 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 188 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
When DDS = 0 : When DRAM space is accessed in DMAC single address transfer mode, full
access (normal access) is always performed. With the DRAM interface, the DACK output goes
low from the Tr state.
In modes other than DMAC single address transfer mode, burst access can be used when accessing
DRAM space.
Figure 6.41 shows the DACK output timing for the DRAM interface when DDS = 0.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK
Note: n = 2, 3
Figure 6.41 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1)
Rev. 5.00 Aug 02, 2006 page 189 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.7
Burst ROM Interface
In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst
ROM interfacing performed. The burst ROM space enables ROM with burst access capability to
be accessed at high speed.
Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the
setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for
burst access.
Settings can be made independently for area 0 and area 1.
In burst ROM space, burst access covers only CPU read accesses.
6.7.1
Basic Timing
The number of access states in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and
CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and
CSACRL are ignored.
From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to
BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up
to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and
BSTS10 in BROMCR.
The basic access timing for burst ROM space is shown in figures 6.42 and 6.43.
Rev. 5.00 Aug 02, 2006 page 190 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1, 0
Figure 6.42 Example of Burst ROM Access Timing
(ASTn = 1, 2-State Burst Cycle)
Rev. 5.00 Aug 02, 2006 page 191 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T1
T1
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1, 0
Figure 6.43 Example of Burst ROM Access Timing
(ASTn = 0, 1-State Burst Cycle)
6.7.2
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4,
Wait Control. Wait states cannot be inserted in a burst cycle.
6.7.3
Write Access
When a write access to burst ROM space is executed, burst access is interrupted at that point and
the write access is executed in line with the basic bus interface settings. Write accesses are not
performed in burst mode even though burst ROM space is designated.
Rev. 5.00 Aug 02, 2006 page 192 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.8
Idle Cycle
6.8.1
Operation
When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS1 = 0)
T2
T3
Data collision
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.44 xample of Idle Cycle Operation
(Consecutive Reads in Different Areas)
Rev. 5.00 Aug 02, 2006 page 193 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.45 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS0 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Figure 6.45 Example of Idle Cycle Operation (Write after Read)
Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.
Figure 6.46 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Rev. 5.00 Aug 02, 2006 page 194 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR, LWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS2 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
Figure 6.46 Example of Idle Cycle Operation (Read after Write)
Relationship between Chip Select (CS
CS)
RD)
CS Signal and Read (RD
RD Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.47. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Rev. 5.00 Aug 02, 2006 page 195 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
T2
Bus cycle B
T3
Overlap period between CS (area B)
and RD may occur
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
(a) No idle cycle insertion
(ICIS1 = 0)
Figure 6.47 Relationship between Chip Select (CS
CS)
RD)
CS and Read (RD
RD
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The
timing in this case is shown in figure 6.48.
External read
T1
T2
T3
DRAM space read
Tp
Tr
Tc1
Tc2
φ
Address bus
RD
Data bus
Figure 6.48 Example of DRAM Full Access after External Read
(CAST = 0)
Rev. 5.00 Aug 02, 2006 page 196 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.49 and 6.50.
DRAM space read
Tp
Tr
Tc1
External read
Tc2
T1
T2
T3
DRAM space read
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 197 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
External read
Tc2
T1
T2
T3
DRAM space write
Ti
Tc1
Tc2
φ
Address bus
RD
HWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.51 and 6.52 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.
Rev. 5.00 Aug 02, 2006 page 198 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tc1
Tr
External address space read
Tc2
Ti
T2
T1
DRAM space read
T3
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.51 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
DRAM space read
Tp
Tr
Tc1
External address space write DRAM space read
Tc2
Ti
T1
T2
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.52 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 199 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
• Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM
space write access, idle cycle is inserted in the first read cycle. The number of states of the idle
cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the
DRMI bit in DRACCR. Figure 6.53 shows an example of idle cycle operation when the ICIS2
bit is set to 1.
DRAM space read
Tp
Tr
Tc1
External space read
Tc2
Ti
T1
T2
DRAM space read
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
Rev. 5.00 Aug 02, 2006 page 200 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Table 6.7 shows whether an idle cycle is inserted or not in mixed access to normal space and
DRAM.
Table 6.7
Idle Cycles in Mixed Accesses to Normal Space and DRAM
Previous Access
Next Access
Normal space read
Normal space read
(different area)
DRAM/ space read
Normal space write
DRAM/ space write
DRAM/ space read
Normal space read
DRAM/ space read
Normal space write
DRAM/ space write
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
—
0
—
—
—
Disabled
—
1
—
—
0
1 state inserted
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
—
0
1 state inserted
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
—
0
1 state inserted
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
—
0
1 state inserted
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
0
—
Disabled
1
0
1 state inserted
1
2 states inserted
—
0
—
—
—
Disabled
—
1
—
0
—
Disabled
1
0
1 state inserted
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
0
—
Disabled
1
0
1 state inserted
1
2 states inserted
—
—
0
—
—
Disabled
—
—
1
0
—
Disabled
1
0
1 state inserted
1
2 states inserted
Rev. 5.00 Aug 02, 2006 page 201 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
Previous Access
Next Access
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
Normal space write
Normal space read
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
1
2 states inserted
DRAM/ space read
DRAM/ space write
Normal space read
DRAM/ space read
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
1
2 states inserted
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
1
2 states inserted
0
—
—
—
—
Disabled
1
—
—
—
0
1 state inserted
1
2 states inserted
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/ space burst access. Figures 6.54 shows an
example of the timing for idle cycle insertion in the case of consecutive read and write accesses to
DRAM/continuous synchronous DRAM space.
Rev. 5.00 Aug 02, 2006 page 202 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
DRAM space write
Tc2
Ti
Tc1
Tc2
φ
Address bus
RASn (CSn)
UCAS, LCAS
HWR
OE (RD)
Data bus
Note: n = 2, 3
Idle cycle
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode
Rev. 5.00 Aug 02, 2006 page 203 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.8.2
Pin States in Idle Cycle
Table 6.8 shows the pin states in an idle cycle.
Table 6.8
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
CSn (n = 7 to 0)
High impedance
1 2
High* *
UCAS, LCAS
High*
AS
High
RD
High
OE
High
HWR, LWR
High
DACKn (n = 1, 0)
High
2
Notes: 1. Remains low in DRAM space RAS down mode.
2. Remains low in a DRAM space refresh cycle.
6.9
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.55 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
Rev. 5.00 Aug 02, 2006 page 204 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
φ
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External address
CSn
External space
write
HWR, LWR
D15 to D0
Figure 6.55 Example of Timing when Write Data Buffer Function is Used
Rev. 5.00 Aug 02, 2006 page 205 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.10
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access. If any of the following requests are issued in the external bus released state, the BREQO
signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
6.10.1
Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters can perform accesses using the internal bus.
When an internal bus master wants to make an external access, it temporarily defers initiation of
the bus cycle, and waits for the bus request from the external bus master to be canceled. If a
refresh request is generated in the external bus released state, or if a SLEEP instruction is executed
to place the chip in software standby mode or all-module-clocks-stopped mode, refresh control
and software standby or all-module-clocks-stopped control is deferred until the bus request from
the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
Rev. 5.00 Aug 02, 2006 page 206 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
(High) External bus release > External access by internal bus master (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)
6.10.2
Pin States in External Bus Released State
Table 6.9 shows pin states in the external bus released state.
Table 6.9
Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn (n = 7 to 0)
High impedance
UCAS, LCAS
High impedance
AS
High impedance
RD
High impedance
OE
High impedance
HWR, LWR
High impedance
DACKn (n = 1, 0)
High
Rev. 5.00 Aug 02, 2006 page 207 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.10.3
Transition Timing
Figure 6.56 shows the timing for transition to the bus released state.
External space
access cycle
CPU
cycle
External bus released state
T1
T2
φ
High impedance
Address bus
High impedance
Data bus
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
BREQ
BACK
BREQO
[1]
[2]
[3]
[4]
[5]
[6]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Note: However that if BREQO is asserted by a CBR refresh request, BREQO signal is
kept low until a CBR refresh cycle starts.
Figure 6.56 Bus Released State Transition Timing
Rev. 5.00 Aug 02, 2006 page 208 of 980
REJ09B0050-0500
[7]
[8]
Section 6 Bus Controller (BSC)
6.11
Bus Arbitration
This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration).
There are three bus masters—the CPU, DTC, and DMAC—which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
6.11.1
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC > DTC > CPU (Low)
An internal bus access by internal bus masters and external bus release, a refresh when the CBRM
bit is 0 can be executed in parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
(High) Refresh > External bus release (Low)
(High) External bus release > External access by internal bus master (Low)
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Rev. 5.00 Aug 02, 2006 page 209 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.11.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing
for transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
• If the CPU is in sleep mode, the bus is transferred immediately.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is
generated.
In the case of an external request in short address mode or normal mode, and in cycle steal mode,
the DMAC releases the bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer. However, in the event of external bus release request, which have a
higher priority than the DMAC, the bus may be transferred to the bus master even if block or burst
transfer is in progress.
External Bus Release: When the BREQ pin goes low and an external bus release request is
issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
Rev. 5.00 Aug 02, 2006 page 210 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.12
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.13
Usage Notes
6.13.1
External Bus Release Function and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =
H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered
in which the clock is also stopped for the bus controller and I/O ports. In this state, the external
bus release function is halted. To use the external bus release function in sleep mode, the ACSE
bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in allmodule-clocks-stopped mode is executed in the external bus released state, the transition to allmodule-clocks-stopped mode is deferred and performed until after the bus is recovered.
6.13.2
External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.13.3
External Bus Release Function and CBR Refreshing
CBR refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to
1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh request is
issued.
Rev. 5.00 Aug 02, 2006 page 211 of 980
REJ09B0050-0500
Section 6 Bus Controller (BSC)
6.13.4
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
Rev. 5.00 Aug 02, 2006 page 212 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Section 7 DMA Controller (DMAC)
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
Features
• Choice of short address mode or full address mode
Short address mode
Maximum of 4 channels can be used
Dual address mode or single address mode can be selected
In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
In single address mode, transfer source or transfer destination address only is specified as
24 bits
In single address mode, transfer can be performed in one bus cycle
Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
Maximum of 2 channels can be used
Transfer source and transfer destination addresses as specified as 24 bits
Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt
A/D converter conversion end interrupt
External request
Auto-request
• Module stop mode can be set
DMAS260A_010020020100
Rev. 5.00 Aug 02, 2006 page 213 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus
Address buffer
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
MAR_0AH
IOAR_0A
ETCR_0A
MAR_0BH
ETCR_0B
MAR_1AH
MAR_1AL
IOAR_1A
ETCR_1A
MAR_1BH
Internal data bus
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Execute transfer count register
Figure 7.1 Block Diagram of DMAC
Rev. 5.00 Aug 02, 2006 page 214 of 980
REJ09B0050-0500
MAR_0BL
IOAR_0B
Data buffer
Legend:
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
MAR_0AL
MAR_1BL
IOAR_1B
ETCR_1B
Module data bus
DMAWER
Channel 1B Channel 1A Channel 0B Channel 0A
Control logic
Channel 0
Processor
Channel 1
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
Section 7 DMA Controller (DMAC)
7.2
Input/Output Pins
Table 7.1 summarizes the pins of the interrupt controller.
Table 7.1
Pin Configuration
Channel
Pin Name
Symbol
I/O
Function
0
DMA request 0
DREQ0
Input
Channel 0 external request
DMA transfer acknowledge 0
DACK0
Output
Channel 0 single address
transfer acknowledge
DMA transfer end 0
TEND0
Output
Channel 0 transfer end
DMA request 1
DREQ1
Input
Channel 1 external request
DMA transfer acknowledge 1
DACK1
Output
Channel 1 single address
transfer acknowledge
DMA transfer end 1
TEND1
Output
Channel 1 transfer end
1
7.3
Register Descriptions
• Memory address register_0AH (MAR_0AH)
• Memory address register_0AL (MAR_0AL)
• I/O address register_0A (IOAR_0A)
• Transfer count register_0A (ECTR_0A)
• Memory address register_0BH (MAR_0BH)
• Memory address register_0BL (MAR_0BL)
• I/O address register_0B (IOAR_0B)
• Transfer count register_0B (ECTR_0B)
• Memory address register_1AH (MAR_1AH)
• Memory address register_1AL (MAR_1AL)
• I/O address register_1A (IOAR_1A)
• Transfer count register_1A (ETCR_1B)
• Memory address register_1BH (MAR_1BH)
• Memory address register_1BL (MAR_1BL)
• I/O address register_1B (IOAR_1B)
• Transfer count register_1B (ETCR_1B)
• DMA control register_0A (DMACR_0A)
• DMA control register_0B (DMACR_0B)
Rev. 5.00 Aug 02, 2006 page 215 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
• DMA control register_1A (DMACR_1A)
• DMA control register_1B (DMACR_1B)
• DMA band control register H (DMABCRH)
• DMA band control register L (DMABCRL)
• DMA write enable register (DMAWER)
• DMA terminal control register (DMATCR)
The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.
Table 7.2
Short Address Mode and Full Address Mode (Channel 0)
0
Short address mode specified (channels 0A and 0B operate independently)
MAR_0AH
MAR_0BH
MAR_0AL
Specifies transfer source/transfer destination address
IOAR_0A
Specifies transfer destination/transfer source address
ETCR_0A
Specifies number of transfers
DMACR_0A
MAR_0BL
Specifies transfer size, mode, activation source
Specifies transfer source/transfer destination address
IOAR_0B
Specifies transfer destination/transfer source address
ETCR_0B
Specifies number of transfers
DMACR_0B
Specifies transfer size, mode, activation source
Full address mode specified (channels 0A and 0B operate in combination as channel 0)
Channel 0
1
Channel 0A
Description
Channel 0B
FAE0
MAR_0AH
MAR_0AL
Specifies transfer source address
MAR_0BH
MAR_0BL
Specifies transfer destination address
IOAR_0A
IOAR_0B
ETCR_0A
ETCR_0B
DMACR_0A DMACR_0B
Rev. 5.00 Aug 02, 2006 page 216 of 980
REJ09B0050-0500
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
Section 7 DMA Controller (DMAC)
7.3.1
Memory Address Registers (MARA and MARB)
MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.
The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).
MAR is not initialized by a reset or in standby mode.
Short Address Mode: In short address mode, MARA and MARB operate independently.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated.
Full Address Mode: In full address mode, MARA functions as the source address register, and
MARB as the destination address register.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination address is constantly updated.
7.3.2
I/O Address Registers (IOARA and IOARB)
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address
(transfer source address) or destination address (transfer destination address). The upper 8 bits of
the transfer address are automatically set to H'FF.
The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0
(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is not incremented or decremented each time a data transfer is executed, so the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
Rev. 5.00 Aug 02, 2006 page 217 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
IOAR can be used in short address mode but not in full address mode.
7.3.3
Execute Transfer Count Registers (ETCRA and ETCRB)
ETCR is a 16-bit readable/writable register that specifies the number of transfers.
The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0
(channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B).
ETCR is not initialized by a reset or in standby mode.
Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that
in repeat mode.
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is
decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit
in DMABCRL is cleared, and transfer ends.
In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer
count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when
the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is
automatically restored to the value it had when the count was started. The DTE bit in DMABCRL
is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the
user.
Full Address Mode: The function of ETCR in normal mode differs from that in block transfer
mode.
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not
used in normal mode.
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH functions
as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1-word
transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in
ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly
transfer blocks consisting of any desired number of bytes or words.
In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
Rev. 5.00 Aug 02, 2006 page 218 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.3.4
DMA Control Registers (DMACRA and DMACRB)
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B).
In short address mode, channels A and B operate independently, and in full address mode,
channels A and B operate together. The bit functions in the DMACR registers differ according to
the transfer mode.
Short Address Mode:
• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit
Bit Name
Initial Value
R/W
Description
7
DTSZ
0
R/W
6
DTID
0
R/W
5
RPE
0
R/W
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
• When DTSZ = 0, MAR is incremented by 1
• When DTSZ = 1, MAR is incremented by 2
1: MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1
• When DTSZ = 1, MAR is decremented by 2
Repeat Enable
Used in combination with the DTIE bit in
DMABCR to select the mode (sequential, idle, or
repeat) in which transfer is to be performed.
• When DTIE = 0 (no transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in repeat mode
• When DTIE = 1 (with transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in idle mode
Rev. 5.00 Aug 02, 2006 page 219 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
4
DTDIR
0
R/W
Data Transfer Direction
Used in combination with the SAE bit in
DMABCR to specify the data transfer direction
(source or destination). The function of this bit is
therefore different in dual address mode and
single address mode.
• When SAE = 0
0: Transfer with MAR as source address and
IOAR as destination address
1: Transfer with IOAR as source address and
MAR as destination address
• When SAE = 1
0: Transfer with MAR as source address and
DACK pin as write strobe
1: Transfer with DACK pin as read strobe and
MAR as destination address
Rev. 5.00 Aug 02, 2006 page 220 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor
(activation source). There are some
differences in activation sources for channel A
and channel B.
•
Channel A
0000: Setting prohibited
0001: Activated by A/D converter conversion
end interrupt
0010: Setting prohibited
0011: Setting prohibited
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
Rev. 5.00 Aug 02, 2006 page 221 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
•
2
DTF2
0
R/W
0000: Setting prohibited
1
DTF1
0
R/W
0
DTF0
0
R/W
0001: Activated by A/D converter conversion
end interrupt
Channel B
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than
one channel. In this case, activation starts with
the highest-priority channel according to the
relative channel priorities. For relative channel
priorities, see section 7.5.12, Multi-Channel
Operation.
Rev. 5.00 Aug 02, 2006 page 222 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Full Address Mode:
• DMACR_0A and DMACR_1A
Bit
Bit Name
Initial Value
R/W
Description
15
DTSZ
0
R/W
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
14
SAID
0
R/W
Source Address Increment/Decrement
13
SAIDE
0
R/W
Source Address Increment/Decrement Enable
These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
•
When DTSZ = 0, MARA is incremented by 1
•
When DTSZ = 1, MARA is incremented by 2
10: MARA is fixed
11: MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1
•
When DTSZ = 1, MARA is decremented by 2
12
BLKDIR
0
R/W
Block Direction
11
BLKE
0
R/W
Block Enable
These bits specify whether normal mode or
block transfer mode is to be used for data
transfer. If block transfer mode is specified, the
BLKDIR bit specifies whether the source side or
the destination side is to be the block area.
×0: Transfer in normal mode
01: Transfer in block transfer mode (destination
side is block area)
11: Transfer in block transfer mode (source side
is block area)
Rev. 5.00 Aug 02, 2006 page 223 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
10
to
8
0
R/W
Reserved
Though these bits can be read from or written to,
the write value should always be 0.
Legend:
×: Don't care
• DMACR_0B and DMACR_1B
Bit
Bit Name
Initial Value
R/W
Description
7
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
6
5
DAID
DAIDE
0
0
R/W
R/W
Destination Address Increment/Decrement
Destination Address Increment/Decrement
Enable
These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
•
When DTSZ = 0, MARB is incremented by 1
•
When DTSZ = 1, MARB is incremented by 2
10: MARB is fixed
11: MARB is decremented after a data transfer
4
—
0
R/W
•
When DTSZ = 0, MARB is decremented by 1
•
When DTSZ = 1, MARB is decremented by 2
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.
Rev. 5.00 Aug 02, 2006 page 224 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
• Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(for the first transfer after data transfer is
enabled, activated by DREQ pin low-level
input)
0011: Activated by DREQ pin low-level input
010×: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1×××: Setting prohibited
• Block Transfer Mode
0000: Setting prohibited
0001: Activated by A/D converter conversion
end interrupt
0010: Activated by DREQ pin falling edge input
(for the first transfer after data transfer is
enabled, activated by DREQ pin low-level
input)
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
complete interrupt
0101: Activated by SCI channel 0 reception
complete interrupt
0110: Activated by SCI channel 1 transmission
complete interrupt
0111: Activated by SCI channel 1 reception
complete interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
Rev. 5.00 Aug 02, 2006 page 225 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
The same factor can be selected for more than
one channel. In this case, activation starts with
the highest-priority channel according to the
relative channel priorities. For relative channel
priorities, see section 7.5.12, Multi-Channel
Operation.
Legend:
×: Don't care
7.3.5
DMA Band Control Registers H and L (DMABCRH and DMABCRL)
DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR
registers differ according to the transfer mode.
Short Address Mode:
• DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in
short address mode or full address mode. In
short address mode, channels 1A and 1B can be
used as independent channels.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in
short address mode or full address mode. In
short address mode, channels 0A and 0B can be
used as independent channels.
0: Short address mode
1: Full address mode
13
SAE1
0
R/W
Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
Rev. 5.00 Aug 02, 2006 page 226 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
12
SAE0
0
R/W
Single Address Enable 0
Specifies whether channel 0B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
11
DTA1B
0
R/W
Data Transfer Acknowledge 1B
10
DTA1A
0
R/W
Data Transfer Acknowledge 1A
9
DTA0B
0
R/W
Data Transfer Acknowledge 0B
8
DTA0A
0
R/W
Data Transfer Acknowledge 0A
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR.
It the DTA bit is set to 1 when DTE = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE = 1 and DTA = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
If the DTA bit is cleared to 0 when DTE = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this
case, the interrupt source should be cleared by
the CPU or DTC transfer.
When DTE = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA bit setting.
Rev. 5.00 Aug 02, 2006 page 227 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
• DMABCRL
Bit
Bit Name
Initial Value
R/W
Description
7
DTE1B
0
R/W
Data Transfer Enable 1B
6
DTE1A
0
R/W
Data Transfer Enable 1A
5
DTE0B
0
R/W
Data Transfer Enable 0B
4
DTE0A
0
R/W
Data Transfer Enable 0A
If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is enabled and the
DMAC ignores the activation source selected by
the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed in a transfer mode other
than repeat mode
•
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0
Rev. 5.00 Aug 02, 2006 page 228 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTIE1B
0
R/W
Data Transfer End Interrupt Enable 1B
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
1
DTIE0B
0
R/W
Data Transfer End Interrupt Enable 0B
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit
is set to 1 when DTE = 0, the DMAC regards this
as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or
DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE bit to 1.
Rev. 5.00 Aug 02, 2006 page 229 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Full Address Mode:
• DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in
short address mode or full address mode.
In full address mode, channels 1A and 1B are
used together as channel 1.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in
short address mode or full address mode.
In full address mode, channels 0A and 0B are
used together as channel 0.
0: Short address mode
1: Full address mode
13
—
0
R/W
Reserved
12
—
0
R/W
Though these bits can be read from or written to,
the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 230 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
11
DTA1
0
R/W
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE1 = 1 and DTA1 =
1, the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1,
the internal interrupt source is not cleared when
a transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
10
—
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 231 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
9
DTA0
0
R/W
Data Transfer Acknowledge 0
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 0.
It the DTA0 bit is set to 1 when DTE0 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE0 = 1 and DTA0 =
1, the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
It the DTA0 bit is cleared to 0 when DTE0 = 1,
the internal interrupt source is not cleared when
a transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE0 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA0 bit setting.
The state of the DTME0 bit does not affect the
above operations.
8
—
0
R/W
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Rev. 5.00 Aug 02, 2006 page 232 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
• DMABCRL
Bit
Bit Name
Initial Value
R/W
7
DTME1
0
R/W
Description
Data Transfer Master Enable 1
Together with the DTE1 bit, this bit controls
enabling or disabling of data transfer on channel
1. When both the DTME1 bit and DTE1 bit are
set to 1, transfer is enabled for channel 1.
If channel 1 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME1 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When
the DTME1 bit is subsequently set to 1 again,
the interrupted transfer is resumed. In block
transfer mode, however, the DTME1 bit is not
cleared by an NMI interrupt, and transfer is not
interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME1 bit
[Setting condition]
When 1 is written to DTME1 after reading
DTME1 = 0
Rev. 5.00 Aug 02, 2006 page 233 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
6
DTE1
0
R/W
Data Transfer Enable 1
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and
the activation source is ignored. If the activation
source is an internal interrupt, an interrupt
request is issued to the CPU or DTC. If the
DTIE1 bit is set to 1 when DTE1 = 0, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to the
CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by
the activation source. When a request is issued
by the activation source, DMA transfer is
executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0
Rev. 5.00 Aug 02, 2006 page 234 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
5
DTME0
0
R/W
Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on channel
0. When both the DTME0 bit and DTE0 bit are
set to 1, transfer is enabled for channel 0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When
the DTME0 bit is subsequently set to 1 again,
the interrupted transfer is resumed. In block
transfer mode, however, the DTME0 bit is not
cleared by an NMI interrupt, and transfer is not
interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME0 bit
[Setting condition]
When 1 is written to DTME0 after reading
DTME0 = 0
Rev. 5.00 Aug 02, 2006 page 235 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
4
DTE0
0
R/W
Data Transfer Enable 0
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 0.
When DTE0 = 0, data transfer is disabled and
the activation source is ignored. If the activation
source is an internal interrupt, an interrupt
request is issued to the CPU or DTC. If the
DTIE0 bit is set to 1 when DTE0 = 0, the DMAC
regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to the
CPU.
When DTE0 = 1 and DTME0 = 1, data transfer is
enabled and the DMAC waits for a request by
the activation source. When a request is issued
by the activation source, DMA transfer is
executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE0 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE0 bit after reading
DTE0 = 0
3
DTIE1B
0
R/W
Data Transfer Interrupt Enable 1B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
When DTME1 is cleared to 0 while this bit is set
to 1, the DMAC regards this as indicating a
break in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE1B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME1 bit to 1.
Rev. 5.00 Aug 02, 2006 page 236 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE1 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
1
DTIE0B
0
R/W
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted.
When DTME0 is cleared to 0 while this bit is set
to 1, the DMAC regards this as indicating a
break in the transfer, and issues a transfer break
interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. When DTE0 is cleared
to 0 while this bit is set to 1, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
Rev. 5.00 Aug 02, 2006 page 237 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.3.6
DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
0
R
Reserved
3
WE1B
These bits are always read as 0 and cannot be
modified.
0
R/W
Write Enable 1B
Enables or disables writes to all bits in
DMACR1B, bits 11, 7, and 3 in DMABCR, and
bit 5 in DMATCR.
0: Writes are disabled
1: Writes are enabled
2
WE1A
0
R/W
Write Enable 1A
Enables or disables writes to all bits in
DMACR1A, and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
1
WE0B
0
R/W
Write Enable 0B
Enables or disables writes to all bits in
DMACR0B, bits 9, 5, and 1 in DMABCR, and
bit 4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
0
WE0A
0
R/W
Write Enable 0A
Enables or disables writes to all bits in
DMACR0A, and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
Rev. 5.00 Aug 02, 2006 page 238 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
First transfer area
MAR_0A
IOAR_0A
ETCR_0A
MAR_0B
IOAR_0B
ETCR_0B
MAR_1A
DTC
IOAR_1A
ETCR_1A
MAR_1B
IOAR_1B
ETCR_1B
Second transfer area
using chain transfer
DMAWER
DMATCR
DMACR_0A
DMACR_0B
DMACR_1A
DMACR_1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
Rev. 5.00 Aug 02, 2006 page 239 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.3.7
DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
In short address mode, the TEND pin is only available for channel B. The transfer end signal
indicates the transfer cycle in which the transfer counter has become 0 regardless of the transfer
source. Note however that the transfer end signal exceptionally indicates the transfer cycle in
which the block counter has become 0 in block transfer mode.
Bit
Bit Name
Initial Value
R/W
Description
7
0
Reserved
6
0
These bits are always read as 0 and cannot be
modified.
5
TEE1
0
R/W
Transfer End Enable 1
Enables or disables transfer end pin 1
(TEND1) output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4
TEE0
0
R/W
Transfer End Enable 0
Enables or disables transfer end pin 0
(TEND0) output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3
to
0
0
Rev. 5.00 Aug 02, 2006 page 240 of 980
REJ09B0050-0500
Reserved
These bits are always read as 0 and cannot be
modified.
Section 7 DMA Controller (DMAC)
7.4
Activation Sources
DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and
channel, as shown in table 7.3.
Table 7.3
DMAC Activation Sources
Short Address Mode
Full Address Mode
Channels
0A and 1A
Channels
0B and 1B
Normal
Mode
Block
Transfer
Mode
ADI
Ο
Ο
X
Ο
TXI0
Ο
Ο
X
Ο
RXI0
Ο
Ο
X
Ο
TXI1
Ο
Ο
X
Ο
RXI1
Ο
Ο
X
Ο
TGI0A
Ο
Ο
X
Ο
TGI1A
Ο
Ο
X
Ο
TGI2A
Ο
Ο
X
Ο
TGI3A
Ο
Ο
X
Ο
Activation Source
Internal
interrupts
External
requests
TGI4A
Ο
Ο
X
Ο
TGI5A
Ο
Ο
X
Ο
DREQ pin falling edge input
X
Ο
Ο
Ο
DREQ pin low-level input
X
Ο
Ο
Ο
X
X
Ο
X
Auto-request
Legend:
Ο: Can be specified
X: Cannot be specified
Rev. 5.00 Aug 02, 2006 page 241 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.4.1
Activation by Internal Interrupt Request
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
7.4.2
Activation by External Request
If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port
should be set to input mode in advance*. Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the DREQ pin. The next data transfer may not be performed if the next edge is input
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Rev. 5.00 Aug 02, 2006 page 242 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Note: * If the relevant port is set as an output pin for another function, DMA transfers using the
channel in question cannot be guaranteed.
7.4.3
Activation by Auto-Request
Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
Rev. 5.00 Aug 02, 2006 page 243 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5
Operation
7.5.1
Transfer Modes
Table 7.4 lists the DMAC transfer modes.
Table 7.4
DMAC Transfer Modes
Transfer Mode
Short
address
mode
Dual address mode
•
•
1-byte or 1-word transfer
for a single transfer
request
Specifies the transfer
destination/source
address and performs
transfer in 2 bus cycles
Transfer Source
Remarks
•
TPU channel 0 to 5
compare match/input
capture A interrupt
•
Up to 4 channels can
operate independently
•
•
SCI transmission
complete interrupt
External request
applies to channel B
only
•
SCI reception
complete interrupt
•
•
A/D converter
conversion end
interrupt
Single address mode
applies to channel B
only
•
External request
(1) Sequential mode
•
•
Memory address
incremented or
decremented by 1 or 2
Number of transfers: 1 to
65,536
(2) Idle mode
•
Memory address fixed
•
Number of transfers: 1 to
65,536
(3) Repeat mode
•
1-byte or 1-word transfer
for a single transfer
request
•
Memory address
incremented or
decremented by 1 or 2
•
Continues transfer after
sending number of
transfers (1 to 256) and
restoring the initial value
Rev. 5.00 Aug 02, 2006 page 244 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Transfer Mode
Short
address
mode
Single address mode
•
•
•
Full
address
mode
1-byte or 1-word transfer
for a single transfer
request
Transfer Source
Remarks
•
TPU channel 0 to 5
compare match/input
capture A interrupt
•
Up to 4 channels can
operate independently
•
•
SCI transmission
complete interrupt
External request
applies to channel B
only
•
Single address mode
applies to channel B
only
•
Max. 2-channel
operation, combining
channels A and B
1-bus cycle transfer by
means of DACK pin
instead of using address
for specifying I/O
•
SCI reception
complete interrupt
•
Sequential mode, idle
mode, or repeat mode
can be specified
A/D converter
conversion end
interrupt
•
External request
•
Auto-request
•
External request
•
TPU channel 0 to 5
compare match/input
capture A interrupt
•
SCI transmission
complete interrupt
Normal mode
(1) Auto-request
•
Transfer request is
internally held
•
Number of transfers (1 to
65,536) is continuously
sent
•
Burst/cycle steal transfer
can be selected
(2) External request
•
1-byte or 1-word transfer
for a single transfer
request
•
Number of transfers: 1 to
65,536
Block transfer mode
•
Transfer of 1-block, size
selected for a single
transfer request
•
Number of transfers: 1 to
•
65,536
•
Source or destination can
be selected as block area •
•
Block size: 1 to 256 bytes
or word
•
SCI reception
complete interrupt
A/D converter
conversion end
interrupt
External request
Rev. 5.00 Aug 02, 2006 page 245 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5
Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
15
H'FF
IOAR
15
0
Operation
0
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7.3 illustrates operation in sequential mode.
Rev. 5.00 Aug 02, 2006 page 246 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Address T
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data
transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or
DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.4 shows an example of the setting procedure for sequential mode.
Rev. 5.00 Aug 02, 2006 page 247 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Sequential mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 248 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6
Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
15
H'FF
IOAR
15
0
Operation
0
Destination Start address of
Fixed
address
transfer destination
register
or transfer source
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
Rev. 5.00 Aug 02, 2006 page 249 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.6 shows an example of the setting procedure for idle mode.
Rev. 5.00 Aug 02, 2006 page 250 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Idle mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 251 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.4
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7
Register Functions in Repeat Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
0
Holds number of
transfers
Number of transfers Fixed
0
Transfer counter
Number of transfers Decremented every
transfer.
Loaded with ETCRH
value when count
reaches H'00
23
MAR
23
15
H'FF
IOAR
7
ETCRH
7
Operation
ETCRL
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer.
Initial setting is
restored when value
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value
Rev. 5.00 Aug 02, 2006 page 252 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)DTID · 2DTSZ · ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the
transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is
not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the
operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
Figure 7.7 illustrates operation in repeat mode.
Rev. 5.00 Aug 02, 2006 page 253 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Transfer
Address T
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Address B
Figure 7.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.8 shows an example of the setting procedure for repeat mode.
Rev. 5.00 Aug 02, 2006 page 254 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Repeat mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in both ETCRH and
ETCRL.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Clear the DTIE bit to 0.
• Set the DTE bit to 1 to enable transfer.
Repeat mode
Figure 7.8 Example of Repeat Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 255 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.5
Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
Register Functions in Single Address Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0
MAR
DACK pin
15
0
Operation
Source
address
register
Destination Start address of
See sections 7.5.2,
address
transfer destination Sequential Mode,
register
or transfer source
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
Write
strobe
Read
strobe
Transfer counter
ETCR
(Set automatically Strobe for external
by SAE bit; IOAR is device
invalid)
Number of transfers See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
Rev. 5.00 Aug 02, 2006 page 256 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Address T
DACK
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
Rev. 5.00 Aug 02, 2006 page 257 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Single address
mode setting
Set DMABCRH
Set transfer source and
transfer destination
addresses
[1]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Set the SAE bit to 1 to select single address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address/transfer
destination address in MAR.
[2]
Set number of transfers
[3]
Set DMACR
[4]
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Single address mode
Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode is
Specified)
Rev. 5.00 Aug 02, 2006 page 258 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.6
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in
DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response
to a single transfer request, and this is executed the number of times specified in ETCRA. The
transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9
summarizes register functions in normal mode.
Table 7.9
Register Functions in Normal Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
MARA
23
MARB
15
0
ETCRA
Transfer counter Number of transfers Decremented every
transfer; transfer ends
when count reaches
H'0000
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time
a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared
and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent
to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Figure 7.11 illustrates operation in normal mode.
Rev. 5.00 Aug 02, 2006 page 259 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Transfer
Address TA
Address TB
Address BB
Address BA
Legend:
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
Address BB = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRA
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends.
Figure 7.12 shows an example of the setting procedure for normal mode.
Rev. 5.00 Aug 02, 2006 page 260 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Normal mode setting
Set DMABCRH
[1]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
Set transfer source and
transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 7.12 Example of Normal Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 261 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.7
Block Transfer Mode
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
Holds block
size
Block size
Fixed
Block size
counter
Block size
Decremented every
transfer; ETCRH value
copied when count
reaches H'00
Block transfer
counter
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
MARA
23
MARB
7
0
ETCRAH
7
0
ETCRAL
15
0
ETCRB
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
Rev. 5.00 Aug 02, 2006 page 262 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Address TB
Address TA
1st block
2nd block
Block area
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BB
Nth block
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)
Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Rev. 5.00 Aug 02, 2006 page 263 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Address TA
Address TB
Block area
Transfer
1st block
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BA
2nd block
Nth block
Address BB
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
Rev. 5.00 Aug 02, 2006 page 264 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
Figure 7.15 shows the operation flow in block transfer mode.
Start
(DTE = DTME = 1)
Transfer request?
No
Yes
Acquire bus
Read address specified by MARA
MARA = MARA + SAIDE·(–1)SAID·2DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE·(–1)DAID ·2DTSZ
ETCRAL = ETCRAL – 1
ETCRAL = H'00
No
Yes
Release bus
ETCRAL = ETCRAH
No
BLKDIR = 0
Yes
MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH
MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH
ETCRB = ETCRB – 1
No
ETCRB = H'0000
Yes
Clear DTE bit to 0
to end transfer
Figure 7.15 Operation Flow in Block Transfer Mode
Rev. 5.00 Aug 02, 2006 page 265 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figure 7.16 shows an example of the setting procedure for block transfer mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Block transfer
mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
[1]
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Block transfer mode
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 7.16 Example of Block Transfer Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 266 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.8
Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle
DMAC cycle (1-word transfer)
T1
T2
Source
address
T1
T2
T3
T1
T2
CPU cycle
T3
Destination address
Address bus
Figure 7.17 Example of DMA Transfer Bus Timing
7.5.9
DMA Transfer (Dual Address Mode) Bus Cycles
Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
Rev. 5.00 Aug 02, 2006 page 267 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
Rev. 5.00 Aug 02, 2006 page 268 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space.
Rev. 5.00 Aug 02, 2006 page 269 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Last transfer cycle
Bus release
Bus release
Burst transfer
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer
enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer
disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on
completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the
DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Rev. 5.00 Aug 02, 2006 page 270 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated
during data transfer, block transfer operation is not affected until data transfer for one block has
ended.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Rev. 5.00 Aug 02, 2006 page 271 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
Bus release
Address
bus
DMA
control
Channel
DMA
write
Bus
release
Transfer source Transfer destination
Idle
Read
Write
Idle
[2]
Transfer source
Transfer destination
Write
Bus
release
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
DMA
write
Read
Request clear period
Request
DMA
read
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
[1]
Acceptance after transfer enabling; the
pin low level is sampled on the rising edge of ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle;
pin high level sampling on the rising edge of φ starts.
pin high level has been sampled, acceptance is resumed after the write cycle
[4] [7] When the
is completed.
(As in [1], the
pin low level is sampled on the rising edge of φ, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
Rev. 5.00 Aug 02, 2006 page 272 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
1 block transfer
1 block transfer
DMA
read
Bus release
DMA
write
DMA Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Channel
Transfer source
Idle
Read
Request
Transfer destination
Write
Dead
Request clear period
Idle
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1
for the channel for which the DREQ pin is selected.
Rev. 5.00 Aug 02, 2006 page 273 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
Bus
release
φ
DREQ
Address
bus
DMA
control
Read
Idle
Channel
Request
Write
Read
Idle
Request clear period
[1]
[2]
Idle
Request clear period
Request
Minimum
of 2 cycles
Write
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
Rev. 5.00 Aug 02, 2006 page 274 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
write
DMA
Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Channel
Transfer source
Idle
Read
Dead
Write
Request clear period
Request
Idle
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Transfer destination
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.10
DMA Transfer (Single Address Mode) Bus Cycles
Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
Rev. 5.00 Aug 02, 2006 page 275 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA read
DMA read
DMA
DMA read dead
DMA read
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
DMA read
DMA read
DMA
dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Rev. 5.00 Aug 02, 2006 page 276 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
DMA write
DMA write
DMA write
DMA
DMA write dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
Rev. 5.00 Aug 02, 2006 page 277 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA write
DMA write
DMA write
DMA
dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
Rev. 5.00 Aug 02, 2006 page 278 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Bus release
DMA single
Bus release
DMA single
Bus release
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Channel
Single
Idle
Request
Single
Idle
Request clear
period
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Rev. 5.00 Aug 02, 2006 page 279 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
Bus release
DMA single
Bus release
Bus
release
DMA single
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Single
Idle
Channel
Idle
Single
Request clear
period
Request
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
Rev. 5.00 Aug 02, 2006 page 280 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.11
Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, external write cycles in dual address transfers or single address transfers are executed in
parallel with internal accesses (on-chip memory or internal I/O registers). Internal accesses are
independent of the bus master, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output from the TEND pin is an external bus cycle. However, a low level is not output from the
TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal
bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7.32 shows an example of dual address transfer using the write data buffer function. In this
example, burst mode transfer from on-chip RAM to external memory is performed.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Internal address
Internal read signal
External address
HWR, LWR
TEND
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function
Rev. 5.00 Aug 02, 2006 page 281 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
Figure 7.33 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
DMA
read
DMA
single
CPU
read
DMA
single
CPU
read
φ
Internal address
Internal read signal
External address
RD
DACK
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12
Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1
Channel 1B
Rev. 5.00 Aug 02, 2006 page 282 of 980
REJ09B0050-0500
Low
Section 7 DMA Controller (DMAC)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA
DMA write read
φ
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A
Write
Idle
Read
Write
Idle
Read
Write
Read
Request clear
Channel 0B
Request
hold
Selection
Channel 1
Request
hold
Nonselection
Bus
release
Channel 0A
transfer
Request clear
Request
hold
Bus
release
Selection
Channel 0B
transfer
Request clear
Bus
release
Channel 1 transfer
Figure 7.34 Example of Multi-Channel Transfer
7.5.13
Relation between DMAC and External Bus Requests and Refresh Cycles
When the DMAC accesses external space, conflict with a refresh cycle or external bus release
cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle
or external bus release cycle, in accordance with the external bus priority order, even if the DMAC
is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has
a lower priority than the DMAC, is not executed until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
Rev. 5.00 Aug 02, 2006 page 283 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle or external bus release cycle.
7.5.14
DMAC and NMI Interrupts
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are
set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE = 1
DTME = 0
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
[2]
Write 1 to the DTME bit.
[1]
No
Yes
Set DTME bit to 1
[2]
Transfer continues
Transfer ends
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt
Rev. 5.00 Aug 02, 2006 page 284 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.15
Forced Termination of DMAC Operation
If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops
on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the
DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.
Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
[1]
Forced termination
of DMAC
Clear DTE bit to 0
Clear the DTE bit in DMABCRL to 0.
To prevent interrupt generation after forced
termination of DMAC operation, clear the DTIE bit
to 0 at the same time.
[1]
Forced termination
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation
Rev. 5.00 Aug 02, 2006 page 285 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.5.16
Clearing Full Address Mode
Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address
mode. After full address mode has been cleared, the channel can be set to another transfer mode
using the appropriate setting procedure.
[1] Clear both the DTE bit and DTME bit in
DMABCRL to 0, or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0. Also clear the corresponding
DTIE bit to 0 at the same time.
Clearing full
address mode
Stop the channel
[1]
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
Initialize DMACR
[2]
Clear FAE bit to 0
[3]
Initialization;
operation halted
Figure 7.37 Example of Procedure for Clearing Full Address Mode
Rev. 5.00 Aug 02, 2006 page 286 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.6
Interrupt Sources
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Source
Interrupt
Name
Interrupt
Priority Order
Short Address Mode
Full Address Mode
DMTEND0A
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
DMTEND0B
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DMTEND1A
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DMTEND1B
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 7.12.
Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
DTE/
DTME
Transfer end/transfer
break interrupt
DTIE
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.
Rev. 5.00 Aug 02, 2006 page 287 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
7.7
Usage Notes
7.7.1
DMAC Register Access during Operation
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
• DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an
example of the update timing for DMAC registers in dual address transfer mode.
DMA last transfer cycle
DMA transfer cycle
DMA read
DMA Internal
address
DMA control
DMA register
operation
Idle
[1]
Transfer
source
Transfer
destination
Read
Write
DMA read
DMA write
[2]
Read
[1]
DMA
dead
Transfer
destination
Transfer
source
Idle
DMA write
Write
[2']
Dead
Idle
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 7.39 DMAC Register Update Timing
Rev. 5.00 Aug 02, 2006 page 288 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
DMA transfer cycle
CPU longword read
MAR upper
word read
MAR lower
word read
DMA internal
address
DMA control
Idle
DMA register
operation
[1]
DMA read
Transfe
source
Transfer
destination
Read
Write
DMA write
Idle
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.40 Contention between DMAC Register Update and CPU Read
7.7.2
Module Stop
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
7.7.3
Write Data Buffer Function
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, external write cycles in dual address transfers or single address transfers are executed in
parallel with internal accesses (on-chip memory or internal I/O registers).
Rev. 5.00 Aug 02, 2006 page 289 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
• Write data buffer function and DMAC register setting
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
• Write data buffer function and DMAC operation timing
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
7.7.4
TEND Output
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1. Write cycle with write buffer mode enabled
2. DMAC single address cycle for a different channel with write buffer mode enabled
3. Bus release cycle
4. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
Rev. 5.00 Aug 02, 2006 page 290 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
φ
Internal address
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 7.41 Example in which Low Level is Not Output at TEND Pin
7.7.5
Activation by Falling Edge on DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
7.7.6
Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request
is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before write to DMABCRL to enable transfer.
Rev. 5.00 Aug 02, 2006 page 291 of 980
REJ09B0050-0500
Section 7 DMA Controller (DMAC)
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
7.7.7
Internal Interrupt after End of Transfer
When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible
termination, the selected internal interrupt request will be sent to the CPU or DTC even if the
DTA bit in DMABCRH is set to 1.
Also, if internal DMAC activation has already been initiated when operation is forcibly
terminated, the transfer is executed but flag clearing is not performed for the selected internal
interrupt even if the DTA bit is set to 1.
An internal interrupt request following the end of transfer or a forcible termination should be
handled by the CPU as necessary.
7.7.8
Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write 1 to them.
Rev. 5.00 Aug 02, 2006 page 292 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 8.1 shows a block diagram of the DTC.
8.1
Features
• Transfer possible over any number of channels
• Three transfer modes
Normal mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
Repeat mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
Block transfer mode
One operation transfers one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte),
enabling 32-bit/1-state reading and writing of the DTC register information.
DTCH803A_000020020100
Rev. 5.00 Aug 02, 2006 page 293 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Internal address bus
On-chip
RAM
CPU interrupt
request
Register information
MRA MRB
CRA
CRB
DAR
SAR
Control logic
DTC
DTC activation
request
Interrupt
request
DTVECR
DTCERA
to
DTCERG
Interrupt controller
Internal data bus
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG:
DTVECR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G
DTC vector register
Figure 8.1 Block Diagram of DTC
Rev. 5.00 Aug 02, 2006 page 294 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.2
Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set
of register information that is stored in an on-chip RAM to the corresponding DTC registers and
transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to G (DTCERA to DTCERG)
• DTC vector register (DTVECR)
8.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
6
SM1
SM0
Undefined
Undefined
−
−
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
4
DM1
DM0
Undefined
Undefined
−
−
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0×: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Rev. 5.00 Aug 02, 2006 page 295 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Bit
Bit Name
Initial Value
R/W
Description
3
2
MD1
MD0
Undefined
Undefined
−
−
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined
−
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in
repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined
−
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 296 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
CHNE
Undefined
−
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 8.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers,
clearing of the activation source flag, and clearing of
DTCER is not performed.
6
DISEL
Undefined
−
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5
CHNS
Undefined
−
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4
to
0
8.2.3
−
Undefined
−
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Rev. 5.00 Aug 02, 2006 page 297 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
8.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
This register is not used in normal mode or repeat mode.
Rev. 5.00 Aug 02, 2006 page 298 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.2.7
DTC Enable Registers A to G (DTCERA to DTCERG)
DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer
has ended
•
When the specified number of transfers have
ended
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of
transfers have not ended
•
When 0 is written to the DTCE bit after reading
DTCE = 1
Rev. 5.00 Aug 02, 2006 page 299 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
Initial Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified
number of transfers have not ended
•
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has
ended or when the specified number of transfers
have ended, this bit will not be cleared.
6
5
4
3
2
1
0
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Aug 02, 2006 page 300 of 980
REJ09B0050-0500
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC
software activation.
The vector address is expressed as H'0400 +
(vector number × 2). For example, when DTVEC6 to
DTVEC0 = H'10, the vector address is H'0420.
When the bit SWDTE is 0, these bits can be written.
Section 8 Data Transfer Controller (DTC)
8.3
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Table 8.1 shows the relationship between the activation sources and DTCER clearing, and figure
8.2 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Table 8.1
Relationship between Activation Sources and DTCER Clearing
Activation Source
DISEL = 0 and Specified
Number of Transfers Has
Not Ended
DISEL = 1 or Specified Number
of Transfers Has Ended
Activation by software
SWDTE bit is cleared to 0
•
SWDTE bit remains set to 1
•
Interrupt request to CPU
Activation by an interrupt
•
Corresponding DTCER bit
remains set to 1.
•
Corresponding DTCER bit is
cleared to 0.
•
Activation source flag is
cleared to 0.
•
Activation source flag remains
set to 1.
•
Interrupt that became the
activation source is requested
to the CPU.
Rev. 5.00 Aug 02, 2006 page 301 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
supporting
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 8.2 Block Diagram of DTC Activation Source Control
8.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 8.3 and the register information start address should be located at the
corresponding vector address to the activation source. Figure 8.4 shows the correspondence
between the DTC vector address and register information. The DTC reads the start address of the
register information from the vector address set for each activation source, and then reads the
register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Not available in this LSI.
Rev. 5.00 Aug 02, 2006 page 302 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Lower addresses
0
Start address of
register information
1
2
3
MRA
SAR
MRB
DAR
Register information
CRB
CRA
Chain transfer
MRA
SAR
MRB
DAR
CRB
CRA
Register information
for second transfer
in case of chain
transfer
Four bytes
Figure 8.3 Correspondence between DTC Vector Address and Register Information
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 8.4 Correspondence between DTC Vector Address and Register Information
Rev. 5.00 Aug 02, 2006 page 303 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Table 8.2
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
Activation
Source
DTC
Vector Number Vector Address
Software
Write to DTVECR
DTVECR
H'0400 + (DTVECR —
[6:0] × 2)
External pin
IRQ0
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
IRQ6
22
H'042C
DTCEA1
IRQ7
23
H'042E
DTCEA0
A/D
ADI
38
H'044C
DTCEC6
TPU_0
TGI0A
40
H'0450
DTCEC5
TGI0B
41
H'0452
DTCEC4
TGI0C
42
H'0454
DTCEC3
TGI0D
43
H'0456
DTCEC2
TPU_1
TGI1A
48
H'0460
DTCEC1
TGI1B
49
H'0462
DTCEC0
TPU_2
TGI2A
52
H'0468
DTCED7
TGI2B
53
H'046A
DTCED6
TGI3A
56
H'0470
DTCED5
TGI3B
57
H'0472
DTCED4
TGI3C
58
H'0474
DTCED3
TGI3D
59
H'0476
DTCED2
TPU_4
TGI4A
64
H'0480
DTCED1
TGI4B
65
H'0482
DTCED0
TPU_5
TGI5A
68
H'0488
DTCEE7
TGI5B
69
H'048A
DTCEE6
TPU_3
Rev. 5.00 Aug 02, 2006 page 304 of 980
REJ09B0050-0500
DTCE*
Priority
High
Low
Section 8 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation
Source
DTC
Vector Number Vector Address
DTCE*
Priority
TMR_0
CMIA0
72
H'0490
DTCEE3
High
CMIB0
73
H'0492
DTCEE2
CMIA1
76
H'0498
DTCEE1
CMIB1
77
H'049A
DTCEE0
DMTEND0A
80
H'04A0
DTCEF7
DMTEND0B
81
H'04A2
DTCEF6
DMTEND1A
82
H'04A4
DTCEF5
TMR_1
DMAC
SCI_0
SCI_1
SCI_2
SCI_3
SCI_4
Note:
*
DMTEND1B
83
H'04A6
DTCEF4
RXI0
89
H'04B2
DTCEF3
TXI0
90
H'04B4
DTCEF2
RXI1
93
H'04BA
DTCEF1
TXI1
94
H'04BC
DTCEF0
RXI2
97
H'04C2
DTCEG7
TXI2
98
H'04C4
DTCEG6
RXI3
101
H'04CA
DTCEF5
TXI3
102
H'04CC
DTCEF4
RXI4
105
H'04D2
DTCEG3
TXI4
106
H'04D4
DTCEG2
Low
DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
Rev. 5.00 Aug 02, 2006 page 305 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 8.5 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Rev. 5.00 Aug 02, 2006 page 306 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1?
Yes
No
CHNS = 0?
Yes
Transfer counter = 0
or DISEL = 1?
No
No
Yes
Transfer
counter = 0?
Yes
No
DISEL = 1?
Yes
No
Clear activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 8.5 Flowchart of DTC Operation
Rev. 5.00 Aug 02, 2006 page 307 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Table 8.3
Chain Transfer Conditions
1st Transfer
2nd Transfer
CHNE
CHNS
DISEL
CR
CHNE
CHNS
DISEL
CR
DTC Transfer
0
—
0
Not 0
—
—
—
—
Ends at 1st transfer
0
—
0
0
—
—
—
—
Ends at 1st transfer
0
—
1
—
—
—
—
—
Interrupt request to CPU
1
0
—
—
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
1
1
0
Not 0
—
—
—
—
Ends at 1st transfer
1
1
—
0
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
—
—
—
—
Ends at 1st transfer
1
1
1
Not 0
Interrupt request to CPU
8.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 8.4 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 8.4
Register Function in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
Rev. 5.00 Aug 02, 2006 page 308 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
SAR
DAR
Transfer
Figure 8.6 Memory Mapping in Normal Mode
8.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 8.5 lists the register
function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of
transfers has ended, the initial state of the transfer counter and the address register specified as the
repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not
reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Table 8.5
Register Function in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
Rev. 5.00 Aug 02, 2006 page 309 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 8.7 Memory Mapping in Repeat Mode
8.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 8.6 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 8.6
Register Function in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Designates transfer count
Rev. 5.00 Aug 02, 2006 page 310 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
First block
SAR
or
DAR
Block area
Transfer
DAR
or
SAR
Nth block
Figure 8.8 Memory Mapping in Block Transfer Mode
8.5.4
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0. It
is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain
transfer only when the transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Rev. 5.00 Aug 02, 2006 page 311 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Source
Destination
Register information
CHNE=1
DTC vector
address
Register information
start address
Register information
CHNE=0
Source
Destination
Figure 8.9 Operation of Chain Transfer
8.5.5
Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
Rev. 5.00 Aug 02, 2006 page 312 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write
Transfer
information read
Transfer
information write
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write Read Write
Transfer
information read
Transfer
information write
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
Rev. 5.00 Aug 02, 2006 page 313 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 8.12 DTC Operation Timing (Example of Chain Transfer)
8.5.7
Number of DTC Execution States
Table 8.7 lists execution status for a single DTC data transfer, and table 8.7 shows the number of
states required for each execution status.
Table 8.7
DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Rev. 5.00 Aug 02, 2006 page 314 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Table 8.8
Number of States Required for Each Execution Status
Object to be Accessed
OnChip
RAM
OnChip
ROM
On-Chip I/O
Registers
External Devices
Bus width
32
16
8
16
8
16
Access states
1
1
2
2
2
3
Execution
Vector read SI
—
1
—
—
4
6+2m 2
2
3+m
3
status
Register information
read/write SJ
1
—
—
—
—
—
—
—
Byte data read SK
1
1
2
2
2
3+m
2
3+m
Word data read SK
1
1
4
2
4
6+2m 2
3+m
Byte data write SL
1
1
2
2
2
3+m
2
3+m
Word data write SL
1
1
4
2
4
6+2m 2
3+m
Internal operation SM
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 5.00 Aug 02, 2006 page 315 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.6
Procedures for Using DTC
8.6.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
8.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check that the SWDTE bit is 0.
4. Write 1 to SWDTE bit and the vector number to DTVECR.
5. Check the vector number written to DTVECR.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
Rev. 5.00 Aug 02, 2006 page 316 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.7
Examples of Use of the DTC
8.7.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
8.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
1. Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
Rev. 5.00 Aug 02, 2006 page 317 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
2. Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in
DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer register information consecutively after the NDR transfer register
information.
4. Set the start address of the NDR transfer register information to the DTC vector address.
5. Set the bit corresponding to TGIA in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
8.7.3
Chain Transfer when Counter = 0
By executing a second data transfer, and performing re-setting of the first data transfer, only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 8.13 shows the chain transfer when the
counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
Rev. 5.00 Aug 02, 2006 page 318 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper 8 bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
an interrupt request is not sent to the CPU.
Input circuit
Input buffer
First data
transfer register
information
Chain transfer
(counter = 0)
Second data
transfer register
information
Upper 8 bits
of DAR
Figure 8.13 Chain Transfer when Counter = 0
Rev. 5.00 Aug 02, 2006 page 319 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.7.4
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Rev. 5.00 Aug 02, 2006 page 320 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
8.8
Usage Notes
8.8.1
Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 23,
Power-Down Modes.
8.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
8.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
8.8.4
DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has
priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer
counter reaches 0.
8.8.5
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI and high-speed A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
Rev. 5.00 Aug 02, 2006 page 321 of 980
REJ09B0050-0500
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Aug 02, 2006 page 322 of 980
REJ09B0050-0500
Section 9 I/O Ports
Section 9 I/O Ports
Table 9.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to
control the on/off state of MOS input pull-up.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 to 3, 5 (P50 to P53), and 8 (P81, P83, P85)can drive a single TTL load and 30 pF
capacitive load. Ports A to G can drive a single TTL load and 50 pF capacitive load.
All of the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. Ports 4, 5, and A (PA4, PA5, PA6, PA7) are Schmitttriggered inputs when used as IRQ inputs.
Rev. 5.00 Aug 02, 2006 page 323 of 980
REJ09B0050-0500
Section 9 I/O Ports
Table 9.1
Port Functions
Mode 7
Port
Description
Port 1 General I/O port
also functioning
as PPG outputs,
TPU I/Os, and
DMAC I/Os
Mode 1*
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
P17/PO15/TIOCB2/TCLKD
Input/
Output
Type
Schmitttriggered
input
P16/PO14/TIOCA2
P15/PO13/TIOCB1/TCLKC/DACK1
P14/PO12/TIOCA1/DACK0
P13/PO11/TIOCD0/TCLKB/TEND1
P12/PO10/TIOCC0/TCLKA/TEND0
P11/PO9/TIOCB0/DREQ1
P10/PO8/TIOCA0/DREQ0
Port 2 General I/O port
also functioning
as PPG outputs,
TPU I/Os, and
TMR I/Os
P27/PO7/TIOCB5
Schmitttriggered
input
P26/PO6/TIOCA5
P25/PO5/TIOCB4/TMO1
P24/PO4/TIOCA4/RxD4/TMO0
P23/PO3/TIOCD3/TxD4/TMCI1
P22/PO2/TIOCC3/TMCI0
P21/PO1/TIOCB3/TMRI1
P20/PO0/TIOCA3/TMIR0
Port 3 General I/O port
also functioning
as SCI I/Os, I2C
I/Os, and bus
control I/Os
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P35/SCK1/
SCL0(OE)
P35/SCK1/
SCL0
Opendrain
output
capability
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
Port 4 General I/O port
also functioning
as A/D converter
analog inputs and
D/A converter
analog outputs
P47/AN7/(IRQ7)
P46/AN6/(IRQ6)
P45/AN5/(IRQ5)
P44/AN4/(IRQ4)
P43/AN3/(IRQ3)
P42/AN2/(IRQ2)
P41/AN1/(IRQ1)
P40/AN0/(IRQ0)
Rev. 5.00 Aug 02, 2006 page 324 of 980
REJ09B0050-0500
Schmitttriggered
input when
used as
IRQ input
Section 9 I/O Ports
Mode 7
Port
Description
Mode 1*
Mode 2*
Port 5 General I/O port
also functioning
as interrupt inputs,
A/D converter
inputs, and SCI
I/Os
P53/ADTRG/IRQ3
Port 8 General I/O port
also functioning
as SCI I/Os
P85/SCK3
Mode 4
EXPE = 1
EXPE = 0
Input/
Output
Type
Schmitttriggered
input when
used as
IRQ input
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
P83/RxD3
P81/TxD3
P95/AN13/DA3
Port 9 Dedicated input
port also
P94/AN12/DA2
functioning as A/D
converter analog
inputs and D/A
converter analog
outputs
Port A General I/O port
also functioning
as address
outputs interrupt
inputs, and bus
control I/Os
PA7/A23/CS7/IRQ7
PA6/A22/IRQ6
PA7/A23/
CS7/
IRQ7
PA7/A23/
CS7/
IRQ7
PA5/A21/IRQ5
PA6/A22/
IRQ6
PA6/A22/
IRQ6
PA5/IRQ5
A20/IRQ4
PA5/A21/
IRQ5
PA5/A21/
IRQ5
PA4/IRQ4
A19
PA4/A20/
IRQ4
PA4/A20/
IRQ4
PA3
A18
PA3/A19
PA3/A19
PA2
PA2/A18
PA2/A18
PA1/A17
PA1/A17
PA0/A16
PA0/A16
A15
PB7/A15
PB7/A15
PB7
A14
PB6/A14
PB6/A14
PB6
A13
PB5/A13
PB5/A13
PB5
A12
PB4/A12
PB4/A12
PB4
A11
PB3/A11
PB3/A11
PB3
A10
PB2/A10
PB2/A10
PB2
A9
PB1/A9
PB1/A9
PB1
A8
PB0/A8
PB0/A8
PB0
A17
A16
Port B General I/O port
also functioning
as address
outputs
PA7/IRQ7
PA6/IRQ6
PA1
PA0
Only PA4
to PA7 are
Schmitttriggered
input when
used as
IRQ input.
Built-in
MOS input
pull-up
Opendrain
output
capability
Built-in
MOS input
pull-up
Rev. 5.00 Aug 02, 2006 page 325 of 980
REJ09B0050-0500
Section 9 I/O Ports
Mode 7
Port
Description
Port C General I/O port
also functioning
as address
outputs
Port D General I/O port
also functioning
as data I/Os
Port E General I/O port
also functioning
as data I/Os
Port F General I/O port
also functioning
as interrupt inputs
and bus control
I/Os
Mode 1*
Mode 2*
Mode 4
EXPE = 1
EXPE = 0
A7
PC7/A7
PC7/A7
PC7
A6
PC6/A6
PC6/A6
PC6
A5
PC5/A5
PC5/A5
PC5
A4
PC4/A4
PC4/A4
PC4
A3
PC3/A3
PC3/A3
PC3
A2
PC2/A2
PC2/A2
PC2
A1
PC1/A1
PC1/A1
PC1
A0
PC0/A0
PC0/A0
PC0
D15
D15
PD7
D14
D14
PD6
D13
D13
PD5
D12
D12
PD4
D11
D11
PD3
D10
D10
PD2
D9
D9
PD1
D8
D8
PD0
PE7/D7
PE7/D7
PE7
PE6/D6
PE6/D6
PE6
PE5/D5
PE5/D5
PE5
PE4/D4
PE4/D4
PE4
PE3/D3
PE3/D3
PE3
PE2/D2
PE2/D2
PE2
PE1/D1
PE1/D1
PE1
PE0/D0
PE0/D0
PE0
PF7/φ
PF7/φ
PF7/φ
PF6/AS
PF6/AS
PF6
RD
RD
PF5
HWR
HWR
PF4
PF3/LWR
PF3/LWR
PF3
PF2/CS6/LCAS
PF2/CS6/
LCAS
PF2
PF1/CS5/UCAS
PF1/CS5/
UCAS
PF1
PF0/WAIT/OE
PF0/WAIT/OE
PF0
Rev. 5.00 Aug 02, 2006 page 326 of 980
REJ09B0050-0500
Input/
Output
Type
Built-in
MOS input
pull-up
Built-in
MOS input
pull-up
Built-in
MOS input
pull-up
Section 9 I/O Ports
Mode 7
Port
Port G General I/O port
also functioning
as bus control
I/Os
Note:
9.1
*
EXPE = 1
EXPE = 0
PG6/BREQ
PG6/BREQ
PG6
PG5/BACK
PG5/BACK
PG5
PG4/CS4/BREQO
PG4/CS4/
BREQO
PG4
PG3/CS3/RAS3
PG3/CS3/
RAS3
PG3
PG2/CS2/RAS2
PG2/CS2/
RAS2
PG2
PG1/CS1
PG1/CS1
PG1
PG0/CS0
PG0/CS0
PG0
Mode 1*
Description
Mode 2*
Mode 4
Input/
Output
Type
Only modes 1 and 2 are available in the ROMless version.
Port 1
Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 register (PORT1)
9.1.1
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Rev. 5.00 Aug 02, 2006 page 327 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
9.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states.
PORT1 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P17
—*
R
6
P16
—*
R
P15
—*
R
If a port 1 read is performed while P1DDR bits are
set to 1, the P1DR values are read. If a port 1 read is
performed while P1DDR bits are cleared to 0, the pin
states are read.
P14
—*
R
P13
—*
R
2
P12
—*
R
1
P11
—*
R
0
P10
—*
R
5
4
3
Note:
*
Determined by the states of pins P17 to P10.
Rev. 5.00 Aug 02, 2006 page 328 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.1.4
Pin Functions
Port 1 pins also function as the pins for PPG outputs, TPU I/Os, and DMAC outputs. The
correspondence between the register specification and the pin functions is shown below.
• P17/PO15/TIOCB2/TCLKD
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in
NDERH, and bit P17DDR.
TPU channel 2
settings
(1) in table below
(2) in table below
P17DDR
—
0
1
1
NDER15
—
—
0
1
TIOCB2 output
P17 input
P17 output
Pin function
PO15 output
TIOCB2 input*
2
TCLKD input*
1
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
TPU channel 2
settings
(2)
MD3 to MD0
B'0000, B'01××
IOB3 to IOB0
(1)
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
Other than B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 329 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P16/PO14/TIOCA2
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bit NDER14 in NDERH, and bit P16DDR.
TPU channel 2
settings
(1) in table below
(2) in table below
P16DDR
—
0
1
1
NDER14
—
—
0
1
TIOCA2 output
P16 input
Pin function
P16 output
PO14 output
TIOCA2 input*
1
Note:
1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
TPU channel 1
settings
(2)
MD3 to MD0
B'0000, B'01××
IOA3 to IOA0
(1)
(2)
(2)
B'001×
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
2
PWM* mode
1 output
PWM
mode 2
output
—
Legend:
×: Don’t care
Note: 2. TIOCB2 output disabled.
Rev. 5.00 Aug 02, 2006 page 330 of 980
REJ09B0050-0500
Other than B'××00
Section 9 I/O Ports
• P15/PO13/TIOCB1/TCLKC/DACK1
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit
NDER13 in NDERH, bit SAE1 in DMA BCRH and bit P15DDR.
SAE1
TPU channel 2
settings
0
1
(1) in table below
1
(2) in table below
—
P15DDR
—
0
1
1
—
NDER13
—
—
0
1
—
TIOCB1 output
P15
input
P15 output
PO13 output
DACK1
output
Pin function
TIOCB1 input*
2
TCLKC input*
1
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101.
TCLKC input when phase counting mode is set for channels 2 and 4.
TPU channel 1
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01××
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
Other than B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 331 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P14/PO12/TIOCA1/DACK0
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bit NDER12 in NDERH, bit SAE0 in DMABCRH and bit P14DDR.
SAE0
0
TPU channel 1
settings
(1) in table below
P14DDR
1
(2) in table below
—
NDER12
Pin function
1
0
1
—
1
—
—
—
0
1
—
TIOCB1 output
P14 input
P14 output
PO12 output
DACK0
output
TIOCA1 input*
1
Note:
1. TIOCA1 input when MD3 to MD0 = B'0000, and B'01×× and IOA3 to IOA0 = B'10××.
TPU channel 1
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01××
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 2. TIOCB1 output disabled.
Rev. 5.00 Aug 02, 2006 page 332 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P13/PO11/TIOCD0/TCLKB/TEND1
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH,
bit TEE1 in DMATCR of DMAC and bit P13DDR.
TEE1
0
1
TPU channel 0 (1) in table below
settings
(2) in table below
—
—
P13DDR
—
0
1
1
—
NDER11
—
—
0
1
—
TIOCD0 output
P13 input
P13 output
PO11 output
TEND1 output
Pin function
1
TIOCD0 input*
TCLKB input*
2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××.
2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2)
MD3 to MD0
IOD3 to IOD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
Other than B'××00
CCLR2, CCLR0
—
—
—
—
Other than
B'110
B'110
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 333 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P12/PO10/TIOCC0/TCLKA/TEND0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH,
bit TEE0 in DMATCR of DMAC and bit P12DDR.
TEE0
TPU channel 2
settings
0
(1) in table below
1
(2) in table below
—
P12DDR
—
0
1
1
—
NDER10
—
—
0
1
—
TIOCO0 output
P12 input
P12 output
Pin function
PO10 output
1
*
TIOCC0 input
TEND0
output
TCLKA input*
2
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2, CCLR0
—
—
—
—
Other than
B'101
B'101
Output function
—
Output
compare
output
—
3
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 3. TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0.
Rev. 5.00 Aug 02, 2006 page 334 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P11/PO9/TIOCB0/DREQ1
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH, and bit P11DDR.
TPU channel 0
settings
(1) in table below
(2) in table below
P11DDR
—
0
1
1
NDER9
—
—
0
1
TIOCB0 output
P11 input
P11 output
PO9 output
Pin function
TIOCB0 input*
DREQ1 input
Note:
*
TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××.
TPU channel 0
settings
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
CCLR2, CCLR0
—
—
—
—
Other than
B'010
B'010
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Other than B'××00
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 335 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P10/PO8/TIOCA0/DREQ0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR.
TPU channel 0
settings
(1) in table below
(2) in table below
P10DDR
—
0
1
1
NDER8
—
—
0
1
TIOCA0 output
P10 input
Pin function
P10 output
PO8 output
TIOCA0 input*
1
DREQ0 input
Note:
1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××.
TPU channel 0
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other
than B'××00
CCLR2, CCLR0
—
—
—
—
Other than
B'001
B'001
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 2. TIOCB0 output disabled.
Rev. 5.00 Aug 02, 2006 page 336 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.2
Port 2
Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 register (PORT2)
9.2.1
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
P2DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
Rev. 5.00 Aug 02, 2006 page 337 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
9.2.3
Port 2 Register (PORT2)
PORT2 shows the pin states.
PORT2 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P27
—*
R
6
P26
—*
R
P25
—*
R
If a port 2 read is performed while P2DDR bits are
set to 1, the P2DR values are read. If a port 2 read
is performed while P2DDR bits are cleared to 0, the
pin states are read.
P24
—*
R
P23
—*
R
2
P22
—*
R
1
P21
—*
R
0
P20
—*
R
5
4
3
Note:
*
Determined by the states of pins P27 to P20.
Rev. 5.00 Aug 02, 2006 page 338 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.2.4
Pin Functions
Port 2 pins also function as PPG outputs, TPU I/Os, and TMR I/Os. The correspondence between
the register specification and the pin functions is shown below.
• P27/PO7/TIOCB5
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL, and bit P27DDR.
TPU channel 5
settings
(1) in table below
(2) in table below
P27DDR
—
0
1
1
NDER7
—
—
0
1
TIOCB5 output
P27 input
P27 output
PO7 output
Pin function
TIOCB5 input*
Note:
*
TIOCB5 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 = 1.
TPU channel 5
settings
(2)
MD3 to MD0
B'0000 to B'01××
IOB3 to IOB0
(1)
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Other than B'××00
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 339 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P26/PO6/TIOCA5
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL, and bit P26DDR.
TPU channel 5
settings
(1) in table below
(2) in table below
P26DDR
—
0
1
1
NDER6
—
—
0
1
TIOCA5 output
P26 input
Pin function
P26 output
PO6 output
TIOCA5 input*
1
Note:
1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
TPU channel 5
settings
(2)
MD3 to MD0
B'0000 to B'00××
IOA3 to IOA0
(1)
(2)
(2)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than
B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 2. TIOCB5 output disabled.
Rev. 5.00 Aug 02, 2006 page 340 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P25/PO5/TIOCB4/TMO1
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bits OS3 to USO in TCSRI
of TMR.
TPU channel 4
settings
(1) in table below
(2) in table below
OS3 to OS0
—
All 0
P25DDR
—
0
NDER5
—
TIOCB4 output
Pin function
Note:
*
All 1
One value is 1
1
1
—
—
0
1
—
P25 input
P25 output
PO5 output
TIOCB4 input*
TMO1 output
TIOCB4 input when MD3 to MD0 = B'0000 or B'01×× and IOB3 to IOB0 = B'10××.
TPU channel 4
settings
(2)
MD3 to MD0
B'0000 to B'01××
IOB3 to IOB0
(1)
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
Other than B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 341 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P24/PO4/TIOCA4/RxD4/TMO0
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR4), bit NDER4 in NDERL, bit RE in SCI_4, bit P24DDR, and bit OS3 to
OS0 in TCSRO of TMR.
RE
0
TPU channel 4
settings
(1) in table below
1
(2) in table below
OS3 to OS0
All 0
—
Not all 0
—
P24DDR
—
0
1
1
—
—
NDER4
—
—
0
1
—
—
TIOCA4 output
P24
input
P24
output
TMO0
output
RXD4 input
Pin function
Note:
PO4
output
1
TIOCA4 input*
1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 to IOA0 = B'10××.
TPU channel 4
settings
(2)
MD3 to MD0
B'0000 to B'01××
IOA3 to IOA0
(1)
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than
B'××00
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 2. TIOCB4 output disabled.
Rev. 5.00 Aug 02, 2006 page 342 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P23/PO3/TIOCD3/TXD4/TMCI1
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, and bit
P23DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
TE
0
1
P23DDR
—
0
1
1
—
NDER3
—
—
0
1
—
TIOCD3 output
P23 input
P23 output
PO3 output
TxD4 output
Pin function
1
TIOCD3 input*
TMCI1 input*
2
Notes: 1. TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10××.
2. When used as the TMR external clock input pin, the external clock is selected by the
CKS2 to CKS0 bits in TCR1.
TPU channel 3
settings
(2)
MD3 to MD0
B'0001 to B'0011
IOD3 to IOD0
(1)
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
Other than B'××00
CCLR2 to
CCLR0
—
—
—
—
Other than
B'110
B'110
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 343 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P22/PO2/TIOCC3/TMCI0
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2
to CCLR0 in TCR_3), bit NDER2 in NDERL, and bit P22DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
P22DDR
—
0
1
1
NDER2
—
—
0
1
TIOCC3 output
P22 input
Pin function
P22 output
PO2 output
TIOCC3 input*
1
TMCI0 input*
2
Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10××.
2. When used as the TMR external clock input pin, the external clock is selected by the
CKS2 to CKS0 bits in TCR_1.
TPU channel 3
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001×
B'0010
B'0011
Other than B'××00
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than
B'××00
CCLR2 to
CCLR0
—
—
—
—
Other than
B'101
B'101
Output function
—
Output
compare
output
—
3
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 3. TIOCD3 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_3.
Rev. 5.00 Aug 02, 2006 page 344 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P21/PO1/TIOCB3/TMRI1
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, and bit P21DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
P21DDR
—
0
1
1
NDER1
—
—
0
1
TIOCB3 output
P21 input
Pin function
P21 output
PO1 output
TIOCB3 input*
1
TMRI1 input*
2
Notes: 1. TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10××.
2. When used as the TMR counter reset pin, set both the CCLR1 and CCLR0 bits in
TCR_1 to 1.
TPU channel 3
settings
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
(2)
(2)
B'0010
B'0011
(1)
(2)
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
—
B'××00
CCLR2 to
CCLR0
—
—
—
—
Other than
B'010
B'010
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
Other than B'××00
Legend:
×: Don’t care
Rev. 5.00 Aug 02, 2006 page 345 of 980
REJ09B0050-0500
Section 9 I/O Ports
• P20/PO0/TIOCA3/TMRI0
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, and bit P20DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
P20DDR
—
0
1
1
NDER0
—
—
0
1
TIOCA3 output
P20 input
Pin function
P20 output
PO0 output
TIOCA0 input*
1
TMRI0 input*
2
Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10××.
2. When used as the TMR counter reset pin, set both the CCLR1 and CCLR0 bits in
TCR_1 to 1.
TPU channel 3
settings
(2)
(1)
(2)
(1)
(1)
B'001×
B'0010
B'0011
(2)
MD3 to MD0
B'0000
IOA3 to IOA0
B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00
Other than
B'××00
Other than
B'××00
CCLR2 to
CCLR0
—
—
—
—
Other than
B'001
B'001
Output function
—
Output
compare
output
—
3
PWM*
mode 1
output
PWM mode
2 output
—
Legend:
×: Don’t care
Note: 3. TIOCB3 output disabled.
Rev. 5.00 Aug 02, 2006 page 346 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.3
Port 3
Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 register (PORT3)
• Port 3 open drain control register (P3ODR)
• Port function control register 2(PFCR2)
9.3.1
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
P3DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
Rev. 5.00 Aug 02, 2006 page 347 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35DR
0
R/W
4
P34DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
9.3.3
Port 3 Register (PORT3)
PORT3 shows the pin states.
PORT3 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35
R
4
P34
—*
—*
3
P33
R
2
P32
—*
—*
If a port 3 read is performed while P3DDR bits are
set to 1, the P3DR values are read. If a port 1 read
is performed while P3DDR bits are cleared to 0, the
pin states are read.
1
P31
—*
R
0
P30
—*
R
Note:
*
R
R
Determined by the states of pins P35 to P30.
Rev. 5.00 Aug 02, 2006 page 348 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.3.4
Port 3 Open Drain Control Register (P3ODR)
P3ODR controls the output status for each port 3 pin.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35ODR
0
R/W
4
P34ODR
0
R/W
3
P33ODR
0
R/W
Setting a P3ODR bit to 1 makes the corresponding
port 3 pin an NMOS open-drain output pin, while
clearing the bit to 0 makes the pin a CMOS output
pin.
2
P32ODR
0
R/W
1
P31ODR
0
R/W
0
P30ODR
0
R/W
Rev. 5.00 Aug 02, 2006 page 349 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.3.5
Port Function Control Register 2 (PFCR2)
PFCR2 controls the I/O port.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
0
—
Reserved
3
ASOE
These bits are always read as 0 and cannot be
modified.
1
R/W
AS Output Enable
Selects to enable or disable the AS output pin.
0: PF6 is designated as I/O port
1: PF6 is designated as AS output pin
2
LWROE
1
R/W
LWR Output Enable
Selects to enable or disable the LWR output pin.
0: PF3 is designated as I/O port
1: PF3 is designated as LWR output pin
1
OES
1
R/W
OE Output Select
Selects the OE output pin port when the OEE bit is
set to 1 in DRAMCR (enabling OE output).
0: P35 is designated as OE output pin
1: PH3 is designated as OE output pin
0
—
0
—
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 5.00 Aug 02, 2006 page 350 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.3.6
Pin Functions
Port 3 pins also function as the pins for SCI I/Os, I2C output, and a bus control signal output. The
correspondence between the register specification and the pin functions is shown below.
•
P35/SCK1/SCL0/(OE)
The pin function is switched as shown below according to the combination of the ICE bit in
ICCRA of I2C_0, C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits OEE in
DRAMCR, bit OES in PFCR2, and bit P35DDR.
Modes 1, 2, 4, 7 (EXPE = 1)
OEE
0
OES
—
ICE
1
0
C/A
0
CKE0
Pin
function
1
—
CKE1
P35DDR
1
0
0
1
1
1
—
—
—
1
—
—
—
—
—
—
—
0
0
1
—
1
—
—
—
—
—
0
0
0
0
1
1
1
—
—
—
—
—
—
—
—
—
P35
P35
SCK1
SCK1 SCK1 SCL0 P35
P35
SCK1
SCK1 SCK1 SCL0
input output*1 output*1 output*1 input I/O*2 input output*1 output*1 output*1 input I/O*2
OE output
Mode 7 (EXPE = 0)
OEE
—
OES
—
ICE
0
CKE1
0
C/A
Pin function
1
—
1
—
—
1
—
—
—
0
CKE0
P35DDR
1
0
0
1
—
—
—
—
P35
input
P35
1
output*
SCK1
1
output*
SCK1
1
output*
SCK1
input
SCL0
2
I/O*
Notes: 1. NMOS open-drain output when P35ODR = 1.
2. NMOS open-drain output regardless of P35ODR
Rev. 5.00 Aug 02, 2006 page 351 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
P34/SCK0/SCK4/SDA0
The pin function is switched as shown below according to the combination of bit ICE in ICCRA
of I2C_0, bit C/A in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR.
ICE
0
CKE1
0
C/A
0
CKE0
P34DDR
Pin function
1
1
0
0
1
P34
input
P34
1
output*
1
—
—
—
1
—
—
—
—
—
—
—
SCK0/SCK4 SCK0/SCK4 SCK0/SCK4
1 3
1 3
output* *
output* *
input
SDA0
2
I/O*
Notes: 1. NMOS open-drain output when P34ODR = 1.
2. NMOS open-drain output regardless of P34ODR
3. Simultaneous output of SCK0 and SCK4 cannot be set.
•
P33/RxD1/SCL1
The pin function is switched as shown below according to the combination of bit ICE in ICCRA
of I2C_0, bit RE in SCR of SCI_1 and bit P33DDR.
ICE
0
RE
0
P33DDR
Pin function
1
1
—
0
1
—
—
P33 input
1
P33 output*
RxD1 input
SCL1 I/O*
2
Notes: 1. NMOS open-drain output when P33ODR = 1.
2. NMOS open-drain output regardless of P33ODR
•
P32/RxD0/IrRxD/SDA1
The pin function is switched as shown below according to the combination of bit ICE in ICCRA
of I2C_0, bit RE in SCR of SCI_0 and bit P32DDR.
ICE
0
RE
P32DDR
Pin function
0
1
1
—
0
1
—
—
P32 input
1
P32 output*
RxD0/IrRxD
input
SDA1 I/O*
Notes: 1. NMOS open-drain output when P32ODR = 1.
2. NMOS open-drain output regardless of P32ODR
Rev. 5.00 Aug 02, 2006 page 352 of 980
REJ09B0050-0500
2
Section 9 I/O Ports
•
P31/TxD1
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_1 and bit P31DDR.
TE
0
P31DDR
Pin function
Note:
•
*
1
0
1
—
P31 input
P31 output*
TxD1 output*
NMOS open-drain output when P31ODR = 1.
P30/TxD0/IrTxD
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_0 and bit P30DDR.
TE
0
P30DDR
Pin function
Note:
*
1
0
1
—
P30 input
P30 output*
TxD0/IrTxD
output*
NMOS open-drain output when P30ODR = 1.
Rev. 5.00 Aug 02, 2006 page 353 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.4
Port 4
Port 4 is an 8-bit input-only port. Port 4 has the following register.
• Port 4 register (PORT4)
9.4.1
Port 4 Register (PORT4)
PORT4 is an 8-bit read-only register that shows port 4 pin states.
PORT4 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
P47
—*
R
The pin states are always read from this register.
P46
—*
R
P45
—*
R
P44
—*
R
3
P43
—*
R
2
P42
R
1
P41
—*
—*
0
P40
—*
R
7
6
5
4
Note:
*
R
Determined by the states of pins P47 to P40.
Rev. 5.00 Aug 02, 2006 page 354 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.4.2
Pin Functions
Port 4 also functions as the pins for A/D converter analog input and D/A converter analog output.
The correspondence between pins are as follows.
P47/AN7/(IRQ7
IRQ7)
IRQ7
Pin function
AN7 input
IRQ7 interrupt input*
Note:
*
IRQ7 input when bit ITS7 in ITSR is 1.
P46/AN6/DA0/(IRQ6
IRQ6)
IRQ6
Pin function
AN6 input
IRQ6 interrupt input*
Note:
*
IRQ6 input when bit ITS6 in ITSR is 1.
P45/AN5/(IRQ5
IRQ5)
IRQ5
Pin function
AN5 input
IRQ5 interrupt input*
Note:
*
IRQ5 input when bit ITS5 in ITSR is 1.
P44/AN4/(IRQ4
IRQ4)
IRQ4
Pin function
AN4 input
IRQ4 interrupt input*
Note:
*
IRQ4 input when bit ITS4 in ITSR is 1.
P43/AN3/(IRQ3
IRQ3)
IRQ3
Pin function
AN3 input
IRQ3 interrupt input*
Note:
*
IRQ3 input when bit ITS3 in ITSR is 1.
Rev. 5.00 Aug 02, 2006 page 355 of 980
REJ09B0050-0500
Section 9 I/O Ports
P42/AN2/(IRQ2
IRQ2)
IRQ2
Pin function
AN2 input
IRQ2 interrupt input*
Note:
*
IRQ2 input when bit ITS2 in ITSR is 1.
P41/AN1/(IRQ1
IRQ1)
IRQ1
Pin function
AN1 input
IRQ1 interrupt input*
Note:
*
IRQ1 input when bit ITS1 in ITSR is 1.
P40/AN0/(IRQ0
IRQ0)
IRQ0
Pin function
AN0 input
IRQ0 interrupt input*
Note:
*
IRQ0 input when bit ITS0 in ITSR is 1.
Rev. 5.00 Aug 02, 2006 page 356 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.5
Port 5
Port 5 is a 4-bit I/O port. The port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
• Port 5 register (PORT5)
9.5.1
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
P5DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
0
—
Reserved
3
P53DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
9.5.2
These bits are always read as 0 and cannot be
modified.
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
0
—
Reserved
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
These bits are always read as 0 and cannot be
modified.
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Rev. 5.00 Aug 02, 2006 page 357 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.5.3
Port 5 Register (PORT5)
PORT5 shows the pin states. PORT5 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
Undefined
R
Reserved
3
P53
—*
R
2
P52
R
1
P51
—*
—*
0
P50
—*
R
Undefined values are read from these bits.
Note:
*
9.5.4
R
If bits P53 to P50 are read while P5DDR bits are set
to 1, the P5DR values are read. If a port 5 read is
performed while P5DDR bits are cleared to 0, the
pin states are read.
Determined by the states of pins P53 to P50.
Pin Functions
Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, and interrupt inputs. The
correspondence between the register specification and the pin functions is shown below.
•
P53/ADTRG/IRQ3
The pin function is switched as shown below according to the combination of bits TRGS1 and
TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P53DDR.
P53DDR
Pin function
0
1
P53 input
P53 output
ADTRG input*
1
IRQ3 interrupt input*
2
Notes: 1. ADTRG input when TRGS1 = TRGS0 = 1.
2. IRQ3 input when ITS3 = 0.
Rev. 5.00 Aug 02, 2006 page 358 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
P52/SCK2/IRQ2
The pin function is switched as shown below according to the combination of bit C/A in SMR of
SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR.
CKE1
0
C/A
1
0
CKE0
0
P52DDR
Pin function
1
1
—
—
—
0
1
—
—
—
P52 input
P52 output
SCK2 output
SCK2 output
SCK2 input
IRQ2 interrupt input*
Note:
•
*
IRQ2 input when ITS2 = 0.
P51/RxD2/IRQ1
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_2, bit ITS1 in ITSR, and bit P51DDR.
RE
0
P51DDR
Pin function
1
0
1
—
P51 input
P51 output
RxD2 input
IRQ1 interrupt input*
Note:
•
*
IRQ1 input when ITS1 = 0.
P50/TxD2/IRQ0
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_2, bit ITS0 in ITSR, and bit P50DDR.
TE
0
P50DDR
Pin function
1
0
1
—
P50 input
P50 output
TxD2 input
IRQ0 interrupt input*
Note:
*
IRQ0 input when ITS0 = 0.
Rev. 5.00 Aug 02, 2006 page 359 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.6
Port 8
Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
• Port 8 register (PORT8)
9.6.1
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8.
P8DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P85DDR
0
W
4
—
0
—
3
P83DDR
0
W
When a pin function is specified to a general
purpose I/O, setting bit 5, 3, or 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
2
—
0
—
Bits 4, 2, and 0 are reserved.
1
P81DDR
0
W
0
—
0
—
Rev. 5.00 Aug 02, 2006 page 360 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.6.2
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P85DR
0
R/W
4
—
0
—
Bits 5, 3, and 1 store output data when the pin
function is specified to a general purpose I/O.
3
P83DR
0
R/W
2
—
0
—
1
P81DR
0
R/W
0
—
0
—
9.6.3
Bits 4, 2, and 0 are reserved.
Port 8 Register (PORT8)
PORT8 shows the pin states.
PORT8 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
6
—
Undefined
—
These bits are reserved, if read they will return an
undefined value.
5
P85
—*
R
4
—
Undefined
R
3
P83
—*
R
If a port 8 read is performed while P8DDR bits are
set to 1, the P8DR values are read. If a port 8 read
is performed while P8DDR bits are cleared to 0, the
pin states are read.
2
—
R
Bits 4, 2, and 0 are reserved.
1
P81
Undefined
—*
0
—
Undefined
R
Note:
*
R
Determined by the states of pins P85, P83 and P81.
Rev. 5.00 Aug 02, 2006 page 361 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.6.4
Pin Functions
Port 8 pins also function as interrupt inputs and SCI_3 I/Os. The correspondence between the
register specification and the pin functions is shown below.
•
P85/SCK3
The pin function is switched as shown below according to the combination of bit C/A in SMR in
SCI_3, bits CKE0 and CKE1 in SCR, and bit P85DDR.
CKE1
0
C/A
Pin function
•
1
1
0
CKE0
P85DDR
1
0
0
1
P85 input
P85 output
SCK3 output
SCK3 output
SCK3 input
P83/RxD3
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_3, and bit P83DDR.
RE
0
0
1
P83 input
P83 output
RxD3 input
P83DDR
Pin function
•
1
P81/TxD3
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_3, and bit P81DDR.
TE
P81DDR
Pin function
0
1
0
1
—
P81 input
P81 output
TxD3 output
Rev. 5.00 Aug 02, 2006 page 362 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.7
Port 9
Port 9 is a 2-bit input-only port. Port 9 has the following register.
• Port 9 register (PORT9)
9.7.1
Port 9 Register (PORT9)
PORT9 is an 8-bit read-only register that shows port 4 pin states.
PORT9 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
R
Reserved
6
—
Undefined
R
If read they will return an undefined value.
P95
—*
R
4
P94
—*
R
The pin states are always read when a port 9 read
is performed.
3
—
Undefined
R
Reserved
2
—
Undefined
R
If read they will return an undefined value.
1
—
Undefined
R
0
—
Undefined
R
5
Note:
9.7.2
*
Determined by the states of pins P95 and P94.
Pin Functions
Port 9 also functions as the pins for A/D converter analog input and D/A converter analog output.
The correspondence between pins are as follows.
P95/AN13/DA3
Pin function
AN13 input
DA3 output
P94/AN12/DA2
Pin function
AN12 input
DA2 output
Rev. 5.00 Aug 02, 2006 page 363 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.8
Port A
Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A MOS zcontrol register (PAPCR)
• Port A open-drain control register (PAODR)
• Port function control register 0 (PFCR0)
• Port function control register 1 (PFCR1)
Rev. 5.00 Aug 02, 2006 page 364 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.8.1
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
•
6
PA6DDR
0
W
Pins PA4 to PA0 are address outputs.
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
For pins PA6 and PA5, when the corresponding
A22E and A21E bits are set to 1, setting a PADDR
bit to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes the
pin an input port. Clearing A22E and A21E bits to 0
makes the corresponding port A pin an I/O port, and
its function can be switched with PADDR. For pin
PA7, when the A23E bit is set to 1, setting the
PA7DDR bit to 1 makes the pin an address output,
while clearing the bit to 0 makes the pin an input
port. When the CS7E bit is set to 1 while the A23E
bit is cleared to 0, pin PA7 functions as the CS7
output pin when PA7DDR is set to 1, and as an
input port when the bit is cleared to 0. When the
CS7E bit is cleared to 0, pin PA7 is an I/O port, and
its function can be switched with PA7DDR.
•
Modes 1 and 2
Modes 4 and 7 (when EXPE = 1)
For pins PA6 to PA0, when the corresponding A22E
to A16E bits are set to 1, setting a PADDR bit to 1
makes the corresponding port A pin an address
output, while clearing the bit to 0 makes the pin an
input port. Clearing A22E to A21E bits to 0 makes
the corresponding port A pin an I/O port, and its
function can be switched with PADDR. For pin PA7,
when the A23E bit is set to 1, setting the PA7DDR
bit to 1 makes the pin an address output, while
clearing the bit to 0 makes the pin an input port.
When the CS7E bit is set to 1 while the A23E bit is
cleared to 0, pin PA7 functions as the CS7 output
pin when PA7DDR is set to 1, and as an input port
when the bit is cleared to 0. When the CS7E bit is
cleared to 0, pin PA7 is an I/O port, and its function
can be switched with PA7DDR.
•
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev. 5.00 Aug 02, 2006 page 365 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.8.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DR
0
R/W
6
PA6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
9.8.3
Port A Register (PORTA)
PORTA shows port A pin states.
PORTA cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7
—*
R
6
PA6
—*
R
PA5
—*
R
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.
PA4
—*
R
PA3
—*
R
2
PA2
—*
R
1
PA1
—*
R
0
PA0
—*
R
5
4
3
Note:
*
Determined by the states of pins PA7 to PA0.
Rev. 5.00 Aug 02, 2006 page 366 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.8.4
Port A MOS Pull-Up Control Register (PAPCR)
PAPCR controls the MOS input pull-up function. Bits 7 to 5 are valid in modes 1 and 2 and all the
bits are valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
5
PA5PCR
0
R/W
When PADDR = 0 (input port), setting the
corresponding bit to 1 turns on the MOS input pullup for that pin.
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
9.8.5
Port A Open Drain Control Register (PAODR)
PAODR specifies an output type of port A.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
5
PA5ODR
0
R/W
When not specified for address output, setting the
corresponding bit to 1 specifies a pin output type to
NMOS open-drain output, while clearing this bit to 0
specifies that to CMOS output.
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
Rev. 5.00 Aug 02, 2006 page 367 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.8.6
Port Function Control Register 0 (PFCR0)
PFCR0 controls the I/O port.
Bit
Bit Name
Initial Value
R/W
Description
7
CS7E
1
R/W
CS7 to CS0 enable
6
CS6E
1
R/W
Enable/disable corresponding CSn output.
5
CS5E
1
R/W
0: Set as I/O port.
4
CS4E
1
R/W
1: Set as CSn output pin.
3
CS3E
1
R/W
2
CS2E
1
R/W
1
CS1E
1
R/W
0
CS0E
1
R/W
Rev. 5.00 Aug 02, 2006 page 368 of 980
REJ09B0050-0500
(n = 7 to 0)
Section 9 I/O Ports
9.8.7
Port Function Control Register 1 (PFCR1)
PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid
in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
A23E
1
R/W
Address 23 Enable
Enables or disables output for address output 23
(A23).
0: DR output when PA7DDR = 1
1: A23 output when PA7DDR = 1
6
A22E
1
R/W
Address 22 Enable
Enables or disables output for address output 22
(A22).
0: DR output when PA6DDR = 1
1: A22 output when PA6DDR = 1
5
A21E
1
R/W
Address 21 Enable
Enables or disables output for address output 21
(A21).
0: DR output when PA5DDR = 1
1: A21 output when PA5DDR = 1
4
A20E
1
R/W
Address 20 Enable
Enables or disables output for address output 20
(A20).
0: DR output when PA4DDR = 1
1: A20 output when PA4DDR = 1
3
A19E
1
R/W
Address 19 Enable
Enables or disables output for address output 19
(A19).
0: DR output when PA3DDR = 1
1: A19 output when PA3DDR = 1
2
A18E
1
R/W
Address 18 Enable
Enables or disables output for address output 18
(A18).
0: DR output when PA2DDR = 1
1: A18 output when PA2DDR = 1
Rev. 5.00 Aug 02, 2006 page 369 of 980
REJ09B0050-0500
Section 9 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
1
A17E
1
R/W
Address 17 Enable
Enables or disables output for address output 17
(A17).
0: DR output when PA1DDR = 1
1: A17 output when PA1DDR = 1
0
A16E
1
R/W
Address 16 Enable
Enables or disables output for address output 16
(A16).
0: DR output when PA0DDR = 1
1: A16 output when PA0DDR = 1
9.8.8
Pin Functions
Port A pins also function as the pins for address outputs and interrupt inputs. The correspondence
between the register specification and the pin functions is shown below.
•
PA7/A23/CS7/IRQ7
The pin function is switched as shown below according to the operating mode, bit EXPE, bits
A23E and CS7E, bits ITS7 to ITS5 in ITSR, and bit PA7DDR.
Operating
mode
1, 2, 4
EXPE
7
—
A23E
0
0
CS7E
0
PADDR
0
Pin function
1
1
0
1
0
1
—
—
—
1
0
1
0
1
0
*
1
1
—
0
1
PA
PA
PA CS7 PA Address PA
PA
PA
PA
PA CS7 PA Address
input output input output output output input output input output input output input output
IRQ7 interrupt input*
Note:
1
0
IRQ7 input when ITS7 = 0.
Rev. 5.00 Aug 02, 2006 page 370 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PA6/A22/IRQ6, PA5/A21/IRQ5
The pin function is switched as shown below according to the operating mode, bit EXPE, bits
A22E and A21E, bits IS6 and ITS5 in ITSR, and bit PAnDDR.
Operating
mode
1, 2, 4
EXPE
7
—
AxxE
0
0
PADDR
Pin function
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PA
input
PA
output
PA
input
Address
output
PA
input
PA
output
PA
input
PA
output
PA
input
Address
output
IRQn interrupt input*
n = 6 or 5
xx = 22 or 21
Note: * IRQn input when ITSn = 0.
•
PA4/A20/IRQ4
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
A20E and bit PA4DDR.
Operating
mode
1, 2
EXPE
—
A20E
—
PA4DDR
Pin function
4
7
—
0
0
1
1
—
0
1
—
0
1
0
1
0
1
0
1
0
1
A20
output
PA4
input
PA4
output
PA4
input
A20
output
PA4
input
PA4
output
PA4
input
PA4
output
PA4
input
A20
output
IRQ4 interrupt input*
Note:
*
IRQ4 input when ITS4 = 0.
Rev. 5.00 Aug 02, 2006 page 371 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PA3/A19, PA2/A18, PA1/A17, PA0/A16
The pin function is switched as shown below according to the operating mode, bit EXPE, bits
A19E to A16E, and bit PADDR.
Operating
mode
1, 2
4
EXPE
—
—
AxxE
—
PAnDDR
—
9.8.9
0
0
Pin function Address
output
xx = 19 to 16
7
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PA
input
PA
output
PA
input
Address
output
PA
input
PA
output
PA
input
PA
output
PA
input
Address
output
n = 3 to 0
Port A MOS Input Pull-Up States
Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used by pins PA7 to PA5 in modes 1 and 2 and by all pins in modes
4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Table 9.2 summarizes the MOS input pull-up states.
Table 9.2
MOS Input Pull-Up States (Port A)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
4, 7
PA7 to PA0
1, 2
PA7 to PA5
On/Off
On/Off
PA4 to PA0
Off
Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PADDR = 0 and PAPCR = 1; otherwise off.
Rev. 5.00 Aug 02, 2006 page 372 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.9
Port B
Port B is an 8-bit I/O port that also has other functions. The port B has the following registers.
• Port B data direction register (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B MOS pull-up control register (PBPCR)
9.9.1
Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
PBDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DDR
0
W
•
6
PB6DDR
0
W
5
PB5DDR
0
W
Port B pins are address outputs regardless of the
PBDDR settings.
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
Setting a PBDDR bit to 1 makes the corresponding
port B pin an address output, while clearing the bit
to 0 makes the pin an input port.
1
PB1DDR
0
W
•
0
PB0DDR
0
W
Port B is an I/O port, and its pin functions can be
switched with PBDDR.
•
Modes 1 and 2
Modes 4 and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Rev. 5.00 Aug 02, 2006 page 373 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.9.2
Port B Data Register (PBDR)
PBDR is stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DR
0
R/W
6
PB6DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
9.9.3
Port B Register (PORTB)
PORTB shows port B pin states. PORTB cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
PB7
—*
R
PB6
—*
R
PB5
—*
R
If this register is read is while PBDDR bits are set to
1, the PBDR values are read. If a port B read is
performed while PBDDR bits are cleared to 0, the pin
states are read.
4
PB4
—*
R
3
PB3
—*
R
2
PB2
R
1
PB1
—*
—*
0
PB0
—*
R
7
6
5
Note:
*
R
Determined by the states of pins PB7 to PB0.
Rev. 5.00 Aug 02, 2006 page 374 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.9.4
Port B MOS Pull-Up Control Register (PBPCR)
PBPCR controls the on/off state of MOS input pull-up of port B. PBPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
5
PB5PCR
0
R/W
When PBDDR = 0 (input port), setting the
corresponding bit to 1 turns on the MOS input pullup for that pin.
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
9.9.5
Pin Functions
Port B pins also function as the pins for address outputs. The correspondence between the register
specification and the pin functions is shown below.
•
PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8
The pin function is switched as shown below according to the operating mode, bit EXPE, and bit
PBDDR.
Operating
mode
1, 2
4
EXPE
—
—
PBDDR
—
0
1
0
1
0
1
Address
output
PB input
Address
output
PB input
PB output
PB input
Address
output
Pin function
7
0
1
Rev. 5.00 Aug 02, 2006 page 375 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.9.6
Port B MOS Input Pull-Up States
Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or
off on a bit-by-bit basis.
In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1
turns on the MOS input pull-up for that pin.
Table 9.3 summarizes the MOS input pull-up states.
Table 9.3
MOS Input Pull-Up States (Port B)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PBDDR = 0 and PBPCR = 1; otherwise off.
Rev. 5.00 Aug 02, 2006 page 376 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.10
Port C
Port C is an 8-bit I/O port that also has other functions. The port C has the following registers.
• Port C data direction register (PCDDR)
• Port C data register (PCDR)
• Port C register (PORTC)
• Port C MOS pull-up control register (PCPCR)
9.10.1
Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the pins of port C.
PCDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
•
6
PC6DDR
0
W
5
PC5DDR
0
W
Port C pins are address outputs regardless of the
PCDDR settings.
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
Setting a PCDDR bit to 1 makes the corresponding
port C pin an address output, while clearing the bit
to 0 makes the pin an input port.
1
PC1DDR
0
W
•
0
PC0DDR
0
W
Port C is an I/O port, and its pin functions can be
switched with PCDDR.
•
Modes 1 and 2
Modes 4 and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Rev. 5.00 Aug 02, 2006 page 377 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.10.2
Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DR
0
R/W
6
PC6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
9.10.3
Port C Register (PORTC)
PORTC is shows port C pin states.
PORTC cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
PC7
—*
R
6
PC6
—*
R
5
PC5
—*
R
If a port C read is performed while PCDDR bits are
set to 1, the PCDR values are read. If a port C read
is performed while PCDDR bits are cleared to 0, the
pin states are read.
4
PC4
—*
R
3
PC3
—*
R
2
PC2
—*
R
PC1
—*
R
PC0
—*
R
7
1
0
Note:
*
Determined by the states of pins PC7 to PC0.
Rev. 5.00 Aug 02, 2006 page 378 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.10.4
Port C MOS Pull-Up Control Register (PCPCR)
PCPCR controls the on/off state of MOS input pull-up of port C. PCPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
5
PC5PCR
0
R/W
When PCDDR = 0 (input port), setting the
corresponding bit to 1 turns on the MOS input pullup for that pin.
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
9.10.5
Pin Functions
Port C pins also function as the pins for address outputs. The correspondence between the register
specification and the pin functions is shown below.
•
PC7/A7, PC6/A6, PC5/A5, PC4/A4, PC3/A3, PC2/A2, PC1/A1, PC0/A0
The pin function is switched as shown below according to the operating mode, bit EXPE, and bit
PCDDR.
Operating
mode
1, 2
4
EXPE
—
—
PCDDR
—
0
1
0
1
0
1
Address
output
PC input
Address
output
PC input
PC output
PC input
Address
output
Pin function
7
0
1
Rev. 5.00 Aug 02, 2006 page 379 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.10.6
Port C MOS Input Pull-Up States
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or
off on a bit-by-bit basis.
In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1
turns on the MOS input pull-up for that pin.
Table 9.4 summarizes the MOS input pull-up states.
Table 9.4
MOS Input Pull-Up States (Port C)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev. 5.00 Aug 02, 2006 page 380 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.11
Port D
Port D is an 8-bit I/O port that also has other functions. The port D has the following registers.
• Port D data direction register (PDDDR)
• Port D data register (PDDR)
• Port D register (PORTD)
• Port D MOS pull-up control register (PDPCR)
9.11.1
Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the pins of port D.
PDDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
•
6
PD6DDR
0
W
5
PD5DDR
0
W
Port D is automatically designated for data
input/output.
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
•
Modes 1, 2, 4, and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Port D is an I/O port, and its pin functions can be
switched with PDDDR.
Rev. 5.00 Aug 02, 2006 page 381 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.11.2
Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DR
0
R/W
6
PD6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
9.11.3
Port D Register (PORTD)
PORTD shows port D pin states.
PORTD cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7
—*
R
6
PD6
—*
R
PD5
—*
R
If a port D read is performed while PDDDR bits are
set to 1, the PDDR values are read. If a port D read
is performed while PDDDR bits are cleared to 0, the
pin states are read.
PD4
—*
R
PD3
—*
R
2
PD2
—*
R
1
PD1
—*
R
0
PD0
—*
R
5
4
3
Note:
*
Determined by the states of pins PD7 to PD0.
Rev. 5.00 Aug 02, 2006 page 382 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.11.4
Port D Pull-up Control Register (PDPCR)
PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in mode 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
When PDDDR = 0 (input port), the input pull-up
MOS of the input pin is on when the corresponding
bit is set to 1.
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
9.11.5
Pin Functions
Port D pins also function as the pins for data I/Os. The correspondence between the register
specification and the pin functions is shown below.
•
PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8
The pin function is switched as shown below according to the operating mode, bit EXPE, and bit
PDDDR.
Operating
mode
1, 2, 4
7
EXPE
—
PDDDR
—
0
1
—
Data I/O
PD input
PD output
Data I/O
Pin function
0
1
Rev. 5.00 Aug 02, 2006 page 383 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.11.6
Port D MOS Input Pull-Up States
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7. MOS input pull-up can be specified as on or off on a
bit-by-bit basis.
In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on
the MOS input pull-up for that pin.
Table 9.5 summarizes the MOS input pull-up states.
Table 9.5
MOS Input Pull-Up States (Port D)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 4
Off
Off
Off
Off
On/Off
On/Off
7
Legend:
OFF: MOS input pull-up is always off.
On/Off: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev. 5.00 Aug 02, 2006 page 384 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.12
Port E
Port E is an 8-bit I/O port that also has other functions. The port E has the following registers.
• Port E data direction register (PEDDR)
• Port E data register (PEDR)
• Port E register (PORTE)
• Port E MOS pull-up control register (PEPCR)
9.12.1
Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the pins of port E.
PEDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
•
6
PE6DDR
0
W
5
PE5DDR
0
W
4
PE4DDR
0
W
When 8-bit bus mode is selected, port E functions
as an I/O port. The pin states can be changed with
PEDDR.
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
For details on 8-bit and 16-bit bus modes, see
section 6, Bus Controller.
0
PE0DDR
0
W
•
Modes 1, 2, and 4
When 16-bit bus mode is selected, port E is
designated for data input/output.
Mode 7 (when EXPE = 1)
When 8-bit bus mode is selected, port E functions
as an I/O port. Setting a PEDDR bit to 1 makes the
corresponding port E pin an output port, while
clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode is selected, port E is
designated for data input/output.
•
Mode 7 (when EXPE = 0)
Port E is an I/O port, and its pin functions can be
switched with PEDDR.
Rev. 5.00 Aug 02, 2006 page 385 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.12.2
Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DR
0
R/W
6
PE6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
9.12.3
Port E Register (PORTE)
PORTE shows port E pin states.
PORTE cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
PE7
—*
R
6
PE6
—*
R
5
PE5
—*
R
If a port E read is performed while PEDDR bits are
set to 1, the PEDR values are read. If a port E read
is performed while PEDDR bits are cleared to 0, the
pin states are read.
4
PE4
—*
R
3
PE3
—*
R
2
PE2
—*
R
PE1
—*
R
PE0
—*
R
7
1
0
Note:
*
Determined by the states of pins PE7 to PE0.
Rev. 5.00 Aug 02, 2006 page 386 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.12.4
Port E Pull-up Control Register (PEPCR)
PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus
mode.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
When PEDDR = 0 (input port), the input pull-up
MOS of the input pin is on when the corresponding
bit is set to 1.
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
9.12.5
Pin Functions
Port E pins also function as the pins for data I/Os. The correspondence between the register
specification and the pin functions is shown below.
•
PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0
The pin function is switched as shown below according to the operating mode, bus mode, bit
EXPE, and bit PEDDR.
Operating
mode
Bus mode
1, 2, 4
All areas
8-bit space
At least
one area
16-bit
space
—
All areas
8-bit space
At least
one area
16-bit
space
—
—
0
1
1
EXPE
PEDDR
Pin function
7
0
1
—
0
1
0
1
—
PE input PE output Data I/O PE input PE output PE input PE output Data I/O
Rev. 5.00 Aug 02, 2006 page 387 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.12.6
Port E MOS Input Pull-Up States
Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or
off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the
corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
Table 9.6 summarizes the MOS input pull-up states.
Table 9.6
MOS Input Pull-Up States (Port E)
Mode
1, 2, and 4
8-bit bus
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
Off
Off
16-bit bus
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off.
9.13
Port F
Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For
details on the port function control register 0, refer to section 9.8.6, Port Function Control Register
0 (PFCR0), and for details on the port function control register 2, refer to section 9.3.5, Port
Function Control Register 2 (PFCR2).
• Port F data direction register (PFDDR)
• Port F data register (PFDR)
• Port F register (PORTF)
• Port Function Control Register 0 (PFCR0)
• Port Function Control Register 2 (PFCR2)
Rev. 5.00 Aug 02, 2006 page 388 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.13.1
Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DDR
1/0*
W
•
6
PF6DDR
0
W
5
PF5DDR
0
W
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
4
PF4DDR
0
W
3
PF3DDR
0
W
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
Modes 1, 2, 4, and 7 (when EXPE = 1)
Pin PF6 functions as the AS output pin when ASOE
is set to 1. When ASOE is cleared to 0, pin PF6 is
an I/O port and its function can be switched with
PF6DDR.
Pins PF5 and PF4 are automatically designated as
bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to 0,
pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 and PF1 function as bus control output
pins (LCAS and UCAS) when the appropriate bus
controller settings are made. When the CS output
enable bits (CS6E and CS5E) are set to 1, they
function as CS outputs. When the CS output enable
bits (CS6E and CS5E) are cleared to 0, pins PF2
and PF1 are I/O ports and their functions can be
switched with the corresponding PFDDR bits.
Pin PF0 functions as a bus control input pin (WAIT)
when the appropriate bus controller settings are
made. Otherwise, this pin is an output port when the
corresponding PFDDR bit is set to 1, and an input
port when the bit is cleared to 0.
•
Mode 7 (when EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions
can be switched with PFDDR.
Note:
*
PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in mode 7.
Rev. 5.00 Aug 02, 2006 page 389 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.13.2
Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DR
0
R/W
6
PF6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
9.13.3
Port F Register (PORTF)
PORTF shows port F pin states.
PORTF cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
PF7
—*
R
6
PF6
—*
R
5
PF5
—*
R
If a port F read is performed while PFDDR bits are
set to 1, the PFDR values are read. If a port F read
is performed while PFDDR bits are cleared to 0, the
pin states are read.
4
PF4
—*
R
3
PF3
—*
R
2
PF2
—*
R
PF1
—*
R
PF0
—*
R
7
1
0
Note:
*
Determined by the states of pins PF7 to PF0.
Rev. 5.00 Aug 02, 2006 page 390 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.13.4
Pin Functions
Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and
system clock outputs (φ). The correspondence between the register specification and the pin
functions is shown below.
•
PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
Operating
mode
1, 2, 4, 7
PFDDR
Pin function
•
0
1
PF7 input
φ output
PF6/AS
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
ASOE, and bit PF6DDR.
Operating
mode
1, 2, 4
EXPE
7
—
ASOE
1
PF6DDR
—
0
0
0
Pin function AS output PF6 input
•
1
—
1
1
0
1
PF6
output
PF6 input
PF6
output
—
0
0
1
AS output PF6 input
PF6
output
PF5/RD
The pin function is switched as shown below according to the operating mode, bit EXPE, and bit
PF5DDR.
Operating
mode
1, 2, 4
7
EXPE
—
PF5DDR
—
0
1
—
RD output
PF5 input
PF5 output
RD output
Pin function
0
1
Rev. 5.00 Aug 02, 2006 page 391 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PF4/HWR
The pin function is switched as shown below according to the operating mode, bit EXPE, and bit
PF4DDR.
Operating
mode
1, 2, 4
7
EXPE
—
PF4DDR
—
0
1
—
HWR output
PF4 input
PF4 output
HWR output
Pin function
•
0
1
PF3/LWR
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
LWROE, and bit PF3DDR.
Operating
mode
1, 2, 4
EXPE
7
—
0
LWROD
1
PF3DDR
—
0
1
0
1
—
0
1
LWR
output
PF3 input
PF3
output
PF3 input
PF3
output
LWR
output
PF3 input
PF3
output
Pin function
0
1
—
Rev. 5.00 Aug 02, 2006 page 392 of 980
REJ09B0050-0500
1
0
Section 9 I/O Ports
•
PF2/CS6/LCAS
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit
PF2DDR.
Operating
mode
1, 2, 4
EXPE
Areas 2 to 5
—
Any
DRAM
space
area is
16-bit
bus
space
CS6E
—
PF2DDR
—
Pin function
•
3, 7
LCAS
output
0
All DRAM space areas are 8bit bus space, or areas 2 to 5
are all normal space
1
0
—
0
1
0
Any
DRAM
space
area is
16-bit
bus
space
—
1
PF2 CS6 PF2
input output input
1
0
All DRAM space areas are 8bit bus space, or areas 2 to 5
are all normal space
—
1
—
PF2
PF2 PF2
LCAS
output input output output
1
0
0
1
0
1
PF2
input
CS6
output
PF2
input
PF2
output
PF1/CS5/UCAS
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Operating
mode
1, 2, 4
EXPE
Areas 2 to 5
—
Any
DRAM
space
area is
16-bit
bus
space
CS6E
—
PF2DDR
—
Pin function
3, 7
UCAS
output
0
All DRAM space areas are 8bit bus space, or areas 2 to 5
are all normal space
1
0
—
0
1
0
PF2 CS5 PF2
input output input
1
Any
DRAM
space
area is
16-bit
bus
space
—
1
0
All DRAM space areas are 8bit bus space, or areas 2 to 5
are all normal space
—
1
—
PF2
PF2 PF2 UCAS
output input output output
1
0
0
1
0
1
PF2
input
CS5
output
PF2
input
PF2
output
Rev. 5.00 Aug 02, 2006 page 393 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PF0/WAIT/OE
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
WAITE, bit OEE in DRAMCR, bit OES in PFCR2, and bit PF0DDR.
Operating
mode
1, 2, 4
EXPE
—
OEE
0
OES
—
WAITE
—
PF0DDR
Pin function
7
0
0
1
0
1
—
—
1
—
—
—
—
—
0
0
1
0
1
1
—
0
1
0
1
0
0
1
0
1
1
1
—
—
—
PF0 PF0 PF0 PF0 WAIT OE PF0 PF0 PF0 PF0 PF0 PF0 WAIT OE
input output input output input output input output input output input output input output
Rev. 5.00 Aug 02, 2006 page 394 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.14
Port G
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
9.14.1
Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
PG6DDR
0
W
•
Pins PG6 and PG5 function as bus control
input/output pins (BREQ and BACK) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR. Pin PG4
functions as the bus control input/output pin
(BREQO) when the appropriate bus controller
settings are made. Otherwise, when the CS7E bit is
set to 1, pin PG4 functions as the CS7 output pin
when PG4DDR is set to 1, and as an input port
when the bit is cleared to 0. When the CS7E bit is
cleared to 0, pin PG4 is an I/O port, and its function
can be switched with PG4DDR. When the CS
output enable bits (CS3E to CS0E) are set to 1, pins
PG3 to PG0 function as CS output pins when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0. When CS3E to
CS0E are cleared to 0, pins PG3 to PG0 are I/O
ports, and their functions can be switched with
PGDDR.
5
PG5DDR
0
W
4
PG4DDR
0
W
3
PG3DDR
0
W
2
PG2DDR
0
W
1
PG1DDR
0
W
PG0DDR
1/0*
W
0
•
Modes 1, 2, 4, and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Note:
*
PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
Rev. 5.00 Aug 02, 2006 page 395 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.14.2
Port G Data Register (PGDR)
PGDR stores output data for the port G pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0, and cannot be
modified.
6
PG6DR
0
R/W
5
PG5DR
0
R/W
4
PG4DR
0
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
9.14.3
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
Port G Register (PORTG)
PORTG shows port G pin states.
PORTG cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
If this bit is read, it will return an undefined value.
—*
—*
R
R
PG3
—*
—*
PG2
—*
R
PG1
—*
R
PG0
—*
R
6
PG6
5
PG5
4
PG4
3
2
1
0
Note:
*
R
If a port G read is performed while PGDDR bits are
set to 1, the PGDR values are read. If a port G read
is performed while PGDDR bits are cleared to 0, the
pin states are read.
R
Determined by the states of pins PG6 to PG0.
Rev. 5.00 Aug 02, 2006 page 396 of 980
REJ09B0050-0500
Section 9 I/O Ports
9.14.4
Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
•
PG6/BREQ
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, and bit PG6DDR.
Operating
mode
1, 2, 4
EXPE
—
BRLE
0
PG6DDR
Pin
function
•
7
0
1
1
—
0
1
0
1
—
0
1
0
1
—
PG6 input
PG6
output
BREQ
input
PG6 input
PG6
output
PG6 input
PG6
output
BREQ
input
PG5/BACK
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, and bit PG5DDR.
Operating
mode
1, 2, 4
EXPE
—
BRLE
PG5DDR
Pin
function
7
0
0
1
1
—
0
1
0
1
—
0
1
0
1
—
PG5 input
PG5
output
BACK
output
PG5 input
PG5
output
PG5 input
PG5
output
BACK
output
Rev. 5.00 Aug 02, 2006 page 397 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PG4/CS4/BREQO
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, bit BREQO, bit CS4E and bit PG4DDR.
Operating
mode
1, 2, 4
−
EXPE
BRLE
0
BREQ0E
−
0
PG4DDR
•
0
0
1
0
1
0
1
1
0
−
0
1
−
−
−
−
1
0
CS4E
Pin
function
7
1
0
1
−
1
1
0
0
0
0
1
1
0
1
1
0
1
1
1
0
1
0
−
1
PG4 PG4 PG4 CS4 PG4 PG4 PG4 CS4 BREQO PG4 PG4 PG4 PG4 PG4 CS4 PG4 PG4 PG4 CS4 BREQO
input output input output input output input output output input output input output input output input output input output output
PG3/CS3/RAS3, PG2/CS2/RAS2
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, bit CSnE, and bits RMTS2 to RMTS0.
Operating
1, 2, 4
7
mode
EXPE
—
CSnE
0
RMTS2 to
RMTS0
—
PGnDDR
Pin
function
0
1
Area n is in
normal space
Area n is in
DRAM
space
1
—
0
—
—
1
Area n is in
normal space
Area n is in
DRAM
space
0
1
0
1
—
0
1
0
1
0
1
—
PGn
input
PGn
output
PGn
input
CSn
output
RASn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
RASn
output
n = 2 or 3
Rev. 5.00 Aug 02, 2006 page 398 of 980
REJ09B0050-0500
Section 9 I/O Ports
•
PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, and bit CsnE.
Operating
mode
1, 2, 4
EXPE
—
CSnE
PGnDDR
Pin function
7
0
0
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PGn
input
PGn
output
PGn
input
CSn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
n =1 or 0
Rev. 5.00 Aug 02, 2006 page 399 of 980
REJ09B0050-0500
Section 9 I/O Ports
Rev. 5.00 Aug 02, 2006 page 400 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure
10.1, respectively.
10.1
Features
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
Waveform output at compare match
Input capture function
Counter clear operation
Synchronous operations:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
Rev. 5.00 Aug 02, 2006 page 401 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0
—
—
TGRC_3
TGRD_3
—
—
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Compare 0 output
match
1 output
output
Toggle
output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Input capture
function
O
O
O
O
O
O
Synchronous
operation
O
O
O
O
O
O
PWM mode
O
—
O
O
O
O
O
O
O
—
O
O
O
—
—
O
—
—
Phase counting
mode
Buffer operation
Rev. 5.00 Aug 02, 2006 page 402 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DTC
TGR
activation compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
DMAC
TGRA
activation compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
A/D
TGRA
converter compare
trigger
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
PPG
trigger
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
—
TGRB
compare
match or
input capture
—
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
•
•
•
•
•
•
•
•
Compare
match or
input
capture
0A
Compare
match or
input
capture
0B
Compare
match or
input
capture
0C
Compare
match or
input
capture
0D
Overflow
•
Legend:
O: Possible
: Not possible
•
•
•
Compare
match or
input
capture
1A
Compare
match or
input
capture
1B
Overflow
Underflow
•
•
•
Compare •
match or
input
capture
2A
Compare •
match or
input
capture
2B
Overflow •
Underflow
•
•
Compare
match or
input
capture
3A
Compare
match or
input
capture
3B
Compare
match or
input
capture
3C
Compare
match or
input
capture
3D
Overflow
•
•
•
Compare
match or
input
capture
4A
Compare
match or
input
capture
4B
Overflow
Underflow
•
•
•
Compare
match or
input
capture
5A
Compare
match or
input
capture
5B
Overflow
Underflow
Rev. 5.00 Aug 02, 2006 page 403 of 980
REJ09B0050-0500
TGRD
TGRB
TGRC
TGRB
A/D conversion start request signal
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 10.1 Block Diagram of TPU
Rev. 5.00 Aug 02, 2006 page 404 of 980
REJ09B0050-0500
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
Module data bus
TGRA
TSR
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TIER
TSR
TIER
TSTR TSYR
TIOR
TIOR
TIER
TMDR
TIORH TIORL
TIOR
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
TCR
Control logic
Common
TMDR
TCR
TMDR
Channel 1
TCR
Channel 0
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 2
Legend:
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 0 to 2
Input/output pins
TIOCA0
Channel 0:
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
Channel 2:
TIOCA2
TIOCB2
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
TIOCA3
Channel 3:
TIOCB3
TIOCC3
TIOCD3
TIOCA4
Channel 4:
TIOCB4
TIOCA5
Channel 5:
TIOCB5
Channel 3
Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
10.2
Input/Output Pins
Table 10.2 Pin Configuration
Channel
Symbol
I/O
Function
All
TCLKA
Input
External clock A input pin
(Channels 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channels 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channels 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channels 2 and 4 phase counting mode B phase input)
TIOCA0
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/PWM output pin
0
1
2
3
4
5
TIOCD0
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/PWM output pin
TIOCA2
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOCA4
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/PWM output pin
Rev. 5.00 Aug 02, 2006 page 405 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3
Register Descriptions
The TPU has the following registers in each channel.
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register H_0 (TIORH_0)
• Timer I/O control register L_0 (TIORL_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_0)
• Timer general register B_0 (TGRB_0)
• Timer general register C_0 (TGRC_0)
• Timer general register D_0 (TGRD_0)
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register _1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_1)
• Timer general register B_1 (TGRB_1)
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
• Timer control register_3 (TCR_3)
• Timer mode register_3 (TMDR_3)
• Timer I/O control register H_3 (TIORH_3)
• Timer I/O control register L_3 (TIORL_3)
Rev. 5.00 Aug 02, 2006 page 406 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
• Timer interrupt enable register_3 (TIER_3)
• Timer status register_3 (TSR_3)
• Timer counter_3 (TCNT_3)
• Timer general register A_3 (TGRA_3)
• Timer general register B_3 (TGRB_3)
• Timer general register C_3 (TGRC_3)
• Timer general register D_3 (TGRD_3)
• Timer control register_4 (TCR_4)
• Timer mode register_4 (TMDR_4)
• Timer I/O control register _4 (TIOR_4)
• Timer interrupt enable register_4 (TIER_4)
• Timer status register_4 (TSR_4)
• Timer counter_4 (TCNT_4)
• Timer general register A_4 (TGRA_4)
• Timer general register B_4 (TGRB_4)
• Timer control register_5 (TCR_5)
• Timer mode register_5 (TMDR_5)
• Timer I/O control register_5 (TIOR_5)
• Timer interrupt enable register_5 (TIER_5)
• Timer status register_5 (TSR_5)
• Timer counter_5 (TCNT_5)
• Timer general register A_5 (TGRA_5)
• Timer general register B_5 (TGRB_5)
Common Registers
• Timer start register (TSTR)
• Timer synchronous register (TSYR)
Rev. 5.00 Aug 02, 2006 page 407 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.1
Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the TCNT counter clearing source.
See tables 10.3 and 10.4 for details.
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and
the phase counting mode setting has priority.
Internal clock edge selection is valid when the input
clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1, or when overflow/underflow of
another channel is selected.
00: Count at rising edge
01: Count at falling edge
1×: Count at both edges
Legend: ×: Don’t care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Rev. 5.00 Aug 02, 2006 page 408 of 980
REJ09B0050-0500
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The
clock source can be selected independently for
each channel. See tables 10.5 to 10.10 for details.
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
2
capture*
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
1
1
0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 6
Bit 7
2
Reserved* CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 409 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.5 TPSC2 to TPSC0 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
1
1
Table 10.6 TPSC2 to TPSC0 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
1
1
0
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 5.00 Aug 02, 2006 page 410 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.7 TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
1
1
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 10.8 TPSC2 to TPSC0 (Channel 3)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
1
1
0
1
Rev. 5.00 Aug 02, 2006 page 411 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.9 TPSC2 to TPSC0 (Channel 4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
4
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
1
1
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 10.10 TPSC2 to TPSC0 (Channel 5)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
1
1
0
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev. 5.00 Aug 02, 2006 page 412 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.2
Timer Mode Register (TMDR)
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
6
–
–
1
1
–
–
Reserved
5
BFB
0
R/W
Buffer Operation B
These bits are always read as 1 and cannot be
modified.
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together
for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit
5 is reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together
for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit
4 is reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 3 to 0
These bits are used to set the timer operating mode.
MD3 is a reserved bit. The write value should
always be 0. See table 10.11 for details.
Rev. 5.00 Aug 02, 2006 page 413 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.11 MD3 to MD0
Bit 3
1
MD3*
Bit 2
2
MD2*
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
0
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
×
—
1
1
1
×
×
Legend: ×: Don’t care
Notes: 1. MD3 is a reserved bit. The write value should always be 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
10.3.3
Timer I/O Control Register (TIOR)
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev. 5.00 Aug 02, 2006 page 414 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B3 to B0
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRB.
For details, see tables 10.12, 10.14, 10.15, 10.16,
10.18, and 10.19.
Specify the function of TGRA.
For details, see tables 10.20, 10.22, 10.23, 10.24,
10.26, and 10.27.
TIORL_0, TIORL_3
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D3 to D0
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C3 to C0
Specify the function of TGRD.
For details, see tables 10.13, and 10.17.
Specify the function of TGRC.
For details, see tables 10.21, and 10.25
Rev. 5.00 Aug 02, 2006 page 415 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.12 TIORH_0
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
TIOCB0 Pin Function
0
0
0
0
Output
Output disabled
1
compare
Initial output is 0 output
register
1
0
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
Capture input source is TIOCB0 pin
capture
Input capture at rising edge
register
Capture input source is TIOCB0 pin
Input capture at falling edge
1
×
Capture input source is TIOCB0 pin
Input capture at both edges
1
×
×
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*
Legend: ×: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev. 5.00 Aug 02, 2006 page 416 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.13 TIORL_0
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
2
register*
1
1
0
TIOCD0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD0 pin
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
1
×
Capture input source is TIOCD0 pin
Input capture at both edges
1
×
×
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
1
Legend: ×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Aug 02, 2006 page 417 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.14 TIOR_1
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCB1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB1 pin
Input capture at rising edge
Capture input source is TIOCB1 pin
Input capture at falling edge
1
×
Capture input source is TIOCB1 pin
Input capture at both edges
1
×
×
TGRC_0 compare match/input capture
Input capture at generation of TGRC_0 compare
match/input capture
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 418 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.15 TIOR_2
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCB2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCB2 pin
Input capture at rising edge
Capture input source is TIOCB2 pin
Input capture at falling edge
1
×
Capture input source is TIOCB2 pin
Input capture at both edges
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 419 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.16 TIORH_3
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCB3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB3 pin
Input capture at rising edge
Capture input source is TIOCB3 pin
Input capture at falling edge
1
×
Capture input source is TIOCB3 pin
Input capture at both edges
1
×
×
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
Legend: ×: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
Rev. 5.00 Aug 02, 2006 page 420 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.17 TIORL_3
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
2
register*
1
1
0
TIOCD3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD3 pin
Input capture at rising edge
Capture input source is TIOCD3 pin
Input capture at falling edge
1
×
Capture input source is TIOCD3 pin
Input capture at both edges
1
×
×
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
1
Legend: ×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Aug 02, 2006 page 421 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.18 TIOR_4
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCB4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB4 pin
Input capture at rising edge
Capture input source is TIOCB4 pin
Input capture at falling edge
1
×
Capture input source is TIOCB4 pin
Input capture at both edges
1
×
×
Capture input source is TGRC_3 compare
match/input capture
Input capture at generation of TGRC_3 compare
match/input capture
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 422 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.19 TIOR_5
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_5
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCB5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCB5 pin
Input capture at rising edge
Capture input source is TIOCB5 pin
Input capture at falling edge
1
×
Capture input source is TIOCB5 pin
Input capture at both edges
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 423 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.20 TIORH_0
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA0 pin
Input capture at rising edge
Capture input source is TIOCA0 pin
Input capture at falling edge
1
×
Capture input source is TIOCA0 pin
Input capture at both edges
1
×
×
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 424 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.21 TIORL_0
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
register*
1
1
0
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
1
×
Capture input source is TIOCC0 pin
Input capture at both edges
1
×
×
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: ×: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Aug 02, 2006 page 425 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.22 TIOR_1
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA1 pin
Input capture at rising edge
Capture input source is TIOCA1 pin
Input capture at falling edge
1
×
Capture input source is TIOCA1 pin
Input capture at both edges
1
×
×
Capture input source is TGRA_0 compare
match/input capture
Input capture at generation of channel
0/TGRA_0 compare match/input capture
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 426 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.23 TIOR_2
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Capture input source is TIOCA2 pin
Input capture at rising edge
Capture input source is TIOCA2 pin
Input capture at falling edge
1
×
Capture input source is TIOCA2 pin
Input capture at both edges
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 427 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.24 TIORH_3
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA3 pin
Input capture at rising edge
Capture input source is TIOCA3 pin
Input capture at falling edge
1
×
Capture input source is TIOCA3 pin
Input capture at both edges
1
×
×
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 428 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.25 TIORL_3
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
register*
1
1
0
TIOCC3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC3 pin
Input capture at rising edge
Capture input source is TIOCC3 pin
Input capture at falling edge
1
×
Capture input source is TIOCC3 pin
Input capture at both edges
1
×
×
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
Legend: ×: Don’t care
Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Aug 02, 2006 page 429 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.26 TIOR_4
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA4 pin
Input capture at rising edge
Capture input source is TIOCA4 pin
Input capture at falling edge
1
×
Capture input source is TIOCA4 pin
Input capture at both edges
1
×
×
Capture input source is TGRA_3 compare
match/input capture
Input capture at generation of TGRA_3 compare
match/input capture
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 430 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.27 TIOR_5
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_5
Function
0
0
0
0
Output
compare
register
1
1
0
TIOCA5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Input capture source is TIOCA5 pin
Input capture at rising edge
Input capture source is TIOCA5 pin
Input capture at falling edge
1
×
Input capture source is TIOCA5 pin
Input capture at both edges
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 431 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.4
Timer Interrupt Enable Register (TIER)
TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has
six TIER registers, one for each channel.
Bit
Bit Name
Initial value
R/W
7
TTGE
0
R/W
Description
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6
–
1
–
Reserved
This bit is always read as 1 and cannot be modified.
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev. 5.00 Aug 02, 2006 page 432 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 5.00 Aug 02, 2006 page 433 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.5
Timer Status Register (TSR)
TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each
channel.
Bit
Bit
Name
Initial value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6
–
1
–
Reserved
This bit is always read as 1 and cannot be
modified.
5
TCFU
0
R/(W)*
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)*
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
Rev. 5.00 Aug 02, 2006 page 434 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
3
Bit
Name
TGFD
Initial value
R/W
Description
0
R/(W)*
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD while TGRD is
functioning as output compare register
•
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
[Clearing conditions]
2
TGFC
0
R/(W)*
•
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD
=1
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRC while TGRC is
functioning as output compare register
•
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
[Clearing conditions]
•
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC
=1
Rev. 5.00 Aug 02, 2006 page 435 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Bit
1
Bit
Name
TGFB
Initial value
R/W
Description
0
R/(W)*
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRB while TGRB is functioning
as output compare register
•
When TCNT value is transferred to TGRB by
input capture signal while TGRB is functioning
as input capture register
[Clearing conditions]
0
TGFA
0
R/(W)*
•
When DTC is activated by TGIB interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFB after reading TGFB
=1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRA while TGRA is functioning
as output compare register
•
When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
[Clearing conditions]
Note:
*
•
When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFA after reading TGFA
=1
•
When DMAC is activated by TGIA interrupt
while DTE bit of DMABCR in DMAC is set to 1
Only 0 can be written, for flag clearing.
Rev. 5.00 Aug 02, 2006 page 436 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.3.7
Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two
each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for
operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must
always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and
TGRB–TGRD.
10.3.8
Timer Start Register (TSTR)
TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit
Bit Name
Initial value
R/W
Description
7
6
–
–
0
0
–
–
Reserved
5
4
3
2
1
0
CST5
CST4
CST3
CST2
CST1
CST0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Counter Start 5 to 0
The write value should always be 0.
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with
the TIOC pin designated for output, the counter
stops but the TIOC pin output compare output level
is retained. If TIOR is written to when the CST bit is
cleared to 0, the pin output level will be changed to
the set initial output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation
Rev. 5.00 Aug 02, 2006 page 437 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9
Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial value
R/W
Description
7
6
–
–
–
–
R/W
R/W
Reserved
5
4
3
2
1
0
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Timer Synchronization 5 to 0
The write value should always be 0.
These bits select whether operation is independent
of or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by
means of bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
Rev. 5.00 Aug 02, 2006 page 438 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.4
Operation
10.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for
the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic
counter, and so on.
1. Example of count operation setting procedure
Figure 10.2 shows an example of the count operation setting procedure.
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count
[5]
<Periodic counter>
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count
<Free-running counter>
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 10.2 Example of Counter Operation Setting Procedure
Rev. 5.00 Aug 02, 2006 page 439 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to
H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER
is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again
from H'0000.
Figure 10.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 10.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts
count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 10.4 illustrates periodic counter operation.
Rev. 5.00 Aug 02, 2006 page 440 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 10.4 Periodic Counter Operation
Rev. 5.00 Aug 02, 2006 page 441 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using a compare match.
1. Example of setting procedure for waveform output by compare match
Figure 10.5 shows an example of the setting procedure for waveform output by a compare
match.
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match
Rev. 5.00 Aug 02, 2006 page 442 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
2. Examples of waveform output operation
Figure 10.6 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the
set level and the pin level match, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
No change
No change
0 output
Figure 10.6 Example of 0 Output/1 Output Operation
Figure 10.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing
performed by compare match B), and settings have been made so that output is toggled by both
compare match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 10.7 Example of Toggle Output Operation
Rev. 5.00 Aug 02, 2006 page 443 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel’s counter input clock or compare match signal
as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ/1 is selected.
1. Example of setting procedure for input capture operation
Figure 10.8 shows an example of the setting procedure for input capture operation.
[1] Designate TGR as an input capture register by
means of TIOR, and select the input capture
source and input signal edge (rising edge, falling
edge, or both edges).
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Input capture operation>
Figure 10.8 Example of Setting Procedure for Input Capture Operation
Rev. 5.00 Aug 02, 2006 page 444 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
2. Example of input capture operation
Figure 10.9 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,
and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 10.9 Example of Input Capture Operation
10.4.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously
(synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously
(synchronous clearing) by making the appropriate setting in TCR.
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
Rev. 5.00 Aug 02, 2006 page 445 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the
same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 10.10 Example of Synchronous Operation Setting Procedure
Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Rev. 5.00 Aug 02, 2006 page 446 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details on PWM modes, see section 10.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 10.11 Example of Synchronous Operation
10.4.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 10.28 shows the register combinations used in buffer operation.
Rev. 5.00 Aug 02, 2006 page 447 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.28 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.12.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 10.12 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 10.13.
Input capture
signal
Buffer register
Timer general
register
Figure 10.13 Input Capture Buffer Operation
Rev. 5.00 Aug 02, 2006 page 448 of 980
REJ09B0050-0500
TCNT
Section 10 16-Bit Timer Pulse Unit (TPU)
Example of Buffer Operation Setting Procedure: Figure 10.14 shows an example of the buffer
operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
<Buffer operation>
Figure 10.14 Example of Buffer Operation Setting Procedure
Rev. 5.00 Aug 02, 2006 page 449 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation:
1. When TGR is an output compare register
Figure 10.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details on PWM modes, see section 10.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
H'0450
TGRC_0 H'0200
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 10.15 Example of Buffer Operation (1)
Rev. 5.00 Aug 02, 2006 page 450 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
2. When TGR is an input capture register
Figure 10.16 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 10.16 Example of Buffer Operation (2)
Rev. 5.00 Aug 02, 2006 page 451 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.
Table 10.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 10.29 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Channels 4 and 5
TCNT_4
TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
<Cascaded operation>
Figure 10.17 Cascaded Operation Setting Procedure
Rev. 5.00 Aug 02, 2006 page 452 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 10.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1
clock
TCNT_1
H'03A1
H'03A2
TCNT_2
clock
TCNT_2
H'FFFF
H'0000
H'0001
TIOCA1,
TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 10.18 Example of Cascaded Operation (1)
Figure 10.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD
FFFE
0000
FFFF
0000
0001
0002
0001
0000
0001
FFFF
0000
Figure 10.19 Example of Cascaded Operation (2)
Rev. 5.00 Aug 02, 2006 page 453 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR
are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The
outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare
matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If
the set values of paired TGRs are identical, the output value does not change when a compare
match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.30.
Rev. 5.00 Aug 02, 2006 page 454 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.30 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGRA_0
TIOCA0
TIOCA0
TGRB_0
TGRC_0
TIOCB0
TIOCC0
TGRD_0
1
TGRA_1
2
TGRA_2
TIOCD0
TIOCA1
TGRB_1
TGRA_3
TIOCA3
TGRA_4
5
TGRA_5
TIOCC3
TIOCC3
TIOCD3
TIOCA4
TGRB_4
TGRB_5
TIOCA3
TIOCB3
TGRD_3
4
TIOCA2
TIOCB2
TGRB_3
TGRC_3
TIOCA1
TIOCB1
TIOCA2
TGRB_2
3
TIOCC0
TIOCA4
TIOCB4
TIOCA5
TIOCA5
TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
Rev. 5.00 Aug 02, 2006 page 455 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGRs.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
<PWM mode>
Figure 10.20 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty.
Rev. 5.00 Aug 02, 2006 page 456 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value
Counter cleared by
TGRA compare match
TGRA
TGRB
H'0000
Time
TIOCA
Figure 10.21 Example of PWM Mode Operation (1)
Figure 10.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 10.22 Example of PWM Mode Operation (2)
Rev. 5.00 Aug 02, 2006 page 457 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.23 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 10.23 Example of PWM Mode Operation (3)
Rev. 5.00 Aug 02, 2006 page 458 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 10.31 shows the correspondence between external clock pins and channels.
Table 10.31 Clock Input Pins in Phase Counting Mode
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
Rev. 5.00 Aug 02, 2006 page 459 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
<Phase counting mode>
Figure 10.24 Example of Phase Counting Mode Setting Procedure
Rev. 5.00 Aug 02, 2006 page 460 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
1. Phase counting mode 1
Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 10.25 Example of Phase Counting Mode 1 Operation
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Aug 02, 2006 page 461 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2
Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 10.26 Example of Phase Counting Mode 2 Operation
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Don’t care
Low level
Don’t care
High level
Don’t care
Low level
Down-count
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Aug 02, 2006 page 462 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3
Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 10.27 Example of Phase Counting Mode 3 Operation
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Down-count
Low level
Don’t care
High level
Don’t care
Low level
Don’t care
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Aug 02, 2006 page 463 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4
Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 10.28 Example of Phase Counting Mode 4 Operation
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
Don’t care
High level
High level
Down-count
Low level
High level
Don’t care
Low level
Legend:
: Rising edge
: Falling edge
Phase Counting Mode Application Example: Figure 10.29 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Rev. 5.00 Aug 02, 2006 page 464 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function, and are set with the speed control cycle and
position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source, and the up/down-counter
values for the control cycles are stored.
This procedure enables accurate position/speed detection to be achieved.
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed cycle capture)
TGRB_1
(position cycle capture)
TCNT_0
TGRA_0
(speed control cycle)
+
-
TGRC_0
(position control cycle)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 10.29 Phase Counting Mode Application Example
Rev. 5.00 Aug 02, 2006 page 465 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.5
Interrupts
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 10.36 lists the TPU interrupt sources.
Rev. 5.00 Aug 02, 2006 page 466 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.36 TPU Interrupts
DTC
Activation
DMAC
Activation
TGRA_0 input capture/compare match TGFA_0
Possible
Possible
TGI0B
TGRB_0 input capture/compare match TGFB_0
Possible
Not possible
TGI0C
TGRC_0 input capture/compare match TGFC_0
Possible
Not possible
TGI0D
TGRD_0 input capture/compare match TGFD_0
Possible
Not possible
TGI0E
TCNT_0 overflow
Not possible Not possible
TGI1A
TGRA_1 input capture/compare match TGFA_1
Possible
Possible
TGI1B
TGRB_1 input capture/compare match TGFB_1
Possible
Not possible
TCI1V
TCNT_1 overflow
TCFV_1
Not possible Not possible
TCI1U
TCNT_1 underflow
TCFU_1
Not possible Not possible
TGI2A
TGRA_2 input capture/compare match TGFA_2
Possible
Possible
TGI2B
TGRB_2 input capture/compare match TGFB_2
Possible
Not possible
Channel Name
Interrupt Source
0
TGI0A
1
2
3
4
5
Interrupt
Flag
TCFV_0
TCI2V
TCNT_2 overflow
TCFV_2
Not possible Not possible
TCI2U
TCNT_2 underflow
TCFU_2
Not possible Not possible
TGI3A
TGRA_3 input capture/compare match TGFA_3
Possible
Possible
TGI3B
TGRB_3 input capture/compare match TGFB_3
Possible
Not possible
TGI3C
TGRC_3 input capture/compare match TGFC_3
Possible
Not possible
TGI3D
TGRD_3 input capture/compare match TGFD_3
Possible
Not possible
TCI3V
TCNT_3 overflow
Not possible Not possible
TGI4A
TGRA_4 input capture/compare match TGFA_4
Possible
Possible
TGI4B
TGRB_4 input capture/compare match TGFB_4
Possible
Not possible
TCI4V
TCNT_4 overflow
TCFV_4
Not possible Not possible
TCI4U
TCNT_4 underflow
TCFU_4
Not possible Not possible
TGI5A
TGRA_5 input capture/compare match TGFA_5
Possible
Possible
TGI5B
TGRB_5 input capture/compare match TGFB_5
Possible
Not possible
TCI5V
TCNT_5 overflow
TCFV_5
Not possible Not possible
TCI5U
TCNT_5 underflow
TCFU_5
Not possible Not possible
TCFV_3
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
Rev. 5.00 Aug 02, 2006 page 467 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to
1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match
on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has
16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for
channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
10.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 9, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
10.7
DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.
For details, see section 7, DMA Controller (DMAC).
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC
activation sources, one for each channel.
10.8
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Rev. 5.00 Aug 02, 2006 page 468 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.9
Operation Timing
10.9.1
Input/Output Timing
TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and
figure 10.31 shows TCNT count timing in external clock operation.
φ
Internal clock
Falling edge
Rising edge
TCNT
input clock
N–1
TCNT
N
N+1
N+2
Figure 10.30 Count Timing in Internal Clock Operation
φ
External clock
Rising edge
Falling edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
N+2
Figure 10.31 Count Timing in External Clock Operation
Rev. 5.00 Aug 02, 2006 page 469 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the (TIOC pin) TCNT input clock is generated.
Figure 10.32 shows output compare output timing.
φ
TCNT
input clock
N
TCNT
N+1
N
TGR
Compare
match signal
TIOC pin
Figure 10.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
N
N+1
N+2
N
TGR
Figure 10.33 Input Capture Input Signal Timing
Rev. 5.00 Aug 02, 2006 page 470 of 980
REJ09B0050-0500
N+2
Section 10 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the
timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows
the timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 10.34 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
TGR
N
H'0000
N
Figure 10.35 Counter Clear Timing (Input Capture)
Rev. 5.00 Aug 02, 2006 page 471 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 10.36 and 10.37 show the timings in buffer operation.
φ
n
TCNT
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 10.36 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 10.37 Buffer Operation Timing (Input Capture)
Rev. 5.00 Aug 02, 2006 page 472 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for
setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal
timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 10.38 TGI Interrupt Timing (Compare Match)
Rev. 5.00 Aug 02, 2006 page 473 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting
of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 10.39 TGI Interrupt Timing (Input Capture)
Rev. 5.00 Aug 02, 2006 page 474 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing.
Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 10.40 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 10.41 TCIU Interrupt Setting Timing
Rev. 5.00 Aug 02, 2006 page 475 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42
shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status
flag clearing by the DTC or DMAC.
TSR write cycle
T2
T1
φ
TSR address
Address
Write signal
Status flag
Interrupt
request
signal
Figure 10.42 Timing for Status Flag Clearing by CPU
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation
Rev. 5.00 Aug 02, 2006 page 476 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10
Usage Notes
10.10.1 Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 22, Power-Down Modes.
10.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
diffediffeOverlap
rence
rence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 5.00 Aug 02, 2006 page 477 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
10.10.4 Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this
case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
Counter clearing
signal
TCNT
N
H'0000
Figure 10.45 Contention between TCNT Write and Clear Operations
Rev. 5.00 Aug 02, 2006 page 478 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 10.46 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 10.46 Contention between TCNT Write and Increment Operations
10.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 10.47 shows the timing in this case.
Rev. 5.00 Aug 02, 2006 page 479 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
TGR write cycle
T1
T2
φ
TGR address
Address
Write signal
Compare
match signal
Disabled
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 10.47 Contention between TGR Write and Compare Match
10.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 10.48 shows the timing in this case.
TGR write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 10.48 Contention between Buffer Register Write and Compare Match
Rev. 5.00 Aug 02, 2006 page 480 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 10.49 shows the timing in this case.
TGR read cycle
T1
T2
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
Internal
data bus
M
M
Figure 10.49 Contention between TGR Read and Input Capture
Rev. 5.00 Aug 02, 2006 page 481 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
TGR write cycle
T1
T2
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
M
TGR
Figure 10.50 Contention between TGR Write and Input Capture
10.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
Rev. 5.00 Aug 02, 2006 page 482 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
Buffer register write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
N
M
TGR
Buffer
register
N
M
Figure 10.51 Contention between Buffer Register Write and Input Capture
10.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clearing signal
TGF
Disabled
TCFV
Figure 10.52 Contention between Overflow and Counter Clearing
Rev. 5.00 Aug 02, 2006 page 483 of 980
REJ09B0050-0500
Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.53 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 10.53 Contention between TCNT Write and Overflow
10.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
10.10.14 Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.
Rev. 5.00 Aug 02, 2006 page 484 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Section 11 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse
unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that
can operate both simultaneously and independently. The block diagram of PPG is shown in figure
11.1
11.1
Features
• 16-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlap mode
• Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC)
• Settable inverted output
• Module stop mode can be set
PPG0001A_000020020100
Rev. 5.00 Aug 02, 2006 page 485 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
Legend:
PMR:
PCR:
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
PODRL
NDRL
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Figure 11.1 Block Diagram of PPG
Rev. 5.00 Aug 02, 2006 page 486 of 980
REJ09B0050-0500
Internal
data bus
Section 11 Programmable Pulse Generator (PPG)
11.2
Input/Output Pins
Table 11.1 summarizes the I/O pins of the PPG.
Table 11.1 Pin Configuration
Pin Name
I/O
Function
PO15
Output
Group 3 pulse output
PO14
Output
PO13
Output
PO12
Output
PO11
Output
PO10
Output
PO9
Output
PO8
Output
PO7
Output
PO6
Output
PO5
Output
PO4
Output
PO3
Output
PO2
Output
PO1
Output
PO0
Output
11.3
Group 2 pulse output
Group 1 pulse output
Group 0 pulse output
Register Descriptions
The PPG has the following registers.
• Next data enable register H (NDERH)
• Next data enable register L (NDERL)
• Output data register H (PODRH)
• Output data register L (PODRL)
• Next data register H (NDRH)
• Next data register L (NDRL)
• PPG output control register (PCR)
• PPG output mode register (PMR)
Rev. 5.00 Aug 02, 2006 page 487 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the
PPG, set the corresponding DDR to 1.
• NDREH
Bit
Bit Name
Initial Value
R/W
Description
7
NDER15
0
R/W
Next Data Enable 15 to 8
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
When a bit is set to 1, the value in the
corresponding NDRH bit is transferred to the
PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for
cleared bits.
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
• NDERL
Bit
Bit Name
Initial Value
R/W
Description
7
NDER7
0
R/W
Next Data Enable 7 to 0
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
When a bit is set to 1, the value in the
corresponding NDRL bit is transferred to the
PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for
cleared bits.
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
Rev. 5.00 Aug 02, 2006 page 488 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse
output by NDER is read-only and cannot be modified.
• PODRH
Bit
Bit Name
Initial Value
R/W
Description
7
POD15
0
R/W
Output Data Register 15 to 8
6
POD14
0
R/W
5
POD13
0
R/W
4
POD12
0
R/W
3
POD11
0
R/W
2
POD10
0
R/W
For bits which have been set to pulse output by
NDERH, the output trigger transfers NDRH values
to this register during PPG operation. While
NDERH is set to 1, the CPU cannot write to this
register. While NDERH is cleared, the initial output
value of the pulse can be set.
1
POD9
0
R/W
0
POD8
0
R/W
• PODRL
Bit
Bit Name
Initial Value
R/W
Description
7
POD7
0
R/W
Output Data Register 7 to 0
6
POD6
0
R/W
5
POD5
0
R/W
4
POD4
0
R/W
3
POD3
0
R/W
2
POD2
0
R/W
For bits which have been set to pulse output by
NDERL, the output trigger transfers NDRL values
to this register during PPG operation. While
NDERL is set to 1, the CPU cannot write to this
register. While NDERL is cleared, the initial output
value of the pulse can be set.
1
POD1
0
R/W
0
POD0
0
R/W
Rev. 5.00 Aug 02, 2006 page 489 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on
whether pulse output groups have the same output trigger or different output triggers.
• NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 8
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 12
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
to
0
—
1
—
Rev. 5.00 Aug 02, 2006 page 490 of 980
REJ09B0050-0500
Reserved
These bits are always read as 1 and cannot be
modified.
Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
1
—
Reserved
3
NDR11
0
R/W
Next Data Register 11 to 8
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
These bits are always read as 1 and cannot be
modified.
• NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 0
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 4
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
to
0
—
1
—
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 491 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
1
—
Reserved
3
NDR3
0
R/W
Next Data Register 3 to 0
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
11.3.4
These bits are always read as 1 and cannot be
modified.
PPG Output Control Register (PCR)
PCR selects output trigger signals on a group-by-group basis. For details on output trigger
selection, refer to section 11.3.5, PPG Output Mode Register (PMR).
Bit
Bit Name
Initial Value
R/W
Description
7
G3CMS1
1
R/W
Group 3 Compare Match Select 1 and 0
6
G3CMS0
1
R/W
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
5
4
G2CMS1
1
R/W
Group 2 Compare Match Select 1 and 0
G2CMS0
1
R/W
Select output trigger of pulse output group 2.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
3
G1CMS1
1
R/W
Group 1 Compare Match Select 1 and 0
2
G1CMS0
1
R/W
Select output trigger of pulse output group 1.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
Rev. 5.00 Aug 02, 2006 page 492 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
1
G0CMS1
1
R/W
Group 0 Compare Match Select 1 and 0
0
G0CMS0
1
R/W
Select output trigger of pulse output group 0.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
11.3.5
PPG Output Mode Register (PMR)
PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a
low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If
non-overlapping operation is selected, PPG updates its output values at compare match A or B of
the TPU that becomes the output trigger. For details, refer to section 11.4.4, Non-Overlapping
Pulse Output.
Bit
Bit Name
Initial Value
R/W
Description
7
G3INV
1
R/W
Group 3 Inversion
Selects direct output or inverted output for pulse
output group 3.
0: Inverted output
1: Direct output
6
G2INV
1
R/W
Group 2 Inversion
Selects direct output or inverted output for pulse
output group 2.
0: Inverted output
1: Direct output
5
G1INV
1
R/W
Group 1 Inversion
Selects direct output or inverted output for pulse
output group 1.
0: Inverted output
1: Direct output
4
G0INV
1
R/W
Group 0 Inversion
Selects direct output or inverted output for pulse
output group 0.
0: Inverted output
1: Direct output
Rev. 5.00 Aug 02, 2006 page 493 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
3
G3NOV
0
R/W
Group 3 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 3.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
2
G2NOV
0
R/W
Group 2 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 2.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
1
G1NOV
0
R/W
Group 1 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 1.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
0
G0NOV
0
R/W
Group 0 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 0.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
Rev. 5.00 Aug 02, 2006 page 494 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4
Operation
Figure 11.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
DDR
NDER
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 11.2 Overview Diagram of PPG
Rev. 5.00 Aug 02, 2006 page 495 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.1
Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 11.3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
PO8 to PO15
m
n
m
n
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)
Rev. 5.00 Aug 02, 2006 page 496 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.2
Sample Setup Procedure for Normal Pulse Output
Figure 11.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
[1] Set TIOR to make TGRA an output
compare register (with output
disabled)
[2] Set the PPG output trigger period
TPU setup
Port and
PPG setup
TPU setup
Set next pulse
output data
[8]
Start counter
[9]
Compare match?
No
[3] Select the counter clock source with
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
Yes
Set next pulse
output data
[10]
[9] Set the CST bit in TSTR to 1 to start
the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 11.4 Setup Procedure for Normal Pulse Output (Example)
Rev. 5.00 Aug 02, 2006 page 497 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.3
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output)
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
Rev. 5.00 Aug 02, 2006 page 498 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
11.4.4
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 11.6 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
Pulse
output
pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 11.6 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 11.7 shows the timing of this operation.
Rev. 5.00 Aug 02, 2006 page 499 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output
0/1 output
Do not write
to NDR here
Write to NDR
here
Figure 11.7 Non-Overlapping Operation and NDR Write Timing
Rev. 5.00 Aug 02, 2006 page 500 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.5
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping
pulse output
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
Start counter
[10]
TPU setup
PPG setup
TPU setup
Compare match A?
[2] Set the pulse output trigger period
in TGRB and the non-overlap
period in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
No
[8] In PMR, select the groups that will
operate in non-overlap mode.
Yes
Set next pulse
output data
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled)
[11]
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
Rev. 5.00 Aug 02, 2006 page 501 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.6
Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output)
Figure 11.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
Rev. 5.00 Aug 02, 2006 page 502 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
Rev. 5.00 Aug 02, 2006 page 503 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
11.4.7
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 11.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 11.9.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 11.10 Inverted Pulse Output (Example)
Rev. 5.00 Aug 02, 2006 page 504 of 980
REJ09B0050-0500
65
Section 11 Programmable Pulse Generator (PPG)
11.4.8
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 11.11 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 11.11 Pulse Output Triggered by Input Capture (Example)
11.5
Usage Notes
11.5.1
Module Stop Mode Setting
PPG operation can be disabled or enabled using the module stop control register. The initial value
is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 22, Power-Down Modes.
11.5.2
Operation of Pulse Output Pins
Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
Rev. 5.00 Aug 02, 2006 page 505 of 980
REJ09B0050-0500
Section 11 Programmable Pulse Generator (PPG)
Rev. 5.00 Aug 02, 2006 page 506 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Section 12 8-Bit Timers (TMR)
This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit
counter. The 8-bit timer module can be used to count external events and be used as a
multifunction timer in a variety of applications, such as generation of counter reset, interrupt
requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two
registers.
12.1
Features
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal
• Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
• Provision for cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode)
TMR_1 can be used to count TMR_0 compare matches (compare match count mode)
• Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated
TIMH260A_000020020100
Rev. 5.00 Aug 02, 2006 page 507 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
External clock source
TMCI0
TMCI1
Internal clock sources
TMR_0 TMR_1
φ/8
φ/8
φ/64
φ/64
φ/8192
φ/8192
Clock 1
Clock 0
Clock select
TCORA_0
Compare match A1
Compare match A0 Comparator A_0
Overflow 1
Overflow 0
TMO0
TMRI0
TCNT_0
TCORA_1
Comparator A_1
TCNT_1
Clear 1
TMO1
TMRI1
Control logic
Compare match B1
Compare match B0 Comparator B_0
A/D
conversion
start request
signal
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Legend:
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 12.1 Block Diagram of 8-Bit Timer Module
Rev. 5.00 Aug 02, 2006 page 508 of 980
REJ09B0050-0500
Internal bus
Clear 0
Section 12 8-Bit Timers (TMR)
12.2
Input/Output Pins
Table 12.1 summarizes the pins of the 8-bit timer module.
Table 12.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
0
Timer output pin
TMO0
Output
Outputs at compare match
Timer clock input pin
TMCI0
Input
Inputs external clock for counter
Timer reset input pin
TMRI0
Input
Inputs external reset to counter
Timer output pin
TMO1
Output
Outputs at compare match
Timer clock input pin
TMCI1
Input
Inputs external clock for counter
Timer reset input pin
TMRI1
Input
Inputs external reset to counter
1
12.3
Register Descriptions
The 8-bit timer module has the following registers. For details on the module stop control register,
refer to section 22.1.2, Module Stop Control Registers H, L (MSTPCRH, MSTPCRL).
• Timer counter_0 (TCNT_0)
• Time constant register A_0 (TCORA_0)
• Time constant register B_0 (TCORB_0)
• Timer control register_0 (TCR_0)
• Timer control/status register_0 (TCSR_0)
• Timer counter_1 (TCNT_1)
• Time constant register A_1 (TCORA_1)
• Time constant register B_1 (TCORB_1)
• Timer control register_1 (TCR_1)
• Timer control/status register_1 (TCSR_1)
12.3.1
Timer Counter (TCNT)
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
Rev. 5.00 Aug 02, 2006 page 509 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.3.2
Time Constant Register A (TCORA)
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
The value in TCORA is continually compared with the value in TCNT. When a match is detected,
the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled
during the T2 state of a TCORA write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match A) and the settings of bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF.
12.3.3
Time Constant Register B (TCORB)
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during
the T2 state of a TCOBR write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF.
12.3.4
Timer Control Register (TCR)
TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.
Rev. 5.00 Aug 02, 2006 page 510 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
7
CMIEB
0
R/W
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests
(CMIB) are enabled or disabled when the CMFB
flag in TCSR is set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests
(CMIA) are enabled or disabled when the CMFA
flag in TCSR is set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI)
are enabled or disabled when the OVF flag in
TCSR is set to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the method by which TCNT is
cleared
00: Clearing is disabled
01: Clear by compare match A
10: Clear by compare match B
11: Clear by rising edge of external reset input
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select the clock input to TCNT and
count condition. See table 12.2.
Rev. 5.00 Aug 02, 2006 page 511 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Table 12.2 Clock Input to TCNT and Count Condition
TCR
Channel
TMR_0
TMR_1
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
1
0
Internal clock, counted at falling edge of φ/64
1
Internal clock, counted at falling edge of φ/8192
1
0
0
Count at TCNT_1 overflow signal*
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
1
All
Note:
*
12.3.5
1
0
0
Internal clock, counted at falling edge of φ/8192
Count at TCNT_0 compare match A*
1
0
1
External clock, counted at rising edge
1
0
External clock, counted at falling edge
1
1
External clock, counted at both rising and falling edges
If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit
Bit Name
Initial Value
R/W
Description
7
CMFB
0
R/(W)*
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
Rev. 5.00 Aug 02, 2006 page 512 of 980
REJ09B0050-0500
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0
Section 12 8-Bit Timers (TMR)
Bit
6
Bit Name
CMFA
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag A
[Setting condition]
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt
while DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4
ADTE
0
R/W
A/D Trigger Enable
Selects enabling or disabling of A/D converter
start requests by compare match A.
0: A/D converter start requests by compare
match A are disabled
1: A/D converter start requests by compare
match A are enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
Rev. 5.00 Aug 02, 2006 page 513 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR_1
Bit
7
Bit Name
CMFB
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt
while DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
Rev. 5.00 Aug 02, 2006 page 514 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
4
—
1
R
Reserved
This bit is always read as 1 and cannot be
modified.
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
12.4
Operation
12.4.1
Pulse Output
Figure 12.2 shows an example that the 8-bit timer is used to generate a pulse output with a
selected duty cycle. The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is
cleared at a TCORA compare match.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
Rev. 5.00 Aug 02, 2006 page 515 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.2 Example of Pulse Output
12.5
Operation Timing
12.5.1
TCNT Incrementation Timing
Figure 12.3 shows the count timing for internal clock input. Figure 12.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
Figure 12.3 Count Timing for Internal Clock Input
Rev. 5.00 Aug 02, 2006 page 516 of 980
REJ09B0050-0500
N+1
Section 12 8-Bit Timers (TMR)
φ
External clock
input pin
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 12.4 Count Timing for External Clock Input
12.5.2
Timing of CMFA and CMFB Setting when Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input.
Figure 12.5 shows this timing.
φ
TCNT
N
TCOR
N
N+1
Compare match
signal
CMF
Figure 12.5 Timing of CMF Setting
Rev. 5.00 Aug 02, 2006 page 517 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.5.3
Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 12.6 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 12.6 Timing of Timer Output
12.5.4
Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 12.7 shows the timing of this operation.
φ
Compare match
signal
TCNT
N
Figure 12.7 Timing of Compare Match Clear
Rev. 5.00 Aug 02, 2006 page 518 of 980
REJ09B0050-0500
H'00
Section 12 8-Bit Timers (TMR)
12.5.5
Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.8
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.8 Timing of Clearance by External Reset
12.5.6
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.9
shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.9 Timing of OVF Setting
Rev. 5.00 Aug 02, 2006 page 519 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
12.6.1
16-Bit Counter Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
12.6.2
Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel
0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Rev. 5.00 Aug 02, 2006 page 520 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.7
Interrupts
12.7.1
Interrupt Sources and DTC Activation
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 12.3. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the
interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB
interrupts.
Table 12.3 8-Bit Timer Interrupt Sources
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
CMIA0
TCORA_0 compare match
CMFA
Possible
High
CMIB0
TCORB_0 compare match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
Low
CMIA1
TCORA_1 compare match
CMFA
Possible
High
CMIB1
TCORB_1 compare match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
12.7.2
Low
A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A.
If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0
compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer
conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is
started.
Rev. 5.00 Aug 02, 2006 page 521 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.8
Usage Notes
12.8.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 12.10 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
TCNT address
Address
Internal write signal
Counter clear signal
N
TCNT
H'00
Figure 12.10 Contention between TCNT Write and Clear
Rev. 5.00 Aug 02, 2006 page 522 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.8.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 12.11 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
TCNT address
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.11 Contention between TCNT Write and Increment
Rev. 5.00 Aug 02, 2006 page 523 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.8.3
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 12.12.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare match signal
Inhibited
Figure 12.12 Contention between TCOR Write and Compare Match
Rev. 5.00 Aug 02, 2006 page 524 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
12.8.4
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 12.4.
Table 12.4 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
12.8.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.5 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in
table 12.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
The erroneous incrementation can also happen when switching between internal and external
clocks.
Rev. 5.00 Aug 02, 2006 page 525 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Table 12.5 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from
1
low to low*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N
CKS bit write
2
Switching from
2
low to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N
CKS bit write
3
Switching from
3
high to low*
Clock before
switchover
Clock after
switchover
*4
TCNT clock
TCNT
N
N
CKS bit write
Rev. 5.00 Aug 02, 2006 page 526 of 980
REJ09B0050-0500
N
Section 12 8-Bit Timers (TMR)
No.
4
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N
N
CKS bit write
Notes: 1.
2.
3.
4.
12.8.6
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
12.8.7
Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should
therefore be disabled before entering module stop mode.
Rev. 5.00 Aug 02, 2006 page 527 of 980
REJ09B0050-0500
Section 12 8-Bit Timers (TMR)
Rev. 5.00 Aug 02, 2006 page 528 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
Section 13 Watchdog Timer
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
At the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 13.1.
13.1
Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not
the entire chip is reset at the same time.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0101A_000020020100
Rev. 5.00 Aug 02, 2006 page 529 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
Clock
WDTOVF
Internal reset signal*
Clock
select
Reset
control
RSTCSR
TCNT
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
TSCR
Module bus
Bus
interface
Internal bus
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
WDT
Legend:
Timer control/status register
TCSR:
Timer counter
TCNT:
RSTCSR: Reset control/status register
Note: * An internal reset signal can be generated by the register setting.
Figure 13.1 Block Diagram of WDT
13.2
Input/Output Pin
Table 13.1 describes the WDT output pin.
Table 13.1 Pin Configuration
Name
Symbol
I/O
Function
Watchdog timer overflow
WDTOVF
Output
Outputs counter overflow signal in watchdog
timer mode
Rev. 5.00 Aug 02, 2006 page 530 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
13.3
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 13.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
13.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
13.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
Bit Name
Initial Value
R/W
Description
7
OVF
0
R/(W)*
Overflow Flag
Indicates that TCNT has overflowed in interval
timer mode. Only a write of 0 is permitted, to
clear the flag.
[Setting condition]
When TCNT overflows in interval timer mode
(changes from H’FF to H’00)
When internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
Rev. 5.00 Aug 02, 2006 page 531 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
Bit
Bit Name
Initial Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer
interrupt (WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows, the WDTOVF signal is
output.
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting
and is initialized to H'00.
4
—
1
—
Reserved
3
—
1
—
These bits are always read as 1 and cannot be
modified.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
Selects the clock source to be input to TCNT.
The overflow frequency for φ = 20 MHz is
enclosed in parentheses.
000: Clock φ/2 (frequency: 25.6 µs)
001: Clock φ/64 (frequency: 819.2 µs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note:
*
Only a write of 0 is permitted, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 532 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
13.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit
7
Bit Name
WOVF
Initial Value
R/W
Description
0
R/(W)*
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval
timer mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
6
RSTE
0
R/W
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
1: Reset signal is generated if TCNT overflows
5
—
0
R/W
Reserved
These bits can be read from or written to, but the
operation is not affected.
4
to
0
Note:
—
1
—
Reserved
These bits are always read as 1 and cannot be
modified.
*
Only a write of 0 is permitted, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 533 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
13.4
Operation
13.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
WDTOVF signal is output.
This ensures that TCNT does not overflow while the system is operating normally. Software must
prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer
mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
Rev. 5.00 Aug 02, 2006 page 534 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
TCNT count
Overflow
H'FF
Time
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WOVF=1
WDTOVF and
internal reset are
generated
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
132 states*2
Internal reset signal*1
518 states
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 13.2 Operation in Watchdog Timer Mode
13.4.2
Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit in the TCSR is set to 1.
Rev. 5.00 Aug 02, 2006 page 535 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WOVI
WT/IT=0
TME=1
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 13.3 Operation in Interval Timer Mode
13.5
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 13.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Impossible
13.6
Usage Notes
13.6.1
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
Rev. 5.00 Aug 02, 2006 page 536 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 13.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 13.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 13.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.
TCNT write or
Writing to RSTE bit in RSTCSR
15
Address: H'FFBC (TCNT)
H'FFBE (RSTCSR)
8
7
H'5A
0
Write data
TCSR write
Address: H'FFBC (TCSR)
15
8
7
H'A5
0
Write data
Writing 0 to WOVF bit in RSTCSR
Address: H'FFBE (RSTCSR)
Figure 13.4
15
8
H'A5
7
0
H'00
Writing to TCNT, TCSR, and RSTCSR
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.
Rev. 5.00 Aug 02, 2006 page 537 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
13.6.2
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write
cycle, the write takes priority and the timer counter is not incremented. Figure 13.5 shows this
operation.
TCNT write cycle
T1
T2
Next cycle
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.5 Contention between TCNT Write and Increment
13.6.3
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
13.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
Rev. 5.00 Aug 02, 2006 page 538 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
13.6.5
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
13.6.6
System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.
Make sure that the WDTOVF signal is not input logically to the RES pin.
To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 13.6.
This LSI
Reset input
Reset signal to entire system
Figure 13.6 Circuit for System Reset by WDTOVF Signal (Example)
Rev. 5.00 Aug 02, 2006 page 539 of 980
REJ09B0050-0500
Section 13 Watchdog Timer
Rev. 5.00 Aug 02, 2006 page 540 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Section 14 Serial Communication Interface (SCI, IrDA)
This LSI has five independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function) in asynchronous mode. The SCI also supports an IC
card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an
asynchronous serial communication interface extension function. One of the five SCI channels
(SCI_0) can generate an IrDA communication waveform conforming to IrDA specification
version 1.0.
Figure 14.1 shows a block diagram of the SCI.
14.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests. The transmit-data-empty interrupt and receive data full
interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC).
• Module stop mode can be set
Asynchronous mode
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
SCI0021AA_000020020100
Rev. 5.00 Aug 02, 2006 page 541 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
• Average transfer rate generator (SCI_2 only): The following transfer rate can be selected.
115.152 or 460.606 kbps at 10.667 MHz operation
115.196, 460.784 or 720 kbps at 16 MHz operation
720 kbps at 32 MHz operation
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
Rev. 5.00 Aug 02, 2006 page 542 of 980
REJ09B0050-0500
Bus interface
Section 14 Serial Communication Interface (SCI, IrDA)
Module data bus
RxD
RDR
TDR
RSR
TSR
SCMR
SSR
SCR
SMR
SEMR
BRR
φ
Baud rate
generator
Transmission/
reception control
TxD
Parity generation
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
SEMR:
Internal
data bus
TEI
TXI
RXI
ERI
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Smart card mode register
Bit rate register
Serial extension mode register (only in SCI_2)
Average transfer
rate generator
(SCI_2)
10.667 MHz operation
• 115.152 kbps
• 460.606 kbps
16 MHz operation
• 115.196 kbps
• 460.784 kbps
• 720 kbps
32 MHz operation
• 720 kbps
Figure 14.1 Block Diagram of SCI
Rev. 5.00 Aug 02, 2006 page 543 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.2
Input/Output Pins
Table 14.1 shows the serial pins for each SCI channel.
Table 14.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
Channel 0 clock input/output
1
2
3
4
Note:
*
RxD0/IrRxD
Input
Channel 0 receive data input (normal/IrDA)
TxD0/IrTxD
Output
Channel 0 transmit data output (normal/IrDA)
SCK1
I/O
Channel 1 clock input/output
RxD1
Input
Channel 1 receive data input
TxD1
Output
Channel 1 transmit data output
SCK2
I/O
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
SCK3
I/O
Channel 3 clock input/output
RxD3
Input
Channel 3 receive data input
TxD3
Output
Channel 3 transmit data output
SCK4
I/O
Channel 4 clock input/output
RxD4
Input
Channel 4 receive data input
TxD4
Output
Channel 4 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Rev. 5.00 Aug 02, 2006 page 544 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3
Register Descriptions
The SCI has the following registers. The serial mode register (SMR), serial status register (SSR),
and serial control register (SCR) are described separately for normal serial communication
interface mode and Smart Card interface mode because their bit functions partially differ.
• Receive shift register_0 (RSR_0)
• Transmit shift register_0 (TSR_0)
• Receive data register_0 (RDR_0)
• Transmit data register_0 (TDR_0)
• Serial mode register_0 (SMR_0)
• Serial control register_0 (SCR_0)
• Serial status register_0 (SSR_0)
• Smart card mode register_0 (SCMR_0)
• Bit rate register_0 (BRR_0)
• IrDA control register_0 (IrCR_0)
• Receive shift register_1 (RSR_1)
• Transmit shift register_1 (TSR_1)
• Receive data register_1 (RDR_1)
• Transmit data register_1 (TDR_1)
• Serial mode register_1 (SMR_1)
• Serial control register_1 (SCR_1)
• Serial status register_1 (SSR_1)
• Smart card mode register_1 (SCMR_1)
• Bit rate register_1 (BRR_1)
• Receive shift register_2 (RSR_2)
• Transmit shift register_2 (TSR_2)
• Receive data register_2 (RDR_2)
• Transmit data register_2 (TDR_2)
• Serial mode register_2 (SMR_2)
• Serial control register_2 (SCR_2)
• Serial status register_2 (SSR_2)
• Smart card mode register_2 (SCMR_2)
• Bit rate register_2 (BRR_2)
• Serial extension mode register_2 (SEMR_2)
• Receive shift register_3 (RSR_3)
Rev. 5.00 Aug 02, 2006 page 545 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
• Transmit shift register_3 (TSR_3)
• Receive data register_3 (RDR_3)
• Transmit data register_3 (TDR_3)
• Serial mode register_3 (SMR_3)
• Serial control register_3 (SCR_3)
• Serial status register_3 (SSR_3)
• Smart card mode register_3 (SCMR_3)
• Bit rate register_3 (BRR_3)
• Receive shift register_4 (RSR_4)
• Transmit shift register_4 (TSR_4)
• Receive data register_4 (RDR_4)
• Transmit data register_4 (TDR_4)
• Serial mode register_4 (SMR_4)
• Serial control register_4 (SCR_4)
• Serial status register_4 (SSR_4)
• Smart card mode register_4 (SCMR_4)
• Bit rate register_4 (BRR_4)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is
receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous
receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
14.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
Rev. 5.00 Aug 02, 2006 page 546 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1.
14.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot
be directly accessed by the CPU.
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock
source.
Some bit functions of SMR differ in normal serial communication interface mode and Smart Card
interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is
fixed and the MSB (bit 7) of TDR is not
transmitted in transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. For a multiprocessor
format, parity bit addition and checking are not
performed regardless of the PE bit setting.
Rev. 5.00 Aug 02, 2006 page 547 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked
regardless of the STOP bit setting. If the second
stop bit is 0, it is treated as the start bit of the next
transmit character.
2
MP
0
R/W
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
1
CKS1
0
R/W
Clock Select 1 and 0:
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 14.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 14.3.9, Bit Rate
Register (BRR)).
Rev. 5.00 Aug 02, 2006 page 548 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
GM
0
R/W
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of 1 bit), and clock
output control mode addition is performed. For
details, refer to section 14.7.8, Clock Output
Control.
6
BLK
0
R/W
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 14.7.3, Block Transfer Mode.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. In Smart Card interface
mode, this bit must be set to 1.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card
interface mode, refer to section 14.7.2, Data
Format (Except for Block Transfer Mode).
3
BCP1
0
R/W
Basic Clock Pulse 1 and 0
2
BCP0
0
R/W
These bits select the number of basic clock
periods in a 1-bit transfer interval on the Smart
Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 14.3.9, Bit
Rate Register (BRR)).
Rev. 5.00 Aug 02, 2006 page 549 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
1
CKS1
0
R/W
Clock Select 1 and 0:
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 14.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 14.3.9, Bit Rate
Register (BRR)).
Rev. 5.00 Aug 02, 2006 page 550 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.6
Serial Control Register (SCR)
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
14.9, SCI Interrupts. Some bit functions of SCR differ in normal serial communication interface
mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
5
TE
0
R/W
Transmit Enable
When this bit s set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
Rev. 5.00 Aug 02, 2006 page 551 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 14.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is
received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF,
FER, and ORER flags in SSR , is not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
is enabled.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled. TEI cancellation can be performed by
reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or
by clearing the TEIE bit to 0.
Rev. 5.00 Aug 02, 2006 page 552 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
1
CKE1
0
R/W
Clock Enable 1 and 0
0
CKE0
0
R/W
Selects the clock source and SCK pin function.
Asynchronous mode
00: On-chip baud rate generator
SCK pin functions as I/O port
01: On-chip baud rate generator
(Outputs a clock of the same frequency as the
bit rate from the SCK pin.)
1×: External clock
(Inputs a clock with a frequency 16 times the
bit rate from the SCK pin.)
Clocked synchronous mode
0×: Internal clock (SCK pin functions as clock
output)
1×: External clock (SCK pin functions as clock
input)
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 553 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
Bit Name
Initial Value
R/W
7
TIE
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled. TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in Smart Card interface mode.
Rev. 5.00 Aug 02, 2006 page 554 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
2
TEIE
0
R/W
Description
Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
1
CKE1
0
0
CKE0
0
R/W
Clock Enable 1 and 0
Enables or disables clock output from the SCK
pin. The clock output can be dynamically
switched in GSM mode. For details, refer to
section 14.7.8, Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an
I/O port pin)
01: Clock output
1×: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Legend: ×: Don’t care
Rev. 5.00 Aug 02, 2006 page 555 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
Bit Name
TDRE
Initial Value
R/W
Description
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading
TDRE = 1
•
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading
RDRF = 1
•
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data
will be lost.
Rev. 5.00 Aug 02, 2006 page 556 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
5
Bit Name
ORER
Initial Value
R/W
Description
0
R/(W)*
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended
abnormally.
[Setting condition]
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
[Clearing condition]
When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
4
FER
0
R/(W)*
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the
reception has ended abnormally.
[Setting condition]
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the RDRF
flag is not set. Also, subsequent serial reception
cannot be continued while the FER flag is set to
1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
When 0 is written to FER after reading FER = 1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Rev. 5.00 Aug 02, 2006 page 557 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
3
Bit Name
PER
Initial Value
R/W
Description
0
R/(W)*
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the
reception has ended abnormally.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In
clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
2
TEND
1
R
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading
TDRE = 1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Note:
*
Only 0 can be written, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 558 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
Bit Name
TDRE
Initial Value
R/W
Description
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading
TDRE = 1
•
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading
RDRF = 1
•
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data
will be lost.
Rev. 5.00 Aug 02, 2006 page 559 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
5
Bit Name
ORER
Initial Value
R/W
Description
0
R/(W)*
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended
abnormally.
[Setting condition]
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
[Clearing condition]
When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
4
ERS
0
R/(W)*
Error Signal Status
[Setting condition]
When the low level of the error signal is sampled
[Clearing condition]
When 0 is written to ERS after reading ERS = 1
Rev. 5.00 Aug 02, 2006 page 560 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
3
Bit Name
PER
Initial Value
R/W
Description
0
R/(W)*
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the
reception has ended abnormally.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In
clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Rev. 5.00 Aug 02, 2006 page 561 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
TEND
1
R
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
When the TE bit in SCR is 0 and the ERS bit
is also 0
•
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1byte data
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu after transmission
GM = 0, BLK = 1: 1.5 etu after transmission
GM = 1, BLK = 0: 1.0 etu after transmission
GM = 1, BLK = 1: 1.0 etu after transmission
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TEND after reading
TEND = 1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Multiprocessor Bit
This bit is not used in Smart Card interface
mode.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Notes: etu: Elementary Time Unit: (time for transfer of 1 bit)
* Only 0 can be written, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 562 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.8
Smart Card Mode Register (SCMR)
SCMR selects Smart Card interface mode and its format.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
1
—
Reserved
3
SDIR
These bits are always read as 1.
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer
data format is 8 bits. For 7-bit data, LSB-first is
fixed.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the
parity bit. To invert the parity bit, invert the O/E
bit in SMR.
0: TDR contents are transmitted as they are.
Receive data is stored as it is in RDR.
1: TDR contents are inverted before being
transmitted. Receive data is stored in inverted
form in RDR.
1
—
1
—
0
SMIF
0
R/W
Reserved
This bit is always read as 1.
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart card interface mode
Rev. 5.00 Aug 02, 2006 page 563 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 14.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Bit Rate
Asynchronous
Mode
B=
Clocked
Synchronous
Mode
B=
Smart Card
Interface Mode
B=
Error
106
64
22n-1
(N + 1)
Error (%) = {
106
B
64
22n-1
S
22n-1
(N + 1)
-1}
100
-1}
100
106
8
22n-1
S
22n-1
(N + 1)
106
(N + 1)
Error (%) = {
106
B
(N + 1)
Notes: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N
settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 14.5 and 14.7 show the maximum bit rates with
external clock input.
Rev. 5.00 Aug 02, 2006 page 564 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
8
9.8304
10
12
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
141
0.03
2
174
–0.26
2
177
–0.25
2
212
0.03
150
2
103
0.16
2
127
0.00
2
129
0.16
2
155
0.16
300
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
600
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
1200
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
2400
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
4800
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
9600
0
25
0.16
0
31
0.00
0
32
–1.38
0
38
0.16
19200
0
12
0.16
0
15
0.00
0
15
1.70
0
19
–2.40
31250
0
7
0.00
0
9
–1.73
0
9
0.00
0
11
0.00
38400
—
—
—
0
7
0.00
0
7
1.70
0
9
–2.40
Operating Frequency φ (MHz)
12.288
14
14.7456
16
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
217
0.08
2
248
–0.17
3
64
0.69
3
70
0.03
150
2
159
0.00
2
181
0.16
2
191
0.00
2
207
0.16
300
2
79
0.00
2
90
0.16
2
95
0.00
2
103
0.16
600
1
159
0.00
1
181
0.16
1
191
0.00
1
207
0.16
1200
1
79
0.00
1
90
0.16
1
95
0.00
1
103
0.16
2400
0
159
0.00
0
181
0.16
0
191
0.00
0
207
0.16
4800
0
79
0.00
0
90
0.16
0
95
0.00
0
103
0.16
9600
0
39
0.00
0
45
–0.94
0
47
0.00
0
51
0.16
19200
0
19
0.00
0
22
–0.94
0
23
0.00
0
25
0.16
31250
0
11
2.34
0
13
0.00
0
14
–1.73
0
15
0.00
38400
0
9
0.00
—
—
—
0
11
0.00
0
12
0.16
Rev. 5.00 Aug 02, 2006 page 565 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ (MHz)
17.2032
18
19.6608
20
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
75
0.48
3
79
–0.12
3
86
0.31
3
88
–0.25
150
2
223
0.00
2
233
0.16
2
255
0.00
3
64
0.16
300
2
111
0.00
2
116
0.16
2
127
0.00
2
129
0.16
600
1
223
0.00
1
233
0.16
1
255
0.00
2
64
0.16
1200
1
111
0.00
1
116
0.16
1
127
0.00
1
129
0.16
2400
0
223
0.00
0
233
0.16
0
255
0.00
1
64
0.16
4800
0
111
0.00
0
116
0.16
0
127
0.00
0
129
0.16
9600
0
55
0.00
0
58
–0.69
0
63
0.00
0
64
0.16
19200
0
27
0.00
0
28
1.01
0
31
0.00
0
32
–1.38
31250
0
16
1.20
0
17
0.00
0
19
–1.73
0
19
0.00
38400
0
13
0.00
0
14
–2.40
0
15
0.00
0
15
1.70
Operating Frequency φ (MHz)
25
30
34*
33
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
110
–0.02
3
132
0.13
3
145
0.33
3
150
–0.05
150
3
80
0.47
3
97
–0.35
3
106
0.39
3
110
–0.29
300
2
162
–0.15
2
194
0.16
2
214
–0.07
2
220
0.16
600
2
80
0.47
2
97
–0.35
2
106
0.39
2
110
–0.29
1200
1
162
–0.15
1
194
0.16
1
214
–0.07
1
220
0.16
2400
1
80
0.47
1
97
–0.35
1
106
0.39
1
110
–0.29
4800
0
162
–0.15
0
194
0.16
0
214
–0.07
0
220
0.16
9600
0
80
0.47
0
97
–0.35
0
106
0.39
0
110
–0.29
19200
0
40
–0.76
0
48
–0.35
0
53
–0.54
0
54
0.61
31250
0
24
0.00
0
29
0
0
32
0
0
33
0.00
0
19
1.70
0
23
1.70
0
26
–0.54
0
27
–1.20
38400
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 566 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
19.6608
614400
0
0
20
625000
0
0
25
781250
0
0
30
937500
0
0
33
1031250
0
0
34*
1062500
0
0
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 567 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
19.6608
4.9152
307200
20
5.0000
312500
25
6.2500
390625
30
7.5000
468750
33
8.2500
515625
34*
8.5000
531250
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 568 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
Bit Rate
(bit/s) n
8
10
16
N
n
N
n
N
20
n
N
25
n
N
30
n
N
3
233
34*1
33
n
N
n
N
110
250
3
124
—
—
3
249
500
2
249
—
—
3
124
—
—
1k
2
124
—
—
2
249
—
—
3
97
3
116
3
128
3
128
2.5 k
1
199
1
249
2
99
2
124
2
155
2
187
2
205
2
212
5k
1
99
1
124
1
199
1
249
2
77
2
93
2
102
2
105
10 k
0
199
0
249
1
99
1
124
1
155
1
187
1
205
1
212
25 k
0
79
0
99
0
159
0
199
0
249
1
74
1
82
1
84
50 k
0
39
0
49
0
79
0
99
0
124
0
149
0
164
0
169
100 k
0
19
0
24
0
39
0
49
0
62
0
74
0
82
0
84
250 k
0
7
0
9
0
15
0
19
0
24
0
29
0
32
0
33
500 k
0
3
0
4
0
7
0
9
—
—
0
14
—
—
0
16
1M
0
1
0
3
0
4
—
—
—
—
—
—
0
1
—
—
0
2
—
—
0
0*
—
—
—
—
—
—
2.5 M
5M
0
0*
Legend:
Blank: Cannot be set.
—:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 569 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
25
4.1667
4166666.7
30
5.0000
5000000.0
33
5.5000
5500000.0
34*
5.6667
5666666.7
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 570 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372)
Operating Frequency φ (MHz)
10.00
10.7136
13.00
14.2848
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
1
30
0
1
25
0
1
8.99
0
1
0.00
Operating Frequency φ (MHz)
16.00
18.00
20.00
25.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
1
12.01
0
2
15.99
0
2
6.60
0
3
12.49
Operating Frequency φ (MHz)
30.00
34.00*
33.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
3
5.01
0
4
7.59
0
4
4.79
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 571 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
20.00
26882
0
0
25.00
33602
0
0
30.00
40323
0
0
33.00
44355
0
0
34.00*
45699
0
0
Note:
*
Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 572 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.10 IrDA Control Register (IrCR)
IrCR selects the function of SCI_0.
Bit
Bit Name
Initial Value
R/W
Description
7
IrE
0
R/W
IrDA Enable
Specifies normal SCI mode or IrDA mode for
SCI_0 input/output.
0: Pins TxD0/IrTxD and RxD0/IrRxD function as
TxD0 and RxD0
1: Pins TxD0/IrTxD and RxD0/IrRxD function as
IrTxD and IrRxD
6
5
4
IrCKS2
IrCKS1
IrCKS0
0
0
0
R/W
R/W
R/W
IrDA Clock Select 2 to 0
Specifies the high pulse width in IrTxD output
pulse encoding when the IrDA function is enabled.
000: Pulse width = B × 3/16 (3/16 of bit rate)
001: Pulse width = φ/2
010: Pulse width = φ/4
011: Pulse width = φ/8
100: Pulse width = φ/16
101: Pulse width = φ/32
110: Pulse width = φ/64
111: Pulse width = φ/128
3
to
0
—
0
—
Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 573 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.3.11 Serial Extension Mode Register (SEMR)
SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by
selecting the average transfer rate.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
Undefined
—
Reserved
3
ABCS
If these bits are read, an undefined value will be
returned. They cannot be modified.
0
R/W
Asynchronous basic clock selection (valid only in
asynchronous mode)
Selects the basic clock for 1-bit period in
asynchronous mode.
0: Operates on a basic clock with a frequency of
16 times the transfer rate.
1: Operates on a basic clock with a frequency of
8 times the transfer rate.
Rev. 5.00 Aug 02, 2006 page 574 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
1
0
ACS2
ACS1
ACS0
0
0
0
R/W
R/W
R/W
Asynchronous clock source selection (valid when
CKE1 = 1 in asynchronous mode)
Selects the clock source for the average transfer
rate.
The basic clock can be automatically set by
selecting the average transfer rate in spite of the
value of ABCS.
000: External clock input
001: Selects 115.152 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a
frequency of 16 times the transfer rate.)
010: Selects 460.606 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a
frequency of 8 times the transfer rate.)
011: Selects 720 kbps which is the average
transfer rate dedicated for φ = 32 MHz.
(Operates on a basic clock with a
frequency of 16 times the transfer rate.)
100: Reserved
101: Selects 115.196 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a
frequency of 16 times the transfer rate.)
110: Selects 460.784 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a
frequency of 16 times the transfer rate.)
111: Selects 720 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a
frequency of 8 times the transfer rate.)
Note that the average transfer rate does not
correspond to the frequency other than 10.667,
16, or 32 MHz.
Rev. 5.00 Aug 02, 2006 page 575 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. In asynchronous serial communication, the
communication line is usually held in the mark state (high level). The SCI monitors the
communication line, and when it goes to the space state (low level), recognizes a start bit and
starts serial communication. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication. Both the transmitter and the receiver also have a doublebuffered structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer.
Idle state
(mark state)
MSB
LSB
1
Serial
data
0
D0
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity Stop bit(s)
bit
1 bit,
or none
1 or
2 bits
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
14.4.1
Data Transfer Format
Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 14.5, Multiprocessor Communication Function.
Rev. 5.00 Aug 02, 2006 page 576 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
STOP:
P:
MPB:
2
3
4
5
6
7
8
9
10
11
12
Start bit
Stop bit
Parity bit
Multiprocessor bit
Rev. 5.00 Aug 02, 2006 page 577 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 14.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
D – 0.5
1
) – (L – 0.5) F –
N
2N
M = { (0.5 –
(1 + F) }
100 [%]
... Formula (1)
Where M: Reception Margin
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
Synchronization
sampling timing
Data sampling
timing
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 5.00 Aug 02, 2006 page 578 of 980
REJ09B0050-0500
D1
Section 14 Serial Communication Interface (SCI, IrDA)
14.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4.
SCK
TxD
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 14.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Rev. 5.00 Aug 02, 2006 page 579 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 14.5. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is
cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external
clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. (Not necessary if
an external clock is used.)
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completed>
Figure 14.5 Sample SCI Initialization Flowchart
Rev. 5.00 Aug 02, 2006 page 580 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.4.5
Data Transmission (Asynchronous Mode)
Figure 14.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request
(TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR
before transmission of the current transmit data has finished, continuous transmission can be
enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Rev. 5.00 Aug 02, 2006 page 581 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 5.00 Aug 02, 2006 page 582 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
[1]
Initialization
Start of transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC* or
DTC is activated by a transmitdata-empty interrupt (TXI) request,
and data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Note: * Not supported by the H8S/2366F.
Clear TE bit in SCR to 0
<End>
Figure 14.7 Sample Serial Transmission Flowchart
Rev. 5.00 Aug 02, 2006 page 583 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.4.6
Serial Data Reception (Asynchronous Mode)
Figure 14.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 14.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 5.00 Aug 02, 2006 page 584 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample
flowchart for serial data reception.
Table 14.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains its state before data reception.
Rev. 5.00 Aug 02, 2006 page 585 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
processing, ensure that the
PER Ú FER Ú ORER = 1?
ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot
No
Error handling
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1?
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DMAC* or DTC is
activated by an RXI interrupt and
the RDR value is read.
Note: * Not supported by the H8S/2366F.
Figure 14.9 Sample Serial Reception Data Flowchart (1)
Rev. 5.00 Aug 02, 2006 page 586 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
[3]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 14.9 Sample Serial Reception Data Flowchart (2)
Rev. 5.00 Aug 02, 2006 page 587 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component
cycles: an ID transmission cycle which specifies the receiving station, and a data transmission
cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the
ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is
an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle.
Figure 14.10 shows an example of inter-processor communication using the multiprocessor
format. The transmitting station first sends communication data with a 1 multiprocessor bit added
to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor
bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that
data with its own ID. The station whose ID matches then receives the data sent next. Stations
whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again
received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On
reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 5.00 Aug 02, 2006 page 588 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'AA
H'01
(MPB= 1)
ID transmission cycle =
receiving station
specification
(MPB= 0)
Data transmission cycle =
data transmission to
receiving station specified by ID
[Legend]
MPB: Multiprocessor bit
Figure 14.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
14.5.1
Multiprocessor Serial Data Transmission
Figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Rev. 5.00 Aug 02, 2006 page 589 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
[1] [1] SCI initialization:
Initialization
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC* or DTC is activated by a
transmit-data-empty interrupt
(TXI) request, and data is written
to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Note: * Not supported by the H8S/2366F.
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 5.00 Aug 02, 2006 page 590 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.5.2
Multiprocessor Serial Data Reception
Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
14.12 shows an example of SCI operation for multiprocessor format reception.
Rev. 5.00 Aug 02, 2006 page 591 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID2
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
(b) Data matches station’s ID
Figure 14.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 5.00 Aug 02, 2006 page 592 of 980
REJ09B0050-0500
Data2
MPIE bit set to 1
again
Section 14 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start of reception
Set MPIE bit in SCR to 1
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1?
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station's ID?
Yes
[5] Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 5.00 Aug 02, 2006 page 593 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
[5]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 5.00 Aug 02, 2006 page 594 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.6
Operation in Clocked Synchronous Mode
Figure 14.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character of communication data consists of 8-bit data. In clocked synchronous serial
communication, data on the transmission line is output from one falling edge of the serial clock to
the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising
edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In
clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex communication by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that
data can be read or written during transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 14.14 Data Format in Clocked Synchronous Communication (For LSB-First)
14.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixed high.
Rev. 5.00 Aug 02, 2006 page 595 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 14.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit
to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. (Not necessary if an
external clock is used.)
[4] Wait at least one bit interval, then set
the TE and RE bits in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enable the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should
both be cleared to 0 or set to 1 simultaneously.
Figure 14.15 Sample SCI Initialization Flowchart
Rev. 5.00 Aug 02, 2006 page 596 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt
request is generated. The SCK pin is fixed high.
Figure 14.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Rev. 5.00 Aug 02, 2006 page 597 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
TXI interrupt
Data written to TDR
request generated
and TDRE flag
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev. 5.00 Aug 02, 2006 page 598 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC* or
DTC is activated by a transmit-dataempty interrupt (TXI) request and data
is written to TDR.
No
TEND = 1?
Note: * Not supported by the H8S/2366F.
Yes
Clear TE bit in SCR to 0
<End>
Figure 14.17 Sample Serial Transmission Flowchart
Rev. 5.00 Aug 02, 2006 page 599 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the received data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 14.18 Example of SCI Operation in Reception
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.19 shows a sample
flowchart for serial data reception.
Rev. 5.00 Aug 02, 2006 page 600 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1?
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC is activated by a receivedata-full interrupt (RXI) request
and the RDR value is read.
<End>
[3]
Error handling
Overrun error handling
Clear ORER flag in SSR to 0
<End>
Figure 14.19 Sample Serial Reception Flowchart
Rev. 5.00 Aug 02, 2006 page 601 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.
To switch from receive mode to simultaneous transmit and receive mode, after checking that the
SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error
flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single
instruction.
Rev. 5.00 Aug 02, 2006 page 602 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start of transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
Yes
[3]
Error handling
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1?
[5] Serial transmission/reception
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE and RE bits to 0,
then set both these bits to 1 simultaneously.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit-dataempty interrupt (TXI) request and
data is written to TDR. Also, the
RDRF flag is cleared automatically
when the DMAC or DTC is activated
by a receive-data-full interrupt (RXI)
request and the RDR value is read.
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Rev. 5.00 Aug 02, 2006 page 603 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.7
Operation in Smart Card Interface Mode
The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification
Card) as a serial communication interface extension function. Switching between the normal
serial communication interface and the Smart Card interface is carried out by means of a register
setting.
14.7.1
Pin Connection Example
Figure 14.21 shows an example of connection with the Smart Card. In communication with an IC
card, since both transmission and reception are carried out on a single data transmission line, the
TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be
pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and
RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be
carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is
input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Connected equipment
Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections
Rev. 5.00 Aug 02, 2006 page 604 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.7.2
Data Format (Except for Block Transfer Mode)
Figure 14.22 shows the transfer data format in Smart Card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit)
is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is sampled during transmission, the same data is retransmitted automatically
after the elapse of 2 etu or longer.
When there is no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Transmitting station output
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Transmitting station output
Receiving station
output
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Figure 14.22 Normal Smart Card Interface Data Format
Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
Figure 14.23 Direct Convention (SDIR = SINV = O/E
E = 0)
Rev. 5.00 Aug 02, 2006 page 605 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to
select even parity mode.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
Figure 14.24 Inverse Convention (SDIR = SINV = O/E
E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1
to invert the parity bit for both transmission and reception.
14.7.3
Block Transfer Mode
Operation in block transfer mode is the same as that in normal Smart Card interface, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
14.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the bit rate (fixed at 16 times in normal
Rev. 5.00 Aug 02, 2006 page 606 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or
128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is
given by the following formula.
M = | (0.5 –
| D – 0.5 |
1
) – (L – 0.5) F –
(1 + F) |
N
2N
100%
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
372 clocks
186 clocks
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate)
Rev. 5.00 Aug 02, 2006 page 607 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.7.5
Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ERS, PER, and ORER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be
checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode,
after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set
RE to 1. Whether SCI has finished transmission can be checked with the TEND flag.
14.7.6
Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 14.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sampled from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next
parity bit is sampled.
2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is
retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Rev. 5.00 Aug 02, 2006 page 608 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
4. Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transfers the next transmit data.
Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt
source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in
SSR, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI
request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will
be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE
and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or
DMAC. In the event of an error, the SCI retransmits the same data automatically. During this
period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore,
the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event
of an error, including retransmission. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 8, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).
nth transfer frame
Transfer
frame n+1
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
Transfer to TSR
from TDR
Transfer to TSR from TDR
TEND
[7]
[9]
FER/ERS
[6]
[8]
Figure 14.26 Retransfer Operation in SCI Transmit Mode
Rev. 5.00 Aug 02, 2006 page 609 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND
flag generation timing is shown in figure 14.27.
I/O data
Ds
D0
D1
D2
TXI
(TEND interrupt)
D3
D4
D5
D6
D7
Dp
DE
Guard
time
12.5etu
When GM = 0
11.0etu
When GM = 1
Legend:
Start bit
Ds:
D0 to D7: Data bits
Parity bit
Dp:
Error signal
DE:
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Figure 14.27 TEND Flag Generation Timing in Transmission Operation
Rev. 5.00 Aug 02, 2006 page 610 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
No
All data transmitted ?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 14.28 Example of Transmission Processing Flow
Rev. 5.00 Aug 02, 2006 page 611 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.7.7
Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled.
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
4. The receive operation is judged to have been completed normally, and the RDRF flag in SSR
is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is
generated.
Figure 14.30 shows a flowchart for reception. The sequence of receive operations can be
performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt
source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR
is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the
DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be
carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a
transfer error interrupt (ERI) request will be generated, and so the error flag must be cleared to 0.
In the event of an error, the DTC or DMAC is not activated and receive data is skipped.
Therefore, receive data is transferred for only the specified number of bytes in the event of an
error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that
has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 14.4, Operation in
Asynchronous Mode.
nth transfer frame
Transfer
frame n+1
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 14.29 Retransfer Operation in SCI Receive Mode
Rev. 5.00 Aug 02, 2006 page 612 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start reception
ORER = 0 and
PER = 0
No
Yes
Error processing
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit to 0
Figure 14.30 Example of Reception Processing Flow
14.7.8
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and
CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 14.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Rev. 5.00 Aug 02, 2006 page 613 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 14.31 Timing for Fixing Clock Output Level
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty.
Powering On: To secure the clock duty from power-on, the following switching procedure should
be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down
resistor to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When changing from smart card interface mode to software standby mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin
to the value for the fixed output state in software standby mode.
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
During this interval, clock output is fixed at the specified level, with the duty preserved.
5. Make the transition to the software standby state.
When returning to smart card interface mode from software standby mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty.
Rev. 5.00 Aug 02, 2006 page 614 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[6] [7]
Figure 14.32 Clock Halt and Restart Procedure
Rev. 5.00 Aug 02, 2006 page 615 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.8
IrDA Operation
When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are
subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD
and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to
implement infrared transmission/reception conforming to the IrDA specification version 1.0
system.
In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600
bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this
LSI does not include a function for varying the transfer rate automatically, the transfer rate setting
must be changed by software.
Figure 14.33 shows a block diagram of the IrDA function.
SCI0
IrDA
TxD0/IrTxD
Pulse encoder
RxD0/IrRxD
Pulse decoder
TxD
RxD
IrCR
Figure 14.33 Block Diagram of IrDA
Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an
IR frame by the IrDA interface (see figure 14.34).
When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one
bit) is output (initial value). The high-level pulse can be varied according to the setting of bits
IrCKS2 to IrCKS0 in IrCR.
Rev. 5.00 Aug 02, 2006 page 616 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can
be set for a high pulse width with a minimum value of 1.41 µs.
When the serial data is 1, no pulse is output.
UART frame
Stop
bit
Data
Start
bit
0
1
0
1
0
0
1
Transmit
1
0
1
Receive
IR frame
Data
Start
bit
0
Bit
cycle
1
0
1
0
Stop
bit
0
1
1
0
1
Pulse width
1.6 µs to 3/16 bit cycle
Figure 14.34 IrDA Transmit/Receive Operations
Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and
input to the SCI.
When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1
data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified
as a 0 signal.
High Pulse Width Selection: Table 14.12 shows possible settings for bits IrCKS2 to IrCKS0
(minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse
width shorter than 3/16 times the bit rate in transmission.
Rev. 5.00 Aug 02, 2006 page 617 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.12 Settings of Bits IrCKS2 to IrCKS0
Bit Rate (bps) (Above) /Bit Period × 3/16 (µs) (Below)
Operating
Frequency
φ (MHz)
2400
9600
19200
38400
57600
115200
78.13
19.53
9.77
4.88
3.26
1.63
8
100
100
100
100
100
100
9.8304
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
25
110
110
110
110
110
—
30
110
110
110
110
110
—
33
110
110
110
110
110
—
34*
110
110
110
110
110
—
Legend:
—: A bit rate setting cannot be made on the SCI side.
Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
Rev. 5.00 Aug 02, 2006 page 618 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.9
SCI Interrupts
14.9.1
Interrupts in Normal Serial Communication Interface Mode
Table 14.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC
or DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data
transfer is performed by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DTC or DMAC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Rev. 5.00 Aug 02, 2006 page 619 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Table 14.13 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC
Activation
DMAC
Activation
0
ERI0
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI0
Receive Data Full
RDRF
Possible
Possible
TXI0
Transmit Data Empty
TDRE
Possible
Possible
TEI0
Transmission End
TEND
Not possible
Not possible
ERI1
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI1
Receive Data Full
RDRF
Possible
Possible
TXI1
Transmit Data Empty
TDRE
Possible
Possible
TEI1
Transmission End
TEND
Not possible
Not possible
ERI2
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI2
Receive Data Full
RDRF
Possible
Not possible
TXI2
Transmit Data Empty
TDRE
Possible
Not possible
TEI2
Transmission End
TEND
Not possible
Not possible
ERI3
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI3
Receive Data Full
RDRF
Possible
Not possible
TXI3
Transmit Data Empty
TDRE
Possible
Not possible
TEI3
Transmission End
TEND
Not possible
Not possible
ERI4
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI4
Receive Data Full
RDRF
Possible
Not possible
TXI4
Transmit Data Empty
TDRE
Possible
Not possible
TEI4
Transmission End
TEND
Not possible
Not possible
1
2
3
4
Rev. 5.00 Aug 02, 2006 page 620 of 980
REJ09B0050-0500
Priority
High
Low
Section 14 Serial Communication Interface (SCI, IrDA)
14.9.2
Interrupts in Smart Card Interface Mode
Table 14.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 14.14 Interrupt Sources
Channel
0
1
2
3
4
Name
Interrupt Source
Interrupt Flag
DTC
Activation
DMAC
Activation
ERI0
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI0
Receive Data Full
RDRF
Possible
Possible
TXI0
Transmit Data Empty
TEND
Possible
Possible
ERI1
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI1
Receive Data Full
RDRF
Possible
Possible
TXI1
Transmit Data Empty
TEND
Possible
Possible
ERI2
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI2
Receive Data Full
RDRF
Possible
Not possible
TXI2
Transmit Data Empty
TEND
Possible
Not possible
ERI3
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI3
Receive Data Full
RDRF
Possible
Not possible
TXI3
Transmit Data Empty
TEND
Possible
Not possible
ERI4
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI4
Receive Data Full
RDRF
Possible
Not possible
TXI4
Transmit Data Empty
TEND
Possible
Not possible
Priority
High
Low
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the
same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is
designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be
activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and
TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC.
In the event of an error, the SCI retransmits the same data automatically. During this period, the
TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and
DTC or DMAC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in
the event of an error, and the ERS flag will be cleared.
Rev. 5.00 Aug 02, 2006 page 621 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 8, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).
In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or
DMAC will be activated by the RXI request, and transfer of the receive data will be carried out.
The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or
DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or
DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the
error flag should be cleared.
14.10
Usage Notes
14.10.1 Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 22, Power-Down Modes.
14.10.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving
a break, even if the FER flag is cleared to 0, it will be set to 1 again.
14.10.3 Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break
during serial data transmission. To maintain the communication line at mark state until TE is set
to 1, set both DDR and DR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an
I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set
DDR to 1 and clear DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
Rev. 5.00 Aug 02, 2006 page 622 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
14.10.5 Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
14.10.6 Restrictions on Use of DMAC or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least five φ clock cycles after TDR is updated by the DMAC or DTC. Abnormal
operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(figure 14.35)
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 14.35 Example of Synchronous Transmission Using DTC
Rev. 5.00 Aug 02, 2006 page 623 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
14.10.7 Operation in Case of Mode Transition
• Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and become
high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after
clearing the relevant mode, the procedure must be started again from initialization.
Figure 14.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 14.37 and 14.38.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode or software standby mode
transition. To perform transmission with the DTC after the relevant mode is cleared, setting
TE and TIE to 1 will set the TXI flag and start DTC transmission.
• Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode
or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made
during reception, the data being received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Rev. 5.00 Aug 02, 2006 page 624 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Figure 14.39 shows a sample flowchart for mode transition during reception.
<Transmission>
All data
transmitted?
No
[1]
[1]
Data being transmitted is interrupted.
After exiting software standby mode,
normal CPU transmission is possible
by setting TE to 1, reading SSR,
writing TDR, and clearing TDRE to 0,
but note that if the DTC has been
activated, the remaining data in
DTCRAM will be transmitted when
TE and TIE are set to 1.
[2]
If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[3]
Includes module stop mode.
Yes
Read TEND flag in SSR
TEND = 1
No
Yes
TE = 0
[2]
Transition to software
standby mode
[3]
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
TE = 1
<Start of transmission>
Figure 14.36 Sample Flowchart for Mode Transition during Transmission
Rev. 5.00 Aug 02, 2006 page 625 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
End of
transmission
Start of transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin
Port input/output
High output
Port
Start
Stop
Port input/output
Port
SCI TxD output
High output
SCI TxD
output
Figure 14.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission)
Start of transmission
End of
transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin Port input/output
Last TxD bit held
Marking output
Port
SCI TxD output
Port input/output
Port
Note: * Initialized by software standby.
Figure 14.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission)
Rev. 5.00 Aug 02, 2006 page 626 of 980
REJ09B0050-0500
High output*
SCI TxD
output
Section 14 Serial Communication Interface (SCI, IrDA)
<Reception>
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Receive data being received
becomes invalid.
[2]
[2] Includes module stop mode.
Yes
Read receive data in RDR
RE = 0
Transition to software
standby mode
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
RE = 1
<Start of reception>
Figure 14.39 Sample Flowchart for Mode Transition during Reception
Rev. 5.00 Aug 02, 2006 page 627 of 980
REJ09B0050-0500
Section 14 Serial Communication Interface (SCI, IrDA)
Rev. 5.00 Aug 02, 2006 page 628 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Section 15 I2C Bus Interface2 (IIC2) (Option)
An I2C bus interface is an option. When using the optional functions, take notice of the following
item:
For the masked ROM version, ‘W’ is added to the model name of the product that uses optional
functions.
For example: HD6432365WTE
This LSI has a two-channel I2C bus interface,
The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however.
Figure 15.1 shows a block diagram of the I2C bus interface2.
Figure 15.2 shows an example of I/O pin connections to external circuits.
15.1
Features
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
• Direct bus drive
Two pins, SCL and SDA pins function as NMOS open-drain outputs.
IFIIC40_000020020100
Rev. 5.00 Aug 02, 2006 page 629 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Transfer clock
generation
circuit
SCL
Transmission/
reception
control circuit
Output
control
ICCRA
ICCRB
ICMR
Internal data bus
Noise canceler
ICDRT
SDA
Output
control
ICDRS
SAR
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICEIR
Legend:
ICCRA:
ICCRB:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
Interrupt
generator
2
I C bus control register A
I2C bus control register B
I2C mode register
I2C status register
I2C interrupt permission register
I2C transmission data register
I2C reception data register
I2C bus shift register
Slave address register
Figure 15.1 Block Diagram of I2C Bus Interface2
Rev. 5.00 Aug 02, 2006 page 630 of 980
REJ09B0050-0500
Interrupt request
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Vcc
SCL in
Vcc
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL out
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Figure 15.2 External Circuit Connections of I/O Pins
15.2
Input/Output Pins
Table 15.1 summarizes the input/output pins used by the I2C bus interface.
Table 15.1 Pin Configuration
Name
Abbreviation
I/O
Function
Serial clock
SCL0
I/O
IIC2_0 serial clock input/output
Serial data
SDA0
I/O
IIC2_0 serial data input/output
Serial clock
SCL1
I/O
IIC2_1 serial clock input/output
Serial data
SDA1
I/O
IIC2_1 serial data input/output
Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this
manual.
Rev. 5.00 Aug 02, 2006 page 631 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.3
Register Descriptions
The I2C bus interface has the following registers.
• I2C bus control register A_0 (ICCRA_0)
• I2C bus control register B_0 (ICCRB_0)
• I2C bus mode register_0 (ICMR_0)
• I2C bus interrupt enable register_0 (ICIER_0)
• I2C bus status register_0 (ICSR_0)
• I2C bus slave address register_0 (SAR_0)
• I2C bus transmit data register_0 (ICDRT_0)
• I2C bus receive data register_0 (ICDRR_0)
• I2C bus shift register_0 (ICDRS_0)
• I2C bus control register A_1 (ICCRA_1)
• I2C bus control register B_1 (ICCRB_1)
• I2C bus mode register_1 (ICMR_1)
• I2C bus interrupt enable register_1 (ICIER_1)
• I2C bus status register_1 (ICSR_1)
• I2C bus slave address register_1 (SAR_1)
• I2C bus transmit data register_1 (ICDRT_1)
• I2C bus receive data register_1 (ICDRR_1)
• I2C bus shift register_1 (ICDRS_1)
Rev. 5.00 Aug 02, 2006 page 632 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.3.1
I2C Bus Control Register A (ICCRA)
ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls
transmission or reception, and selects master or slave mode, transmission or reception, and transfer
clock frequency in master mode.
Bit
Bit Name
Initial Value R/W
Description
7
ICE
0
I C Bus Interface Enable
R/W
2
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL and SDA
pins are bus drive state.)
6
RCVD
0
R/W
Reception Disable
This bit enables or disables the next operation when TRS is
0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
When arbitration is lost in master mode, MST and TRS are
both reset by hardware, causing a transition to slave
receive mode. Modification of the TRS bit should be made
between transfer frames. In addition, TRS is set to 1
automatically in slave receive mode when the seventh bit of
the start condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according to MST
and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Transfer clock select 3 to 0
In master mode, these bits should be set according to the
necessary transfer rate. In slave mode, they are used to
secure the data setup time in transmit mode. The data
setup time is 10 tcyc when CKS3 is cleared to 0; 20 tcyc
when CKS3 is set to 1.
Rev. 5.00 Aug 02, 2006 page 633 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Table 15.2 Transfer Rate
Bit3
Bit2
Bit1
Bit0
Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock
0*
3
0*
3
0
1
1
0
1
1
0
1
φ=
8MHz
φ=
10MHz
φ=
20MHz
φ=
25 MHz
φ=
33 MHz
φ=
1
34 MHz*
0
φ/28 286 kHz
357 kHz
714 kHz*
893 kHz*
1179
2
kHz*
1
φ/40 200 kHz
250 kHz
500 kHz*
625 kHz*
825 kHz*
850 kHz*
0
φ/48 167 kHz
208 kHz
417 kHz*
521 kHz*
688 kHz*
2
708 kHz*
*2
531 kHz*
2
2
2
2
2
2
*2
1214
2
kHz*
2
2
2
2
1
φ/64 125 kHz
156 kHz
313 kHz
391 kHz
0
φ/168 47.6 kHz
59.5 kHz
119 kHz
149 kHz
196 kHz
202 kHz
1
φ/100 80.0 kHz
100 kHz
200 kHz
250 kHz
330 kHz
340 kHz
0
φ/112 71.4 kHz
89.3 kHz
179 kHz
223 kHz
295 kHz
304 kHz
1
φ/128 62.5 kHz
78.1 kHz
156 kHz
195 kHz
258 kHz
266 kHz
607 kHz*
516 kHz
0
φ/56 143 kHz
179 kHz
357 kHz
1
φ/80 100 kHz
125 kHz
250 kHz
2
2
446 kHz* 589 kHz*
2
313 kHz
413 kHz*
1
0
φ/96 83.3 kHz
104 kHz
208 kHz
260 kHz
344 kHz
354 kHz
1
φ/128 62.5 kHz
78.1 kHz
156 kHz
195 kHz
258 kHz
266 kHz
0
0
φ/336 23.8 kHz
29.8 kHz
59.5 kHz
74.4 kHz
98.2 kHz
101 kHz
1
φ/200 40.0 kHz
50.0 kHz
100 kHz
125 kHz
165 kHz
170 kHz
0
φ/224 35.7 kHz
44.6 kHz
89.3 kHz
112 kHz
147 kHz
152 kHz
1
φ/256 31.3 kHz
39.1 kHz
78.1 kHz
97.7 kHz
129 kHz
133 kHz
0
1
2
425 kHz*
2
Notes: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT Group.
2
2. Does not conform to the I C bus interface specification (normal mode: max. 100 kHz,
high-speed mode: max. 400 kHz).
3. If CKS3 and CKS2 are both cleared to 0 (7.5 tcyc bit synchronization) and the operating
frequency is 20 MHz or greater, it may not be possible to maintain the prescribed
transfer rate under certain load conditions. Therefore, a bit synchronization setting other
than 7.5 tcyc should be used if the operating frequency exceeds 20 MHz.
Rev. 5.00 Aug 02, 2006 page 634 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.3.2
I2C Bus Control Register B (ICCRB)
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I2C control.
Bit
Bit Name
Initial Value R/W
Description
7
BBSY
0
Bus Busy
R/W
2
This bit enables to confirm whether the I C bus is occupied
or released and to issue start and stop conditions in master
mode. This bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is cleared
to 0 when the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to SCP
to issue a start condition. Follow this procedure when also
re-transmitting a start condition. Write 0 to BBSY and 0 to
SCP to issue a stop condition. To issue a start/stop
condition, use the MOV instruction.
6
SCP
1
W
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP. This
bit is always read as 1. If 1 is written, the data is not stored.
5
SDAO
1
R/W
Monitors the output level of SDA.
0: When reading, SDA pin outputs low.
1: When reading, SDA pin outputs high.
The write value should always be 1.
4
1
R/W
Reserved
The write value should always be 1.
3
SCLO
1
R
This bit monitors SCL output level. When reading and
SCLO is 1, SCL pin outputs high. When reading and SCLO
is 0, SCL pin outputs low.
2
1
Reserved
This bit is always read as 1.
1
IICRST
0
R/W
IIC control part reset
2
This bit resets control parts except for I C registers. If this
bit is set to 1 when hang-up is occurred because of
2
2
communication failure during I C operation, I C control part
can be reset without setting ports and initializing registers.
Rev. 5.00 Aug 02, 2006 page 635 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Bit
Bit Name
Initial Value R/W
0
1
Description
Reserved
This bit is always read as 1.
15.3.3
I2C Bus Mode Register (ICMR)
ICMR performs master mode wait control and selects the transfer bit count.
Bit
Bit Name
Initial Value R/W
Description
7
0
R/W
Reserved
6
WAIT
0
R/W
The write value should always be 0.
Wait Insertion Bit
This bit selects whether to insert a wait after data transfer
except for the acknowledge bit. When WAIT is set to 1,
after the fall of the clock for the final data bit, low period is
extended for two transfer clocks. If WAIT is cleared to 0,
data and acknowledge bits are transferred consecutively
with no wait inserted.
The setting of this bit is invalid in slave mode.
5
4
1
1
Reserved
3
BCWP
1
R/W
BC Write Protect
These bits are always read as 1.
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
Rev. 5.00 Aug 02, 2006 page 636 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Bit
Bit Name
Initial Value R/W
Description
2
BC2
0
R/W
Bit Counter 2 to 0
1
BC1
0
R/W
0
BC0
0
R/W
These bits specify the number of bits to be transferred next.
When read, the remaining number of transfer bits is
indicated. The data is transferred with one addition
acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to
BC0 are set to a value other than 000, the setting should
be made while the SCL line is low. The value returns to 000
at the end of a data transfer, including the acknowledge bit.
With the clock synchronous serial format, these bits should
not be modified.
000: 9
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
15.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit
Bit Name
Initial Value R/W
Description
7
TIE
0
Transmit Interrupt Enable
R/W
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI)
at the rising of the ninth clock while the TDRE bit in ICSR is
1. TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Rev. 5.00 Aug 02, 2006 page 637 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Bit
Bit Name
Initial Value R/W
Description
5
RIE
0
Receive interrupt enable
R/W
This bit enables or disables the receive data full interrupt
request (RXI) when a received data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI
can be canceled by clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) is disabled.
1: Receive data full interrupt request (RXI) is enabled.
4
NAKIE
0
R/W
NACK receive interrupt enable
This bit enables or disables the NACK receive interrupt
request (NAKI) when the NACKF and AL bits in ICSR are
set to 1. NAKI can be canceled by clearing the NACKF, AL,
or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop condition detection interrupt enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgement Select
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed.
1: If the acknowledge bit is 1, continuous transfer is
interrupted.
1
ACKBR
0
R
Receive acknowledge
In transmit mode, this bit stores the acknowledge data that
are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
Rev. 5.00 Aug 02, 2006 page 638 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.3.5
I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit
Bit Name
Initial Value R/W
Description
7
TDRE
0
Transmit Data Register Empty
R/W
[Setting conditions]
•
•
•
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a start condition (including retransmission) is
issued
When a transition from receive mode to transmit mode is
made in slave mode
[Clearing conditions]
6
TEND
0
R/W
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written to ICDRT
Transmit end
[Setting condition]
When the ninth clock of SCL is rose while the TDRE flag is
1
[Clearing conditions]
•
•
5
RDRF
0
R/W
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT
Receive Data Register Full
[Setting condition]
When a received data is transferred from ICDRS to ICDRR
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
•
When ICDRR is read
Rev. 5.00 Aug 02, 2006 page 639 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Bit
Bit Name
Initial Value R/W
Description
4
NACKF
0
No acknowledge detection flag
R/W
[Setting condition]
When no acknowledge is detected from the receive device
in transmission while the ACKE bit in ICIER is 1
[Clearing condition]
When 0 is written in NACKF after reading NACKF = 1
Note: When NACKF = 1 is detected, NACKF must be
cleared to 0. Subsequent transmission in not made
until NACKF is cleared to 0.
3
STOP
0
R/W
Stop condition detection flag
[Setting conditions]
•
In master mode, when a stop condition is detected after
frame transfer
•
In slave mode, when a stop condition is detected after
the general call address or the first byte slave address,
next to detection of start condition, accords with the
address set in SAR
[Clearing condition]
When 0 is written in STOP after reading STOP = 1
2
AL
0
R/W
Arbitration Lost Flag
This flag indicates that arbitration was lost in master mode.
When two or more master devices attempt to seize the bus
2
at nearly the same time, if the I C bus interface detects data
differing from the data it sent, it sets AL to 1 to indicate that
the bus has been taken by another master.
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
When the SDA pin outputs high in master mode while a
start condition is detected
[Clearing condition]
When 0 is written in AL/OVE after reading AL/OVE=1
Rev. 5.00 Aug 02, 2006 page 640 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Bit
Bit Name
Initial Value R/W
Description
1
AAS
0
Slave Address Recognition Flag
R/W
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
[Setting conditions]
•
When the slave address is detected in slave receive
mode
•
When the general call address is detected in slave
receive mode.
[Clearing condition]
When 0 is written in AAS after reading AAS=1
0
ADZ
0
R/W
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
When the general call address is detected in slave receive
mode
[Clearing conditions]
When 0 is written in ADZ after reading ADZ=1
15.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit
Initial Value R/W
Description
7 to SVA6 to
1
SVA0
0
Slave Address 6 to 0
0
0
Bit Name
R/W
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
2
connected to the I C bus.
R/W
Reserved
Though this bit can be read from or written to, the write
value should always be 0.
Rev. 5.00 Aug 02, 2006 page 641 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in
ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF.
15.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot be written to this register. The initial value of
ICDRR is H'FF.
15.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read from the CPU.
Rev. 5.00 Aug 02, 2006 page 642 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.4
Operation
15.4.1
I2C Bus Format
Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format
S
SLA
1
7
R/
1
A
DATA
A
A/
P
1
n
1
1
1
1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
m
(b) I2C bus format (start condition retransmission)
S
SLA
1
7
R/
1
A
DATA
1
n1
1
A/
S
SLA
1
1
7
m1
R/
1
A
DATA
1
n2
1
A/
P
1
1
m2
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
Figure 15.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/
A
1-7
DATA
8
9
A
1-7
DATA
8
9
A
P
Figure 15.4 I2C Bus Timing
Rev. 5.00 Aug 02, 2006 page 643 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Legend:
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
Slave address
R/W:
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receiving device drives SDA to low.
DATA: Transferred data
P:
15.4.2
Stop condition. The master device drives SDA from low to high while SCL is high.
Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. For master transmit mode operation
timing, refer to figures 15.5 and 15.6. The transmission procedure and operations in master
transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in
ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. After this, when TDRE is cleared to 0, data is
transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT, and clear TDRE and
TEND. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop
condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL
is fixed low until the transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set, thus
clearing TDRE.
Rev. 5.00 Aug 02, 2006 page 644 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
SCL
(master output)
1
2
3
4
5
6
SDA
(master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Slave address
SDA
(slave output)
7
Bit 1
8
9
1
Bit 0
Bit 7
2
Bit 6
R/
A
TDRE
TEND
Address + R/
ICDRT
ICDRS
User
processing
Address + R/
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte).
Clear TDRE.
Data 1
Data 2
Data 1
[4] Write data to ICDRT (second byte).
Clear TDRE and TEND.
[5] Write data to ICDRT (third byte).
Clear TDRE.
Figure 15.5 Master Transmit Mode Operation Timing 1
Rev. 5.00 Aug 02, 2006 page 645 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
SCL
(master output)
9
SDA
(master output)
SDA
(slave output)
1
2
3
4
5
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
A
7
Bit 1
8
9
Bit 0
A/
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT. Clear TDRE.
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 15.6 Master Transmit Mode Operation Timing 2
15.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the received data is read by reading ICDRR.
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while
RDRF is 1, SCL is fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear
RCVD.
Rev. 5.00 Aug 02, 2006 page 646 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the
RCVD bit to 0.
8. The operation returns to the slave receive mode.
Master transmit mode
SCL
(master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
SDA
(slave output)
9
1
A
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[3] Read ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 15.7 Master Receive Mode Operation Timing 1
Rev. 5.00 Aug 02, 2006 page 647 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
SCL
(master output)
9
SDA
(master output)
A
SDA
(slave output)
1
2
3
4
5
6
7
8
9
A/
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n
Data n-1
ICDRR
Data n
Data n-1
User
processing
[5] Read ICDRR and clear RDRF
after setting RCVD.
[7] Read ICDRR, clear RDRF,
and clear RCVD.
[6] Issue stop
condition [8] Set slave
receive mode
Figure 15.8 Master Receive Mode Operation Timing 2
15.4.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 15.9 and 15.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by clearing TDRE after writing transmit data to ICDRT every time
TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Rev. 5.00 Aug 02, 2006 page 648 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Slave receive mode
SCL
(master output)
Slave transmit mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
9
1
A
SCL
(slave output)
SDA
(slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
ICDRT
ICDRS
Data 1
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1),
and clear TDRE.
[2] Write data to ICDRT (data 2),
and clear TDRE.
[2] Write data to ICDRT (data 3),
and clear TDRE.
Figure 15.9 Slave Transmit Mode Operation Timing 1
Rev. 5.00 Aug 02, 2006 page 649 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Slave receive
mode
Slave transmit mode
SCL
(master output)
9
SDA
(master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(slave output)
SDA
(slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
[5] Clear TDRE
Figure 15.10 Slave Transmit Mode Operation Timing 2
15.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF
is cleared. (Since the read data show the slave address and R/W, it is not used.)
Rev. 5.00 Aug 02, 2006 page 650 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge
before reading ICDRR, to be returned to the master device, is reflected to the next transmit
frame.
4. The last byte data is read by reading ICDRR.
SCL
(master output)
9
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(slave output)
SDA
(slave output)
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[2] Read ICDRR (dummy read), and clear RDRF.
[2] Read ICDRR, and clear RDRF.
Figure 15.11 Slave Receive Mode Operation Timing 1
Rev. 5.00 Aug 02, 2006 page 651 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
SCL
(master output)
9
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(slave output)
SDA
(slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[3] Set ACKBT
[3] Read ICDRR,
and clear RDRF.
Figure 15.12 Slave Receive Mode Operation Timing 2
Rev. 5.00 Aug 02, 2006 page 652 of 980
REJ09B0050-0500
[4] Read ICDRR,
and clear RDRF.
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.4.6
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or SDA
input signal
D
C
Q
Latch
D
Q
Latch
March detector
Internal
SCL or SDA
signal
System clock
period
Sampling
clock
Figure 15.13 Block Diagram of Noise Canceler
15.4.7
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.14 to 15.17.
Rev. 5.00 Aug 02, 2006 page 653 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Start
Initialize
Read BBSY in ICCRB
[1]
Test the status of the SCL and SDA lines.
[2]
Select master transmit mode.
[3]
Start condition issuance.
[4]
Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
[5]
Wait for 1 byte to be transmitted.
[6]
Test the acknowledge bit, transferred from the specified slave device.
[7]
Set transmit data for the second and subsequent data (except for the final byte),
and clear TDRE and TEND to 0.
[8]
Wait for ICDRT empty.
[9]
Set the final byte of transmit data, and clear TDRE and TEND to 0.
[1]
No
BBSY=0 ?
Yes
Set MST = 1 and TRS
= 1 in ICCRA.
[2]
Write BBSY = 1
and SCP = 0.
[3]
Write transmit data
in ICDRT
[4]
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
[6]
ACKBR=0 ?
No
[10] Wait for the completion of transmission for the final byte.
Yes
Transmit
mode?
Yes
[11] Clear TEND flag.
No
Write transmit data in ICDRT
Master receive mode
[12] Clear STOP flag.
[7]
[13] Stop condition issuance.
Read TDRE in ICSR
No
[8]
[14] Wait for the creation of the stop condition.
TDRE=1 ?
[15] Set slave receive mode. Clear TDRE.
Yes
No
Final byte?
[9]
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ICSR
[12]
Write BBSY = 0
and SCP = 0
[13]
Read STOP in ICSR
No
[14]
STOP=1 ?
Yes
Set MST = 1 and TRS
= 0 in ICCRA
[15]
Clear TDRE in ICSR
End
Figure 15.14 Sample Flowchart for Master Transmit Mode
Rev. 5.00 Aug 02, 2006 page 654 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Mater receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmitting device.*
[3]
Dummy read ICDDR*
[4]
Wait for 1 byte to be received.
[5]
Check if (last receive - 1)
[6]
Read the receive data, and clear RDRF to 0.
[7]
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
[8]
Read receive data of (final byte - 1), and clear RDRF to 0.
[9]
Wait for the final byte to be received.
Clear TEND in ICSR
Set TRS = 0 (ICCRA)
[1]
Clear TDRE of ICSR
Set ACKBT = 0 (ICIER)
[2]
Dummy read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF=1 ?
Yes
(Last receive
- 1)?
No
Read ICDRR
Yes
[5]
[10] Clear STOP flag.
[6]
[11] Stop condition issuance
[12] Wait for the creation of stop condition.
Set ACKBT = 1 (ICIER)
[7]
Set RCVD - 1 (ICCRA)
Read ICDRR
[13] Read the receive data of the final byte, and clear RDRF to 0.
[14] Clear RCVD to 0.
[8]
[15] Set slave receive mode.
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP of ICSR
Write BBSY = 0
and SCP = 0
[9]
[10]
[11]
Read STOP of ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Set RCVD = 0 (ICCRA)
[14]
Set MST = 0 (ICCRA)
[15]
End
Note: * Prevent any interrupts while steps [1] to [3] are executed.
Additional information: When receiving one-byte data, execute step [1], and then step [7] omitting steps [2] to [6].
In step [8], dummy read ICDRR.
Figure 15.15 Sample Flowchart for Master Receive Mode
Rev. 5.00 Aug 02, 2006 page 655 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
[1] Clear the flag AAS.
Slave transmit mode
Clear AAS in ICSR
[1]
[2] Set transmit data for ICDRT (except for the last data),
and clear TDRE to 0.
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of the transmit data, and clear TDRE to 0.
Read TDRE in ICSR
No
[3]
TDRE=1 ?
[5] Wait the transmission end of the last byte.
[6] Clear the flag TEND.
Yes
No
[7] Set slave receive mode.
End of
transmission?
Yes
[4]
Write transmit data
in ICDRT
[8] Dummy read ICDRR to release the SCL line.
[9] Clear the flag TDRE.
Read TEND in ICSR
No
[5]
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Set TRS=0 in ICCRA
[7]
Dummy read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 15.16 Sample Flowchart for Slave Transmit Mode
Rev. 5.00 Aug 02, 2006 page 656 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Slave receive mode
[1] Clear the flag AAS.
Clear AAS in ICSR
[1]
Set ACKBT=0 in ICIER
[2]
[2] Set the acknowledge for the transmit device.
[3] Dummy read ICDRR.
[3]
Dummy read ICDRR
[5] Judge the (last receive - 1).
Read RDRF in ICSR
No
[4]
RDRF=1 ?
[6] Read the received data, and clear RDRF to 0.
[7] Set the acknowledge for the last byte.
Yes
The last receive
- 1?
[4] Wait the reception end of 1 byte.
Yes
No
Read ICDRR
[5]
[8] Read the received data of the (last byte - 1),
and clear RDRF to 0.
[6]
[9] Wait the reception end of the last byte.
[10] Read the received data of the last byte,
and clear RDRF to 0.
Set ACKBT=1 in ICIER
[7]
Read ICDRR
[8]
Read RDRF in ICSR
No
[9]
RDRF=1 ?
Yes
Read ICDRR
[10]
End
Additional information: When receiving one byte of data, execute step [1], and then step [7] omitting steps [2] to [6].
In step [8], dummy read ICDRR.
Figure 15.17 Sample Flowchart for Slave Receive Mode
Rev. 5.00 Aug 02, 2006 page 657 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
15.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each
interrupt request.
Table 15.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Transmit Data Empty
TXI
(TDRE = 1) • (TIE = 1)
Transmit End
TEI
(TEND = 1) • (TEIE = 1)
Receive Data Full
RXI
(RDRF = 1) • (RIE = 1)
STOP Recognition
STPI
(STOP = 1) • (STIE = 1)
NACK Detection
NAKI
{(NACKF = 1)+(AL = 1)} • (NAKIE = 1)
Arbitration Lost
When interrupt conditions described in table 15.3 are 1 and the CPU is ready to receive interrupts,
an interrupt execution handling is executed. Clear each interrupt source during an interrupt
execution handling. Note that TDRE and TEND are automatically cleared by writing the transmit
data to ICDRT, and RDRF is automatically cleared by reading ICDRR. When the transmit data is
written to ICDRT, TDRE is set again simultaneously. When TDRE is cleared, extra one byte of
data may be transmitted.
15.6
Bit Synchronous Circuit
In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization.
Figure 15.18 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
Rev. 5.00 Aug 02, 2006 page 658 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 15.18 Timing of the Bit Synchronous Circuit
Table 15.4 Time for monitoring SCL
CKS3
CKS2
Time for monitoring SCL
0
0
7.5 tcyc*
1
19.5 tcyc
0
17.5 tcyc
1
41.5 tcyc
1
Note:
15.7
*
If the operating frequency exceeds 20 MHz, it may not be possible to maintain the
prescribed transfer rate under certain load conditions. A setting other than 7.5 tcyc
should therefore be used.
Usage Notes
1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
Check SCLO in the I2C control register B (ICCRB)* to confirm the fall of the ninth clock.
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
ninth clocks, that is driven by the slave device
2. Control WAIT in the I2C bus mode register (ICMR) to be set to 0.
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.
Rev. 5.00 Aug 02, 2006 page 659 of 980
REJ09B0050-0500
2
Section 15 I C Bus Interface2 (IIC2) (Option)
Rev. 5.00 Aug 02, 2006 page 660 of 980
REJ09B0050-0500
Section 16 A/D Converter
Section 16 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to ten
analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1.
16.1
Features
• 10-bit resolution
• Ten input channels
• Conversion time: 7.6 µs per channel (at 34 MHz operation)
• Two kinds of operating modes
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels or 1 to 8 channels
• Eight data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
Conversion can be started by software, 16-bit timer pulse unit (TPU), conversion start
trigger by 8-bit timer (TMR), or external trigger signal.
• Interrupt request
A/D conversion end interrupt (ADI) request can be generated
• Module stop mode can be set
ADCMS04A_010020020100
Rev. 5.00 Aug 02, 2006 page 661 of 980
REJ09B0050-0500
Section 16 A/D Converter
Module data bus
Vref
Bus interface
Successive approximations
register
AVCC
10-bit A/D
AVSS
A
D
D
R
A
AN0
+
AN1
–
AN2
Internal data bus
A
D
D
R
B
Comparator
A
D
D
R
C
A
D
D
R
D
A
D
D
R
E
A
D
D
R
F
A
D
D
R
G
A
D
D
R
H
A
D
C
S
R
A
D
C
R
Control circuit
AN4
AN5
AN6
Multiplexer
AN3
Sample-andhold circuit
AN7
AN12
ADI interrupt
signal
AN13
Conversion start
trigger from 8-bit
timer or TPU
ADTRG
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
ADDRD:
ADDRE:
ADDRF:
ADDRG:
ADDRH:
A/D data register D
A/D data register E
A/D data register F
A/D data register G
A/D data register H
Figure 16.1 Block Diagram of A/D Converter
Rev. 5.00 Aug 02, 2006 page 662 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.2
Input/Output Pins
Table 16.1 summarizes the input pins used by the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The
Vref pin is the A/D conversion reference voltage pin.
The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and
channel set 1 (AN12 and AN13).
Table 16.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground
Reference voltage pin
Vref
Input
A/D conversion reference voltage
Analog input pin 0
AN0
Input
Channel set 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
Analog input pin 12
AN12
Input
Analog input pin 13
AN13
Input
A/D external trigger input
pin
ADTRG
Input
Channel set 1 analog inputs
External trigger input for starting A/D
conversion
Rev. 5.00 Aug 02, 2006 page 663 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.3
Register Descriptions
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D data register E (ADDRE)
• A/D data register F (ADDRF)
• A/D data register G (ADDRG)
• A/D data register H (ADDRH)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
16.3.1
A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 16.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width. The data can be read
directly from the CPU.
Rev. 5.00 Aug 02, 2006 page 664 of 980
REJ09B0050-0500
Section 16 A/D Converter
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0)
Channel Set 1 (CH3 = 1)
A/D Data Register which Stores
Conversion Result
AN0
ADDRA
AN1
ADDRB
AN2
ADDRC
AN3
ADDRD
AN4
AN12
ADDRE
AN5
AN13
ADDRF
AN6
ADDRG
AN7
ADDRH
Rev. 5.00 Aug 02, 2006 page 665 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit
Bit Name
Initial Value
R/W
Description
7
ADF
0
R/(W)*
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
6
ADIE
0
R/W
•
When 0 is written after reading ADF = 1
•
When the DTC or DMAC is activated by an
ADI interrupt and ADDR is read
A/D Interrupt Enable
A/D conversion end interrupt (ADI) request
enabled when 1 is set
5
ADST
0
R/W
A/D Start
Clearing this bit to 0 stops A/D conversion, and
the A/D converter enters wait state. When this bit
is set to 1 by software, TPU (trigger), TMR
(trigger), or the ADTRG pin, A/D conversion
starts. This bit remains set to 1 during A/D
conversion. In single mode, cleared to 0
automatically when conversion on the specified
channel ends. In scan mode, conversion
continues sequentially on the specified channels
until this bit is cleared to 0 by a reset, or a
transition to hardware standby mode or software
standby mode.
4
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 5.00 Aug 02, 2006 page 666 of 980
REJ09B0050-0500
Section 16 A/D Converter
Bit
Bit Name
Initial Value
R/W
Description
3
CH3
0
R/W
Channel select 3 to 0
2
CH2
0
R/W
1
CH1
0
R/W
Selects analog input together with bits SCANE
and SCANS in ADCR.
0
CH0
0
R/W
Set the input channel when conversion is
stopped (ADST = 0).
When SCANE = 0 and SCANS = X
0000: AN0
10××: Cannot be set
0001: AN1
10××: Cannot be set
0010: AN2
10××: Cannot be set
0011: AN3
10××: Cannot be set
0100: AN4
1100: AN12
0101: AN5
1101: AN13
0110: AN6
111×: Cannot be set
0111: AN7
111×: Cannot be set
When SCANE = 1 and SCANS = 0
0000: AN0
1000: AN8
0001: AN0 and AN1
1001: AN8 and AN9
0010: AN0 to AN2
1010: AN8 to AN10
0011: AN0 to AN3
1011: AN8 to AN11
0100: AN4
1100: AN12
0101: AN4 and AN5
1101: AN12 and AN13
0110: AN4 to AN6
1110: AN12 to AN14
0111: AN4 to AN7
1111: AN12 to AN15
When SCANE = 1 and SCANS = 1
0000: AN0
1×××: Cannot be set
0001: AN0 and AN1
1×××: Cannot be set
0010: AN0 to AN2
1×××: Cannot be set
0011: AN0 to AN3
1×××: Cannot be set
0100: AN0 to AN4
1×××: Cannot be set
0101: AN0 to AN5
1×××: Cannot be set
0110: AN0 to AN6
1×××: Cannot be set
0111: AN0 to AN7
1×××: Cannot be set
Legend: ×: Don’t care.
Note: * Only 0 can be written in bit 7, to clear the flag.
Rev. 5.00 Aug 02, 2006 page 667 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion start by an external trigger input.
It also sets the A/D converter operating mode and the A/D conversion time.
Bit
Bit Name
Initial Value
R/W
Description
7
TRGS1
0
R/W
Timer Trigger Select 1 and 0
6
TRGS0
0
R/W
These bits select enabling or disabling of the start
of A/D conversion by a trigger signal.
00: A/D conversion start by external trigger is
disabled
01: A/D conversion start by external trigger (TPU)
is enabled
10: A/D conversion start by external trigger (TMR)
is enabled
11: A/D conversion start by external trigger pin
(ADTRG) is enabled
5
SCANE
0
R/W
Scan Mode
4
SCANS
0
R/W
Selects single mode or scan mode as the A/D
conversion operating mode.
0×: Single mode
10: Scan mode. A/D conversion is performed
continuously for channels 1 to 4
11: Scan mode. A/D conversion is performed
continuously for channels 1 to 8.
3
CKS1
0
R/W
Clock Select 1 to 0
2
CKS0
0
R/W
Sets the A/D conversion time.
Only set bits CKS1 and CKS0 while conversion is
stopped (ADST = 0).
00: A/D conversion time = 530 states (max)
01: A/D conversion time = 266 states (max)
10: A/D conversion time = 134 states (max)
11: A/D conversion time = 68 states (max)
1
—
0
—
Reserved
0
—
0
—
These bits are always read as 0 and cannot be
modified.
Legend: ×: Don’t care.
Rev. 5.00 Aug 02, 2006 page 668 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
16.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software
or external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters wait state.
16.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software, TPU or external trigger input, A/D
conversion starts on the first channel in the group.
The consecutive A/D conversion on maximum four channels (SCANE and SCANS = 10) or on
maximum eight channels (SCANE and SCANS = 11) can be selected. When the consecutive
A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when
CH3 = 1 and CH2 = 1, AN4 when CH3 and CH2 = 01, or AN12 when CH3 and CH2 = 11.
When the consecutive A/D conversion is performed on the eight channels, the A/D conversion
starts on AN0 when CH3 = 0.
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the corresponding A/D data register to each channel.
Rev. 5.00 Aug 02, 2006 page 669 of 980
REJ09B0050-0500
Section 16 A/D Converter
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
4. The ADST bit is not cleared automatically, and steps [2] and [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
16.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (tD) passes after the ADST bit is set to 1, then starts
conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (tCONV) includes tD and the input sampling
time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The
total conversion time therefore varies within the ranges indicated in tables 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. The values given
in table 16.4 apply to the second and subsequent conversions.
Rev. 5.00 Aug 02, 2006 page 670 of 980
REJ09B0050-0500
Section 16 A/D Converter
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
Legend:
(1):
ADCSR write cycle
(2):
ADCSR address
tD:
A/D conversion start delay time
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 16.2 A/D Conversion Timing
Rev. 5.00 Aug 02, 2006 page 671 of 980
REJ09B0050-0500
Section 16 A/D Converter
Table 16.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS1 = 1
CKS0 = 0
CKS0 = 1
CKS0 = 0
CKS0 = 1
Item
Symbol
Min Typ Max
Min Typ Max
Min Typ Max
Min Typ Max
A/D conversion
start delay time
tD
18
—
33
10
—
16
6
—
9
4
—
5
Input sampling
time
tSPL
—
127 —
—
63
—
—
31
—
—
15
—
A/D conversion
time
tCONV
515 —
266
131 —
134
67
—
68
530
259 —
Note: Values in the table are the number of states.
Table 16.4 A/D Conversion Time (Scan Mode)
CKS1
CKS0
Conversion Time (State)
0
0
512 (Fixed)
1
256 (Fixed)
0
128 (Fixed)
1
64 (Fixed)
1
Rev. 5.00 Aug 02, 2006 page 672 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the
timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
16.5
Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to
1 after A/D conversion is completed. The DTC or DMAC can be activated by an ADI interrupt.
Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables
continuous conversion to be achieved without imposing a load on software.
Table 16.5 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
DMAC Activation
ADI
End of conversion
ADF
Possible
Possible
Rev. 5.00 Aug 02, 2006 page 673 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.6
A/D Conversion Precision Definitions
This LSI’s A/D conversion precision definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 16.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 16.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error
(see figure 16.5).
• Absolute precision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Rev. 5.00 Aug 02, 2006 page 674 of 980
REJ09B0050-0500
Section 16 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 16.4 A/D Conversion Precision Definitions
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 16.5 A/D Conversion Precision Definitions
Rev. 5.00 Aug 02, 2006 page 675 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.7
Usage Notes
16.7.1
Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing module stop mode. For details, refer to section 22, Power-Down Modes.
16.7.2
Permissible Signal Source Impedance
This LSI’s analog input is designed so that conversion precision is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee the A/D conversion precision. However, if a large capacitance is provided
externally for conversion in single mode, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see figure 16.6). When converting a high-speed
analog signal or conversion in scan mode, a low-impedance buffer should be inserted.
This LSI
Equivalent circuit of A/D converter
Sensor output
impedance
10 kΩ
Up to 10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Figure 16.6 Example of Analog Input Circuit
Rev. 5.00 Aug 02, 2006 page 676 of 980
REJ09B0050-0500
20 pF
Section 16 A/D Converter
16.7.3
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
16.7.4
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ AVn ≤ Vref.
• Relation between AVcc, AVss and Vcc, Vss
As the relationship between AVcc, AVss and Vcc, Vss, set AVcc ≥ Vcc and AVss = Vss. If
the A/D converter is not used, the AVcc and AVss pins must not be left open.
• Vref setting range
The reference voltage at the Vref pin should be set in the range Vref ≤ AVcc.
16.7.5
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7, AN12, AN13),
analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground
(AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital
ground (Vss) on the board.
Rev. 5.00 Aug 02, 2006 page 677 of 980
REJ09B0050-0500
Section 16 A/D Converter
16.7.6
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7, AN12, AN13) should be connected between AVcc
and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the filter
capacitor connected to AN0 to AN15 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7, AN12,
AN13) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore
required when deciding the circuit constants.
AVCC
Vref
100 Ω
Rin* 2
*1
AN0 to AN7, AN12, AN13
*1
0.1 µF
AVSS
Notes:
Values are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 16.7 Example of Analog Input Protection Circuit
Rev. 5.00 Aug 02, 2006 page 678 of 980
REJ09B0050-0500
Section 16 A/D Converter
Table 16.6 Analog Pin Specifications
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
Permissible signal source impedance
—
5
kΩ
Rev. 5.00 Aug 02, 2006 page 679 of 980
REJ09B0050-0500
Section 16 A/D Converter
Rev. 5.00 Aug 02, 2006 page 680 of 980
REJ09B0050-0500
Section 17 D/A Converter
Section 17 D/A Converter
17.1
Features
D/A converter features are listed below.
• 8-bit resolution
• Two output channels
• Maximum conversion time of 10 µs (with 20 pF load)
• Output voltage of 0 V to Vref
• D/A output hold function in software standby mode
• Setting the module stop mode
DAC0004A_000020020100
Rev. 5.00 Aug 02, 2006 page 681 of 980
REJ09B0050-0500
Section 17 D/A Converter
Internal data bus
Bus interface
Module data bus
Vref
D/A
DADR3
8-bit
DA2
DADR2
DA3
DACR23
AVCC
AVSS
Control circuit
Legend:
DADR2: D/A data register 2
DADR3: D/A data register 3
DADR4: D/A data register 4
DACR23: D/A control register 23
Figure 17.1 Block Diagram of D/A Converter
Rev. 5.00 Aug 02, 2006 page 682 of 980
REJ09B0050-0500
Section 17 D/A Converter
17.2
Input/Output Pins
Table 17.1 summarizes the input and output pins of the D/A converter.
Table 17.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power pin
AVCC
Input
Analog power
Analog ground pin
AVSS
Input
Analog ground
Reference voltage pin
Vref
Input
Reference voltage of D/A converter
Analog output pin 2
DA2
Output
Channel 2 analog output
Analog output pin 3
DA3
Output
Channel 3 analog output
17.3
Register Descriptions
The D/A converter has the following registers.
• D/A data register 2 (DADR2)
• D/A data register 3 (DADR3)
• D/A control register 01 (DACR01)
• D/A control register 23 (DACR23)
17.3.1
D/A Data Registers 2 and 3 (DADR2 and DADR3)
DADR2 and DADR3 are 8-bit readable/writable registers that store data for conversion.
Whenever output is enabled, the values in DADR are converted and output to the analog output
pins.
Rev. 5.00 Aug 02, 2006 page 683 of 980
REJ09B0050-0500
Section 17 D/A Converter
17.3.2
D/A Control Register 23 (DACR23)
DACR23 control the operation of the D/A converter.
Bit
Bit Name
Initial Value
R/W
Description
7
DAOE3
0
R/W
D/A Output Enable 3
Controls D/A conversion and analog output.
0: Analog output (DA3) is disabled
1: Channel 3 D/A conversion is enabled; analog
output (DA3) is enabled
6
DAOE2
0
R/W
D/A Output Enable 2
Controls D/A conversion and analog output.
0: Analog output (DA2) is disabled
1: Channel 2 D/A conversion is enabled; analog
output (DA2) is enabled
5
DAE
0
R/W
D/A Enable
Used together with the DAOE0 and DAOE1 bits to
control D/A conversion. When the DAE bit is
cleared to 0, channel 2 and 3 D/A conversions are
controlled independently. When the DAE bit is set
to 1, channel 2 and 3 D/A conversions are
controlled together.
Output of conversion results is always controlled
independently by the DAOE0 and DAOE1 bits.
For details, see table 17.2.
4
to
0
—
1
—
Rev. 5.00 Aug 02, 2006 page 684 of 980
REJ09B0050-0500
Reserved
These bits are always read as 1 and cannot be
modified.
Section 17 D/A Converter
Table 17.2 Control of D/A Conversion
Bit 5
DAE
Bit 7
DAOE3
Bit 6
DAOE2
Description
0
0
0
D/A conversion disabled
1
Channel 2 D/A conversion enabled, channel3 D/A conversion
disabled
0
Channel 3 D/A conversion enabled, channel2 D/A conversion
disabled
1
Channel 2 and 3 D/A conversions enabled
0
D/A conversion disabled
1
Channel 2 and 3 D/A conversions enabled
1
1
0
1
0
1
17.4
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate
independently.
When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the conversion result is
output.
The operation example concerns D/A conversion on channel 2. Figure 17.2 shows the timing of
this operation.
[1] Write the conversion data to DADR2.
[2] Set the DAOE0 bit in DACR23 to 1. D/A conversion is started. The conversion result is output
from the analog output pin DA2 after the conversion time tDCONV has elapsed. The conversion
result is continued to output until DADR0 is written to again or the DAOE0 bit is cleared to 0.
The output value is expressed by the following formula:
DADRcontents × Vref
256
[3] If DADR2 is written to again, the conversion is immediately started. The conversion result is
output after the conversion time tDCONV has elapsed.
[4] If the DAOE0 bit is cleared to 0, analog output is disabled.
Rev. 5.00 Aug 02, 2006 page 685 of 980
REJ09B0050-0500
Section 17 D/A Converter
DADR2
write cycle
DADR2
write cycle
DACR23
write cycle
DACR23
write cycle
φ
Address
DADR2
Conversion data 1
Conversion data 2
DAOE0
DA2
Conversion
result 2
Conversion
result 1
High-impedance state
tDCONV
tDCONV
Legend:
tDCONV: D/A conversion time
Figure 17.2 Example of D/A Converter Operation
17.5
17.5.1
Usage Notes
Setting for Module Stop Mode
It is possible to enable/disable the D/A converter operation using the module stop control register,
the D/A converter does not operate by the initial value of the register. The register can be accessed
by releasing the module stop mode. For details, see section 22, Power-Down Modes.
17.5.2
D/A Output Hold Function in Software Standby Mode
If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and
analog power supply current remains at the same level during D/A conversion. When the analog
power supply current is required to go low in software standby mode, bits DAOE2, DAOE3 and
DAE should be cleared to 0, and D/A output should be disabled.
Rev. 5.00 Aug 02, 2006 page 686 of 980
REJ09B0050-0500
Section 18 RAM
Section 18 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2,
System Control Register (SYSCR).
ROM Type
RAM
Capacitance
RAM Address
Flash memory version
32 kbytes
H'FF4000 to H'FFBFFF
HD64F2367
24 kbytes
H'FF6000 to H'FFBFFF
HD64F2364
32 kbytes
H'FF4000 to H'FFBFFF
HD64F2361
24 kbytes
H'FF6000 to H'FFBFFF
HD64F2360
16 kbytes
H'FF8000 to H'FFBFFF
Product Type Name
H8S/2368F
HD64F2368
HD64F2362
HD6432365
Masked ROM version
HD6412363
ROMless version
Rev. 5.00 Aug 02, 2006 page 687 of 980
REJ09B0050-0500
Section 18 RAM
Rev. 5.00 Aug 02, 2006 page 688 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
The features of the flash memory included in the flash memory version are summarized below.
The block diagram of the flash memory is shown in figure 19.1.
19.1
Features
• Size
Product Classification
ROM Size
ROM Address
H8S/2368 Group
384 kbytes
H'000000 to H'05FFFF (Modes 3, 4, and 7)
HD64F2367
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory of 384 kbytes is configured as follows: 64 kbytes × 5 blocks, 32
kbytes × 1 block, and 4 kbytes × 8 blocks. To erase the entire flash memory, each block must
be erased in turn.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• Two on-board programming modes
Boot mode
User program mode
On-board programming/erasing can be done in boot mode in which the on-chip boot program
is started for erase or programming of the entire flash memory. In normal user program mode,
individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
• Automatic bit rate adjustment
With data transfer in boot mode, the bit rate of this LSI can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase operations.
Rev. 5.00 Aug 02, 2006 page 689 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
Bus interface/controller
EBR1
Operating
mode
EBR2
SYSCR
Flash memory
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
SYSCR:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
System control register
Figure 19.1
Block Diagram of Flash Memory
Rev. 5.00 Aug 02, 2006 page 690 of 980
REJ09B0050-0500
Mode pins
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.2
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an
operating mode as shown in figure 19.2. In user mode, flash memory can be read but not
programmed or erased.
The boot, user program and programmer modes are provided as modes to write and erase the flash
memory.
The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3
shows boot mode. Figure 19.4 shows user program mode.
=0
=
ES
R
SWE = 0
SWE = 1
User
program mode
RES = 0
RES
0
User mode
(on-chip ROM
enabled)
Reset state
=1
MD0 = 1, MD1 = 1, MD2 = 0
MD2
RES = 0
MD0 = 0, MD1 = 0,
MD2 = 0, P50 = 0,
P51 = 0, P52 = 1
Programmer
mode
Boot mode
On-board programming mode
Note:
Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
Figure 19.2 Flash Memory State Transitions
Rev. 5.00 Aug 02, 2006 page 691 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Table 19.1 Differences between Boot Mode and User Program Mode
Boot Mode
User Program Mode
Total erase
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify Erase/erase-verify/program/
program-verify
Note:
*
To be provided by the user, in accordance with the recommended algorithm.
Rev. 5.00 Aug 02, 2006 page 692 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started and the programming control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host
Host
Programming control
program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
Host
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
prewrite-erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Figure 19.3 Boot Mode
Rev. 5.00 Aug 02, 2006 page 693 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
1. Initial state
(1) the program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes the transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
Transfer program
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
RAM
Transfer program
Transfer program
Programming/
erase control program
Flash memory
erase
Programming/
erase control program
New application
program
Program execution state
Figure 19.4 User Program Mode
Rev. 5.00 Aug 02, 2006 page 694 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.3
Block Configuration
Figure 19.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The 384kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8
blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units
starting from an address whose lower eight bits are H'00 or H'80.
Rev. 5.00 Aug 02, 2006 page 695 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
EB0
Erase unit
4 kbytes
H'000000
H'000001
H'000002
Programming unit: 128 bytes
EB1
Erase unit
4 kbytes
H'001000
H'001001
H'001002
Programming unit: 128 bytes
H'00007F
H'000FFF
H'00107F
H'001FFF
EB2
Erase unit
4 kbytes
H'002000
H'002001
H'002002
Programming unit: 128 bytes
EB3
Erase unit
4 kbytes
H'003000
H'003001
H'003002
Programming unit: 128 bytes
H'00407F
H'00707F
H'00207F
H'002FFF
H'00307F
H'003FFF
EB4
Erase unit
4 kbytes
H'004000
H'004001
H'004002
Programming unit: 128 bytes
EB7
Erase unit
4 kbytes
H'007000
H'007001
H'007002
Programming unit: 128 bytes
EB8
Erase unit
32 kbytes
H'008000
H'008001
H'008002
Programming unit: 128 bytes
EB9
Erase unit
64 kbytes
H'010000
H'010001
H'010002
Programming unit: 128 bytes
EB10
Erase unit
64 kbytes
H'020000
EB11
Erase unit
64 kbytes
H'030000
H'030001
H'030002
Programming unit: 128 bytes
H'03007F
EB12
Erase unit
64 kbytes
H'040000
H'040001
H'040002
Programming unit: 128 bytes
H'04007F
EB13
Erase unit
64 kbytes
H'050000
H'007FFF
H'00807F
H'00FFFF
H'01007F
H'01FFFF
H'020001
H'020002
Programming unit: 128 bytes
H'02007F
H'02FFFF
H'03FFFF
H'04FFFF
H'050001
H'050002
Programming unit: 128 bytes
H'05007F
H'05FFFF
Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)
Rev. 5.00 Aug 02, 2006 page 696 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuration
Pin Name
I/O
Function
RES
Input
Reset
MD2
Input
Sets this LSI’s operating mode
MD1
Input
Sets this LSI’s operating mode
MD0
Input
Sets this LSI’s operating mode
P52
Input
Sets operating mode in programmer mode
P51
Input
Sets operating mode in programmer mode
P50
Input
Sets operating mode in programmer mode
TxD1
Output
Serial transmit data output
RxD1
Input
Serial receive data input
19.5
Register Descriptions
The flash memory has the following registers. For details on the system control register, refer to
section 3.2.2, System Control Register (SYSCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
Rev. 5.00 Aug 02, 2006 page 697 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory transit to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8,
Flash Memory Programming/Erasing.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0/1
R
This bit is reserved. This bit is always read as 0 in
modes 1 and 2. This bit is always read as 1 in
modes 3 to 7.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all
EBR1 and EBR2 bits cannot be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it is
cleared to 0, the erase setup state is cancelled.
4
PSU
0
R/W
Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When
it is cleared to 0, the program setup state is
cancelled.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to erase-verify mode. When it is
cleared to 0, erase-verify mode is cancelled.
2
PV
0
R/W
Program-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to program-verify mode. When it is
cleared to 0, program-verify mode is cancelled.
1
E
0
R/W
Erase
When this bit is set to 1 while SWE = 1, and ESU =
1, the flash memory transits to erase mode. When it
is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program
When this bit is set to 1 while SWE = 1, and PSU =
1, the flash memory transits to program mode.
When it is cleared to 0, program mode is cancelled.
Rev. 5.00 Aug 02, 2006 page 698 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. When the
SWE bit in FLMCR1 is cleared to 0, FLMCR2 is initialized to H'00. FLMCR2 is a read-only
register, and should not be written to.
Bit
Bit Name
Initial Value
R/W
Description
7
FLER
0
R
Indicates that an error has occurred during an
operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory
goes to the error-protection state.
See section 19.9.3, Error Protection, for details.
6
to
0
—
0
R
Reserved
These bits always read 0.
Rev. 5.00 Aug 02, 2006 page 699 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.5.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the
same time. Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). For
details, see table 19.3.
Bit
Bit Name
Initial Value
R/W
Description
7
EB7
0
R/W
When this bit is set to 1, 4 kbytes of EB7 are to be
erased.
6
EB6
0
R/W
When this bit is set to 1, 4 kbytes of EB6 are to be
erased.
5
EB5
0
R/W
When this bit is set to 1, 4 kbytes of EB5 are to be
erased.
4
EB4
0
R/W
When this bit is set to 1, 4 kbytes of EB4 are to be
erased.
3
EB3
0
R/W
When this bit is set to 1, 4 kbytes of EB3 are to be
erased.
2
EB2
0
R/W
When this bit is set to 1, 4 kbytes of EB2 are to be
erased.
1
EB1
0
R/W
When this bit is set to 1, 4 kbytes of EB1 are to be
erased.
0
EB0
0
R/W
When this bit is set to 1, 4 kbytes of EB0 are to be
erased.
19.5.4
Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the
same time. Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). For
details, see table 19.3.
Rev. 5.00 Aug 02, 2006 page 700 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
0
R/W
Reserved
5
EB13
0
R/W
When this bit is set to 1, 64 kbytes of EB13 are to
be erased.
4
EB12
0
R/W
When this bit is set to 1, 64 kbytes of EB12 are to
be erased.
3
EB11
0
R/W
When this bit is set to 1, 64 kbytes of EB11 are to
be erased.
2
EB10
0
R/W
When this bit is set to 1, 64 kbytes of EB10 are to
be erased.
1
EB9
0
R/W
When this bit is set to 1, 64 kbytes of EB9 are to
be erased.
0
EB8
0
R/W
When this bit is set to 1, 32 kbytes of EB8 are to
be erased.
The initial value should not be changed.
Table 19.3 Erase Blocks
Address
Block (Size)
Modes 3, 4, and 7
EB0 (4 kbytes)
H'000000 to H'000FFF
EB1 (4 kbytes)
H'001000 to H'001FFF
EB2 (4 kbytes)
H'002000 to H'002FFF
EB3 (4 kbytes)
H'003000 to H'003FFF
EB4 (4 kbytes)
H'004000 to H'004FFF
EB5 (4 kbytes)
H'005000 to H'005FFF
EB6 (4 kbytes)
H'006000 to H'006FFF
EB7 (4 kbytes)
H'007000 to H'007FFF
EB8 (32 kbytes)
H'008000 to H'00FFFF
EB9 (64 kbytes)
H'010000 to H'01FFFF
EB10 (64 kbytes)
H'020000 to H'02FFFF
EB11 (64 kbytes)
H'030000 to H'03FFFF
EB12 (64 kbytes)
H'040000 to H'04FFFF
EB13 (64 kbytes)
H'050000 to H'05FFFF
Rev. 5.00 Aug 02, 2006 page 701 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.6
On-Board Programming Modes
In an on-board programming mode, programming, erasing, and verification for the on-chip flash
memory can be performed. There are two on-board programming modes: boot mode and user
program mode. Table 19.4 shows how to select boot mode. User program mode can be selected by
setting the control bits by software. For a diagram that shows mode transitions of flash memory,
see figure 19.2.
Table 19.4 Setting On-Board Programming Mode
Mode Setting
Boot mode
19.6.1
Single-chip activation expanded mode
with on-chip ROM enabled
MD2
MD1
MD0
0
1
1
Boot Mode
When this LSI enters boot mode, the embedded boot program is started. The boot program
transfers the programming control program from the externally connected host to the on-chip
RAM via the SCI_1. When the flash memory is all erased, the programming control program is
executed.
Table 19.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip
measures the low-level period of asynchronous SCI communication data (H'00) transmitted
continuously from the host. The chip then calculates the bit rate of transmission from the host,
and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop
bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should
be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states
before the chip is ready to measure the low-level period.
2. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the end of
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to the chip. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 19.6.
Rev. 5.00 Aug 02, 2006 page 702 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
3. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 19.8, Flash Memory Programming/Erasing.
4. Before branching to the programming control program, the chip terminates transfer operations
by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of program data or verify data with the host. The TxD pin is high. The contents of the CPU
general registers are undefined immediately after branching to the programming control
program. These registers must be initialized at the beginning of the programming control
program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
5.
In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are
erased. Boot mode is used for the initial programming in the on-board state or for a forcible
return when a program that is to be initiated in user program mode was accidentally erased
and could not be executed in user program mode.
Notes: 1. In boot mode, a part of the on-chip RAM area (H'FF8000 to H'FF87FF) is used by the
boot program. Addresses H'FF8800 to H'FFBFFF is the area to which the
programming control program is transferred from the host. The boot program area
cannot be used until the execution state in boot mode switches to the programming
control program.
2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after
waiting at least 20 states since driving the reset pin low. Boot mode is also cleared
when the WDT overflow reset occurs.
3. Do not change the MD pin input levels in boot mode.
4. All interrupts are disabled during programming or erasing of the flash memory.
Rev. 5.00 Aug 02, 2006 page 703 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Host Operation
Communication Contents
Processing Contents
Bit rate adjustment
Boot mode initiation
Item
Table 19.5 Boot Mode Operation
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Continuously transmits data H'00
at specified bit rate.
H'00, H'00 . . . H'00
H'00
Transmits data H'55 when data H'00
is received error-free.
• Measures low-level period of receive data H'00.
• Calculates bit rate and sets BRR in SCI_1.
• Transmits data H'00 to host as adjustment end
indication.
H'55
H'AA
Transmits data H'AA to host when data H'55 is
received.
Flash memory erase
Transfer of number of bytes of
programming control program
H'AA reception.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte).
Upper bytes, lower bytes
Transmits 1-byte of programming
control program (repeated for N times).
Boot program
erase error
H'AA reception.
Echoback
H'XX
Echoback
H'FF
H'AA
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Rev. 5.00 Aug 02, 2006 page 704 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
19,200 bps
8 to 25 MHz
9,600 bps
8 to 25 MHz
19.6.2
User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the program/erase program or a program which provides the program/erase program from
external memory. Because the flash memory itself cannot be read during programming/erasing,
transfer the program/erase program to on-chip RAM, as like in boot mode. Figure 19.6 shows a
sample procedure for programming/erasing in user program mode. Prepare a program/erase
program in accordance with the description in section 19.7, Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory programming)
Branch to flash memory application
program
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode
Rev. 5.00 Aug 02, 2006 page 705 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.7
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory
operates in one of the following four modes: program mode, erase mode, program-verify mode,
and erase-verify mode. The programming control program in boot mode and the user
program/erase program in user mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 19.7.1, Program/Program-Verify and section 19.7.2,
Erase/Erase-Verify, respectively.
19.7.1
Program/Program-Verify
When programming data or programs to the flash memory, the program/program-verify flowchart
shown in figure 19.7 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be programmed to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if programming fewer than 128 bytes. In this case, H'FF data must be written
to the extra addresses.
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 19.7.
4. Consecutively transfer 128 bytes of data in byte units from the programming data area,
reprogramming data area, or additional-programming data area to the flash memory. The
program address and 128-byte data are latched in the flash memory. The lower 8 bits of the
start address in the flash memory destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 19.7 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (y + z2 + α + β) µs as the WDT overflow period.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
Rev. 5.00 Aug 02, 2006 page 706 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
8. The maximum number of repetitions of the program/program-verify sequence to the same bit
(N) must not be exceeded.
Write pulse application subroutine
Start of programming
Write pulse application
Start
Enable WDT
Set SWE bit in FLMCR1
Wait (x) µs
*6
Store 128-byte program data in program
data area and reprogram data area
*4
Set PSU bit in FLMCR1
Wait (y) µs
*6
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Set P bit in FLMCR1
n=1
Wait (z1) µs or (z2) ms or (z3) µs
*5 *6
m=0
Clear P bit in FLMCR1
Write 128-byte data in RAM reprogram *1
data area consecutively to flash memory
Wait (α) µs
Sub-routine-call
Clear PSU bit in FLMCR1
Wait (β) µs
Write pulse application
(z1) µs or (z2) µs
Disable WDT
Set PV bit in FLMCR1
See Note 7 for pulse width
Wait (γ) µs
End sub
*6
H'FF dummy write to verify address
Note 7: Write Pulse Width
Write Time (z) µs
Number of Writes (n)
z1
1
z1
2
z1
3
z1
4
z1
5
z1
6
z2
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
13
.
.
.
.
.
.
z2
998
z2
999
z2
1000
Wait (ε) µs
Increment address
Read verify data
NG
Write data = verify
data?
OK
6≥n?
n←n+1
*2
m=1
NG
OK
Additional program data computation
Note: Use a z3 µs write pulse for additional
programming.
Transfer additional program data to
additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram
data area
*4
NG
RAM
Program data storage
area (128 bytes)
128-byte
data verification
completed?
OK
Clear PV bit in FLMCR1
Wait (η) µs
Reprogram data storage
area (128 bytes)
6≥n?
*6
NG
OK
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Subroutine-call
Write pulse application
(z3) µs
*6
(additional programming)
Additional program data
storage area (128 bytes)
m = 0?
NG
n ≥ (N)?
End of programming
NG
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
OK
OK
*6
Wait (θ) µs
*6
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison between stored data in the program data area and verify data).
Programming is executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for which programming has been completed will
be subjected to additional programming if they fail the subsequent verify operation.
4. A 128-byte areas for storing program data, reprogram data, and additional program data must be provided in the RAM. The contents of the
reprogram and additional program data are modified as programming proceeds.
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the programming operation. See Note *7 for the pulse widths.
When writing of additional-programming data is executed, a (z3) µs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 24.3, Flash Memory Characteristics.
Program Data Operation Chart
Original Data (D)
0
1
Verify Data (V)
0
1
0
1
Reprogram Data (X)
1
0
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional Program Data Operation Chart
Reprogram Data (X')
0
1
Verify Data (V)
0
1
0
1
Additional Program Data (Y)
Comments
0
Additional programming executed
1
Additional programming not executed
Additional programming not executed
Additional programming not executed
Figure 19.7 Program/Program-Verify Flowchart
Rev. 5.00 Aug 02, 2006 page 707 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.7.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.8 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a
value greater than (y + z + α + β) ms as the WDT overflow period.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is not erased, set erase mode again, and repeat the erase/erase-verify sequence
as before. The maximum number of repetitions of the erase/erase-verify sequence (N) must
not be exceeded.
19.7.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased, and while the boot program is executing in boot mode. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. If the interrupt exception handling is started when the vector address has not been programmed
yet or the flash memory is being programmed or erased, the vector would not be read correctly,
possibly resulting in CPU runaway.
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Rev. 5.00 Aug 02, 2006 page 708 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Start
*1
Set SWE bit in FLMCR1
Wait (x) µs
*2
n=1
Set EBR1, EBR2
*4
Enable WDT
Set ESU bit in FLMCR1
Wait (y) µs
*2
Start of erase
Set E bit in FLMCR1
Wait (z) µs
*2
Clear E bit in FLMCR1
n←n+1
Halt erase
Wait (α) µs
*2
Clear ESU bit in FLMCR1
Wait (β) µs
*2
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
*2
Set block start address to verify address
H'FF dummy write to verify address
Increment
address
Wait (ε) µs
*2
Read verify data
*3
Verify data = all 1?
NG
OK
NG
Last address of block?
OK
Clear EV bit in FLMCR1
Clear EV bit in FLMCR1
Wait (η) µs
Wait (η) µs
*2
*2
NG
*5
*2
End of
erasing of all erase
blocks?
OK
n ≥ N?
OK
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
Wait (θ) µs
End of erasing
Notes: 1.
2.
3.
4.
5.
NG
*2
Wait (θ) µs
*2
Erase failure
Prewriting (setting erase block data to all 0) is not necessary.
The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 24.3, Flash Memory Characteristics.
Verify data is read in 16-bit (W) units.
Set only one bit in EBR1or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 19.8 Erase/Erase-Verify Flowchart
Rev. 5.00 Aug 02, 2006 page 709 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.8
Program/Erase Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
19.8.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or
standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a
reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation
stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the
RES pulse width specified in the AC Characteristics section.
19.8.2
Software Protection
Protection can be implemented against programming/erasing of all flash memory blocks by
clearing the SWE bit in FLMCR1 to 0. When protection is in effect, setting the P or E bit in
FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 (EBR1) and erase block register 2 (EBR2), erase protection can be set for individual
blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
19.8.3
Error Protection
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• When an exception handling (excluding a reset) is started during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU releases the bus during programming/erasing
Rev. 5.00 Aug 02, 2006 page 710 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode
cannot be re-entered by re-setting the P or E bit. However, since PV and EV bit setting is enabled,
and a transition can be made to verify mode. The error protection state can be canceled by a reset
or in hardware standby mode.
19.9
Programmer Mode
In programmer mode, a PROM programmer can perform programming/erasing via a socket
adapter, just like for a discrete flash memory. Use a PROM programmer which supports the
Renesas 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12-MHz input
clock is needed.
19.10
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read.
• Standby mode
All flash memory circuits are halted.
Table 19.7 shows the correspondence between the operating modes of this LSI and the flash
memory. When the flash memory returns to normal operation from a standby state, a power
supply circuit stabilization period is needed. When the flash memory returns to its normal
operating state, bits STS3 to STS0 in SBYCR must be set to provide a wait time of at least 100 µs,
even when the external clock is being used.
Table 19.7 Flash Memory Operating States
Operating Mode
Flash Memory Operating State
Active mode
Normal operating state
Sleep mode
Normal operating state
Standby mode
Standby state
Rev. 5.00 Aug 02, 2006 page 711 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
19.11
Usage Notes
Precautions concerning the use of on-board programming mode, and programmer mode are
summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip
flash memory (FZTAT512V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter.
2. Reset the flash memory before turning on/off the power.
When applying or disconnecting Vcc power, fix the RES pin low and place the flash memory
in the hardware protection state. The power-on and power-off timing requirements should also
be satisfied in the event of a power failure and subsequent recovery.
3. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
4. Do not set or clear the SWE bit during execution of a program in flash memory.
Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data
in flash memory.
When the SWE bit is set, data in flash memory can be rewritten. When the SWE bit is set to 1,
data in flash memory can be read only in program-verify/erase-verify mode. Access flash
memory only for verify operations (verification during programming/erasing). Also, do not
clear the SWE bit during programming, erasing, or verifying.
5. Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled during programming/erasing the
flash memory to give priority to program/erase operations.
6. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte
programming unit block. In programmer mode, too, perform only one programming operation
on a 128-byte programming unit block. Programming should be carried out with the entire
programming unit block erased.
7. Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
Rev. 5.00 Aug 02, 2006 page 712 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
8. Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
9. Apply the reset signal after the SWE, bit is cleared during its operation.
The reset signal is applied at least 100 µs after the SWE bit has been cleared.
Rev. 5.00 Aug 02, 2006 page 713 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Wait time: x
Programming/
erasing
possible Wait time: 100 µs
φ
Min 0 µs
tOSC1
VCC
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
(1) Boot Mode
Wait time: x
Programming/
erasing
possible Wait time: 100 µs
φ
Min 0 µs
tOSC1
VCC
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
(2) User Program Mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
2. See section 24.3, Flash Memory Characteristics.
3. Mode programming setup time tMDS (min) = 200 ns
Figure 19.9 Power-On/Off Timing
Rev. 5.00 Aug 02, 2006 page 714 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Wait time: x
Wait time: x
Programming/erasing Programming/erasing
possible
possible
*4
Wait time: x
Programming/erasing
possible
*4
Wait time: x
Programming/erasing
possible
*4
*4
φ
tOSC1
VCC
2
tMDS*
MD2 to MD0
tMDS
tRESW
RES
SWE bit
SWE
set
Mode
change*1
SWE
cleared
Boot
mode
Mode
change*1
User
mode
User
User
program mode
mode
User
program
mode
User mode
User
program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be
carried out by means of RES input. The state of ports with multiplexed address functions and bus control output
pins (AS, RD, HWR, LWR) will change during this switchover interval (the interval during which the RES pin
input is low), and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200
ns is necessary with respect to RES clearance timing.
3. See section 24.3, Flash Memory Characteristics.
4. Wait time: 100 µs
Figure 19.0 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
Rev. 5.00 Aug 02, 2006 page 715 of 980
REJ09B0050-0500
Section 19 Flash Memory (0.35-µm F-ZTAT Version)
Rev. 5.00 Aug 02, 2006 page 716 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
The flash memory has the following features. Figure 20.1 shows a block diagram of the flash
memory.
20.1
Features
• Size
Product Classification
ROM Size
ROM Address
H8S/2368F
HD64F2368
512 kbytes
H'000000 to H'07FFFF
(Modes 3 to 5 and 7)
H8S/2364F
HD64F2364
384 kbytes
H'000000 to H'05FFFF
(Modes 3 to 5 and 7)
H8S/2362F
HD64F2362
256 kbytes
H8S/2361F
HD64F2361
H'000000 to H'03FFFF
(Modes 3 to 5 and 7)
H8S/2360F
HD64F2360
• Two flash-memory MATs according to LSI initiation mode
The on-chip flash memory has two memory spaces in the same address space (hereafter
referred to as memory MATs). The mode setting in the initiation determines which memory
MAT is initiated first. The MAT can be switched by using the bank-switching method after
initiation.
The user memory MAT is initiated at a power-on reset in user mode: 512 kbytes
(H8S/2368F), 384 kbytes (H8S/2364F), 256 kbytes (H8S/2362F, H8S/2361F, H8S/2360F)
The user boot memory MAT is initiated at a power-on reset in user boot mode: 8 kbytes
• Programming/erasing interface by the download of on-chip program
This LSI has a dedicated programming/erasing program. After downloading this program to
the on-chip RAM, programming/erasing can be performed by setting the argument parameter.
The user branch is also supported.
• Programming/erasing time
The flash memory programming time is 1 ms (typ) in 128-byte simultaneous programming and
8 µs per byte. The erasing time is 750 ms (typ) per 64-kbyte block.
• Number of programming
The number of flash memory programming can be up to 100 times.
Rev. 5.00 Aug 02, 2006 page 717 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
• Three on-board programming modes and one off-board programming mode
Boot mode
This mode is a program mode that uses an on-chip SCI interface. The user MAT and user
boot MAT can be programmed. This mode can automatically adjust the bit rate between
host and this LSI.
User program mode
The user MAT can be programmed by using the optional interface.
User boot mode
The user boot program of the optional interface can be made and the user MAT can be
programmed.
• One off-board programming mode
PROM mode
This mode uses the PROM programmer. The user MAT and user boot MAT can be
programmed.
• Protection modes
There are two protection modes: software protection by the register setting and hardware
protection by the FWE pin. The protection state for flash memory programming/erasing can be
set.
Rev. 5.00 Aug 02, 2006 page 718 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Internal address bus
Internal data bus (16 bits)
FCCS
Module bus
FPCS
FECS
FKEY
Memory MAT unit
User MAT: 512 kbytes*
User boot MAT: 8 kbytes
Control unit
FMATS
FTDAR
FVACR
Mode pin
Legend:
FCCS:
FPCS:
FECS:
FKEY:
FMATS:
FTDAR:
FVACR:
Notes:
Flash memory
Operating
mode
Flash code control status register
Flash program code select register
Flash erase code select register
Flash key code register
Flash MAT select register
Flash transfer destination address register
Flash vector address control register
To read from or write to the registers, the FLSHE bit in the system control
register (SYSCR) must be set to 1.
* 384 kbytes, 256 kbytes
Figure 20.1 Block Diagram of Flash Memory
Rev. 5.00 Aug 02, 2006 page 719 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.1.1
Operating Mode
When each mode pin and the FWE pin are set in the reset state and reset start is performed, the
microcomputer enters each operating mode as shown in figure 20.2.
• Flash memory cannot be read, programmed, or erased in ROM invalid mode.
• Flash memory can be read in user mode, but cannot be programmed or erased.
• Flash memory can be read, programmed, or erased on the board only in user program mode,
user boot mode, and boot mode.
• Flash memory can be read, programmed, or erased by means of the PROM programmer in
PROM mode.
RES = 0
ROM invalid
mode
ROM invalid
mode setting
s
de
mo
=0
Us
RE
S
Bo
S
er
g
in
ett
RE
R
=0
PROM mode
PROM mode setting
Reset state
ot g
bo tin
er set
Us de
mo
ES
RES = 0
ot
mo
de
=0
se
ttin
g
FLSHE = 0
User mode
User program
mode
FLSHE = 1
User boot
mode
Boot mode
On-board programming mode
Figure 20.2 Mode Transition of Flash Memory
Rev. 5.00 Aug 02, 2006 page 720 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.1.2
Mode Comparison
The comparison table of programming and erasing related items about boot mode, user program
mode, user boot mode, and PROM mode is shown in table 20.1.
Table 20.1 Comparison of Programming Modes
Boot mode
User program
mode
User boot mode
PROM mode
Programming/
erasing
environment
On-board
programming
On-board
programming
On-board
programming
Off-board
programming
Programming/
erasing enable
MAT
User MAT
User boot MAT
User MAT
User MAT
User MAT
User boot MAT
All erasure
Block division
erasure
(Automatic)
*1
(Automatic)
×
Program data
transfer
From host via
SCI
From optional
device via RAM
Via programmer
User MAT
From optional
device via RAM
2
User boot MAT*
Reset initiation
MAT
Embedded
program storage
MAT
Transition to
user mode
Changing mode
setting and reset
Changing FLSHE
bit
Changing mode
setting and reset
Notes: 1. All-erasure is performed. After that, the specified block can be erased.
2. Firstly, the reset vector is fetched from the embedded program storage MAT. After the
flash memory related registers are checked, the reset vector is fetched from the user
boot MAT.
• The user boot MAT can be programmed or erased only in boot mode and PROM mode.
• The user MAT and user boot MAT are erased in boot mode. Then, the user MAT and user boot
MAT can be programmed by means of the command method. However, the contents of the
MAT cannot be read until this state.
Only user boot MAT is programmed and the user MAT is programmed in user boot mode or
only user MAT is programmed because user boot mode is not used.
• The boot operation of the optional interface can be performed by the mode pin setting different
from user program mode in user boot mode.
Rev. 5.00 Aug 02, 2006 page 721 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.1.3
Flash MAT Configuration
This LSI’s flash memory is configured by the 256-kbyte/384-kbyte/512-kbyte user MAT and 8kbyte user boot MAT.
The start address is allocated to the same address in the user MAT and user boot MAT. Therefore,
when the program execution or data access is performed between two MATs, the MAT must be
switched by using FMATS.
The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However,
the user boot MAT can be programmed only in boot mode and PROM mode.
Address H'000000
<User MAT>
Address H'000000
<User Boot MAT>
8 kbytes
Address H'001FFF
256 kbytes
(384 kbytes/512 kbytes)
Address H'03FFFF
(H'05FFFF/H'07FFFF)
Figure 20.3 Flash Memory Configuration
The size of the user MAT is different from that of the user boot MAT. An address which exceeds
the size of the 8-kbyte user boot MAT should not be accessed. If the attempt is made, data is read
as undefined value.
Rev. 5.00 Aug 02, 2006 page 722 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.1.4
Block Division
The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight
blocks) as shown in figure 20.4. The user MAT can be erased in this divided-block units and the
erase-block number of EB0 to EB15 is specified when erasing.
<User MAT> Erase block
EB0
4 kbytes × 8 to
Address H'000000
256 kbytes
EB7
32 kbytes
EB8
64 kbytes
EB9
64 kbytes
EB10
64 kbytes
EB11
64 kbytes
EB12
64 kbytes
EB13
64 kbytes
EB14
64 kbytes
EB15
Address H'03FFFF
384 kbytes
Address H'05FFFF
512 kbytes
Address H'07FFFF
Figure 20.4 Block Division of User MAT
Rev. 5.00 Aug 02, 2006 page 723 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.1.5
Programming/Erasing Interface
Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and
specifying the program address/data and erase block by using the interface register/parameter.
The procedure program is made by the user in user program mode and user boot mode. An
overview of the procedure is given as follows. For details, see section 20.4.2, User Program Mode.
Start user procedure
program for programming/erasing.
Select on-chip program to be
downloaded and
specify the destination.
Download on-chip program
by setting FKEY and SCO bits.
Initialization execution
(downloaded program execution)
Programming (in 128-byte units)
or erasing (in one-block units)
(downloaded program execution)
Programming/erasing
completed?
No
Yes
End user procedure
program
Figure 20.5 Overview of User Procedure Program
1. Selection of on-chip program to be downloaded
For programming/erasing execution, the FLSHE bit must be set to 1 to transition to user
program mode.
This LSI has programming/erasing programs which can be downloaded to the on-chip RAM.
The on-chip program to be downloaded is selected by setting the corresponding bits in the
programming/erasing interface register. The address of the programming destination is
specified by the FTDAR.
Rev. 5.00 Aug 02, 2006 page 724 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
2. Download of on-chip program
The on-chip program is automatically downloaded by setting the SCO bit in the flash key
register (FKEY) and the flash control register (FCCS) of the programming/erasing interface
register.
The flash memory is replaced to the embedded program storage area when downloading. Since
the flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in the space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameter,
whether the normal download is executed or not can be confirmed.
3. Initialization of programming/erasing
The operating frequency is set before execution of programming/erasing. This setting is
performed by using the programming/erasing interface parameter.
4. Programming/erasing execution
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameter and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction and performing the subroutine call of the specified address in the on-chip RAM.
The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory.
All interrupts are prohibited during programming and erasing. Interrupts must be masked
within the user system.
5. When programming/erasing is executed consecutively
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.
Rev. 5.00 Aug 02, 2006 page 725 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.2
Input/Output Pins
Table 20.2 shows the flash memory pin configuration.
Table 20.2 Pin Configuration
Pin Name
Abbreviation
Input/Output
Function
Reset
RES
Input
Reset
Mode 2
MD2
Input
Sets operating mode of this LSI
Mode 1
MD1
Input
Sets operating mode of this LSI
Mode 0
MD0
Input
Sets operating mode of this LSI
Port 52
P52
Input
Sets operating mode of programmer
mode
Port 51
P51
Input
Sets operating mode of programmer
mode
Port 50
P50
Input
Sets operating mode of programmer
mode
Transmit data
TxD1
Output
Serial transmit data output (used in boot
mode)
Receive data
RxD1
Input
Serial receive data input (used in boot
mode)
Note: For the pin configuration in PROM mode, see section 20.7, Programmer Mode.
20.3
Register Descriptions
The registers/parameters which control flash memory are shown as follows.
• Flash code control status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass and fail result (DPFP)
• Flash pass and fail result (FPFR)
• Flash multipurpose address area (FMPAR)
• Flash multipurpose data destination area (FMPDR)
• Flash erase Block select (FEBS)
Rev. 5.00 Aug 02, 2006 page 726 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
• Flash program and erase frequency control (FPEFEQ)
• Flash vector address control register (FVACR)
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 20.3.
Table 20.3 Register/Parameter and Target Mode
InitialiDownload zation
Programming/erasing
interface register
Read
FCCS
FPCS
FECS
FKEY
FMATS
Programming/erasing
interface parameter
Programming
Erasure
*1
*1
*2
FTDAR
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
Rev. 5.00 Aug 02, 2006 page 727 of 980
REJ09B0050-0500
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
20.3.1
Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
• Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state an