SILABS CP2400-DK Development kit users guide Datasheet

C P2 4 0 0 / 1 -DK
CP2400
AND
C P 2 4 0 1 D EVELOPMENT K IT U S E R ’ S G U I D E
1. Overview
The LCD Development Kits (CP2400-DK and CP2401-DK) provide all the hardware and software required to
develop and test LCD applications. The CP240x LCD Firmware Library is included to aid in the code development
process and handle the communication between the C8051F9xx MCU and the CP2400/1 LCD controller. The LCD
library can be used to communicate with the LCD controller through the SPI interface (CP2400-DK) or the SMBus
interface (CP2401-DK). Example code using the LCD library is included with both development kits.
The LCD development kit hardware includes a C8051F930 target board, CP2400 or CP2401 LCD Development
Board, USB Debug adapter, and an ac to dc power adapter. The C8051F930 Target Board features the 25 MIPS,
64 kB Flash, over 4 kB RAM, 8051-based C8051F930 MCU. The C8051F930 MCU is part of the low-power family
and can operate with a supply voltage from 0.9 to 3.6 V. The MCU LCD interface provided by the AB board
consists of the CP2400/1 LCD controller and an LCD and is compatible with the C8051F930-DK and C8051F912DK. The LCD development kit includes example code which uses either the SPI interface (CP2400-DK) or SMBus
interface (CP2401-DK) on the C8051F930 to control the LCD using the LCD library.
The Silicon Labs’ IDE supports full-speed, non-intrusive MCU debugging and is bundled with an evaluation version
of the Keil C51 Toolchain allowing immediate application code evaluation in C. Projects with up to 4 kB of object
code and unlimited library code can be developed using the included toolset. Numerous application code examples
are included in the development kit and a walkthrough of an LCD example is included in 6. "Example Source
Code‚" on page 11.
Figure 1. C8051F912-TB Target Board and CP2400 LCD Development Board
Rev. 0.1 10/09
Copyright © 2009 by Silicon Laboratories
CP2400/1-DK
CP2400/1-DK
2. Kit Contents
The CP2400/1 LCD development kit contains the following items:

C8051F930 target board
CP2400 or CP2401 LCD development board
 CP240x development kit quick-start guide
 Silicon Laboratories IDE and product information CD-ROM. CD content includes the following:

Silicon
Laboratories Integrated Development Environment (IDE)
8051 development tools (macro assembler, linker, evaluation C compiler)
Source code examples and register definition files
Documentation
CP2400 and CP2401 Development Kit User’s Guide (this document)
Keil

AC to DC power adapter
USB Debug Adapter (USB to debug interface)
 2 USB cables
 2 AAA batteries

Figure 2. C8051F930 Target Board
2
Rev. 0.1
CP2400/1-DK
Figure 3. CP2400 Development Board
3. Software Overview
All software required to develop firmware and communicate with the target microcontroller is included in the CDROM. The CD-ROM also includes other useful software.
Below is the software necessary for firmware development and communication with the target microcontroller:

Silicon Laboratories Integrated Development Environment (IDE)
 Keil 8051 development tools (macro assembler, linker, evaluation C compiler)
Other useful software that is provided in the CD-ROM includes the following:

Configuration Wizard 2
 Keil µVision drivers
 CP210x USB to UART Virtual COM Port (VCP) drivers
3.1. Software Installation
The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), Keil software
8051 tools and additional documentation. Insert the CD-ROM into your PC’s CD-ROM drive. An installer will
automatically launch, allowing you to install the IDE software or read documentation by clicking buttons on the
Installation Panel. If the installer does not automatically start when you insert the CD-ROM, run autorun.exe found
in the root directory of the CD-ROM. Refer to the ReleaseNotes.txt file on the CD-ROM for the latest information
regarding known problems and restrictions. After installing the software, see the following sections for information
regarding the software and running one of the demo applications.
3.2. CP210x USB to UART VCP Driver Installation
The C8051F930 Target Board includes a Silicon Laboratories CP2103 USB-to-UART Bridge Controller. Device
drivers for the CP2103 need to be installed before PC software such as HyperTerminal can communicate with the
target board over the USB connection. If the "Install CP210x Drivers" option was selected during installation, this
will launch a driver “unpacker” utility.
Rev. 0.1
3
CP2400/1-DK
1. Follow the steps to copy the driver files to the desired location. The default directory is C:\Silabs\MCU\CP210x.
2. The final window will give an option to install the driver on the target system. Select the “Launch the CP210x
VCP Driver Installer” option if you are ready to install the driver.
3. If selected, the driver installer will now launch, providing an option to specify the driver installation location. After
pressing the “Install” button, the installer will search your system for copies of previously installed CP210x
Virtual COM Port drivers. It will let you know when your system is up to date. The driver files included in this
installation have been certified by Microsoft.
4. If the “Launch the CP210x VCP Driver Installer” option was not selected in step 3, the installer can be found in
the location specified in step 2, by default C:\Silabs\MCU\CP210x\Windows_2K_XP_S2K3_Vista. At this
location run CP210xVCPInstaller.exe.
5. To complete the installation process, connect the included USB cable between the host computer and the USB
connector (P3) on the C8051F930 Target Board. Windows will automatically finish the driver installation.
Information windows will pop up from the taskbar to show the installation progress.
6. If needed, the driver files can be uninstalled by selecting “Silicon Laboratories CP210x USB to UART Bridge
(Driver Removal)” option in the “Add or Remove Programs” window.
3.3. Silicon Laboratories IDE
The Silicon Laboratories IDE integrates a source-code editor, a source-level debugger, and an in-system Flash
programmer. See Section 5. "Using the Keil Software 8051 Tools with the Silicon Laboratories IDE‚" on page 10 for
detailed information on how to use the IDE. The Keil Evaluation Toolset includes a compiler, linker, and assembler
and easily integrates into the IDE. The use of third-party compilers and assemblers is also supported.
3.3.1. IDE System Requirements
The Silicon Laboratories IDE requirements:
 Pentium-class host PC running Microsoft Windows 2000 or newer
 One available USB port
 64 MB RAM and 40 MB free HD space recommended
3.3.2. 3rd Party Toolsets
The Silicon Laboratories IDE has native support for many 8051 compilers. The full list of natively supported tools is
as follows:
 Keil
 IAR
 Raisonance
 Tasking
 Hi-Tech
 SDCC
The demo applications for the C8051F930 target board are written to work with the Keil and SDCC toolsets.
3.4. Keil Evaluation Toolset
3.4.1. Keil Assembler and Linker
The Keil demonstration toolset assembler and linker place no restrictions on code size.
3.4.2. Keil Evaluation C51 C Compiler
The evaluation version of the C51 compiler is the same as the full version with the following limitations: (1)
Maximum 4 kB code generation, (2) There is no floating point library included. When installed from the CD-ROM,
the C51 compiler is initially limited to a code size of 2 kB, and programs start at code address 0x0800. Refer to
“AN104: Integrating Keil Tools into the Silicon Labs IDE" for instructions to change the limitation to 4 kB and have
the programs start at code address 0x0000.
4
Rev. 0.1
CP2400/1-DK
3.5. Configuration Wizard 2
The Configuration Wizard 2 is a code generation tool for all of the Silicon Laboratories devices. Code is generated
through the use of dialog boxes for each of the device's peripherals.
Figure 4. Configuration Wizard 2 Utility
The Configuration Wizard utility helps accelerate development by automatically generating initialization source
code to configure and enable the on-chip resources needed by most design projects. In just a few steps, the wizard
creates complete startup code for a specific Silicon Laboratories MCU. The program is configurable to provide the
output in C or assembly language. For more information, refer to the Configuration Wizard documentation.
Documentation and software is available on the kit CD and from the downloads webpage: www.silabs.com/
mcudownloads.
Rev. 0.1
5
CP2400/1-DK
3.6. Silicon Labs Battery Life Estimator
The Battery Life Estimator is a system design tool for battery operated devices. It allows the user to select the type
of battery they are using in the system and enter the supply current profile of their application. Using this
information, it performs a simulation and provides an estimated system operating time. The Battery Life Estimator
is shown in Figure 5.
Figure 5. Battery Life Estimator Utility
From Figure 5, the two inputs to the Battery Life Estimator are battery type and discharge profile. The utility
includes battery profiles for common battery types such as AAA, AA, A76 Button Cell, and CR2032 coin cell. The
discharge profile is application-specific and describes the supply current requirements of the system under various
supply voltages and battery configurations. The discharge profile is independent of the selected power source.
Several read-only discharge profiles for common applications are included in the pulldown menu. The user may
also create a new profile for their own applications.
To create a new profile:
1. Select the profile that most closely matches the target application or choose the "Custom Profile".
2. Click Manage
3. Click Duplicate
4. Click Edit
Profiles may be edited with the easy-to-use GUI (shown in Figure 6).
6
Rev. 0.1
CP2400/1-DK
Figure 6. Battery Life Estimator Discharge Profile Editor
The Discharge Profile Editor allows the user to modify the profile name and description. The four text entry boxes
on the left hand side of the form allow the user to specify the amount of time the system spends in each power
mode. On the right hand side, the user may specify the supply current of the system in each power mode.
Since supply current is typically dependent on supply voltage, the discharge profile editor provides two columns for
supply current. The V2 and V1 voltages at the top of the two columns specify the voltages at which the current
measurements were taken. The Battery Life Estimator creates a linear approximation based on the input data and
is able to feed the simulation engine with an approximate supply current demand for every input voltage.
The minimum system operating voltage input field allows the system operating time to stop increasing when the
simulated battery voltage drops below a certain threshold. This is primarily to allow operating time estimates for
systems that cannot operate down to 1.8 V, which is the voltage of two fully drained single-cell batteries placed in
series.
Rev. 0.1
7
CP2400/1-DK
The wakeup frequency box calculates the period of a single iteration through the four power modes and displays
the system wake up frequency. This is typically the "sample rate" in low power analog sensors.
Once the battery type and discharge profile is specified, the user can click the "Simulate" button to start a new
simulation. The simulation engine calculates the estimated battery life when using one single-cell battery, two
single-cell batteries in series, and two single-cell batteries in parallel. Figure 7 shows the simulation output window.
Figure 7. Battery Life Estimator Utility Simulation Results Form
The primary outputs of the Battery Life Estimator are an estimated system operating time and a simulated graph of
battery voltage vs. time. Additional outputs include estimated battery capacity, average current, self-discharge
current, and the ability to export graph data to a comma delimited text file for plotting in an external graphing
application.
3.7. Keil µVision2 and µVision3 Silicon Laboratories Drivers
As an alternative to the Silicon Laboratories IDE, the µVision debug driver allows the Keil µVision2 and µVision3
IDEs to communicate with Silicon Laboratories’ on-chip debug logic. In-system Flash memory programming
integrated into the driver allows for rapid updating of target code. The µVision2 and µVision3 IDEs can be used to
start and stop program execution, set breakpoints, check variables, inspect and modify memory contents, and
single-step through programs running on the actual target hardware. For more information, refer to the µVision
driver documentation. The documentation and software are available on the kit CD and from the downloads
webpage: www.silabs.com/mcudownloads.
8
Rev. 0.1
CP2400/1-DK
4. Hardware Setup using a USB Debug Adapter
The target board is connected to a PC running the Silicon Laboratories IDE via the USB Debug Adapter as shown
in Figure 9.
1. Connect the LCD development board to the F930 target board as shown in Figure 8.
2. Connect the USB Debug Adapter to the DEBUG connector on the C8051F930 target board with the 10-pin
ribbon cable.
3. Connect one end of the USB cable to the USB connector on the USB Debug Adapter.
4. Connect the other end of the USB cable to a USB Port on the PC.
5. Verify that a shorting block is installed on J17 and that SW5 is in the ON position on the C8051F930 target
board.
6. Verify that a shorting block is installed on J2 of the CP2400/1 LCD Development Board.
7. Connect the ac/dc power adapter to power jack P1 on the C8051F930 target board (Optional).
Notes:
Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.
Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the
ribbon cable from the target board. Connecting or disconnecting the cable when the devices have power can
damage the device and/or the USB Debug Adapter.
P1
P1.6
R15
J16
P1.5
J15
TOUCH SENSE SWITCH
P2.0
P0.2
P0.3
USB POWER P3
TOUCH SENSE SWITCH
P2.1
CP
2103
U3
SILICON LABS
J9
J12
U1
+1VD
F930
J11
J5
J7
IMEASURE
J13
J3
VBAT
AAA_BAT
WALL_PWR
+3VD
J14
RESET
VDD/DC+
IMEASURE
J6
SILICON LABS
www.silabs.com
J1
D1
J5J4
`
J5
J17
H2
D2
LED
J2
PWR
VBAT
OFF
ON
SW5
H1
POWER OFF BEFORE
SWITCHING MODE
J2
J10
COIN_CELL
U1 CP2400
1 CELL
CP2400-GQ LCD
DEVELOPMENT BOARD
J8
2 CELL
www.silabs.com
DEBUG
J4
SW4
J1 P2
Figure 8. CP2400/1 LCD Development Board Attachment
PC
Target Board
P1
P1.6
R15
P0.2
P0.3
USB Debug
Adapter
P1.5
J16
USB POWER P3
J15
TOUCH SENSE SWITCH
P2.0
TOUCH SENSE SWITCH
P2.1
+1VD
J11
COIN_CELL
J5
J2
J7
IMEASURE
AAA_BAT
WALL_PWR
J13
J3
J14
VBAT
+3VD
RESET
J6
J1
SILICON LABS
www.silabs.com
D1
LED
J5J4
J5
D2
PWR
VDD/DC+
H1
IMEASURE
`
J2
J17
H2
OFF
ON
SW5
1 CELL
F930
U1 CP2400
SW4
VBAT
J1
Power
J9
J12
DEBUG
J8
U1
2 CELL
www.silabs.com
CP2400-GQ LCD
DEVELOPMENT BOARD
Run
U3
SILICON LABS
Silicon Laboratories
USB DEBUG ADAPTER
CP
2103
J4
USB
Cable
Stop
LCD Development Board
POWER OFF BEFORE
SWITCHING MODE

J10

AC/DC
Adapter
P2
Figure 9. Hardware Setup Using a USB Debug Adapter
Rev. 0.1
9
CP2400/1-DK
5. Using the Keil Software 8051 Tools with the Silicon Laboratories IDE
To perform source-level debugging with the IDE, configure the Keil 8051 tools to generate an absolute object file in
the OMF-51 format with object extensions and debug records enabled. Build the OMF-51 absolute object file by
calling the Keil 8051 tools at the command line (e.g., batch file or make file) or by using the project manager built
into the IDE. The default configuration when using the Silicon Laboratories IDE project manager enables object
extension and debug record generation. Refer to "AN104: Integrating Keil 8051 Tools into the Silicon Labs IDE" in
the “Silabs\MCU\Documentation\ApplicationNotes” directory on the CD-ROM for additional information on using the
Keil 8051 tools with the Silicon Laboratories IDE.
To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project.
A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and
tool configurations used as input to the assembler, compiler, and linker when building an output object file).
The following sections illustrate the steps necessary to manually create a project with one or more source files,
build a program, and download it to the target in preparation for debugging. (The IDE will automatically create a
single-file project using the currently open and active source file if you select Build/Make Project before a project is
defined.)
5.1. Creating a New Project
1. Select ProjectNew Project to open a new project and reset all configuration settings to default.
2. Select FileNew File to open an editor window. Create your source file(s) and save the file(s) with a
recognized extension, such as .c, .h, or .asm, to enable color syntax highlighting.
3. Right-click on “New Project” in the Project Window. Select Add files to project. Select files in the file browser
and click Open. Continue adding files until all project files have been added.
4. For each of the files in the Project Window that you want assembled, compiled and linked into the target build,
right-click on the file name and select Add file to build. Each file will be assembled or compiled as appropriate
(based on file extension) and linked into the build of the absolute object file.
5. If a project contains a large number of files, the “Group” feature of the IDE can be used to organize. Right-click
on “New Project” in the Project Window. Select Add Groups to project. Add pre-defined groups or add
customized groups. Right-click on the group name and choose Add file to group. Select files to be added.
Continue adding files until all project files have been added.
5.2. Building and Downloading the Program for Debugging
1. Once all source files have been added to the target build, build the project by clicking on the Build/Make Project
button in the toolbar or selecting ProjectBuild/Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the files that
have been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild
All button in the toolbar or select ProjectRebuild All from the menu.
2. Before connecting to the target device, several connection options may need to be set. Open the Connection
Options window by selecting OptionsConnection Options... in the IDE menu. First, select the appropriate
adapter in the “Serial Adapter” section. Next, the correct “Debug Interface” must be selected. C8051F93xC8051F92x family devices use the Silicon Labs 2-wire (C2) debug interface. Once all the selections are made,
click the OK button to close the window.
3. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
4. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful select Enable automatic connect/
download after build in the ProjectTarget Build Configuration dialog. If errors occur during the build process,
the IDE will not attempt the download.
5. Save the project when finished with the debug session to preserve the current target build configuration, editor
settings and the location of all open debug views. To save the project, select ProjectSave Project As... from
the menu. Create a new name for the project and click on Save.
10
Rev. 0.1
CP2400/1-DK
6. Example Source Code
Example source code and register definition files are provided in the “SiLabs\MCU\Examples\C8051F93x_92x\”
default directory during IDE installation. These files may be used as a template for code development. Example
applications include a blinking LED example which configures the green LED on the target board to blink at a fixed
rate.
6.1. Register Definition Files
Register definition files C8051F930.inc and C8051F930_defs.h define all SFR registers and bit-addressable
control/status bits. A macro definition header file compiler_defs.h is also included, and is required to be able to use
the C8051F930_defs.h header file with various tool chains. These files are installed into the
“Silabs\MCU\Examples\C8051F93x_92x\Header_Files\” directory during IDE installation by default. The register
and bit names are identical to those used in the C8051F93x-C8051F92x data sheet. These register definition files
are also installed in the default search path used by the Keil Software 8051 tools. Therefore, when using the Keil
8051 tools included with the development kit (A51, C51), it is not necessary to copy a register definition file to each
project’s file directory.
6.2. Blinking LED Example
The example source files F93x_Blinky.asm and F93x_Blinky.c installed in the default directory
“Silabs\MCU\Examples\C8051F93x_92x\Blinky” show examples of several basic C8051F930 functions. These
include disabling the watchdog timer (WDT), configuring the Port I/O crossbar, configuring a timer for an interrupt
routine, initializing the system clock, and configuring a GPIO port pin. When compiled/assembled and linked this
program flashes the green LED on the C8051F930 Target Board about five times a second using the interrupt
handler with a C8051F930 timer.
6.3. Touch Sensitive Switch Example
The example source file F93x_CapTouchSense_Switch.c demonstrates the configuration and usage of the touch
sensitive (contactless) switches located on P2.0 and P2.1. Refer to the source file for step-by-step instructions to
build and test this example. This is installed in the following directory by default:
Silabs\MCU\Examples\C8051F93x_92x\ CapTouchSense_Switch
6.4. LCD Examples
The example source files in the project CP240x_LCD_Example show how to initialize the C8051F9xx as well as
the CP2400/1. The project uses the LCD library to configure the CP2400/1 through the SPI interface (CP2400) or
SMBus interface (CP2401). This project contains many examples that can be selected and customized through
modifications to header files. This is installed in the following directory by default:
Silabs\MCU\Examples\CP240x\CP240x_LCD_Example\Source
6.4.1. Target Board Selection
The target board that is connected to the CP2400/1 LCD Development Board must be specified in the file
lcd_lib_portdefs.h. The section labeled “Development Board Definition” has a global definition that specifies which
target board is connected to the CP2400/1 LCD development board. It is important to note that the target board
specified in this section must match the target board that is connected to the CP2400/1 LCD development board.
The following line of code would configure the code to use the C8051F930 target board:
#define DEV_BOARD
F930DK
6.4.2. Control Interface Selection
The control interface that is used to configure the CP2400/1 can be selected by modifying the file,
lcd_lib_portdefs.h. In this file, there is a section called “Interface Definition” where either the SPI interface
(CP2400) or the SMBus interface (CP2401) can be selected. It is important to note that the correct control interface
must be selected in this particular header file before compiling the project or the CP2400/1 will not function
correctly. The CP2400 uses the SPI interface, and the CP2401 uses the SMBus interface. The following line of
code would configure the code to use the SMBus interface to configure a CP2401:
#define BUS_INTERFACE
SMBUS
Rev. 0.1
11
CP2400/1-DK
If using a CP2400, this line should say:
#define BUS_INTERFACE
SPI
6.4.3. Example Selection
The example that is run on the CP2400/1 LCD development board can be selected in the file, app_config.h. The
available examples include a voltage display example, digit display example, and several current measurement
examples. A list of available examples is included in the file, app_config.h. The following line of code would select
the digit display example:
#define EXAMPLE
DISPLAY_DIGITS
The display digits example will first show the numbers “01234567”, clear the LCD, and then show “76543210”. For
the voltage display example, the channel being measured can be selected by modifying the CHANNEL_SELECT
definition in app_config.h. The available selections are VDD and the potentiometer (POT). To measure VDD,
change the corresponding EXAMPLE definition in app_config.h. The VDD voltage will now be displayed on the
LCD. To measure the potentiometer voltage, change the corresponding EXAMPLE definition in app_config.h, and
place shorting blocks on J16 and J15[2-3] on the C8501F930 Target Board. The potentiometer voltage will now be
displayed on the LCD.
The various current measurement examples can also be selected in app_config.h. These examples place the
CP240x in various power modes. The file, lcd_lib_config.h, has parameters that can be modified that will affect the
current draw, such as the LCD refresh rate, the mux mode, and the bias mode.
12
Rev. 0.1
CP2400/1-DK
7. C8051F930 Target Board
The CP2400/1 Development Kit includes a target board with a C8051F930 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 10 for the locations of the various I/O connectors. Figure 12 on page 15
shows the factory default shorting block positions.
P1
P2
P3
J1
J2, J3, J4
J5
J6
J7
J8
J9
J10, J11
J12
J13
J14
J15
J16
J17
H1
H2
SW4
SW5
Expansion connector (96-pin)
Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
USB connector (connects to PC for serial communication)
Enable/Disable VBAT Power LED
Port I/O headers (provide access to Port I/O pins)
Enable/Disable VDD/DC+ Power LED
Provides an easily accessible ground clip
Connects pin P0.7 (IREF0 Output) to resistor R14 and capacitor C19
Connects P0.2 and P0.3 to switches and P1.5 and P1.6 to LEDs
DEBUG connector for Debug Adapter interface
Selects the power supply source (Wall Power, AAA Battery, or Coin Cell)
Connects Port I/O to UART0 interface
Connects external VREF capacitor to the P0.0/VREF
Connects the PCB ground plane to P0.1/AGND
Connects negative potentiometer (R14) terminal to pin P1.4 or to GND
Connects the potentiometer (R14) wiper to P0.6/CNVSTR
Creates an open in the power supply path to allow supply current measurement
Analog I/O terminal block
Provides terminal block access to the input and output nodes of J17
Switches the device between One-Cell (0.9–1.8 V supply) or Two-Cell (1.8–3.6 V) mode
Turns power to the MCU on or off
P1.6
R15
J16
P1.4
J15
GND
P0.2
P1.5 SW2
P0.3
SW3
USB POWER P3
TOUCH SENSE SWITCH
P2.0
TOUCH SENSE SWITCH
P2.1
CP
2103
U3
SILICON LABS
J8
U1
+1VD
F930
P1
J9
J12
J11
AAA_BAT
WALL_PWR
J13
SW1
J14
J3
+3VD
RESET
J6
VDD/DC+
J5
IMEASURE
PORT0
`
J2
J17
H2
OFF
ON
H1
VBAT
POWER OFF BEFORE
SWITCHING MODE
J7
PORT1
J10
COIN_CELL
Pin 1
Pin 2
SW4
VBAT
SW5
1 CELL
PORT2
2 CELL
www.silabs.com
DEBUG
J4
J1
P2
Pin 1
Figure 10. C8051F930 Target Board
Rev. 0.1
13
CP2400/1-DK
The following items are located on the bottom side of the board. See Figure 11.
BT1
BT2
BT3
BT4
Battery Holder for 1.5 V AAA. Use for one-cell or two-cell mode.
Battery Holder for 1.5 V AAA. Use for two-cell mode only.
Battery Holder for 3 V Coin Cell (CR2032).
Battery Holder for 1.5 V Button Cell (A76 or 357).
NEG
POS
Note: BT2 is
only used in
two-cell mode.
BT3
(CR2032)
BT2
(AAA) POS
BT1
NEG (AAA)
BT4
(A76 or 357)
Figure 11. Bottom of C8051F930 Target Board
14
Rev. 0.1
CP2400/1-DK
7.1. Target Board Shorting Blocks: Factory Defaults
The C8051F930 target board comes from the factory with pre-installed shorting blocks on many headers. Figure 12
shows the positions of the factory default shorting blocks.
P1.6
R15
USB POWER P3
TOUCH SENSE SWITCH
P2.0
TOUCH SENSE SWITCH
P2.1
CP
2103
U3
SILICON LABS
www.silabs.com
PORT2
J8
U1
+1VD
F930
P1
J9
J12
J11
J13 AAA_BAT
WALL_PWR
SW1
J14
+3VD
J7
PORT1
J3
RESET
J6
VDD/DC+
J5
PORT0
IMEASURE
`
J2
J17
H2
OFF
ON
H1
SW5
VBAT
POWER OFF BEFORE
SWITCHING MODE
J10
COIN_CELL
1 CELL
J4
Pin 1
Pin 2
2 CELL
P1.4
J15
GND
P0.3
SW3
DEBUG
J16
P0.2
P1.5 SW2
SW4
VBAT
J1
P2
Pin 1
Figure 12. C8051F930 Target Board Shorting Blocks: Factory Defaults
Rev. 0.1
15
CP2400/1-DK
7.2. Target Board Power Options and Current Measurement
The C8051F930 Target Board supports three power options, selectable by the three-way header (J10/J11). The
power options vary based on the configuration (one-cell or two-cell mode) selected by SW4. Power to the MCU
may be switched on/off using the power switch (SW5). Important Note: The power switch (SW5) must be in the
OFF position prior to switching between one-cell and two-cell mode using SW4. The power options are
described in the paragraphs below.
7.2.1. Wall Power
When the J10/J11 three-way header is set to WALL_PWR, the C8051F930 Target Board may be powered from the
following power sources:

9 VDC power using the ac to dc power adapter (P2)
5 VDC USB VBUS power from PC via the USB Debug Adapter (J9)
 5 VDC USB VBUS power from PC via the CP2103 USB connector (P3)

All the three power sources are ORed together using reverse-biased diodes (D1, D2, D3), eliminating the need for
headers to choose between the sources. The target board will operate as long as any one of the power sources is
present. The ORed power is regulated to a 3.3 V dc voltage using a LDO regulator (U2). The output of the regulator
powers the +3 VD net on the target board.
If SW4 is configured to select two-cell mode, the VBAT supply net on the target board is powered directly from the
+3 VD net. If SW4 is configured to select one-cell mode, the VBAT supply net is powered directly from the +1 VD.
This power supply net takes +3 VD and passes it through a 1.65 V LDO. The LDO’s output voltage is variable and
can be set by changing the value of resistor R32.
J11
J10
COIN_CELL
VBAT
AAA_BAT
WALL_PWR
7.2.2. AAA Battery
When the J10/J11 three-way header is set to AAA_BAT, the C8051F930 Target Board may be powered from a
single AAA battery inserted in BT1 or from the series combination of the AAA batteries inserted in BT1 and BT2. A
single battery is selected when SW4 is configured to one-cell mode. The two AAA batteries configured in series to
provide a voltage of ~3 V are selected when SW4 is configured to two-cell mode.
J11
J10
COIN_CELL
VBAT
AAA_BAT
WALL_PWR
7.2.3. Coin Cell Battery
When the J10/J11 three-way header is set to COIN_CELL, the C8051F930 Target Board may be powered from a
single 1.5 V Alkaline (A76) or Silver Oxide (357) button cell inserted in BT4 or from a single 3 V Lithium (CR2032)
coin cell inserted in BT3. The button cell (BT4) is selected when SW4 is configured to one-cell mode, and the coin
cell (BT3) is selected when SW4 is configured to two-cell mode.
J11
J10
COIN_CELL
AAA_BAT
WALL_PWR
16
Rev. 0.1
VBAT
CP2400/1-DK
7.2.4. Measuring Current
The header (J17) and terminal block (H2) provide a way to measure the total supply current flowing from the power
supply source to the MCU. The measured current does not include any current from the VBAT LED (DS2), the
address latch (U4) or the quiescent current from the power supply; however, it does include the current used by
any LEDs powered from the VDD/DC+ supply net or sourced through a GPIO pin. See the target board schematics
in Figures 19 through 21 for additional information.
7.3. System Clock Sources
7.3.1. Internal Oscillators
The C8051F930 device installed on the target board features a factory calibrated programmable high-frequency
internal oscillator (24.5 MHz base frequency, ±2%) and a low power internal oscillator (20 MHz ±10%). After each
reset, the low power oscillator divided by 8 results in a default system clock frequency of 2.5 MHz (±10%). The
selected system clock and the system clock divider may be configured by software for operation at other
frequencies. For low-frequency operation, the C8051F930 features a smaRTClock real time clock. A 32.768 kHz
Watch crystal (Y2) is included on the target board. If you wish to operate the C8051F930 device at a frequency not
available with the internal oscillators, an external crystal may be used. Refer to the C8051F93x-C8051F92x data
sheet for more information on configuring the system clock source.
7.3.2. External Oscillator Options
The target board is designed to facilitate the installation of an external crystal (Y1). Install a 10 M resistor at R9
and install capacitors at C20 and C21 using values appropriate for the crystal you select. If you wish to operate the
external oscillator in capacitor or RC mode, options to install a capacitor or an RC network are also available on the
target board. Populate C21 for capacitor mode, and populate R16 and C21 for RC mode. Refer to the C8051F93xC8051F92x data sheet for more information on the use of external oscillators.
7.4. Port I/O Headers (J2, J3, J4, J6)
Access to all Port I/O on the C8051F930 is provided through the headers J2, J3, and J4. The header J6 provides
access to the ground plane for easy clipping of oscilloscope probes.
7.5. Switches and LEDs
Three push-button switches are provided on the target board. Switch SW1 is connected to the reset pin of the
C8051F930. Pressing SW1 puts the device into its hardware-reset state. Switches SW2 and SW3 are connected to
the C8051F930’s general purpose I/O (GPIO) pins through headers. Pressing SW2 or SW3 generates a logic low
signal on the port pin. Remove the shorting block from the header (J8) to disconnect the switches from the port
pins. The port pin signal is also routed to pins on the J2 and P1 I/O connectors. See Table 1 for the port pins and
headers corresponding to each switch.
Two touch sensitive (contactless) switches are provided on the target board. The operation of these switches
require appropriate firmware running on the C8051F930 MCU that can sense the state of the switch. See Section
6.3. "Touch Sensitive Switch Example‚" on page 11 for details about example source code.
Five power LEDs are provided on the target board to serve as indicators. Each of the two regulators has a red LED
used to indicate the presence of power at the output of the regulator. A red USB Power LED turns on when a USB
cable is plugged into the USB connector P3. One power LED is also added to each of the two primary supply nets
powering the MCU (VDD/DC+ and VBAT). The LEDs connected to the supply nets may be disabled by removing
the shorting blocks from J1 and J5.
Two LEDs are connected to GPIO pins P1.5 and P1.6 for use by application software. See Table 1 for the port pins
and headers corresponding to each LED.
A potentiometer (R15) is also provided on the target board for generating analog signals. Place a shorting block on
J16 to connect the wiper to P0.6/CNVSTR. The header J15 allows the negative terminal of the potentiometer to be
tied to GND or to P1.4. When tied to GND, the potentiometer is always enabled and will draw a measurable
amount of supply current. When tied to P1.4, it only draws current when P1.4 is driving a logic 0 and draws no
current when P1.4 is driving a logic 1.
Rev. 0.1
17
CP2400/1-DK
Table 1. Target Board I/O Descriptions
Description
I/O
Header(s)
SW1
SW2
SW3
P2.0 (Touch Sense Switch)
P2.1 (Touch Sense Switch)
Red LED (P1.5)
Yellow LED (P1.6)
Red LED (VDD/DC+)
Red LED (VBAT)
Red LED (USB Power)
Red LED (+1 VD Power)
Red LED (+3 VD Power)
Potentiometer (R15)
Reset
P0.2
P0.3
P2.0
P2.1
P1.5
P1.6
VDD/DC+ Supply Net
VBAT Supply Net
USB VBUS
+1 VD Regulator Output
+3 VD Regulator Output
P0.6/P1.4
none
J8[5–6]
J8[7–8]
none
none
J8[1–2]
J8[3–4]
J5
J1
none
none
none
J15, J16
7.6. Expansion I/O Connector (P1)
The 96-pin Expansion I/O connector P1 provides access to all signal pins of the C8051F930 device (except the C2
debug interface signals). In addition, power supply and ground pins are included. A small through-hole prototyping
area is also provided. See Table 2 for a list of pin descriptions for P1.
Table 2. P1 Pin Descriptions
18
Row A
Pin #
Description
Row B
Pin #
Description
Row C
Pin #
Description
1
+3 VD
1
GND
1
nc
2
nc
2
nc
2
nc
3
nc
3
nc
3
nc
4
nc
4
nc
4
nc
5
nc
5
nc
5
nc
6
nc
6
nc
6
nc
7
nc
7
nc
7
nc
8
nc
8
nc
8
nc
9
nc
9
nc
9
nc
10
nc
10
P0.7/IREF0
10
P0.6/CNVSTR
11
P0.5/RX
11
P0.4/TX
11
P0.3H
12
P0.2H
12
P0.1/AGND
12
P0.0/VREF
13
P1.7/AD7
13
P1.6/AD6
13
P1.5/AD5
14
P1.4/AD4
14
P1.3/AD3
14
P1.2/AD2
15
P1.1/AD1
15
P1.0/AD0
15
A7-Latch
16
A6-Latch
16
A5-Latch
16
A4-Latch
17
A3-Latch
17
A2-Latch
17
A1-Latch
18
A0-Latch
18
P2.3/A11
18
nc
Rev. 0.1
CP2400/1-DK
Table 2. P1 Pin Descriptions (Continued)
Row A
Pin #
Description
Row B
Pin #
Description
Row C
Pin #
Description
19
nc
19
nc
19
P2.3/A11
20
P2.2/A10
20
P2.1/A9
20
P2.0/A8
21
/WR
21
/RD
21
P0.2H
22
P2.3/A11
22
P2.2/A10
22
P2.1/A9
23
P2.0/A8
23
ALE
23
nc
24
nc
24
nc
24
nc
25
nc
25
GND
25
nc
26
GND
26
nc
26
nc
27
nc
27
nc
27
nc
28
nc
28
VDD/DC+
28
VBAT
29
nc
29
nc
29
nc
30
nc
30
nc
30
nc
31
nc
31
nc
31
nc
32
nc
32
GND
32
nc
7.7. Target Board DEBUG Interface (J9)
The DEBUG connector J9 provides access to the DEBUG (C2) pins of the C8051F930. It is used to connect the
Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.
Table 3 shows the DEBUG pin definitions.
Table 3. DEBUG Connector Pin Descriptions
Pin #
Description
1
+3 VD (+3.3 VDC)
2, 3, 9
GND (Ground)
4
P2.7/C2D
5
RST (Reset)
6
P2.7
7
RST/C2CK
8
Not Connected
10
USB Power (+5 VDC from J9)
7.8. Serial Interface (J12)
A USB-to-UART bridge circuit (U3) and USB connector (P3) are provided on the target board to facilitate serial
connections to UART0 of the C8051F930. The Silicon Labs CP2103 (U3) USB-to-UART bridge provides data
connectivity between the C8051F930 and the PC via a USB port. The VIO power supply and TX, RX, RTS and
CTS signals of UART0 may be connected to the CP2103 by installing shorting blocks on header J12. The shorting
block positions for connecting each of these signals to the CP2103 are listed in Table 4. To use this interface, the
USB-to-UART device drivers should be installed as described in Section 3.2. "CP210x USB to UART VCP Driver
Installation‚" on page 3.
Rev. 0.1
19
CP2400/1-DK
Table 4. Serial Interface Header (J12) Description
Header Pins UART0 Pin Description
J12[9–10]
J12[7–8]
J12[5–6]
J12[3–4]
J12[1–2]
CP2103_VIO (VDD/DC+)
TX_MCU (P0.5)
RX_MCU (P0.4)
RTS (P0.6)
CTS (P0.7)
7.9. Analog I/O (H1)
Several of the C8051F930 target device’s port pins are connected to the H1 terminal block. Refer to Table 5 for the
H1 terminal block connections.
Table 5. H1 Terminal Block Pin Descriptions
Pin #
Description
1
2
3
4
P0.6/CNVSTR
P0.7/IREF0
GND (Ground)
P0.0/VREF (Voltage Reference)
7.10. IREF Connector (J7)
The C8051F930 Target Board also features a current-to-voltage 1 k load resistor that may be connected to the
current reference (IREF0) output that can be enabled on port pin (P0.7). Install a shorting block on J7 to connect
port pin P0.7 of the target device to the load resistor. If enabled by software, the IREF0 signal is then routed to the
J2[8] and H1[2] connectors.
7.11. VREF and AGND Connector (J13, J14)
The C8051F930 Target Board also features 4.7 µF capacitor in parallel with a 0.1 µF that can be connected to
P0.0/VREF when using the Precision Voltage Reference. The capacitors are connected to P0.0/VREF when a
shorting block is installed on J13. Using the Precision Voltage Reference is optional since 'F93x-'F92x devices
have an on-chip High-Speed Voltage Reference.
The shorting block J14 allows P0.1/AGND to be connected to ground. This provides a noise-free ground reference
to the analog-to-digital Converter. The use of this dedicated analog ground is optional.
7.12. C2 Pin Sharing
On the C8051F930, the debug pins C2CK and C2D are shared with the pins RST and P2.7, respectively. The
target board includes the resistors necessary to enable pin sharing which allow the RST and P2.7 pins to be used
normally while simultaneously debugging the device. See Application Note “AN124: Pin Sharing Techniques for the
C2 Interface” at www.silabs.com for more information regarding pin sharing.
20
Rev. 0.1
CP2400/1-DK
8. CP2400/1 AB LCD Development Board
The CP2400 and CP2401 Development Kits include a CP2400 or CP2401 LCD Development Board designed to
connect to C8051F9xx target boards. Various input/output (I/O) connectors are provided to facilitate prototyping
using the development board. Refer to Figure 13 for the locations of the various I/O connectors. Figure 14 on page
22 shows the factory default shorting block positions.
P1
DS1
U1
J1
J2
J3
J4
J5
D1
D2
Expansion connector (96-pin)
Liquid Crystal Display (LCD)
CP2400/1 LCD Controller
CP2400/1 Port I/O headers (provide access to Port I/O pins on CP2400/1)
Creates an open in the power supply path to allow supply current measurement
Provides an easily accessible ground clip
Connects the LED signal from the C8051F9xx Target Board to the LED on the CP2400/1
Development Board
Enable/Disable CP2400/1 Power LED
LED controlled by C8051F9xx Target Board
CP2400/1 Power LED
P1
CP2400-GQ LCD
DEVELOPMENT BOARD
U1 CP2400
J5
J1
J2
IMEASURE
SILICON LABS
www.silabs.com
D1
LED
J5J4
D2
PWR
Figure 13. CP2400 AB LCD Development Board
Rev. 0.1
21
CP2400/1-DK
8.1. Target Board Shorting Blocks: Factory Defaults
The CP2400/1 target board comes from the factory with pre-installed shorting blocks on many headers. Figure 14
shows the positions of the factory default shorting blocks.
P1
CP2400-GQ LCD
DEVELOPMENT BOARD
U1 CP2400
J5
J1
J2
IMEASURE
SILICON LABS
www.silabs.com
D1
LED
J5J4
D2
PWR
Figure 14. CP2400 AB LCD Development Board Shorting Blocks: Factory Defaults
22
Rev. 0.1
CP2400/1-DK
8.2. AB Board Current Measurement
The header (J2) provides a way to measure the total supply current flowing from the power supply source to the
CP2400/1. The measured current does not include any current from the LED (D1) or the Power LED (D2). See the
target board schematics in Figures 15 through 18 for additional information.
8.3. Port I/O Headers (J1, J3)
Access to the CP2400/1 control interface signals (SMBus or SPI) as well as /RST, /LED, /INT, /CLK, VDD, and
GND is provided through J1 on the AB board. The header J3 provides access to the ground plane for easy clipping
of oscilloscope probes.
8.4. LEDs
Two LEDs are provided on the AB board: one labeled “LED” and one labeled “PWR”. The PWR LED is powered by
VDD being supplied to the CP2400/1. The other LED labeled “LED” is powered through from P1.7 on the
C8051F930 Target Board or P2.7 on the C8051F912 Target Board. Tables 6 and 7 contain more information
regarding which port pins’ control signals are connected to on the target board. Headers are provided on the AB
board to allow for the LEDs to be physically disconnected from the circuit. Placing a jumper on the header J4 will
connect the PWR LED to ground, which will allow it to turn on when a voltage is applied on the CP2400/1’s VDD
pin. Placing a jumper on the header J5 will connect LED labeled LED to the LED signal on the attached Target
Board. Tables 6 and 7 list information on which port pin on the attached Target Board is connected to the LED
signal. The CP2400 LCD Development Board schematic and the CP2401 LCD Development Board schematic
have more information about the LED and control signals.
8.5. Target Board Connections
Tables 6 and 7 list details regarding the port pin connections to the control signals on the CP2400/1.
Table 6. CP2400 Control Signals
Signal
F930 TB
F912 TB
SCK
P1.0
P1.0
MISO
P1.1
P1.1
MOSI
P1.2
P1.2
NSS
P1.3
P1.3
/INT
P0.1
P0.1
/RST
P0.0
P0.0
/CLK
P1.4
P1.4
/LED
P1.7
P2.7
Table 7. CP2401 Control Signals
Signal
F930 TB
F912 TB
SDA
P1.0
P1.0
SCL
P1.1
P1.1
/PWR
P1.3
P1.3
/INT
P0.1
P0.1
/RST
P0.0
P0.0
/CLK
P1.4
P1.4
/LED
P1.7
P2.7
Rev. 0.1
23
CP2400/1-DK
8.6. Expansion I/O Connector (P1)
The 96-pin Expansion I/O connector P1 provides access to all signal pins of the CP2400/1 device. In addition,
power supply and ground pins are included. A small through-hole prototyping area is also provided. See Table 8
for a list of pin descriptions for P1.
Table 8. P1 Pin Descriptions
24
Row A
Pin #
Description
Row B
Pin #
Description
Row C
Pin #
Description
1
+3 VD
1
GND
1
nc
2
nc
2
nc
2
nc
3
nc
3
nc
3
nc
4
nc
4
nc
4
nc
5
nc
5
nc
5
nc
6
nc
6
nc
6
nc
7
nc
7
nc
7
nc
8
nc
8
nc
8
nc
9
nc
9
nc
9
nc
10
nc
10
nc
10
nc
11
nc
11
nc
11
nc
12
nc
12
/INT_H
12
/RST_H
13
/LED_H
13
nc
13
nc
14
/CLK_H
14
NSS_H/PWR_H
14
MOSI_H
15
MISO_H/SCL_H
15
SCK_H/SDA_H
15
nc
16
nc
16
nc
16
nc
17
nc
17
nc
17
nc
18
nc
18
nc
18
nc
19
nc
19
nc
19
nc
20
nc
20
nc
20
nc
21
nc
21
nc
21
nc
22
nc
22
nc
22
nc
23
nc
23
nc
23
nc
24
nc
24
nc
24
nc
25
nc
25
GND
25
nc
26
GND
26
nc
26
nc
27
nc
27
nc
27
nc
28
nc
28
+1.8 VD
28
nc
29
nc
29
nc
29
nc
30
nc
30
nc
30
nc
31
nc
31
nc
31
nc
32
nc
32
GND
32
nc
Rev. 0.1
Figure 15. CP2400 LCD Development Board Schematic (Page 1 of 2)
CP2400/1-DK
9. Schematics
Rev. 0.1
25
Figure 16. CP2400 LCD Development Board Schematic (Page 2 of 2)
CP2400/1-DK
26
Rev. 0.1
Figure 17. CP2401 LCD Development Board Schematic (Page 1 of 2)
CP2400/1-DK
Rev. 0.1
27
Figure 18. CP2401 LCD Development Board Schematic (Page 2 of 2)
CP2400/1-DK
28
Rev. 0.1
Figure 19. C8051F930 Target Board Schematic (Page 1 of 3)
CP2400/1-DK
Rev. 0.1
29
Figure 20. C8051F930 Target Board Schematic (Page 2 of 3)
CP2400/1-DK
30
Rev. 0.1
Figure 21. C8051F930 Target Board Schematic (Page 3 of 3)
CP2400/1-DK
Rev. 0.1
31
CP2400/1-DK
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
32
Rev. 0.1