UltraHighSpeed
Deglitched
0/ A Converter
rill ANALOG
W DEVICES
MODSERIES
I
FEATURES
Ultra-HighSpeed:20MHzWord Rate
8- and 10-Bit Versions Available
TTL Compatible
Smallest Size Available: 3" X 4" X 0.5"
Completely Self.Contained with Input Register, D/A,
Deglitcher, Timing, Internal References, and Output
Buffering
APPLICATIONS
Color-Television Video Reconstruction, Time-Base Correction and Frame Synchronization
OBS
.
Graphic Displays
Deflection Systems
Character Generators
High Speed D/A Systems
OLE
GENERAL DESCRIPTION
The MDD Series is a subsystem module which contains an
input digital register, ultra-high speed current output D/A
converter, deglitcher, output buffer amplifier~ precision references, and timing circuitry within a 3"X4"XO.S" case, The output of the device is an ultra-linear analog representation of
the digital input. Requiring only external gain and offset
potentiometers for final calibration, the MDD D/A solves the
. glitch problem associated with high-speed DI A converters. The
incorporation of an internal register virtually eliminates the
need for input bit time deskewing. While not totally eliminating the glitch per se, the remnant glitch is very smaIl, and more
importantly, constant (and therefore filterable) over the output range,
The MDD Series is available with 8- or lO-bit resolution and in
two versions. The basic versions contain a unity gain output
buffer and can deliver ZV POpopen circuit (or 1V Pop into a
load) when the MDD output is both source and load terminated. The "A" versions contain a very high speed output gain
amplifier to allow the MDD to deliver 4V pop open circuit (or
ZV POpinto a load) when the device is source and load terminated. Higher output voltages may be obtained-up
to :tlOV by
external feedback resistor selection. However, settling time
degradation must be expected.
the internal operational amplifier is less than H2, the transmission-line match obtained with the internal source terminating
resistor is almost perfect. Other applications include waveform
generation, automatic test equipment, and fast process control systems.
Designed primarily for PC board mounting, these D/A's may
also be plugged into pin sockets. The pins are 0,04" diameter,
gold plated, and are on O.Z" centers. For increased reliability,
each module is burned in for 96 hours at +ZSoC befo~e final
test and shipment,
TE
z.
:~1
. 165n. " . -ISmA
19
DIA
lB
DIGITAL
INPUTS
Is.. No.. 11
j
2.,
- AMPLIFIER
I
I
I
I
I
20
INPUT
93!1OUTPUT
21
7s.n OUTPUT
22
,.
{ BIT
LSB
STROBE
DUTPUT
DEGlITCHERINPUT
son
OUTPUT
23
LO Z OUTPUT
-
13
16
- -REF OUT
15
.1SV
-REf
OUT
's.. No..2
NOTES,
,. INPUTSSHOWNfOR IGBIT VERSIONS.FOR."'T VERSIONSPINS11 AND12ARE UNUSED.
2. THESEPARTS'" ARE OMITTEDINBASICVERSIONS.BUTPRESENTIN "A" VERSIONS.
TV APPLICATION
MDD Series Block Diagram
The "A" version of the MDD Series deglitched DI A is ideally
suited for color television video reconstruction. Its output can
directly drive the low impedances normaIly associated with
video baseband transmission. Since the output impedance of
---
""""'T"'"
---~
T"ro ".., J\, ro~
rn""/CQTCpC:
Ilnl
1/ 1n-.~.q
.
SPECIFICATIONS
(typical at +25°C and nominalsupply voltagesunlessotherwisenoted)
MODEL
RESOLUTION
Accuracy (including linearity) at
Maximum Word Rate of 20MHz
Monotonicity
MDD-O820
MDD-O820A
MDD-1O20
MDD-1O2OA
8 Bits
10 Bits
iO.2%
iO.05%
Guaranteed
"'>1""
!0.50
1 Standard "S" TTL Load
"I" = +2.4V to +5V
"0" = OV to +0.4V
"
DIGITAL STROBE INPUT
Risetime and Falltime
Width
"
'"
Change
20M Hz max
OBS
Bipolar
Impedance
Pin 23,
Pin 22,
Pin 21,
Pin 20,
22,
Low Z
50n
75n
93n
IOn
50n
75n
93n
Amplifier Current
max
i5%
is%
i5%
MDD-O820A
MDD-I020A
SETTLING TIME
DAC Current Output (to 0.1%)
Voltage Output
ISns
SOns to 0.1%
2V pop
= lOOn
min,
120ns to 0.1 %
4V pop
30m V for 2V POpF.S. Output
or 1.5% of F.S.
PEDESTAL
1OmV for 2V pop F.5. Output
or 0.5% of F.S.
OUTPUT ZERO OFFSET
Adjustable to Zero
l00ppm/oC
GAIN
Adjustable
i6.2V
REFERENCES
AVAILABLE
POWER REQUIREMENTS
+15Vi3%
-15Vi3%
+5Vi5%
Power Supply Rejection Ratio
CASE
TEMPERATURE
PIN DESIGNATIONS
-PIN
FUNCTION
PIN
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GROUND"
BIT 1 INPUT (MSB)
BIT 2 INPUT
BIT 3 INPUT
BIT 4 INPUT
BIT 5 INPUT
BIT61NPUT
BIT 7 INPUT
BIT 8 INPUT
NC
BIT 9 INPUT
BIT 10 INPUT (LSBI
STROBE INPUT
GROUND"
15
16
17
IB
19
20
21
22
23
24
25
26
27
28
-REF OUT
+REF OUT
GROUND"
DEGlITCHER INPUT
DIA OUTPUT
93Sl OUTPUT
7511 OUTPUT
5OIJ OUTPUT
LO Z OUTPUT
AMP FEEDBACK
GROUND"
-15V POWER INPUT
+15V POWER INPUT
+5V POWER INPUT
OLE
In max
50n il %
75n il %
93n il%
RESIDUAL GLITCH 1
OUTPUT ZERO OFFSET vs. TEMP
--11--0.",.641
"NS ARE GOlO 'LA TEO "R MIL.Q.""
TYPE n
OOT ON TOP 'ND>CATES POSInON OF "N ,.
Externally Programmable with
Gain and Offset Resistors
to il0V max
=ZOUT + RLOAD
+15mA
DAC Current
VOEW
WE>G"U~,'43G
i50mA for dc load
de load
"
BOTTOM
MDD-O820
MDD-I0W
0 to +2V
+IVto-lV
12
H
,.
11
H
"
Negative-Going Trailing Edge to Occur a
Minimum of 20ns After Last Data Bit
Timing
1
I.4
2 Standard "S" TTL Loads
"I" = +2.4V to +5V
"0" = OV to +0.4V
IOns max
15ns min
Logic Level/Load
positive Logic
Voltage, No Load, Unipolar
00..,.0210>A~.:r
LO"",.>M>N
(BIN)
Frequency
OUTPUT
j~
~
L~
0 to +70° C
DIGITAL DATA BIT INPUTS
Logic LeveIlLoad
Positive Logic-Binary
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
"ALL
TE
GROUNDS
INTERNALL
Y CORRECTED
120mA
150mA
2SOmA
0.1%/V
Diallyl Phthalate (per MIL-M-14
type SDG-F)
RANGE
Operating
Storage
0 to +700C
-55°C to +8SoC
NOTES
I Occ:un at the update rate.
Specifications ..bject to ch...,e without notice.
VOL. II, 10-40 DIGITAL-TO-ANALOG CONVERTERS
--
1
NOTES ON "DEGLITCHING"
An MDD Series D/A converter operating with a full-scale p-p
analog output of 1V will typically have a glitch, or transient,
in its output which is 15mV in amplitude and is 25ns wide,
at the 50% points. These typical values are independent of
whether the D/A converter is an 8-bit unit or a 10-bit unit.
these 1M products appear in the video pass-band as spurious
signals and increased noise level. The deglitcher circuits effectively eliminate these products. When they do, the SIN ratio
approaches that of an ideally-quantized signal, where the rms
noise is QI.Jli, when frequencies above Nyquist are filtered
out.
This glitch remains constant, regardless of the transition
points. In other words, it is the same for the transition from
0000000001 to 1000000000 as it is for the transition from
1000000000 to 1000000001 or any other two input words.
A constant glitch is the purpose of the deglitcher circuits.
They are intended to hold the area under the curve at a constant value; they are not intended to get rid of all glitches
per se.
When the area under the transient curve is held constant, the
frequency spectrum of the glitch is a fine line; i.e., a singleline spectrum at the sample rate frequency, and harmonics of
the sample frequency.
In summary then:
OBS
,
-L-
t
f-
\l-
RESIDUAL GLITCH
Figure 1. Pedestal/Glitch
z
DATA
INPUTS
(CHANGING)
-j
I-
--.J
- I
z
MINIMUM
AND
20ns
STROBE
D/A converters without deglitching circuits have smaller,
shorter glitches, on the average; but this type of converter has
larger glitches at the major crossings, especially at the midscale transition.
OLE
If the glitch is a function of signal dynamics, as it is in the
case of a D/A converter output which is not deglitched, a
multitude of intermodulation products art! formed. Some of
PEOESTA~
8 The residual glitch for an MDD Series D/A converter is
typically 15m V for a full-scale IV p-p output; this is 1.5%
ofF.S.
8 The glitch width is typically 25ns at the 50% points.
8 The amplitude and width of the glitch are constant, and
independent of:
-the magnitude of change in successive transitions
-number of bits of digital output
-input (update) data rates
Relationship
BETWEEN
TRAILING
z
LAST
1OdB/DIV
BIT
CHANGE
EDGE
'--- MINIMUM15ns MAXIMUM65% OF PERIOD
1 ~ OF UPDATE RATE
STROBE
INPUT
500kHz/DIV
!-50ns(MIN!-j
I
MDD-O820 OR
MDD-1020 OUTPUT
MDD-O820-A OR
MDD-1020-A OUTPUT
TE
APPROx.
!-40ns-
I r-60ns
APPROX.
Figure 4. Spectrum of TO-bit D/A Operating at 11MHz Update
Rate Without Deglitching
- Unfiltered
v....
f
"-.
-1
Figure 2. MDD Series Timing Diagram
r---
I
I
~s..o:,
- - - --,
15
750Q
16
19
I :l6.2V
I~
1+
,
/
-REF OUT
1OdB/DIV
+REF OUT
DIA OUTPUT
J
CURRENT CONTROLLED BY
INPUT DIGITAL CODE
lo~OTO+15mA
Figure 3. D/A Current Equivalent Circuit
5O0kHz/DIV
Figure 5. Spectrum of TO-bitD/A Operating at 11MHz Update
Rate With Deglitching - Unfiltered
I
16
MSB
BIT 1
I
I
I
DIGITAL I
INPUTS
I
I
I
I
I
BIT10
LSB
-REF OUT
19
DIAOUTPUT
10k
OEGLITCHER
GAINADJ
INPUT
21
75f! OUTPUT
n
son OUTPUT
23
DIGITAL
INPUTS
lk
93n OUTPUT
13
STROBE
INPUT
MSB
BIT 1
OFFSET ADJ
25k
15
IS
OFFSET
ADJ
+REF OUT
SELECT OUTPUT
TO MATCH 20 OF
TRANSMISSION
LINE
}
LO 2 OUTPUT
75On
I
I
I
I
I
I
I
I
BIT 10
LSB
13
STROBE
INPUT
115
-REF OUT
19
DIA OUTPUT
0 TO +2V
DEGLITCHER
INPUT
750n
18
20
93n OUTPUT
21
75'1 OUTPUT
22
son OUTPUT
23
LO Z OUTPUT
24
AMPLIFIER
FEEDBACK
SELECT
OUTPUT
TOMATCH
}
Zo OF
LINE
TRANSMISSION
RGAON
Cee
VL ~OTO+1V
NOTES,
,. SELECT RGAINTO
Figure 6. Unipolar Output Configuration Basic Versions
GIVE DESIRED OPEN CIRCUIT OUTPUT VOLTAGE. THE INPUT
VOLTAGE
TO THE DP AMP IS APPROXIMATELY
0 TO +2V. THE OUTPUT OF THE
OP AMP IS THEREFORE ((2 x RGAINII5OO'I1VOLTS p.p.
2. THE LOGIC IS INVERTED INTERNALLY FOR THE "A" VERSIONS SUCH THAT ALL
"I'S" AT THE DIGITAL INPUTS YIELDS A FULL.SCALE POSITIVE VOLTAGE AT THE
DIGITAL
INPUTS
15
MSB
BIT1
I
I
I
I
I
I
I
I
I
SIT 10
LSB
MDD.l02O
DEGLITCHED
DIA
DP AMP OUTPUT.
-REF OUT
OFFSET ADJ
soon
ADJUST FOR ZERO VOLTS
OUTPUT WITH AN INPUT
CODEOFloo
00
19
DIA OUTPUT
18
DEGLITCHER INPUT
GAIN ADJ
13
20
21
93!! OUTPUT
75n OUTPUT
22
son OUTPUT
23
LO Z OUTPUT
O
0
SELECT OUTPUT
.
}
UNIPOLAR OPERATION, THE NOMINAL OFFSET
RESISTANCE SHOULD BE SET FOR A VALUE
A 2000!! POTENTIOMETER
IDEAL
OF APPROXIMATEL
POTENTIOMETER
Y 800'1. MAKING
4. FOR BIPOLAR OPERATION,
THE NOMINAL OFFSET POTENTIOMETER
RESISTANCE
SHOULD BE SET FOR A VALUE OF APPROXIMATELY
2300<2, MAKING A 5000!!
POTENTIOMETER
IDEAL THE OUTPUT VOLTAGE SHOULD BE ADJUSTED
FOR ZERO
WITH ANINPUT
CODEOF10. . . . . . . . 00.
5. MAKECFBNOMINALLY IOpF. SELECT FOR OPTIMUM SETTLING TIME IF DESIRED.
6. IF ADJUSTABLE
GAIN IS DESIRED, ADD A LOW-VALUE,
LDW.INDUCTANCE
CERMET
TRIMMING
POTENTIOMETER
IN SERIES WITH RGAIN' BY PUTTING THE GAIN ADJUSTMENT
HERE, THE GAIN AND OFFSET ADJUSTMENTS
ARE INDEPENDENT OF EACH OTHER.
51<
OBS
STROBE
INPUT
CONVERTER.
3. FOR POSITIVE
TO MA"rCHZo OF
TRANSMISSION
LINE
Figure 8. Output Configuration - "A" Versions
VL ' -0.5V TO +0.5V
OLE
Figure 7. Bipolar Output Configuration Basic Versions
ANALOG
INPUT
ANALOG
GROUND
ENCODE
COMMAND
INPUT
9
ENCODE
GROUND
+15V
-15V
+5V
-5.2V
2
MATV-OSll
AID
12
CONVERTER
~
I
15
TE
DIGITAL
SIGNAL
PROCESSOR,
MEMORY
INTERFACE,
ETC.
CFB
10pF
DATA
.
GAIN AOJ
2k
11 11 10122 READY
OUT
+5V
Figure 9. Typical A/D-D/A Back-to-Back
for Video Applications or Testing
The typical video differential phase and gain errors (disregarding quantization effects) for the configuration shown are
3° and 3%, respectively, using an encode command frequency
of three times the NTSC color subcarrier (l0.74MHz). For
applications requiring digitization at frequencies of four times
NTSC (14.32MHz) or three times PAL (13.29MHz) the
MATV-0816.A/D
Converter should be substituted. For applications requiringdigitization
at four times PAL (17. 74MHz),
the MATV-0820 AID Converter should be substituted. Results
are applicable for either NTSC or PAL test signals using the
20 IRE modulated ramp.
Due to the inherently stable characteristics of the output operational amplifier, the "A" versions are recommended for
driving properly terminated video terminated lines.
VOL. II, 10-42 DIGITAL-TO-ANALOG CONVERTERS
--
~-
Connections
ORDERING INFORMA nON
For 8-Bit Models,
Order:
MDD-Q826 without output amplifier
MDD-Q820A with output amplifier
For lO-Bit Models,
Order:
MDD-1020
without output amplifier
MDD-1020A with output amplifier
Mating pin socket connectors for the MDD Series is model
MSB-2. Prototyping socket is MSD-l.
The MDD Series D/A"s are normally burned-in at +2SoC for a
minimum of 96 hours. For extended burn-in, consult the
factory. All of Analog Devices' data acquisition products are
covered by a one-year warranty.