Product Folder Order Now Support & Community Tools & Software Technical Documents OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 OPAx170 36-V, Single-Supply, SOT553, Low-Power Operational Amplifiers Value Line Series 1 Features 3 Description • • • • • • • • • • • The OPA170, OPA2170, and OPA4170 devices (OPAx170) are a family of 36-V, single-supply, lownoise operational amplifiers (op amps) that feature micro packages with the ability to operate on supplies ranging from 2.7 V (±1.35 V) to 36 V (±18 V). They offer good offset, drift, and bandwidth with low quiescent current. The single, dual, and quad versions all have identical specifications for maximum design flexibility. 1 • Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V Low Noise: 19 nV/√Hz RFI Filtered Inputs Input Range Includes the Negative Supply Input Range Operates to Positive Supply Rail-to-Rail Output Gain Bandwidth: 1.2 MHz Low Quiescent Current: 110 µA per Amplifier High Common-Mode Rejection: 120 dB Low Bias Current: 15 pA (Maximum) Industry-Standard Packages and micro Packages Available Create a Custom Design Using the OPAx170 With the WEBENCH® Power Designer 2 Applications • • • • • • • • • Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment Unlike most op amps, which are specified at only one supply voltage, the OPAx170 family of op amps is specified from 2.7 V to 36 V. Input signals beyond the supply rails do not cause phase reversal. The OPAx170 family is stable with capacitive loads up to 300 pF. The input can operate 100 mV below the negative rail and within 2 V of the positive rail for normal operation. Note that these devices can operate with full rail-to-rail input 100 mV beyond the positive rail, but with reduced performance within 2 V of the positive rail. The OPAx170 op amps are specified from –40°C to +125°C. Device Information(1) PART NUMBER OPA170 OPA2170 OPA4170 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOT (5) 1.60 mm × 1.20 mm SOT-23 (5) 2.90 mm × 1.60 mm SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm VSSOP (8), micro size 2.30 mm × 2.00 mm WSON (8) 2.00 mm × 2.00 mm SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Smallest Packaging for 36-V Operational Amplifiers Package Footprint Comparison (to Scale) Package Height Comparison (to Scale) D (SO-8) DBV (SOT23-5) DRL (SOT553) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 3 4 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information: OPA170 .................................. 8 Thermal Information: OPA2170 ................................ 8 Thermal Information: OPA4170 ................................ 8 Electrical Characteristics........................................... 9 Typical Characteristics ............................................ 11 Detailed Description ............................................ 18 8.1 Overview ................................................................. 18 8.2 Functional Block Diagram ...................................... 18 8.3 Feature Description................................................. 18 8.4 Device Functional Modes........................................ 22 9 Application and Implementation ........................ 23 9.1 Application Information............................................ 23 9.2 Typical Application .................................................. 23 10 Power Supply Recommendations ..................... 26 11 Layout................................................................... 26 11.1 Layout Guidelines ................................................. 26 11.2 Layout Example .................................................... 26 12 Device and Documentation Support ................. 28 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 29 29 29 29 30 30 30 13 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2016) to Revision D Page • Added WEBENCH links and sections and Receiving Notification of Documentation Updates.............................................. 1 • Added 8-Pin DSG (WSON) package...................................................................................................................................... 1 • Changed values in Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application from: 250 Ω to: 2.5 Ω........ 20 Changes from Revision B (September 2012) to Revision C Page • Added current package designators to Features list and final paragraph of Description section .......................................... 1 • Added Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1 Changes from Revision A (September 2011) to Revision B • 2 Page Added "Value Line Series" to document title.......................................................................................................................... 1 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 5 Device Comparison Table DEVICE NO OF CHANNELS PACKAGE-LEAD SOT SOT23-5 D DSG VSSOP VSSOP (micro size) TSSOP — OPA170 1 5 5 8 — — — OPA2170 2 — — 8 8 8 8 — OPA4170 4 — — 14 — — — 14 Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 3 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 6 Pin Configuration and Functions OPA170: DRL Package 5-Pin SOT Top View IN+ 1 V- 2 IN- 3 5 4 OPA170: DBV Package 5-Pin SOT-23 Top View V+ OUT 1 V- 2 +IN 3 5 V+ 4 -IN OUT OPA170: D Package 8-Pin SOIC Top View NC(1) 1 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) Pin Functions: OPA170 PIN NAME I/O DESCRIPTION SOT SOT-23 D IN– (–IN) 3 4 2 I Negative (inverting) input IN+ (+IN) 1 3 3 I Positive (noninverting) input (1) NC — — 1, 5, 8 — No internal connection (can be left floating) OUT 4 1 6 O Output V+ 5 5 7 — Positive (highest) power supply V– 2 2 4 — Negative (lowest) power supply (1) 4 NC indicates no internal connection. Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 OPA2170: D, DGK, and DCU Packages 8-Pin VSSOP, SOIC, and VSSOP (micro size) Top View OUT A 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B OPA2170: DSG Package 8-Pin WSON Top View OUT A 1 ±IN A 2 +IN A 3 V± 4 Thermal Pad 8 V+ 7 OUT B 6 ±IN B 5 +IN B Pin Functions: OPA2170 PIN NAME SOIC VSSOP VSSOP (micro size) WSON –IN A 2 2 2 2 I Inverting input, channel A –IN B 6 6 6 6 I Inverting input, channel B +IN A 3 3 3 3 I Noninverting input, channel A +IN B 5 5 5 5 I Noninverting input, channel B OUT A 1 1 1 1 O Output, channel A OUT B 7 7 7 7 O Output, channel B V– 4 4 4 4 — Negative (lowest) power supply V+ 8 8 8 8 — Positive (highest) power supply I/O DESCRIPTION Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 5 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com OPA4170: D and PW Packages 14-Pin SOIC and TSSOP Top View OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C Pin Functions: OPA4170 PIN I/O DESCRIPTION NAME SOIC TSSOP –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B –IN C 9 9 I Inverting input, channel C –IN D 13 13 I Inverting input, channel D +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C 10 10 I Noninverting input, channel C +IN D 12 12 I Noninverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C 8 8 O Output, channel C OUT D 14 14 O Output, channel D V– 11 11 — Negative (lowest) power supply V+ 4 4 — Positive (highest) power supply 6 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted. (1) MIN MAX UNIT –20 20 V 40 V Signal input pin voltage (V–) – 0.5 (V+) + 0.5 V Signal input pin current –10 10 mA 150 °C 150 °C 150 °C Supply voltage Single supply voltage Output short-circuit current (2) Continuous Operating ambient temperature, TA –55 Junction temperature, TJ Storage temperature, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage (V+ – V–) 2.7 36 V TA Operating temperature –40 125 °C Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 7 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 7.4 Thermal Information: OPA170 OPA170 THERMAL METRIC (1) D (SOIC) DBV (SOT-23) DRL (SOT) 8 PINS 5 PINS 5 PINS UNIT 208.1 °C/W RθJA Junction-to-ambient thermal resistance 149.5 245.8 RθJC(top) Junction-to-case (top) thermal resistance 97.9 133.9 0.1 °C/W RθJB Junction-to-board thermal resistance 87.7 83.6 42.4 °C/W ψJT Junction-to-top characterization parameter 35.5 18.2 0.5 °C/W ψJB Junction-to-board characterization parameter 89.5 83.1 42.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Thermal Information: OPA2170 OPA2170 THERMAL METRIC (1) D (SOIC) DCU (VSSOP, micro size) DGK (VSSOP) DSG (WSON) UNIT 8 PINS 8 PINS 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 134.3 175.2 180 71.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 72.1 74.9 55 89.1 °C/W RθJB Junction-to-board thermal resistance 60.6 22.2 130 38.8 °C/W ψJT Junction-to-top characterization parameter 18.2 1.6 5.3 3.8 °C/W ψJB Junction-to-board characterization parameter 53.8 22.8 120 38.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — 13 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.6 Thermal Information: OPA4170 OPA4170 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 7.7 Electrical Characteristics at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 ±1.8 mV OFFSET VOLTAGE TA = 25°C VOS Input offset voltage dVOS/dT Input offset voltage drift TA = –40°C to +125°C PSRR Input offset voltage vs power supply VS = 4 V to 36 V, TA = –40°C to +125°C TA = –40°C to +125°C Channel separation, dc ±2 mV ±0.3 ±2 µV/°C 1 ±5 µV/V 5 µV/V INPUT BIAS CURRENT IB Input bias current IOS Input offset current TA = 25°C ±8 TA = –40°C to +125°C TA = 25°C ±4 TA = –40°C to +125°C ±15 pA ±3.5 nA ±15 pA ±3.5 nA NOISE Input voltage noise en Input voltage noise density ƒ = 0.1 Hz to 10 Hz 2 µVPP ƒ = 100 Hz 22 nV/√Hz ƒ = 1 kHz 19 nV/√Hz INPUT VOLTAGE Common-mode voltage range (1) VCM CMRR Common-mode rejection ratio (V–) – 0.1 (V+) – 2 V VS = ±2 V, (V–) - 0.1 V < VCM < (V+) - 2 V, TA = –40°C to +125°C 90 104 dB VS = ±18 V, (V–) - 0.1 V < VCM < (V+) - 2 V, TA = –40°C to +125°C 104 120 dB INPUT IMPEDANCE Differential 100 || 3 Common-mode MΩ || pF 6 || 3 1012 Ω || pF 130 dB OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 4 V to 36 V, (V–) + 0.35 V < VO < (V+) - 0.35 V, TA = –40°C to +125°C 110 FREQUENCY RESPONSE GBP Gain bandwidth product SR Slew rate tS THD+N (1) 1.2 MHz G = +1 0.4 V/µs To 0.1%, VS = ±18 V, G = +1, 10-V step 20 µs Settling time To 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step 28 µs Overload recovery time VIN × Gain > VS 2 µs Total harmonic distortion + noise G = +1, ƒ = 1 kHz, VO = 3 VRMS 0.0002% The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation sections for additional information. Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 9 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com Electrical Characteristics (continued) at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO VO Voltage output swing from positive rail Voltage output swing from negative rail VO Voltage output swing from rail ISC Short-circuit current CLOAD Capacitive load drive RO Open-loop output resistance IL = 0 mA, VS = 4 V to 36 V 10 IL sourcing 1 mA, VS = 4 V to 36 V mV 115 mV IL = 0 mA, VS = 4 V to 36 V IL sinking 1 mA, VS = 4 V to 36 V 8 mV 70 mV VS = 5 V, RL = 10 kΩ; TA = –40°C to +125°C (V–) + 0.03 (V+) – 0.05 V RL = 10 kΩ, AOL ≥ 110 dB, TA = –40°C to +125°C (V–) + 0.35 (V+) – 0.35 V –20 17 See Typical Characteristics ƒ = 1 MHz, IO = 0 A mA pF 900 Ω POWER SUPPLY VS IQ Specified voltage range Quiescent current per amplifier 2.7 IO = 0 A; TA = 25°C 110 IO = 0 A; TA = –40°C to +125°C 36 V 145 µA 155 µA TEMPERATURE 10 Specified range –40 125 °C Operating range –55 150 °C Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 7.8 Typical Characteristics VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted. Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4 Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5 Offset Voltage vs Power Supply Figure 6 IB and IOS vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to-Input) Figure 10 CMRR vs Temperature Figure 11 PSRR vs Temperature Figure 12 0.1-Hz to 10-Hz Noise Figure 13 Input Voltage Noise Spectral Density vs Frequency Figure 14 THD+N Ratio vs Frequency Figure 15 THD+N vs Output Amplitude Figure 16 Quiescent Current vs Temperature Figure 17 Quiescent Current vs Supply Voltage Figure 18 Open-Loop Gain and Phase vs Frequency Figure 19 Closed-Loop Gain vs Frequency Figure 20 Open-Loop Gain vs Temperature Figure 21 Open-Loop Output Impedance vs Frequency Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 22 Figure 23, Figure 24 No Phase Reversal Figure 25 Positive Overload Recovery Figure 26 Negative Overload Recovery Figure 27 Small-Signal Step Response (100 mV) Figure 28, Figure 29 Large-Signal Step Response Figure 30, Figure 31 Large-Signal Settling Time (10-V Positive Step) Figure 32 Large-Signal Settling Time (10-V Negative Step) Figure 33 Short-Circuit Current vs Temperature Figure 34 Maximum Output Voltage vs Frequency Figure 35 EMIRR IN+ vs Frequency Figure 36 Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 11 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 25 20 Distribution Taken From 400 Amplifiers Distribution Taken From 104 Amplifiers Percentage of Amplifiers (%) Percentage of Amplifiers (%) 18 16 14 12 10 8 6 4 20 15 10 5 2 0 −1200 −1100 −1000 −900 −800 −700 −600 −500 −400 −300 −200 −100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 0 Offset Voltage (µV) Offset Voltage Drift (µV/°C) G001 Figure 1. Offset Voltage Production Distribution G002 Figure 2. Offset Voltage Drift Distribution 1000 800 5 Typical Units Shown Offset Voltage (mV) Offset Voltage (µV) 600 400 200 0 −200 −400 VCM = - 18.1V −600 −800 −1000 −50 −25 0 25 50 75 Temperature (°C) 100 125 150 Common-Mode Voltage (V) G003 Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage 500 VSUPPLY = ±1.35V to ± 18V 5 Typical Units Shown 5 Typical Units Shown Offset Voltage (µV) Offset Voltage (mV) 300 Normal Operation 100 −100 −300 −500 0 2 4 Common-Mode Voltage (V) Figure 5. Offset Voltage vs Common-Mode Voltage (Upper Stage) 12 Submit Documentation Feedback 6 8 10 12 VSUPPLY (V) 14 16 18 20 G006 Figure 6. Offset Voltage vs Power Supply Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 12 2000 IB+ +IB IOS Input Bias Current (pA) IB and IOS (pA) IB- 1500 10 8 6 IOS 4 1000 500 0 -IB -500 2 VCM = 16.1V VCM = -18.1V -1000 0 -20 -15 -10 0 VCM (V) -5 5 10 15 -75 20 -25 0 50 75 100 125 150 Figure 8. Input Bias Current vs Temperature Figure 7. IB and IOS vs Common-Mode Voltage 140 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 17 16 15 14.5 -14.5 -15 -40°C +25°C +125°C -16 -17 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 -18 0 1 2 3 4 5 6 7 8 9 1 10 10 100 1k 10k 100k 1M Frequency (Hz) Output Current (mA) Figure 9. Output Voltage Swing vs Output Current (Maximum Supply) Figure 10. CMRR and PSRR vs Frequency (Referred-to Input) 3 30 VS = ±1.35V VS = ±2V 25 VS = ±18V 20 15 10 5 0 -75 -50 -25 0 25 50 75 100 125 150 Power−Supply Rejection Ratio (µV/V) Common-Mode Rejection Ratio (mV/V) 25 Temperature (°C) 18 Output Voltage (V) -50 2 1 0 −1 −2 −3 −75 VS = 2.7V to 36V VS = 4V to 36V −50 −25 Temperature (°C) Figure 11. CMRR vs Temperature 0 25 50 75 Temperature (°C) 100 125 150 G012 Figure 12. PSRR vs Temperature Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 13 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 1mV/div Voltage Noise Density (nV/ Hz) 1000 100 10 1 Figure 13. 0.1-Hz to 10-Hz Noise -120 0.0001 1k 1k 10k Frequency (Hz) -140 100k 10k 0.1 Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) -100 0.001 100 100 100k 1M G014 BW = 80kHz G = +1 RL = 10kW -60 0.01 -80 0.001 -100 0.0001 -120 0.00001 0.01 0.1 1 10 Total Harmonic Distortion + Noise (dB) -80 VOUT = 3VRMS BW = 80kHz G = +1 RL = 10kW 0.00001 10 10 Figure 14. Input Voltage Noise Spectral Density vs Frequency Total Harmonic Distortion + Noise (dB) 0.01 1 -140 20 Output Amplitude (VRMS) Frequency (Hz) Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude 140 130 VS = ±18V 120 IQ (µA) IQ (PA) 110 100 90 80 VS = ±1.35V 70 60 -50 -25 0 25 50 75 Temperature (qC) 100 125 150 Figure 17. Quiescent Current vs Temperature 14 Submit Documentation Feedback G017 Figure 18. Quiescent Current vs Supply Voltage Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 140 135 120 90 Gain 100 40 45 30 0 -45 Phase (°) Phase 60 Gain (dB) 80 Gain (dB) 50 20 40 -90 20 -135 0 -180 -20 -225 −10 -270 10M −20 -40 0.1 1 10 100 1k 10k 100k 1M 10 0 G = −1 G=1 G = 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 19. Open-Loop Gain and Phase vs Frequency 10M 100M G020 Figure 20. Closed-Loop Gain vs Frequency 10k 3 VS = 2.7V VS = 4V 2.5 1k VS = 36V ZO (W) AOL (mV/V) 2 1.5 100 10 1 1 0.5 1m 0 -75 -50 -25 0 25 50 75 100 125 150 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Temperature (°C) Figure 21. Open-Loop Gain vs Temperature W Figure 22. Open-Loop Output Impedance vs Frequency W G = +1 +18V RI = 10kW RF = 10kW ROUT W W W -18V G = -1 +18V OPA170 RL W W W CL 100-mV output step Figure 23. Small-Signal Overshoot vs Capacitive Load ROUT OPA170 CL -18V 100-mV output step Figure 24. Small-Signal Overshoot vs Capacitive Load Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 15 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com +18V OPA170 20kW 5V/div 5V/div -18V 37VPP Sine Wave (±18.5V) +18V 2kW OPA170 VOUT VIN -18V G = -10 Time (100ms/div) Time (10ms/div) Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery 20kW 2kW RL = 10kW CL = 10pF +18V OPA170 VOUT VIN 5V/div G = -10 20mV/div -18V +18V OPA170 -18V Time (10ms/div) RL CL Time (5ms/div) Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV) G = +1 RL = 10kW CL = 10pF RI = 2kW RF 2V/div RL = 10kW CL = 10pF 20mV/div G = +1 = 2kW +18V OPA170 CL -18V G = -1 Time (50ms/div) Time (5ms/div) Figure 29. Small-Signal Step Response (100 mV) 16 Submit Documentation Feedback Figure 30. Large-Signal Step Response Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 10 G = -1 RL = 10kW CL = 10pF 2V/div D From Final Value (mV) 8 6 4 12-Bit Settling 2 0 -2 (±1/2LSB = ±0.012%) -4 -6 -8 -10 0 Time (50ms/div) 10 20 30 40 50 60 70 80 90 100 Time (ms) 10-V positive step Figure 32. Large-Signal Settling Time Figure 31. Large-Signal Step Response 10 G = -1 6 4 12-Bit Settling 2 ISC (mA) D From Final Value (mV) 8 0 -2 (±1/2LSB = ±0.012%) -4 -6 -8 -10 0 10 20 30 40 50 60 30 25 20 15 10 5 0 −5 −10 −15 −20 −25 −30 −50 ISC, Source ISC, Sink −25 0 25 50 75 Temperature (°C) Time (ms) 100 125 150 G034 10-V negative step Figure 33. Large-Signal Settling Time Figure 34. Short-Circuit Current vs Temperature 15 140 VS = ±15 V 120 Maximum output range without slew−rate induced distortion 10 EMIRR IN+ (dB) Output Voltage (VPP ) 12.5 7.5 VS = ±5 V 5 2.5 0 10k 80 60 40 PRP = -10dBm VS = ±18V VCM = 0V 20 VS = ±1.35 V 1k 100 100k Frequency (Hz) 1M 10M Figure 35. Maximum Output Voltage vs Frequency 0 10M 100M 1G 10G Frequency (Hz) G035 Figure 36. EMIRR IN+ vs Frequency Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 17 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 8 Detailed Description 8.1 Overview The OPAx170 family of operational amplifiers provides high overall performance, making them ideal for many general-purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL. 8.2 Functional Block Diagram PCH FF Stage Ca Cb +IN PCH Input Stage Output Stage 2nd Stage OUT -IN NCH Input Stage 8.3 Feature Description 8.3.1 Operating Characteristics The OPAx170 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. 18 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 Feature Description (continued) 8.3.2 Phase-Reversal Protection The OPAx170 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx170 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 37. +18V OPA170 5V/div -18V 37VPP Sine Wave (±18.5V) Time (100ms/div) Figure 37. No Phase Reversal 8.3.3 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 38 illustrates the ESD circuits contained in the OPAx170 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 19 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com Feature Description (continued) TVS + ± RF +VS R1 IN± 2.5 NŸ RS IN+ 2.5 NŸ + Power-Supply ESD Cell ID VIN RL + ± + ± ±VS TVS Figure 38. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx170 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit (refer to Figure 38), the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device. Figure 38 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. 20 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 Feature Description (continued) Another common question involves what happens to the amplifier if an input signal is applied to the input when the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the supply pins; see Figure 38. Select the Zener voltage so that the diode does not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe-operating, supply-voltage level. The OPAx170 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure 38. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the input signal current. This input series resistor degrades the low-noise performance of the OPAx170. Figure 38 illustrates an example configuration that implements a current-limiting feedback resistor. 8.3.4 Capacitive Load and Stability The dynamic characteristics of the OPAx170 have been optimized for common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Refer to Figure 39 and Figure 40 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to applications bulletin AB-028, Feedback Plots Define Op Amp AC Performance, for details of analysis techniques and application circuits. W W G = +1 +18V RI = 10kW RF = 10kW ROUT W W W 100-mV Output Step -18V G = -1 +18V OPA170 RL G=1 Figure 39. Small-Signal Overshoot vs Capacitive Load ROUT W W W CL 100-mV Output Step OPA170 CL -18V G = –1 Figure 40. Small-Signal Overshoot vs Capacitive Load Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 21 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 8.4 Device Functional Modes 8.4.1 Common-Mode Voltage Range The input common-mode voltage range of the OPAx170 series extends 100 mV below the negative rail and within 2 V of the top rail for normal operation. This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is summarized in Table 2. Table 2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply PARAMETER MIN Input common-mode voltage Offset voltage TYP (V+) – 2 MAX (V+) + 0.1 vs temperature Common-mode rejection UNIT V 7 mV 12 µV/°C 65 dB Open-loop gain 60 dB Gain-bandwidth product 0.3 MHz Slew rate 0.3 V/µs 8.4.2 Overload Recovery Overload recovery is defined as the time required for the operational amplifier output to recover from the saturated state to the linear state. The output devices of the operational amplifier enter the saturation region when the output voltage exceeds the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices need time to return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx170 is approximately 2 µs. 22 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The OPAx170 family of operational amplifiers provides high overall performance in a large number of generalpurpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional recommendations in Layout Guidelines in order to achieve the maximum performance from this device. Many applications may introduce capacitive loading to the output of the amplifier (potentially causing instability). One method of stabilizing the amplifier in such applications is to add an isolation resistor between the amplifier output and the capacitive load. The design process for selecting this resistor is given in Typical Application. 9.2 Typical Application This circuit can be used to drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses an isolation resistor (Riso) to stabilize the output of an operational amplifier. Riso modifies the open-loop gain of the system to ensure the circuit has sufficient phase margin. +VS VOUT RISO + VIN + ± CLOAD -VS Figure 41. Unity-Gain Buffer With RISO Stability Compensation 9.2.1 Design Requirements The design requirements are: • Supply voltage: 30 V (±15 V) • Capacitive loads: 100 pF, 1000 pF, 0.01 µF, 0.1 µF, and 1 µF • Phase margin: 45° and 60° 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the OPAx170 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 23 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com Typical Application (continued) • • • Run thermal simulations to understand board thermal performance Export customized schematic and layout into popular CAD formats Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.2.2 Unity-Gain Buffer Figure 41 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 41. Not shown in Figure 41 is the open-loop output resistance of the operational amplifier, Ro. 1 + CLOAD × RISO × s T(s) = 1 + Ro + RISO × CLOAD × s (1) The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB/decade. Figure 42 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB. 120 AOL 100 1 fp 2 u Œ u RISO Gain (dB) 80 60 Ro u CLOAD 40 dB fz 40 1 2 u Œ u RISO u CLOAD 1 dec 1/ 20 ROC 20 dB dec 0 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 42. Unity-Gain Amplifier With RISO Compensation ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and ac gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3 shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can be used in place of the OPA170, see the Precision Design, Capacitive Load Drive Solution Using an Isolation Resistor. Table 3. Phase Margin versus Overshoot and AC Gain Peaking 24 PHASE MARGIN OVERSHOOT AC GAIN PEAKING 45° 23.3% 2.35 dB 60° 8.8% 0.28 dB Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 9.2.3 Application Curve Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various capacitive loads were determined. The results are shown in Figure 43. 10000 45° Phase Margin Isolation Resistor (RISO, ) 60° Phase Margin 1000 100 10 0.1 1 10 100 Capacitive Load (nF) 1000 C002 Figure 43. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 25 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 10 Power Supply Recommendations The OPAx170 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see application report SLOA089, Circuit Board Layout Techniques. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than in parallel with the noisy trace. • Place the external components as close to the device as possible. As illustrated in Figure 45, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 11.2 Layout Example + VIN VOUT RG RF Figure 44. Schematic Representation 26 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 Layout Example (continued) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C Use a low-ESR, ceramic bypass capacitor RG GND ±IN V+ VIN +IN OUTPUT V± N/C GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Copyright © 2017, Texas Instruments Incorporated Figure 45. Operational Amplifier Board Layout for a Noninverting Configuration Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 27 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.1.2 Development Support 12.1.2.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 12.1.2.2 DIP Adapter EVM The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits. 12.1.2.3 Universal Operational Amplifier EVM The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits for a variety of IC package types. The evaluation module board design allows many different circuits to be constructed easily and quickly. Five models are offered, with each model intended for a specific package type. PDIP, SOIC, MSOP, TSSOP and SOT23 packages are all supported. NOTE These boards are unpopulated, so users must provide their own ICs. TI recommends requesting several op amp device samples when ordering the Universal Op Amp EVM. 12.1.2.4 TI Precision Designs TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. 28 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 OPA170, OPA2170, OPA4170 www.ti.com SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 Device Support (continued) 12.1.2.5 WEBENCH® Filter Designer WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. 12.1.2.6 Custom Design With WEBENCH® Tools Click here to create a custom design using the OPAx170 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following (available for download from www.ti.com): • Feedback Plots Define Op Amp AC Performance • Capacitive Load Drive Solution Using an Isolation Resistor • Circuit Board Layout Techniques 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 4. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA170 Click here Click here Click here Click here Click here OPA2170 Click here Click here Click here Click here Click here OPA4170 Click here Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 Submit Documentation Feedback 29 OPA170, OPA2170, OPA4170 SBOS557D – AUGUST 2011 – REVISED OCTOBER 2017 www.ti.com Community Resources (continued) TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.6 Trademarks TINA-TI, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated Product Folder Links: OPA170 OPA2170 OPA4170 PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA170AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O170A OPA170AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSVI OPA170AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSVI OPA170AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O170A OPA170AIDRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAQ OPA170AIDRLT ACTIVE SOT-5X3 DRL 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAQ OPA2170AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2170A OPA2170AIDCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPQC OPA2170AIDCUT ACTIVE VSSOP DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPQC OPA2170AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPNI OPA2170AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPNI OPA2170AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2170A OPA2170AIDSGR ACTIVE WSON DSG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1D4U OPA2170AIDSGT ACTIVE WSON DSG 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1D4U OPA4170AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4170 OPA4170AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4170 OPA4170AIPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4170 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Feb-2018 Status (1) OPA4170AIPWR ACTIVE Package Type Package Pins Package Drawing Qty TSSOP PW 14 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) -40 to 125 OPA4170 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF OPA170, OPA2170, OPA4170 : • Automotive: OPA170-Q1, OPA2170-Q1, OPA4170-Q1 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2018 • Enhanced Product: OPA170-EP NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) OPA170AIDBVR SOT-23 DBV 5 3000 179.0 8.4 OPA170AIDBVR SOT-23 DBV 5 3000 180.0 OPA170AIDBVT SOT-23 DBV 5 250 179.0 OPA170AIDBVT SOT-23 DBV 5 250 OPA170AIDR SOIC D 8 OPA170AIDRLR SOT-5X3 DRL OPA170AIDRLT SOT-5X3 DRL OPA2170AIDCUR VSSOP W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.23 3.17 1.37 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 5 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 OPA2170AIDCUT VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 OPA2170AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2170AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2170AIDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 OPA2170AIDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 OPA4170AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4170AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA170AIDBVR SOT-23 DBV 5 3000 195.0 200.0 45.0 OPA170AIDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0 OPA170AIDBVT SOT-23 DBV 5 250 195.0 200.0 45.0 OPA170AIDBVT SOT-23 DBV 5 250 202.0 201.0 28.0 OPA170AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA170AIDRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0 OPA170AIDRLT SOT-5X3 DRL 5 250 202.0 201.0 28.0 OPA2170AIDCUR VSSOP DCU 8 3000 202.0 201.0 28.0 OPA2170AIDCUT VSSOP DCU 8 250 202.0 201.0 28.0 OPA2170AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 OPA2170AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA2170AIDSGR WSON DSG 8 3000 210.0 185.0 35.0 OPA2170AIDSGT WSON DSG 8 250 210.0 185.0 35.0 OPA4170AIDR SOIC D 14 2500 367.0 367.0 38.0 OPA4170AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DSG0008A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 A B PIN 1 INDEX AREA 2.1 1.9 0.3 0.2 0.4 0.2 OPTIONAL TERMINAL TYPICAL C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C EXPOSED THERMAL PAD (0.2) TYP 0.9 0.1 5 4 6X 0.5 2X 1.5 SEE OPTIONAL TERMINAL 9 8 1 PIN 1 ID 1.6 0.1 8X 0.4 8X 0.2 0.3 0.2 0.1 0.05 C A B C 4218900/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DSG0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.9) 8X (0.5) ( 0.2) VIA TYP 1 8 8X (0.25) (0.55) SYMM 9 (1.6) 6X (0.5) 5 4 SYMM (R0.05) TYP (1.9) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4218900/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DSG0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 8X (0.5) SYMM METAL 1 8 8X (0.25) (0.45) SYMM 9 (0.7) 6X (0.5) 5 4 (R0.05) TYP (0.9) (1.9) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4218900/B 09/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated