TI1 ADS41B29IRGZ25 Ultralow-power adc Datasheet

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ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers
1 Features
•
1
•
•
•
•
•
•
•
•
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ADS41B49: 14-Bit, 250 MSPS
ADS41B29: 12-Bit, 250 MSPS
Integrated High-Impedance
Analog Input Buffer:
– Input Capacitance: 2 pF
– 200-MHz Input Resistance: 3 kΩ
Maximum Sample Rate: 250 MSPS
Ultralow Power:
– 1.8-V Analog Power: 180 mW
– 3.3-V Buffer Power: 96 mW
– I/O Power: 135 mW (DDR LVDS)
High Dynamic Performance:
– SNR: 69 dBFS at 170 MHz
– SFDR: 82.5 dBc at 170 MHz
Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350 mV
– Low Swing: 200 mV
– Default Strength: 100-Ω Termination
– 2x Strength: 50-Ω Termination
– 1.8-V Parallel CMOS Interface Also Supported
Programmable Gain for SNR, SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: VQFN-48 (7 mm × 7 mm)
The ADS41Bx9 have features such as digital gain
and offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
The devices support both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500 MBPS)
makes using low-cost field-programmable gate array
(FPGA)-based receivers possible. The devices have
a low-swing LVDS mode that can be used to further
reduce the power consumption. The strength of the
LVDS output buffers can also be increased to support
50-Ω differential termination.
Device Information(1)
PART NUMBER
ADS41Bx9
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ADS41B49 Block Diagram
AVDD
AGND
DRVDD
DDR LVDS
Interface
DRGND
CLKP
CLKOUTP
CLOCKGEN
CLKOUTM
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
AVDD_BUF
D2_D3_M
2 Applications
D4_D5_P
INP
•
•
•
Power Amplifier Linearization
Software Defined Radio
Wireless Communications Infrastructure
Common
Digital Functions
14-Bit
ADC
Sampling
Circuit
DDR
Serializer
D4_D5_M
D6_D7_P
INM
D6_D7_M
D8_D9_P
Analog Buffers
D8_D9_M
Control
Interface
Reference
VCM
D10_D11_P
3 Description
D10_D11_M
D12_D13_P
D12_D13_M
OVR_SDOUT
DFS
SEN
SCLK
SDATA
ADS41B49
RESET
The ADS41Bx9 are members of the ultralow-power
ADS4xxx analog-to-digital converter (ADC) family,
featuring integrated analog input buffers. These
devices use innovative design techniques to achieve
high dynamic performance, and consume extremely
low power. The analog input pins have buffers, with
benefits of constant performance and input
impedance across a wide frequency range. The
devices are well-suited for multi-carrier, wide
bandwidth communications applications such as PA
linearization.
OE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics: General ............................ 9
Electrical Characteristics: ADS41B29, ADS41B49 . 10
Digital Characteristics ............................................. 11
Timing Requirements: LVDS and CMOS Modes.... 12
Timing Requirements: Reset .................................. 13
Timing Requirements: LVDS Timing Across
Sampling Frequencies ............................................. 13
6.11 Timing Requirements: CMOS Timing Across
Sampling Frequencies ............................................. 13
6.12 Timing Requirements: CMOS Timing Across
Sampling Frequencies ............................................. 13
6.13 Typical Characteristics: ADS41B49 ...................... 14
6.14 Typical Characteristics: ADS41B29 ...................... 17
6.15 Typical Characteristics: General ........................... 20
6.16 Typical Characteristics: Contour ........................... 21
7
Parameter Measurement Information ................ 22
8
Detailed Description ............................................ 25
7.1 Timing Diagrams ..................................................... 22
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
25
25
26
36
38
40
Application and Implementation ........................ 48
9.1 Application Information............................................ 48
10 Power Supply Recommendations ..................... 50
10.1 Power-Supply Sequence....................................... 50
11 Layout................................................................... 50
11.1 Layout Guidelines ................................................. 50
12 Device and Documentation Support ................. 51
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
51
51
51
51
51
51
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
Changes from Revision E (July 2012) to Revision F
Page
•
Changed title and changed ADS41B49/29 to ADS41Bx9 and QFN to VQFN throughout document .................................... 1
•
Added Applications section, Device Information table, front-page figure, ESD Ratings table, Feature Description
section, Device Functional Modes section, Programming section, Register Maps section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information table ....................................................................................................................................... 1
•
Changed Pin Functions table: changed title and format ....................................................................................................... 6
•
Added Added last row to Voltage applied to input pins section in Absolute Maximum Ratings table ................................... 7
•
Changed Temperature parameters in Absolute Maximum Ratings table: changed format of Temperature section and
changed maximum specifications for TA and TJ ..................................................................................................................... 7
•
Changed TYP column header to NOM in Recommended Operating Conditions table ......................................................... 8
•
Changed Digital Outputs, TJ parameter in Recommended Operating Conditions table ........................................................ 8
•
Deleted High-Performance Modes section from Recommended Operating Conditions table ............................................... 8
•
Changed conditions of Electrical Characteristics: General table from temperature to ambient temperature ........................ 9
•
Changed conditions of Electrical Characteristics: ADS41B29, ADS41B49 table from temperature to ambient
temperature .......................................................................................................................................................................... 10
•
Added footnote 1 to Electrical Characteristics: ADS41B29, ADS41B49 table ..................................................................... 10
•
Changed conditions of Timing Requirements: LVDS and CMOS Modes table from temperature to ambient temperature 12
•
Added footnotes 6 and 7 to Timing Requirements: LVDS and CMOS Modes table............................................................ 12
•
Added footnote 1 to Timing Requirements: Reset table ..................................................................................................... 13
•
Changed title of Figure 13 and Figure 14 ............................................................................................................................ 16
•
Changed title of Figure 31 and Figure 32 ............................................................................................................................ 19
2
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SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
Revision History (continued)
•
Changed conditions of Table 6 ............................................................................................................................................ 38
•
Added Summary of High-Performance Modes section ........................................................................................................ 40
•
Changed bit registers to satisfy new standard requirements .............................................................................................. 41
Changes from Revision D (December 2010) to Revision E
Page
•
Updated Thermal Information table values............................................................................................................................. 8
•
Changed Analog Inputs, Differential input capacitance parameter typical specification in Electrical Characteristics:
General table .......................................................................................................................................................................... 9
•
Changed value of input capacitance in Analog Input section............................................................................................... 26
•
Updated Figure 54 and footnotes ......................................................................................................................................... 26
•
Changed register 25h default value in Table 7 .................................................................................................................... 40
•
Changed register 42 default and bit D3 values in Table 7 ................................................................................................... 40
•
Changed default value for Register Address 25h................................................................................................................. 42
•
Changed default and bit 3 values for Register Address 42h................................................................................................ 45
•
Updated Figure 83................................................................................................................................................................ 48
•
Updated Figure 84................................................................................................................................................................ 48
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ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
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5 Pin Configuration and Functions
(1)
4
D8_D9_M
D6_D7_P
D6_D7_M
45
44
43
42
41
D2_D3_M
D8_D9_P
46
D2_D3_P
D10_D11_M
47
D4_D5_P
D10_D11_P
48
D4_D5_M
D12_D13_P
D12_D13_M
ADS41B49 LVDS Mode: RGZ Package(1)
48-Pin VQFN
Top View
40
39
38
37
DRGND
1
36
DRGND
DRVDD
2
35
DRVDD
OVR_SDOUT
3
34
D0_D1_P
CLKOUTM
4
33
D0_D1_M
CLKOUTP
5
32
NC
DFS
6
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
15
16
17
18
19
20
21
22
23
24
AVDD
14
RESERVED
13
AVDD
AGND
AVDD_BUF
25
AVDD
AGND 12
AVDD
AVDD
AGND
26
INM
CLKM 11
AGND
SEN
INP
SDATA
27
VCM
28
AGND
9
CLKP 10
The PowerPAD™ is connected to DRGND.
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SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
D10_D11_P
D10_D11_M
D8_D9_P
D8_D9_M
D6_D7_P
D6_D7_M
D4_D5_P
D4_D5_M
D2_D3_P
D2_D3_M
D0_D1_P
D0_D1_M
ADS41B29 LVDS Mode: RGZ Package(2)
48-Pin VQFN
Top View
48
47
46
45
44
43
42
41
40
39
38
37
DRGND
1
36
DRGND
DRVDD
2
35
DRVDD
OVR_SDOUT
3
34
NC
CLKOUTM
4
33
NC
CLKOUTP
5
32
NC
DFS
6
31
NC
OE
7
30
RESET
AVDD
8
29
SCLK
AGND
15
16
17
18
19
20
21
22
23
24
AVDD
14
RESERVED
13
AVDD
AGND
AVDD
25
AVDD_BUF
AGND 12
AVDD
AVDD
AGND
26
AGND
CLKM 11
INP
SEN
INM
SDATA
27
AGND
28
VCM
9
CLKP 10
(1) The PowerPAD is connected to DRGND.
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ADS41B29, ADS41B49
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
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Pin Functions
PIN
NO.
NAME
ADS41B49
ADS41B29
I/O
AGND
9, 12, 14, 17, 19, 25
9, 12, 14, 17, 19, 25
I
Analog ground
DESCRIPTION
AVDD
8, 18, 20, 22, 24, 26
8, 18, 20, 22, 24, 26
I
1.8-V analog power supply
AVDD_BUF
21
21
I
3.3-V input buffer supply
CLKM
11
11
I
Differential clock input, negative
CLKP
10
10
I
Differential clock input, positive
CLKOUTP
5
5
O
Differential output clock, true
CLKOUTM
4
4
O
Differential output clock, complement
D0_D1_M
33
37
O
Differential output data D0 and D1 multiplexed, complement
D0_D1_P
34
38
O
Differential output data D0 and D1 multiplexed, true
D2_D3_M
37
39
O
Differential output data D2 and D3 multiplexed, complement
D2_D3_P
38
40
O
Differential output data D2 and D3 multiplexed, true
D4_D5_M
39
41
O
Differential output data D4 and D5 multiplexed, complement
D4_D5_P
40
42
O
Differential output data D4 and D5 multiplexed, true
D6_D7_M
41
43
O
Differential output data D6 and D7 multiplexed, complement
D6_D7_P
42
44
O
Differential output data D6 and D7 multiplexed, true
D8_D9_M
43
45
O
Differential output data D8 and D9 multiplexed, complement
D8_D9_P
44
46
O
Differential output data D8 and D9 multiplexed, true
D10_D11_M
45
47
O
Differential output data D10 and D11 multiplexed, complement
D10_D11_P
46
48
O
Differential output data D10 and D11 multiplexed, true
D12_D13_M
47
—
O
Differential output data D12 and D13 multiplexed, complement
D12_D13_P
48
—
O
Differential output data D12 and D13 multiplexed, true
DFS
6
6
I
Data format select input. This pin sets the DATA FORMAT (twos
complement or offset binary) and the LVDS, CMOS output interface
type.
DRGND
1, 36
1, 36
I
Digital and output buffer ground
DRVDD
2, 35
2, 35
I
1.8-V digital and output buffer supply
INM
16
16
I
Differential analog input, negative
INP
15
15
I
Differential analog input, positive
NC
31, 32
31-34
—
OE
7
7
I
Output buffer enable input, active high; this pin has an internal 100-kΩ
pull-up resistor to DRVDD.
OVR_SDOUT
3
3
O
This pin functions as an out-of-range indicator after reset, when register
bit READOUT = 0, and functions as a serial register readout pin when
READOUT = 1. This pin is a 1.8-V CMOS output pin (running off of
DRVDD).
RESERVED
23
23
I
Digital control pin, reserved for future use
Do not connect
RESET
30
30
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must
initialize through hardware RESET by applying a high pulse on this pin
or by using the software reset option; see the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default
values. In this condition, SDATA can be used as a control pin.
RESET has an internal 100-kΩ pull-down resistor.
SCLK
29
29
I
This pin functions as a serial interface clock input when RESET is low.
When RESET is high, SCLK has no function and must be tied to
ground. This pin has an internal 180-kΩ pull-down resistor
SDATA
28
28
I
This pin functions as a serial interface data input when RESET is low.
When RESET is high, SDATA functions as a STANDBY control pin (see
Table 7). This pin has an internal 180-kΩ pull-down resistor.
SEN
27
27
I
This pin functions as a serial interface enable input when RESET is low.
When RESET is high, SEN has no function and must be tied to AVDD.
This pin has an internal 180-kΩ pull-up resistor to AVDD.
VCM
13
13
O
Outputs the common-mode voltage that can be used externally to bias
the analog input pins.
6
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SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply voltage range, AVDD
–0.3
2.1
V
Supply voltage range, AVDD_BUF
–0.3
3.9
V
Supply voltage range, DRVDD
–0.3
2.1
V
Voltage between AGND and DRGND
–0.3
0.3
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
–2.4
2.4
V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
–2.4
2.4
V
Voltage between AVDD_BUF to DRVDD, AVDD
–4.2
4.2
V
INP, INM
–0.3
Minimum
(1.9, AVDD + 0.3)
CLKP, CLKM (2)
–0.3
AVDD + 0.3
RESET, SCLK, SDATA, SEN, DFS
–0.3
3.6
Operating free-air, TA
–40
125
Voltage applied to input pins
Temperature
Operating junction, TJ
Storage, Tstg
(1)
(2)
V
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When AVDD is turned off, switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|) is recommended.
Doing so prevents the ESD protection diodes at the clock input pins from turning on.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
1.7
1.8
1.9
V
3
3.3
3.6
V
1.7
1.8
1.9
V
SUPPLIES
AVDD
Analog supply voltage
AVDD_BUF
Analog buffer supply voltage
DRVDD
Digital supply voltage
ANALOG INPUTS
Differential input voltage range (1)
1.5
Input common-mode voltage
VPP
1.7 ± 0.05
V
Maximum analog input frequency with 1.5-VPP input amplitude (2)
400
MHz
Maximum analog input frequency with 1-VPP input amplitude (2)
600
MHz
CLOCK INPUT
Low-speed mode enabled (3)
20
80
MSPS
Low-speed mode disabled (3)
> 80
250
MSPS
Input clock amplitude differential (VCLKP – VCLKM)
Sine wave, ac-coupled
1.5
VPP
LVPECL, ac-coupled
0.2
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.8
Input clock duty cycle
V
Low-speed mode enabled
40%
50%
60%
Low-speed mode disabled
35%
50%
65%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
TJ
(1)
(2)
(3)
(4)
Operating junction temperature
5
pF
Ω
100
Recommended
108
Maximum rated (4)
125
°C
With 0-dB gain. See the Gain for SFDR, SNR Trade-Off section in Feature Description for the relationship between input voltage range
and gain.
See the Overview section in the Detailed Description.
See the Serial Interface section for details on the low-speed mode.
Prolonged use at this junction temperature can increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
THERMAL METRIC
ADS41B29,
ADS41B49
(1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
27.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.1
°C/W
RθJB
Junction-to-board thermal resistance
5.4
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
5.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: General
Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, and 50% clock duty cycle, unless
otherwise noted. Minimum and maximum values are across the full ambient temperature range: TA, MIN = –40°C to TA, MAX =
85°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
1.5
VPP
10
kΩ
Differential input capacitance
(see Figure 84)
3.5
pF
Analog input bandwidth
800
MHz
Differential input resistance
At dc (see Figure 83)
Analog input common-mode current
(per input pin)
VCM
2
Common-mode output voltage
µA
1.7
VCM output current capability
V
4
mA
DC ACCURACY
Offset error
–15
Temperature coefficient of offset error
EGREF
Gain error as a result of
internal reference inaccuracy alone
EGCHAN
Gain error of channel alone
2.5
15
0.003
–2
mV
mV/°C
2
2.5
%FS
%FS
POWER SUPPLY
IAVDD
Analog supply current
IAVDD_BUF Analog input buffer supply current
IDRVDD
Output buffer supply current
(2)
IDRVDD output buffer supply current (2) (3)
mA
42
mA
63
LVDS interface with 100-Ω external
termination, standard LVDS swing
(350 mV)
75
CMOS interface (3), 8-pF external load
capacitance, fIN = 2.5 MHz
35
mA
10
Standby
(3)
115
29
LVDS interface with 100-Ω external
termination, low LVDS swing (200 mV)
Global power-down
(1)
(2)
99.5
90
mA
25
200
mW
mW
Minimum values for ADS41B49 are specified across the ambient temperature range of –40°C to +105°C.
The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10 pF.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Feature Description).
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6.6 Electrical Characteristics: ADS41B29, ADS41B49
Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 1.5-VPP clock amplitude, 50% clock
duty cycle, –1-dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum
values are across the full ambient temperature range: TA, MIN = –40°C to TA, MAX = 85°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V,
and DRVDD = 1.8 V, unless otherwise noted.
ADS41B49 (1)
ADS41B29
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Resolution
SNR
Signal-to-noise ratio, LVDS
Signal-to-noise and distortion
ratio, LVDS
68.4
69.7
fIN = 70 MHz
68.3
69.5
fIN = 100 MHz
68.3
69.5
65.5
68.4
fIN = 20 MHz
68.3
69.5
fIN = 70 MHz
68.1
69.3
fIN = 100 MHz
68.2
65
Total harmonic distortion
66.5
67.4
89
89
fIN = 70 MHz
85
85
fIN = 100 MHz
87
Second-order harmonic
distortion
Third-order harmonic distortion
72
75
75
85
85
fIN = 70 MHz
82
82
fIN = 100 MHz
83
68
83
79.5
69
72
72
fIN = 20 MHz
93
93
fIN = 70 MHz
85
85
fIN = 100 MHz
87
87
87
72
80
80
fIN = 20 MHz
93
93
fIN = 70 MHz
88
88
fIN = 100 MHz
88
88
82
72
75
75
fIN = 20 MHz
89
89
fIN = 70 MHz
90
90
fIN = 100 MHz
90
fIN = 300 MHz
76
dBc
82
fIN = 300 MHz
fIN = 170 MHz
dBc
87
fIN = 300 MHz
71
dBc
79.5
fIN = 300 MHz
71
dBc
82
fIN = 20 MHz
fIN = 170 MHz
Worst spur
(other than second- and thirdorder harmonics)
87
82
fIN = 300 MHz
fIN = 170 MHz
HD3
71
dBFS
68.8
fIN = 20 MHz
fIN = 170 MHz
HD2
66
90
88
77.5
Bits
dBFS
69.3
67.8
UNIT
69.1
67.5
fIN = 170 MHz
THD
66.5
fIN = 300 MHz
fIN = 300 MHz
Spurious-free dynamic range
68
MAX
14
fIN = 20 MHz
fIN = 170 MHz
SFDR
TYP
12
fIN = 170 MHz
SINAD
MIN
dBc
88
88
88
–86
–86
dBFS
Recovery to within 1% (of final
value) for 6-dB overload with
sine-wave input
1
1
Clock
cycles
AC power-supply rejection ratio
For 100-mVPP signal on AVDD
supply, up to 10 MHz
> 30
> 30
ENOB
Effective number of bits
fIN = 170 MHz
11
INL
Integrated nonlinearity
fIN = 170 MHz
±1.5
Two-tone intermodulation
distortion
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
Input overload recovery
PSRR
IMD
(1)
10
dB
11.2
±3.5
±2.5
LSBs
±5
LSBs
Minimum values for the ADS41B49 are specified across the ambient temperature range of –40°C to +105°C.
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6.7 Digital Characteristics (1)
Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. Minimum
and maximum values are across the full ambient temperature range: TA, MIN = –40°C to TA, MAX = 85°C, AVDD = 1.8 V,
AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
SDATA, SCLK
(2)
RESET, SCLK, SDATA, and SEN
support 1.8-V and 3.3-V CMOS logic
levels
1.3
V
OE only supports 1.8-V CMOS logic
levels
1.3
V
RESET, SCLK, SDATA, and SEN
support 1.8-V and 3.3-V CMOS logic
levels
0.4
V
OE only supports 1.8-V CMOS logic
levels
0.4
V
VHIGH = 1.8 V
10
µA
SEN (3)
VHIGH = 1.8 V
0
µA
SDATA, SCLK
VLOW = 0 V
0
µA
SEN
VLOW = 0 V
–10
µA
DRVDD
V
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)
DRVDD –
0.1
High-level output voltage
Low-level output voltage
0
0.1
V
350
430
mV
DIGITAL OUTPUTS (LVDS INTERFACE: D0_D1_P/M to D12_D13_P/M, CLKOUTP/M)
VODH
VODL
Low-level output voltage (4)
VOCM
Output common-mode voltage
(1)
(2)
(3)
(4)
Standard swing LVDS
High-level output voltage (4)
270
Low swing LVDS
Standard swing LVDS
200
–430
Low swing LVDS
–350
mV
–270
–200
0.85
1.05
mV
mV
1.25
V
Minimum values for ADS41B49 are specified across the ambient temperature range of –40°C to +105°C.
SDATA and SCLK have an internal 180-kΩ pull-down resistor.
SEN has an internal 180-kΩ pull-up resistor to AVDD.
With an external 100-Ω termination.
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6.8 Timing Requirements: LVDS and CMOS Modes
Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS,
sine-wave input clock, CLOAD = 5 pF (1), and RLOAD = 100 Ω (2), unless otherwise noted. Minimum and maximum values are
across the full ambient temperature range: TA, MIN = –40°C to TA, MAX = 85°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, and
DRVDD = 1.7 V to 1.9 V. (3)
MIN
TYP
MAX
0.6
0.8
1.2
UNIT
GENERAL
tA
Aperture delay
Variation of aperture delay between two devices at the same temperature and DRVDD
supply
tJ
±100
Aperture jitter
ps
100
Time to valid data after coming out of STANDBY mode
Wakeup time
Time to valid data after coming out of PDN GLOBAL mode
ADC latency (4)
ns
fS rms
5
25
100
500
µs
Gain enabled (default after reset)
21
Gain and offset correction enabled
22
Clock
cycles
0.75 (6)
1.1
ns
0.35 (7)
0.6
ns
3
4.2
DDR LVDS MODE
Data setup time (2): data valid (5) to zero-crossing of CLKOUTP
tSU
(2)
(5)
tH
Data hold time : zero-crossing of CLKOUTP to data becoming invalid
tPDI
Clock propagation delay: input clock rising edge cross-over to output clock rising edge
cross-over, 1 MSPS ≤ sampling frequency ≤ 250 MSPS
Variation of tPDI between two devices at the same temperature and DRVDD supply
5.4
±0.6
LVDS bit clock duty cycle of differential clock, (CLKOUTP – CLKOUTM),
1 MSPS ≤ sampling frequency ≤ 250 MSPS
42%
48%
ns
ns
54%
tRISE, tFALL
Data rise and fall time: rise time measured from –100 mV to +100 mV, fall time
measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.14
ns
tCLKRISE,
tCLKFALL
Output clock rise and fall time: rise time measured from –100 mV to +100 mV, fall time
measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.14
ns
tOE
Output enable (OE) to data delay time to valid data after OE becomes active
50
100
ns
1.6
ns
PARALLEL CMOS MODE (8)
tSTART
Input clock to data delay: input clock rising edge cross-over to start of data valid (5)
tDV
Data valid time interval of valid data (5)
tPDI
Clock propagation delay: input clock rising edge cross-over to, output clock rising edge
cross-over, 1 MSPS ≤ sampling frequency ≤ 200 MSPS
2.5
3.2
4
5.5
ns
7
ns
Output clock duty cycle of output clock (CLKOUT),
1 MSPS ≤ sampling frequency ≤ 200 MSPS
47%
tRISE, tFALL
Data rise and fall time: rise time measured from 20% to 80% of DRVDD, fall time
measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.35
ns
tCLKRISE,
tCLKFALL
Output clock rise and fall time: rise time measured from 20% to 80% of DRVDD, fall
time measured from 80% to 20% of DRVDD,
1 MSPS ≤ sampling frequency ≤ 200 MSPS
0.35
ns
tOE
Output enable (OE) to data delay time to valid data after OE becomes active
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
12
20
40
ns
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
Timing parameters are ensured by design and characterization but are not production tested.
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.
For an ambient temperature range of –40°C to +105°C, the minimum value of setup time reduces to 0.7 ns.
For an ambient temperature range of –40°C to +105°C, the minimum value of setup time reduces to 0.3 ns.
For fS > 200 MSPS, using an external clock is recommended for data capture instead of the device output clock signal (CLKOUT).
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6.9 Timing Requirements: Reset
Typical values at TA = 25°C and minimum and maximum values across the full ambient temperature range: TA, MIN = –40°C to
TA, MAX = 85°C, unless otherwise noted. (1)
MIN
t1
Power-on delay from power-up of AVDD and DRVDD
to RESET pulse active
t2
Reset pulse duration of active RESET signal that
resets the serial registers
t3
Delay from RESET disable to SEN active
(1)
(2)
TYP
MAX
1
UNIT
ms
10
ns
1 (2)
100
µs
ns
For the ADS41B49, the minimum and maximum values are given for the ambient temperature range of TA, MIN = –40°C to TA, MAX =
105°C.
The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1 µs, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
6.10 Timing Requirements: LVDS Timing Across Sampling Frequencies
SAMPLING
FREQUENCY
(MSPS)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
TYP
MIN
TYP
230
0.85
1.25
0.35
0.6
200
1.05
1.55
0.35
0.6
185
1.1
1.7
0.35
0.6
160
1.6
2.1
0.35
0.6
125
2.3
3
0.35
0.6
80
4.5
5.2
0.35
0.6
MAX
MAX
6.11 Timing Requirements: CMOS Timing Across Sampling Frequencies
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
200
1
185
160
tSETUP (ns)
tHOLD (ns)
MAX
MIN
TYP
1.6
2
1.3
2
1.8
2.5
125
2.5
80
4.8
tPDI (ns)
MAX
MIN
TYP
MAX
2.8
4
5.5
7
2.2
3
4
5.5
7
2.5
3.3
4
5.5
7
3.2
3.5
4.3
4
5.5
7
5.5
5.7
6.5
4
5.5
7
6.12 Timing Requirements: CMOS Timing Across Sampling Frequencies
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
SAMPLING FREQUENCY
(MSPS)
tSTART (ns)
MIN
TYP
tDV (ns)
MAX
MIN
TYP
250
1.6
2.5
3.2
230
1.1
2.9
3.5
200
0.3
3.5
4.2
185
0
3.9
4.5
170
–1.3
4.3
5
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6.13 Typical Characteristics: ADS41B49
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
-60
-80
-60
-80
-100
-100
-120
-120
0
25
75
50
100
125
0
25
125
SFDR = 82.9 dBc, SNR = 69.3 dBFS, SINAD = 69 dBFS,
THD = 80.3 dBc
Figure 1. FFT for 20-MHz Input Signal
Figure 2. FFT for 170-MHz Input Signal
0
-20
-20
-40
-40
Amplitude (dB)
0
-60
-80
-60
-80
-100
-100
-120
-120
0
25
75
50
100
0
125
25
75
50
100
125
Frequency (MHz)
Frequency (MHz)
SFDR = 70.7 dBc, SNR = 68.4 dBFS, SINAD = 66.3 dBFS,
THD = 69.3 dBc
Each tone at –7-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz,
two-tone IMD = 87.3 dBFS, SFDR = 96.0 dBFS
Figure 3. FFT for 300-MHz Input Signal
Figure 4. FFT for Two-Tone Input Signal
0
95
-20
90
85
-40
SFDR (dBc)
Amplitude (dB)
100
Frequency (MHz)
SFDR = 90.3 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS,
THD = 85.2 dBc
Amplitude (dB)
75
50
Frequency (MHz)
-60
80
75
-80
70
-100
65
-120
0
25
50
75
100
125
60
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
Frequency (MHz)
Each tone at –36-dBFS amplitude, fIN1 = 185 MHz, fIN2 =
190 MHz, two-tone IMD = 89.7 dBFS, SFDR = 106.4 dBFS
Figure 5. FFT for Two-Tone Input Signal
14
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Figure 6. SFDR vs Input Frequency
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Typical Characteristics: ADS41B49 (continued)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
96
70
300 MHz
400 MHz
150 MHz
170 MHz
220 MHz
92
69.5
88
84
SFDR (dBc)
SNR (dBFS)
69
68.5
80
76
72
68
68
67.5
64
0
50
100
150
200
250
300
350
60
400
0
0.5
1
1.5
110
150 MHz
170 MHz
220 MHz
69
300 MHz
400 MHz
3
3.5
73
SFDR (dBFS)
SFDR (dBc)
SNR
100
68
72.5
72
80
71.5
70
71
60
70.5
50
70
62
40
69.5
61
30
69
SFDR (dBc, dBFS)
90
67
SINAD (dBFS)
2.5
Figure 8. SFDR Across Gain and Input Frequency
Figure 7. SNR vs Input Frequency
70
2
Gain (dB)
Input Frequency (MHz)
66
65
64
63
60
0
0.5
1
1.5
2
2.5
3
20
−70
3.5
−60
−50
Gain (dB)
−40
−30
−20
−10
0
SNR (dBFS)
67
68.5
Amplitude (dBFS)
Input frequency = 40 MHz
Figure 9. SINAD Across Gain and Input Frequency
110
71.5
80
71
70
70.5
60
70
50
69.5
40
69
30
68.5
−50
−40
−30
−20
−10
0
68
SFDR (dBc)
SFDR (dBc, dBFS)
90
SNR (dBFS)
72
−60
SFDR
SNR
72.5
100
20
−70
92
73
SFDR (dBFS)
SFDR (dBc)
SNR
70
88
69.5
84
69
80
68.5
76
68
72
67.5
68
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
SNR (dBFS)
120
Figure 10. Performance Across Input Amplitude
(Single Tone)
67
Input Common−Mode Voltage (V)
Amplitude (dBFS)
Input frequency = 170 MHz
Figure 11. Performance Across Input Amplitude
(Single Tone)
Input frequency = 170 MHz
Figure 12. Performance vs Input Common-Mode Voltage
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Typical Characteristics: ADS41B49 (continued)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
90
70
-40
-25
88
25
55
85
105
-40
-25
69.6
25
55
85
105
SNR (dBFS)
SFDR (dBc)
69.2
86
84
68.8
68.4
68
82
67.6
80
67.2
1.75
1.8
AVDD Supply (V)
1.85
66.8
1.7
1.9
1.75
Input frequency = 170 MHz
92
68.2
86
67.8
84
67.4
1.85
67
1.95
1.9
SFDR (dBc)
88
SNR (dBFS)
SFDR (dBc)
95
68.6
1.8
D001
71
SFDR
SNR
93
90
1.75
1.9
Figure 14. SNR Across Ambient Temperature vs AVDD
Supply
69
SNR
SFDR
1.7
1.85
Input frequency = 170 MHz
Figure 13. SFDR Across Ambient Temperature vs AVDD
Supply
82
1.65
1.8
AVDD Supply (V)
D001
70
91
69
89
68
87
67
85
66
83
65
81
64
79
63
77
62
75
61
73
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
3.4
SNR (dBFS)
78
1.7
60
Differential Clock Amplitude (VPP)
DRVDD Supply (V)
Input frequency = 170 MHz
Input frequency = 170 MHz
Figure 15. Performance Across DRVDD Supply Voltage
Figure 16. Performance Across Input Clock Amplitude
71
92
2.5
THD
SNR
2
1.5
88
70.5
70
INL (LSB)
84
SNR (dBFS)
THD (dBc)
1
0.5
0
−0.5
−1
80
69.5
−1.5
−2
76
35
40
45
50
55
60
65
69
−2.5
0
2048
4096
Input Clock Duty Cycle (%)
6144 8192 10240 12288 14336 16384
Output Code (LSB)
Input frequency = 10 MHz
Figure 17. Performance Across Input Clock Duty Cycle
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Figure 18. Integral Nonlinearity
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6.14 Typical Characteristics: ADS41B29
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
-60
-80
-60
-80
-100
-100
-120
-120
0
25
50
75
100
125
0
25
125
SFDR = 82.3 dBc, SNR = 68.1 dBFS, SINAD = 67.8 dBFS,
THD = 79.9 dBc
Figure 19. FFT for 20-MHz Input Signal
Figure 20. FFT for 170-MHz Input Signal
0
-20
-20
-40
-40
Amplitude (dB)
0
-60
-80
-60
-80
-100
-100
-120
-120
0
25
50
75
100
0
125
25
75
50
100
125
Frequency (MHz)
Frequency (MHz)
SFDR = 70.8 dBc, SNR = 67.4 dBFS, SINAD = 65.7 dBFS,
THD = 69.4 dBc
Each tone at –7-dBFS amplitude, fIN1 = 185 MHz, fIN2 = 190 MHz,
two-tone IMD = 87.3 dBFS, SFDR = 85.9 dBFS
Figure 22. FFT for Two-Tone Input Signal
Figure 21. FFT for 300-MHz Input Signal
0
95
-20
90
85
-40
SFDR (dBc)
Amplitude (dB)
100
Frequency (MHz)
SFDR = 89.6 dBc, SNR = 68.6 dBFS, SINAD = 68.5 dBFS,
THD = 85.2 dBc
Amplitude (dB)
75
50
Frequency (MHz)
-60
80
75
-80
70
-100
65
-120
0
25
50
75
100
125
60
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
Frequency (MHz)
Each tone at –36-dBFS amplitude, fIN1 = 185 MHz, fIN2 =
190 MHz, two-tone IMD = 89.8 dBFS, SFDR = 98.5 dBFS
Figure 23. FFT for Two-Tone Input Signal
Figure 24. SFDR vs Input Frequency
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Typical Characteristics: ADS41B29 (continued)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
96
69
150 MHz
170 MHz
220 MHz
92
68.5
300 MHz
400 MHz
88
84
SFDR (dBc)
SNR (dBFS)
68
67.5
80
76
72
67
68
66.5
64
0
50
100
150
200
250
300
350
60
400
0
0.5
1
1.5
120
150 MHz
170 MHz
220 MHz
68
300 MHz
400 MHz
3
3.5
71.5
SFDR (dBFS)
SFDR (dBc)
SNR
110
71
70.5
100
SFDR (dBc, dBFS)
67
SINAD (dBFS)
2.5
Figure 26. SFDR Across Gain and Input Frequency
Figure 25. SNR vs Input Frequency
69
2
Gain (dB)
Input Frequency (MHz)
90
70
80
69.5
70
69
60
68.5
50
68
62
40
67.5
61
30
67
60
20
−70
66
65
64
63
0
0.5
1
1.5
2
2.5
3
3.5
−60
−50
Gain (dB)
−40
−30
−20
−10
0
SNR (dBFS)
66
66.5
Amplitude (dBFS)
Input frequency = 170 MHz
120
71
80
70.5
70
70
60
69.5
50
69
40
68.5
30
68
−60
−50
−40
−30
−20
−10
0
67.5
69
88
68.5
84
68
80
67.5
76
67
72
66.5
68
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
66
1.95
Input Common−Mode Voltage (V)
Amplitude (dBFS)
Input frequency = 40 MHz
Figure 29. Performance Across Input Amplitude
(Single Tone)
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SFDR (dBc)
90
SNR (dBFS)
SFDR (dBc, dBFS)
71.5
20
−70
SFDR
SNR
72
100
18
92
72.5
SFDR (dBFS)
SFDR (dBc)
SNR
110
Figure 28. Performance Across Input Amplitude
(Single Tone)
SNR (dBFS)
Figure 27. SINAD Across Gain and Input Frequency
Input frequency = 170 MHz
Figure 30. Performance vs input Common-Mode Voltage
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Typical Characteristics: ADS41B29 (continued)
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
90
−40°C
−25°C
25°C
88
68.6
55°C
85°C
68.2
SNR (dBFS)
SFDR (dBc)
86
84
82
55°C
85°C
−40°C
−25°C
25°C
67.8
67.4
67
80
66.6
78
1.75
1.8
AVDD Supply (V)
1.85
66.2
1.7
1.9
1.75
Input frequency = 170 MHz
90
SNR
SFDR
67.1
66.7
84
SFDR (dBc)
86
66.3
82
65.9
65.5
1.9
1.85
70
SFDR
SNR
92
SNR (dBFS)
SFDR (dBc)
94
68.3
67.5
1.8
1.9
Figure 32. SNR Across Ambient Temperature vs AVDD
Supply
67.9
88
1.75
1.85
Input frequency = 170 MHz
Figure 31. SFDR Across Ambient Temperature vs AVDD
Supply
80
1.7
1.8
AVDD Supply (V)
69
90
68
88
67
86
66
84
65
82
64
80
63
78
62
76
61
74
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
SNR (dBFS)
76
1.7
60
3.4
Differential Clock Amplitude (VPP)
DRVDD Supply (V)
Input frequency = 170 MHz
Input frequency = 170 MHz
Figure 33. Performance Across DRVDD Supply Voltage
Figure 34. Performance Across Input Clock Amplitude
95
69
90
68.5
85
68
80
67.5
75
35
40
45
50
55
60
65
SNR (dBFS)
THD (dBc)
THD
SNR
67
Input Clock Duty Cycle (%)
Input frequency = 10 MHz
Figure 35. Performance Across Input Clock Duty Cycle
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6.15 Typical Characteristics: General
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
0
0
−10
-20
−20
-40
Amplitude (dB)
CMRR (dB)
fIN = 170 MHz
−30
−40
−50
−60
-60
-80
fIN - fCM =
160 MHz
fIN + fCM =
180 MHz
fCM = 10 MHz
-100
0
50
100
150
200
250
300
-120
0
25
50
Frequency of Input Common−Mode Signal (MHz)
Input frequency = 170 MHz, 50-mVPP signal superimposed on
input common-mode voltage (1.7 V)
125
Figure 37. CMRR FFT
0
PSRR on AVDD Supply 50mVPP
PSRR on AVDD 3 V Supply 100mVPP
−10
100
fIN = 170 MHz; fCM = 10 MHz, 50 mVPP; SFDR = 77.69 dB;
amplitude: (fIN) = –1 dBFS; (fCM) = –93.8 dBFS;
(fIN + fCM) = –78.8 dBFS; (fIN – fCM) = –81 dBFS
Figure 36. CMRR Across Frequency
0
75
Frequency (MHz)
-20
Amplitude (dB)
PSRR (dB)
−20
−30
−40
−50
-40
fIN
-60
fIN - fPSRR
fIN + fPSRR
-80
−60
fPSRR
-100
−70
−80
0
10
20
30
40
50
60
70
80
90
100
-120
0
5
10
15
20
Frequency of Signal on Supply (MHz)
25
30
35
40
45
50
Frequency (MHz)
fIN = 10 MHz; fPSRR = 10 MHz, 50 mVPP;
amplitude: (fIN) = –1 dBFS; (fPSRR) = –65.6 dBFS;
(fIN + fPSRR) = –67.5 dBFS; (fIN – fPSRR) = –68.3 dBFS
Figure 39. PSRR FFT
Figure 38. PSRR Across Frequency
290
80
Analog Power
DRVDD Power
270
250
DRVDD Current (mA)
70
230
Power (mW)
210
190
170
150
130
60
50
40
110
30
90
70
50
0
25
50
75
100
125
150
175
200
225
250
20
0
25
Sampling Speed (MSPS)
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75
100
125
150
175
200
225
250
Sampling Speed (MSPS)
Figure 40. Power Across Sampling Frequency
20
50
Figure 41. DRVDD Current Across Sampling Frequency
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6.16 Typical Characteristics: Contour
At 25°C, AVDD = 1.8 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
250
240
83
86
76
220
86
60
64
68
72
80
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
250
240
200
83
180
89
160
120
80
86
89
140
76
60
64
68
72
83
89
100
89
86
83
80
65
20 50
100
80
150
200
76
250
72
64
68
300
350
400
450
160
140
86
65
70
75
120
80
89
20 50
85
100
60
150
200
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
68
67
69
180
69.5
68
140
67
120
69
66
100
69.5
70
68
69
100
150
65
70
200
65
250
66
67
350
400
64
450
66
65
65
500
65
100
80
65
66
300
67
66.5
67
100
150
200
69
70
62.5
160
68
67
67.5
66
120
100
150
200
250
65
67
63
63.5
63.5
64
64.5
65
65.5
300
66
63
400
450
500
64
64.5
65
65.5
66
66.5
67
350
400
450
66
200
65.5
66
65
180
160
66
140
65.5
120
65
100
500
65
66
20 50
100
66.5
65.5
150
200
250
64
65
300
350
400
63
450
500
Input Frequency (MHz)
Input Frequency (MHz)
63
350
65
80
64
66
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
66
180
100
300
Figure 45. SNR Contour
(3.5-dB Gain, Applies to ADS41B49)
67
67.5
250
SNR (dBFS)
67.5
68
64
65
66
20 50
Input Frequency (MHz)
68
68
20 50
85
66
120
220
65
80
66.5
220
80
75
140
250
240
68.5
500
160
250
240
140
64
450
180
Figure 44. SNR Contour
(0-dB Gain, Applies to ADS41B49)
68.5
68
400
66.5
200
SNR (dBFS)
200
72
350
220
Input Frequency (MHz)
64
300
Figure 43. SFDR Contour
(3.5-dB Gain, Applies to ADS41Bx9)
69.5
20 50
250
250
240
200
65
68
SFDR (dBc)
220
80
83 80 76
72
76
Input Frequency (MHz)
69
70
86
80
100
Figure 42. SFDR Contour
(0-dB Gain, Applies to ADS41Bx9)
160
83
89
SFDR (dBc)
250
240
86
89
Input Frequency (MHz)
60
68
180
65
500
64
72
76
86
200
80
60
80
83
86
220
67
67.5
68
68.5
62.5
63
63.5
64
64.5
65
65.5
66
SNR (dBFS)
SNR (dBFS)
Figure 46. SNR Contour
(0-dB Gain, Applies to ADS41B29)
Figure 47. SNR Contour
(0-dB Gain, Applies to ADS41B29)
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7 Parameter Measurement Information
7.1 Timing Diagrams
Dn_Dn + 1_P
Logic 0
VODL
Logic 1
VODH
Dn_Dn + 1_M
VOCM
GND
(1)
With external 100-Ω termination.
Figure 48. LVDS Output Voltage Levels
Sample N
N+3
N+2
N+1
N+4
N + 23
N + 22
N + 21
Input Signal
tA
CLKP
Input Clock
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
21 Clock Cycles
DDR LVDS
(1)
tSU
(2)
Output Data
(DXP, DXM)
E
O
N - 21
E
O
N - 21
E
O
N - 19
E
O
N - 18
O
E
O
E
N - 17
O
E
E
O
N+1
N
E
O
E
O
N+2
tPDI
CLKOUT
tSU
Parallel CMOS
21 Clock Cycles
Output Data
N - 21
N - 20
N - 19
(1)
tH
N - 18
N-1
N
N+1
(1)
At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall latency = ADC
latency + 1.
(2)
E = Even bits (D0, D2, D4, and so forth). O = Odd bits (D1, D3, D5, and so forth).
Figure 49. Latency Diagram
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Timing Diagrams (continued)
CLKM
Input
Clock
CLKP
tPDI
CLKOUTP
Output
Clock
CLKOUTM
tSU
Output Dn_Dn + 1_P
Data Pair Dn_Dn + 1_M
(1)
tSU
tH
Dn
(1)
Dn + 1
tH
(1)
Dn = bits D0, D2, D4, and so forth. Dn + 1 = Bits D1, D3, D5, and so forth.
Figure 50. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
Dn
tH
Dn
(1)
CLKM
Input
Clock
CLKP
tSTART
tDV
Output
Data
Dn
Dn
(1)
Dn = bits D0, D1, D2, and so forth.
Figure 51. CMOS Mode Timing
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Timing Diagrams (continued)
Power Supply
AVDD, DRVDD
t1
RESET
t3
t2
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through
hardware reset. For parallel interface operation, RESET must be permanently tied high.
Figure 52. Reset Timing Diagram
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8 Detailed Description
8.1 Overview
The ADS41Bx9 is a family of buffered analog input and ultralow power analog-to-digital converters (ADCs) with
maximum sampling rates up to 250 MSPS. The conversion process is initiated by a rising edge of the external
input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of
small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the
sample propagates through the pipeline, resulting in a data latency of 21 clock cycles. The output is available as
14-bit data or 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or
binary twos complement format.
8.2 Functional Block Diagram
AVDD
AGND
DRVDD
DDR LVDS
Interface
DRGND
CLKP
CLKOUTP
CLOCKGEN
CLKOUTM
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
AVDD_BUF
D2_D3_M
D4_D5_P
INP
Common
Digital Functions
14-Bit
ADC
Sampling
Circuit
DDR
Serializer
D4_D5_M
D6_D7_P
INM
D6_D7_M
D8_D9_P
Analog Buffers
D8_D9_M
Control
Interface
Reference
VCM
D10_D11_P
D10_D11_M
D12_D13_P
D12_D13_M
OVR_SDOUT
DFS
SEN
SDATA
SCLK
RESET
ADS41B49
OE
Figure 53. ADS41B49 Block Diagram
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8.3 Feature Description
8.3.1 Analog Input
The analog input pins have analog buffers (running off the AVDD_BUF supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 3.5-pF input capacitance). The buffer helps to isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easy
when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to 1.7 V, so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.375 V)
and (VCM – 0.375 V), resulting in a 1.5-VPP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins
to the sampled voltage). Figure 54 shows an equivalent circuit for the analog input.
LPKG
1nH
INP
RROUTING
23W
CPAD
2.5pF
CPIN
0.5pF
Buffer
RBIAS
5kW
RPAD
200W
(2)
VCM = 1.7V
LPKG
1nH
INM
CPIN
0.5pF
(1)
CEQ
RROUTING
23W
Sampling
Circuit
REQ
RBIAS
5kW
CPAD
2.5pF
RPAD
200W
Buffer
CEQ
REQ
(1)
CEQ refers to the equivalent input capacitance of the buffer = 4 pF.
(2)
REQ refers to the REQ buffer = 10 Ω.
(3)
This equivalent circuit is an approximation and valid for frequencies less than 700 MHz.
Figure 54. Analog Input Equivalent Circuit
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Feature Description (continued)
8.3.2 Clock Input
The ADS41Bx9 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 55 shows an equivalent circuit for the input
clock.
Clock Buffer
LPKG
1nH
20W
CLKP
CBOND
1pF
RESR
100W
5kW
2pF
LPKG
1nH
20W
CEQ
CEQ
0.95V
5kW
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 55. Input Clock Equivalent Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 56. For best performance, the clock inputs must be driven differentially, reducing
susceptibility to common-mode noise. For high input frequency sampling, using a clock source with very low jitter
is recommended. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change
in performance with a non-50% duty cycle clock input. Figure 57 shows a differential circuit.
CMOS
Clock Input
0.1mF
0.1mF
CLKP
CLKP
Differential Sine-Wave,
PECL, or LVDS
Clock Input
VCM
0.1mF
0.1mF
CLKM
CLKM
Figure 57. Differential Clock Driving Circuit
Figure 56. Single-Ended Clock Driving Circuit
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8.3.3 Gain for SFDR, SNR Trade-Off
The ADS41Bx9 includes gain settings that can be used to get improved SFDR performance. The gain is
programmable from 0 dB to 3.5 dB (in 0.5-dB steps) using the GAIN register bits. For each gain setting, the
analog input full-scale range scales proportionally, as shown in Table 1.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.
After a reset, the gain is enabled with 0dB gain setting. For other gain settings, program the GAIN register bits.
Table 1. Full-Scale Range Across Gains
GAIN (dB)
TYPE
0
Default after reset
FULL-SCALE (VPP)
1.5
0.5
Programmable gain
1.41
1
Programmable gain
1.33
1.5
Programmable gain
1.26
2
Programmable gain
1.19
2.5
Programmable gain
1.12
3
Programmable gain
1.06
3.5
Programmable gain
1
8.3.4 Offset Correction
The ADS41Bx9 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV.
The correction can be enabled using the EN OFFSET CORR serial register bit. When enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 2.
Table 2. Time Constant of Offset Correction Loop
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1 / fS (sec) (1)
0000
1M
4 ms
0001
2M
8 ms
0010
4M
16.7 ms
0011
8M
33.5 ms
0100
16M
67 ms
0101
32M
134 ms
0110
64M
268 ms
0111
128M
537 ms
1000
256M
1.1 s
1001
512M
2.15 s
1010
1G
4.3 s
1011
2G
8.6 s
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
(1)
Sampling frequency, fS = 250 MSPS.
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After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. When frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by a default after reset.
After a reset, the offset correction is disabled. To use offset correction set EN OFFSET CORR to 1 and program
the required time constant. Figure 58 shows the time response of the offset correction algorithm after it is
enabled.
Output Code (LSB)
OFFSET CORRECTION
Time Response
8200
8190
8180
8170
8160
8150
8140
8130
8120
8110
8100
8090
8080
8070
8060
8050
8181
Offset of
10 LSBs
8192
Final converged value
Offset correction
converges to output
code of 8192
Offset correction
begins
-5
5
15
25
35
45
55
65
75
85
95
105
Time (ms)
Figure 58. Time Response of Offset Correction
8.3.5 Digital Output Information
The ADS41Bx9 provides either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the
data.
8.3.5.1 Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
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8.3.5.2 DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as illustrated in Figure 59 and Figure 60.
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0, D1
LVDS Buffers
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
12-Bit
ADC Data
Data Bits D4, D5
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
ADS41B29
Figure 59. ADS41B29 LVDS Data Outputs
30
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Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
LVDS Buffers
Data Bits D0, D1
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
Data Bits D4, D5
14-Bit
ADC Data
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
D12_D13_P
Data Bits D12, D13
D12_D13_M
ADS41B49
Figure 60. ADS41B49 LVDS Data Outputs
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Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1,
D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP
must be used to capture all 14 data bits, as shown in Figure 61.
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
D12_D13_P,
D12_D13_M
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 61. DDR LVDS Interface
32
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8.3.5.3 LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 62. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100-Ω termination.
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination.
This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a
100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT
STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, signal integrity is improved.
VDIFF
High
Low
OUTP
External
100W Load
OUTM
1.1V
ROUT
VDIFF
Low
High
NOTE: Use the default buffer strength to match 100-Ω external termination (ROUT = 100 Ω). To match with a 50-Ω
external termination, set the LVDS STRENGTH bit (ROUT = 50 Ω).
Figure 62. LVDS Buffer Equivalent Circuit
8.3.5.4 Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 63 depicts the CMOS
output interface.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength
ensures a wide data stable window (even at 250 MSPS) is provided so the data outputs have minimal load
capacitance. Using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load
capacitance is recommended; see Figure 64.
For sampling frequencies greater than 200 MSPS, using an external clock to capture data is recommended. The
delay from input clock to output data and the data valid times are specified for higher sampling frequencies.
These timings can be used to delay the input clock appropriately and use it to capture data.
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Pins
OVR
CLKOUT
CMOS Output Buffers
D0
D1
D2
D3
¼
¼
14-Bit
ADC Data
D11
D12
D13
ADS41B49
Figure 63. CMOS Output Interface
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Use External Clock Buffer
(> 200MSPS)
Input Clock
Receiver (FPGA, ASIC, etc.)
Flip-Flops
CLKOUT
CMOS Output Buffers
D0
D1
D2
CLKIN
D0_In
D1_In
D2_In
14-Bit ADC Data
D12
D13
D12_In
D13_In
ADS41Bx9
Use short traces between
ADC output and receiver pins (1 to 2 inches).
Figure 64. Using the CMOS Data Outputs
8.3.5.5 CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG)
where:
CL = load capacitance,
N × FAVG = average number of output bits switching.
(1)
Figure 41 illustrates the current across sampling frequencies at 2-MHz analog input frequency.
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8.3.5.6 Input Overvoltage Indication (OVR Pin)
The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the
sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR
remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off
DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).
For a positive overload, the D[13:0] output data bits are 0x3FFF in offset binary output format and 0x1FFF in
twos complement output format. For a negative input overload, the output code is 0x0000 in offset binary output
format and 0x2000 in twos complement output format.
8.3.5.7 Output Data Format
Two output data formats are supported: twos complement and offset binary. They can be selected using the
DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event
of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.
8.4 Device Functional Modes
8.4.1 Device Configuration
The ADS41Bx9 have several modes that can be configured using a serial programming interface, as described in
Table 3, Table 4, and Table 5. In addition, the devices have two dedicated parallel pins for quickly configuring
commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The
analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).
Table 3. DFS: Analog Control Pin
VOLTAGE APPLIED ON DFS
DESCRIPTION
(Data Format, Output Interface)
0, 100 mV / 0 mV
Twos complement, DDR LVDS
(3/8) AVDD ± 100 mV
Twos complement, parallel CMOS
(5/8) AVDD ± 100 mV
Offset binary, parallel CMOS
AVDD, 0 mV / –100 mV
Offset binary, DDR LVDS
Table 4. OE: Digital Control Pin
VOLTAGE APPLIED ON OE
DESCRIPTION
0
Output data buffers disabled
AVDD
Output data buffers enabled
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have
any alternative functions. Keep SEN tied high and SCLK tied low on the board.
Table 5. SDATA: Digital Control Pin
36
VOLTAGE APPLIED ON SDATA
DESCRIPTION
0
Normal operation
Logic high
Device enters standby
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A simple diagram to configure DFS pin is shown in Figure 65.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
Figure 65. Simplified Diagram to Configure the DFS Pin
8.4.2 Power-Down
The ADS41Bx9 has three power-down modes: power-down global, standby, and output buffer disable.
8.4.2.1 Power-Down Global
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down,
resulting in reduced total power dissipation of approximately 7 mW. The output buffers are in a high-impedance
state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100 µs.
To enter the global power-down mode, set the PDN GLOBAL register bit.
8.4.2.2 Standby
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up
time of 5 µs. The total power dissipation in standby mode is approximately 200mW. To enter the standby mode,
set the STBY register bit.
8.4.2.3 Output Buffer Disable
The output buffers can be disabled and put in a high-impedance state; wake-up time from this mode is fast,
approximately 100 ns. This can be controlled using the PDN OBUF register bit or using the OE pin.
8.4.2.4 Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The
power dissipation is approximately 92 mW.
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8.5 Programming
8.5.1 Serial Interface
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)
pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial SDATA are latched at every
falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK
falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the
register address and the remaining eight bits are the register data. The interface can work with SCLK frequency
from 20 MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.
8.5.1.1 Register Initialization
After power-up, the internal registers must be
accomplished in one of two ways:
1. Either through hardware reset by applying a
shown in Figure 66; or
2. By applying a software reset. When using the
This setting initializes the internal registers to
this case, the RESET pin is kept low.
initialized to the default values. This initialization can be
high pulse on RESET pin (of width greater than 10 ns), as
serial interface, set the RESET bit (D7 in register 0x00) high.
the default values and then self-resets the RESET bit low. In
Register Address
SDATA
A7
A6
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
tSCLK
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 66. Serial Interface Timing
Table 6. Serial Interface Timing Characteristics (1) (2)
MIN
TYP
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
(1)
(2)
38
> dc
MAX
Typical values are at 25°C, minimum and maximum values for the ADS41B29 are specified across the ambient temperature range of
TA, MIN = –40°C to TA, MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
Typical values are at 25°C, minimum and maximum values for the ADS41B49 are specified across the ambient temperature range of
TA, MIN = –40°C to TA, MAX = 105°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
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8.5.2 Serial Register Readout
The serial register readout function allows the contents of the internal registers to be read back on the
OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the ADC.
After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When
the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:
1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any
further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is
also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of
the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the
device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.
Figure 67 shows the process of reading out register contents on the OVR_SDOUT pin, using register 43h as
example.
Register Address A[7:0] = 00h
SDATA
0
0
0
0
0
Register Data D[7:0] = 01h
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
OVR_SDOUT
(1)
a) Enable Serial Readout (READOUT = 1)
Register Address A[7:0] = 43h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
0
SCLK
SEN
OVR_SDOUT
(2)
b) Read Contents of Register 43h. This Register Has Been Initialized with 40h (device is put in global power-down mode).
(1)
The OVR_SDOUT pin functions as OVR (READOUT = 0).
(2)
The OVR_SDOUT pin functions as a serial readout (READOUT = 1).
Figure 67. Serial Readout Timing Diagram
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8.6 Register Maps
8.6.1 Serial Register Map
Table 7 summarizes the functions supported by the serial interface.
Table 7. Serial Interface Register Map (1)
(1)
REGISTER
ADDRESS
DEFAULT VALUE
AFTER RESET
A[7:0] (Hex)
D[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
00
0
0
0
0
0
0
RESET
READOUT
01
00
0
0
03
00
0
0
0
0
0
HIGH PERF MODE 1
25
50
26
00
0
3D
00
DATA FORMAT
3F
00
0
40
00
41
00
LVDS CMOS
42
08
CLKOUT FALL POSN
0
0
1
STBY
43
00
0
PDN
GLOBAL
0
PDN OBUF
0
0
4A
00
0
0
0
0
0
0
BF
00
REGISTER DATA
LVDS SWING
0
GAIN
0
0
TEST PATTERNS
0
0
0
0
EN
OFFSET
CORR
0
0
0
0
LVDS
LVDS DATA
CLKOUT
STRENGTH
STRENGTH
0
0
CUSTOM PATTERN D[13:8]
CUSTOM PATTERN D[7:0]
CMOS CLKOUT
STRENGTH
EN
CLKOUT
RISE
CLKOUT RISE POSN
OFFSET PEDESTAL
CF
00
FREEZE
OFFSET
CORR
DF
00
0
0
0
OFFSET CORR TIME CONSTANT
LOW SPEED
0
0
0
EN
CLKOUT
FALL
0
EN LVDS SWING
0
HIGH PERF
MODE 2
0
0
0
0
0
0
Multiple functions in a register can be programmed in a single write operation.
8.6.1.1 Summary of High-Performance Modes
Table 8 lists the location and functions of high-performance mode registers in the device.
Table 8. High-Performance Modes Summary (1) (2) (3)
MODE
LOCATION
FUNCTION
MODE 1
Register address = 03h, register data = 03h
Set the MODE 1 register bits to get the best performance
across sample clock and input signal frequencies.
MODE 2
Register address = 4Ah, register data = 01h
Set the MODE 2 register bit to get the best performance at
high input signal frequencies greater than 230 MHz.
(1)
(2)
(3)
40
Using these modes is recommended to get best performance. These modes can only be set with the serial interface.
See the Serial Interface section for details on register programming.
Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device
Configuration section.
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8.6.1.2 Description of Serial Registers
For best performance, two special mode register bits must be enabled:
HI PERF MODE 1 and HI PERF MODE 2.
8.6.1.2.1 Register Address 00h (address = 00h) [reset = 00h]
Figure 68. Register Address 00h
7
0
6
0
5
0
4
0
Bits 7-2
Always write 0
Bit 1
RESET: Software reset applied
3
0
2
0
1
RESET
0
READOUT
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage
indicator.
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.
8.6.1.2.2 Register Address 01h (address = 01h) [reset = 00h]
Figure 69. Register Address 01h
7
6
5
4
3
2
1
0
LVDS SWING
Bits 7-2
LVDS SWING: LVDS swing programmability (1)
000000 =
011011 =
110010 =
010100 =
111110 =
001111 =
Bits 1-0
(1)
0
0
Default LVDS swing; ±350 mV with external 100-Ω termination
LVDS swing increases to ±410 mV
LVDS swing increases to ±465 mV
LVDS swing increases to ±570 mV
LVDS swing decreases to ±200 mV
LVDS swing decreases to ±125 mV
Always write 0
The EN LVDS SWING register bits must be set to enable LVDS swing control.
8.6.1.2.3 Register Address 03h (address = 03h) [reset = 00h]
Figure 70. Register Address 03h
7
0
6
0
5
0
4
0
Bits 7-2
Always write 0
Bits 1-0
HI PERF MODE 1: High performance mode 1
3
0
2
0
1
0
HI PERF MODE 1
00 = Default performance after reset
01 = Do not use
10 = Do not use
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF
MODE 1 bits
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8.6.1.2.4 Register Address 25h (address = 25h) [reset = 50h]
Figure 71. Register Address 25h
7
6
5
4
GAIN
Bits 7-4
3
0
2
1
TEST PATTERNS
0
GAIN: Gain programmability
These bits set the gain programmability in 0.5-dB steps.
0000, 0001, 0010, 0011, 0100 = Do not use
0101 = 0-dB gain (default after reset)
0110 = 0.5-dB gain
0111 = 1-dB gain
1000 = 1.5-dB gain
1001 = 2-dB gain
1010 = 2.5-dB gain
1011 = 3-dB gain
1100 = 3.5-dB gain
Bit 3
Always write 0
Bits 2-0
TEST PATTERNS: Data capture
These bits verify data capture.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In the ADS41B49, output data D[13:0] is an alternating sequence of 01010101010101 and
10101010101010.
In the ADS41B29, output data D[11:0] is an alternating sequence of 010101010101 and
101010101010.
100 = Outputs digital ramp
In ADS41B46, output data increments by one LSB (14-bit) every clock cycle from code 0 to
code 16383
In ADS41B26, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to
code 4095
101 = Output custom pattern (use registers 0x3F and 0x40 for setting the custom pattern)
110 = Unused
111 = Unused
42
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8.6.1.2.5 Register Address 26h (address = 26h) [reset = 00h]
Figure 72. Register Address 26h
7
6
5
4
3
2
0
0
0
0
0
0
1
LVDS CLKOUT
STRENGTH
Bits 7-2
Always write 0
Bit 1
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
0
LVDS DATA
STRENGTH
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100-Ω external termination (default strength)
1 = 50-Ω external termination (2x strength)
Bit 0
LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100-Ω external termination (default strength)
1 = 50-Ω external termination (2x strength)
8.6.1.2.6 Register Address 3Dh (address = 3Dh) [reset = 00h]
Figure 73. Register Address 3Dh
7
6
DATA FORMAT
Bits 7-6
5
EN OFFSET
CORR
4
3
2
1
0
0
0
0
0
0
2
CUSTOM
PATTERN D10
1
CUSTOM
PATTERN D9
0
CUSTOM
PATTERN D8
DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits 4-0
Always write 0
8.6.1.2.7 Register Address 3Fh (address = 3Fh) [reset = 00h]
Figure 74. Register Address 3Fh
7
6
0
0
5
CUSTOM
PATTERN D13
Bits 7-6
Always write 0
Bits 5-0
CUSTOM PATTERN (1)
4
CUSTOM
PATTERN D12
3
CUSTOM
PATTERN D11
These bits set the custom pattern.
(1)
For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
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8.6.1.2.8 Register Address 40h (address = 40h) [reset = 00h]
Figure 75. Register Address 40h
7
CUSTOM
PATTERN D7
Bits 7-0
6
CUSTOM
PATTERN D6
5
CUSTOM
PATTERN D5
4
CUSTOM
PATTERN D4
3
CUSTOM
PATTERN D3
2
CUSTOM
PATTERN D2
1
CUSTOM
PATTERN D1
0
CUSTOM
PATTERN D0
CUSTOM PATTERN (1)
These bits set the custom pattern.
(1)
For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
8.6.1.2.9 Register Address 41h (address = 41h) [reset = 00h]
Figure 76. Register Address 41h
7
6
LVDS CMOS
Bits 7-6
5
4
CMOS CLKOUT STRENGTH
3
EN CLKOUT
RISE
2
1
CLKOUT RISE POSN
0
EN CLKOUT
FALL
LVDS CMOS: Interface selection
These bits select the interface.
00, 10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits 5-4
CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3
ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits 2-1
CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500 ps, hold increases by 500 ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200 ps, hold increases by 200 ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100 ps, hold increases by 100 ps
10 = Setup reduces by 200 ps, hold increases by 200 ps
11 = Setup reduces by 1.5 ns, hold increases by 1.5 ns
Bit 0
ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge
44
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SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
8.6.1.2.10 Register Address 42h (address = 42h) [reset = 08h]
Figure 77. Register Address 42h
7
6
CLKOUT FALL POSN
Bits 7-6
5
0
4
0
3
1
2
STBY
1
0
0
0
CLKOUT FALL POSN
Controls position of output clock falling edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400 ps, hold increases by 400 ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200 ps, hold increases by 200 ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100 ps
10 = Falling edge is advanced by 200 ps
11 = Falling edge is advanced by 1.5 ns
Bits 5-4
Always write 0
Bit 3
Always write 1
Bit 2
STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time
from standby is fast
Bits 1-0
Always write 0
8.6.1.2.11 Register Address 43h (address = 43h) [reset = 00h]
Figure 78. Register Address 43h
7
0
6
PDN GLOBAL
5
0
4
PDN OBUF
Bit 7
Always write 0
Bit 6
PDN GLOBAL: Power-down
3
0
2
0
1
0
EN LVDS SWING
This bit sets the state of operation.
0 = Normal operation
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow
wake-up time.
Bit 5
Always write 0
Bit 4
PDN OBUF: Power-down output buffer
This bit set the output data and clock pins.
0 = Output data and clock pins enabled
1 = Output data and clock pins powered down and put in high- impedance state
Bits 3-2
Always write 0
Bits 1-0
EN LVDS SWING: LVDS swing control
00 = LVDS swing control using LVDS SWING register bits is disabled
01, 10 = Do not use
11 = LVDS swing control using LVDS SWING register bits is enabled
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8.6.1.2.12 Register Address 4Ah (address = 4Ah) [reset = 00h]
Figure 79. Register Address 4Ah
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Bits 7-1
Always write 0
Bit 0
HI PERF MODE 2: High performance mode 2
0
HI PERF
MODE 2
This bit is recommended for high input signal frequencies greater than 230 MHz.
0 = Default performance after reset
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit
8.6.1.2.13 Register Address BFh (address = BFh) [reset = 00h]
Figure 80. Register Address BFh
7
Bits 7-2
6
5
4
OFFSET PEDESTAL
3
2
1
0
0
0
OFFSET PEDESTAL
These bits set the offset pedestal. For the ADS41B49, bits 7-2 set the pedestal; for the ADS41B29,
bits 7-4 set the pedestal.
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC mid-code value. A pedestal can be added to the final converged value by programming these
bits.
Bits 1-0
46
ADS41Bx9 VALUE
PEDESTAL
011111
011110
011101
—
000000
—
111111
111110
—
100000
31 LSB
30 LSB
29 LSB
—
0 LSB
—
–1 LSB
–2 LSB
—
–32 LSB
Always write 0
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8.6.1.2.14 Register Address CFh (address = CFh) [reset = 00h]
Figure 81. Register Address CFh
7
FREEZE
OFFSET
CORR
Bit 7
6
5
4
0
3
2
OFFSET CORR TIME CONSTANT
1
0
0
0
FREEZE OFFSET CORR
This bit sets the freeze offset correction.
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the
last estimated value is used for offset correction every clock cycle; see the Offset Correction
section.
Bit 6
Always write 0
Bits 5-2
OFFSET CORR TIME CONSTANT
These bits set the offset correction time constant for the correction loop time constant in number of
clock cycles.
Bits 1-0
VALUE
TIME CONSTANT (Number of Clock Cycles)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Always write 0
8.6.1.2.15 Register Address DFh (address = DFh) [reset = 00h]
Figure 82. Register Address DFh
7
0
6
0
5
4
LOW SPEED
Bits 7-6
Always write 0
Bits 5-4
LOW SPEED: Low-speed mode
3
0
2
0
1
0
0
0
00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for
sampling rates greater than 80 MSPS.
11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal
to 80 MSPS.
Bits 3-0
Always write 0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 83 and Figure 84 show the differential impedance (ZIN = RIN || CIN) between the ADC analog input pins
INP and INM. The presence of the analog input buffer results in an almost constant input capacitance up to
1 GHz.
10
5
4
CIN (pF)
RIN (kW)
1
3
2
0.1
1
RIN Simulation
CIN Simulation
CIN Measurement
RIN Measurement
0.01
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
Frequency (GHz)
Submit Documentation Feedback
0.3
0.4
0.5
0.6
0.7
Frequency (GHz)
Figure 83. ADC Analog Input Resistance (RIN) Across
Frequency
48
0.2
Figure 84. ADC Analog Input Capacitance (CIN) Across
Frequency
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Product Folder Links: ADS41B29 ADS41B49
ADS41B29, ADS41B49
www.ti.com
SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
Application Information (continued)
9.1.2 Driving Circuit
Two example driving circuit configurations are shown in Figure 85 and Figure 86—one optimized for low input
frequencies and the other optimized for high input frequencies. Notice in both cases that the board circuitry is
simplified compared to the non-buffered ADS4149.
In Figure 85, a single transformer is used and is suited for low input frequencies. To optimize even-harmonic
performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is
recommended (see Figure 86). Note that both drive circuits have been terminated by 50 Ω near the ADC side.
The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage.
5W
T1
INP
0.1mF
25W
0.1mF
25W
INM
1:1
5W
Figure 85. Drive Circuit for Low Input Frequencies
5W
T2
T1
INP
0.1mF
50W
0.1mF
50W
50W
50W
INM
1:1
1:1
5W
Figure 86. Drive Circuit for High Input Frequencies
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 85 and Figure 86. The center point of this termination
is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of
the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω
(for a 50-Ω source impedance).
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www.ti.com
10 Power Supply Recommendations
10.1 Power-Supply Sequence
During power-up, the AVDD, AVDD_BUF, and DRVDD supplies can come up in any sequence. These supplies
are separated in the device. Externally, AVDD and DRVDD can be driven from separate supplies or from a single
supply.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Design Considerations
11.1.1.1 Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide, SLWU067 for details on layout
and grounding.
11.1.1.2 Supply Decoupling
Because the ADS41Bx9 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum
number of capacitors depends on the actual application. Place the decoupling capacitors very close to the
converter supply pins.
11.1.1.3 Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the
digital ground. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical
performance. For detailed information, see application notes VQFN Layout Guidelines, SLOA122, and
VQFN/SON PCB Attachment, SLUA271, both available for download at the TI web site (www.ti.com).
50
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SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
ADS4149 Data Sheet, SBAS483
ADS414x, ADS412x EVM User Guide, SLWU067
Application Note VQFN Layout Guidelines, SLOA122
Application Note VQFN/SON PCB Attachment, SLUA271
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS41B29
Click here
Click here
Click here
Click here
Click here
ADS41B49
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2016, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS41B29IRGZ25
ACTIVE
VQFN
RGZ
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ41B29
ADS41B29IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ41B29
ADS41B29IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ41B29
ADS41B49IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ41B49
ADS41B49IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ41B49
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS41B29IRGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS41B29IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS41B49IRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS41B49IRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS41B29IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS41B29IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
ADS41B49IRGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
ADS41B49IRGZT
VQFN
RGZ
48
250
213.0
191.0
55.0
Pack Materials-Page 2
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