Supertex inc. CW01 Four-Channel, Low Phase Noise, Low Power, Continuous Wave Transmitter Features General Description The Supertex CW01 is a four-channel, low phase noise, continuous wave transmit IC. A high speed D flip-flop is provided to allow the DIN frequency to be aligned to a high frequency clock. The output N-channel is turned on when a logic high is clocked into the D flip-flop. Data are clocked in during the low to high transition. ►► Low phase noise ►► 100V open drain N-channel ►► High speed D flip-flop ►► High speed MOSFET gate driver ►► Up to 200MHz clock input VD1, VD2, VD3 and VD4 are four individual input supply voltages for the N-channel output MOSFET gate drivers. High peak currents are drawn from these gate drives when the output MOSFETs are switching. To minimize jitter caused by voltage ripples, each channel has its own gate drive voltage pin; VD1, VD2, VD3 and VD4. A series ferrite bead and a decoupling capacitor are recommended on each VDX pin to minimize output jitter and channel to channel crosstalk. ►► VDD and VLL undervoltage lockout Applications ►► Diagnostic medical ultrasound ►► Fluid flow measurement Both VDD and VLL have undervoltage lockout to prevent spurious turn-on. Typical Application Circuit 8.0V (one of four channels) 0.1µF 0.1µF 96MHz VDD OE 2.5V 2.0 to 5.0MHz 270µH VD1 5.0V BAV99 VLL VLL DIN1 CLK VSS Supertex inc. DIN1 CLK VD1 BAV23 HVOUT1 Q1 PGND1 Translator and Driver Tx ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com PZT CW01 Ordering Information DIN1 Parameter Value VLL, logic supply -0.3 to +6.0V VDD, level translator voltage -0.5 to +6.0V VDX, gate drive voltage -0.5 to +6.0V HVOUT, high voltage output drain voltage Storage temperature range -65°C to +150°C 3.0W1 26.9°C/W θja Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note: 1. Device mounted on a 4 layer 3” by 4” board. PGND1 PGND2 VDD HVOUT2 CLK VSS VSS HVOUT3 DIN3 PGND3 DIN4 HVOUT4 24-Lead QFN (K6) +125°C Power dissipation, TA = 25°C Supertex inc. DIN2 -0.5 to 120V Maximum junction temperature HVOUT1 PGND4 Absolute Maximum Ratings 1 VD3 -G indicates package is RoHS compliant (‘Green’) VD4 CW01K6-G 24 VSS CW01 VD2 OE 24-Lead QFN 4.00x5.00mm body 1.00mm height (max) 0.50mm pitch VLL Device VD1 Package Option VSS Pin Configuration (top view) Product Marking CW01 YWLL AAA CCC Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 24-Lead QFN (K6) ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 CW01 DC Electrical Characteristics (VDD = VDX =5.0V, VLL = 2.5V, TJ = 25ºC unless otherwise specified) Symbol Min Typ Max Unit 0 - 100 V --- VDD voltage range 4.5 5.0 5.5 V --- VDD rise time 50 - - µs --- 1.65 2.5 5.5 V --- VLL rise time 50 - - µs --- VDIN Logic input voltage range 0 - VLL V --- VDX Gate drive voltage 4.5 5.0 5.5 V --- VDX rise time 50 - - µs --- HVOUT VDD tVDD-ON VLL tVLL-ON tVDX-ON Parameter High voltage output VLL voltage range Test Conditions IDDQ VDD quiescent current - 63 100 µA --- IDD VDD average current - 23.5 30 mA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active ILLQ VLL quiescent current - 8.1 20 µA --- ILL VLL average current - 380 600 µA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active IDXQ VDX quiescent current - 0 1.0 µA --- IDX VDX average current - 11.3 30 mA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active VIH Input logic high voltage 0.8VLL - VLL V --- VIL Input logic low voltage 0 - 0.2VLL V --- IIH Input logic high current - - 1.0 µA --- IIL Input logic high current -1.0 - - µA --- RON Output on resistance - 4.7 7.0 Ω IIN = 100mA ISAT Output saturation current - 0.8 - A VDD = HVOUT = 5.0V High voltage output leakage - - 10 µA HVOUT = 100V UVLO_VLL UVLO trip point for VLL - 1.5 - V --- UVLO_VDD UVLO trip point for VDD - 4.0 - V --- -40 - +125 °C --- IHVleak TJ Operating junction temperature Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 CW01 AC Electrical Characteristics (VDD = VDX =5.0V, VLL = 2.5V, TJ = 25ºC unless otherwise specified) Symbol Parameter Min Typ Max Unit Test Conditions fCLK Clock frequency 0 - 200 MHz - tr, tf Clock rise and fall times - 0.5 5.0 ns - tSU Set-up time, DIN to CLK 2.0 - - ns - tH Hold time, DIN from CLK 1.0 - - ns - tHVf HVOUT fall time - 0.8 - ns Load = 50Ω to 8.0V. See timing diagram tHVr HVOUT rise time - 3.3 - ns Load = 50Ω to 8.0V. See timing diagram tdLH Delay time from CLK to HVOUT from low to high - 5.1 - ns Load = 50Ω to 8.0V. See timing diagram tdHL Delay time from CLK to HVOUT from high to low - 2.6 - ns Load = 50Ω to 8.0V. See timing diagram ∆tdLHdelay Delay time matching for tdLH - 0.5 1.0 ns - ∆tdHLdelay Delay time matching for tdHL - 0.5 1.0 ns - tOE(ON) Output enable turn-on time - - 10 µs - tOE(OFF) Output enable turn-off time - - 0.1 µs - - 8.0 - pF At 8.0V - 4.0 - pF At 100V COUT Phase noise Output capacitance Phase noise Supertex inc. - -171 -160 dB below carrier CLK = 80MHz, DIN = 2.0MHz dBC/Hz freq offset = 1.0kHz noise bandwidth = 140Hz See test circuit. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4 CW01 Block Diagram VDD VLL UVLO VLL VDD UVLO OE DIN1 DIN1 CLK DIN2 CLK PGND1 DIN3 CLK DIN4 CLK CLK HVOUT2 Q1 PGND2 VD3 VDD HVOUT3 Q1 PGND3 VD4 VDD VLL DIN4 VD2 VDD VLL DIN3 HVOUT1 Q1 VLL DIN2 VD1 VDD VLL HVOUT4 Q1 PGND4 VSS SUB Timing Diagram CLK 50% 50% tSU DIN 50% tH 50% tdHL 90% HVOUT 90% tdLH 10% 10% tHVr Supertex inc. tHVf ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 5 CW01 Test Circuits AC Timing (one of four channels) 5.0V 2.5V 8.0V VD1 0.1µF 0.1µF VDD 50Ω OE 0.1µF DIN1 DIN CLK CLK VD1 VLL VLL DIN1 CLK HVOUT HVOUT1 Q1 PGND1 VSS Translator and Driver Phase Noise (one of four channels) 5.0V 2.5V 3.0V VD1 0.1µF 0.1µF 390µH VDD OE 0.1µF 50Ω VLL VLL DIN1 2.0MHz CLK 80MHz DIN1 CLK VD1 0.1µF HVOUT1 Q1 50Ω HVOUT PGND1 VSS Translator and Driver Typical Performance Curve (Test conditions: VLL = 2.5V, VDD = 5.0V, VD1 = VD2 = VD3 = VD4 = 5.0V, no load) IDD vs DIN Frequency 30 fCLK = 200MHz 25 IDD (mA) 20 fCLK = 100MHz 15 fCLK = 50MHz 10 5 0 0 5 10 15 20 25 Data In Frequency (MHz) Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 6 CW01 Pin Configuration and Description Pin # Function Description 1 DIN1 D flip-flop logic input for HVOUT1. Logic high will turn on output N-channel. 2 DIN2 D flip-flop logic input for HVOUT2. Logic high will turn on output N-channel. 3 VDD Level translator supply. Should be at the same potential as VDX. 4 CLK Logic clock input. 5 VSS Ground. Should be externally shorted to all PGND and VSS pins. 6 DIN3 D flip-flop logic input for HVOUT3. Logic high will turn on output N-channel. 7 DIN4 D flip-flop logic input for HVOUT4. Logic high will turn on output N-channel. 8 VLL Logic input supply voltage. 9 VSS Ground. Should be externally shorted to all PGND and VSS pins. 10 VD4 Gate drive supply voltage for HVOUT4. Should be at the same potential as VDD. 11 VD3 Gate drive supply voltage for HVOUT3. Should be at the same potential as VDD. 12 PGND4 Power ground for HVOUT4. Should be externally shorted to all PGND and VSS pins. 13 HVOUT4 Drain output for HVOUT4. 14 PGND3 Power ground for HVOUT3. Should be externally shorted to all PGND and VSS pins. 15 HVOUT3 Drain output for HVOUT3. 16 VSS 17 HVOUT2 Drain output for HVOUT2. 18 PGND2 Power ground for HVOUT2. Should be externally shorted to all PGND and VSS pins. 19 HVOUT1 Drain output for HVOUT1. 20 PGND1 Power ground for HVOUT1. Should be externally shorted to all PGND and VSS pins. 21 VD2 Gate drive supply voltage for HVOUT2. Should be at the same potential as VDD. 22 VD1 Gate drive supply voltage for HVOUT1. Should be at the same potential as VDD. 23 VSS Ground. Should be externally shorted to all PGND and VSS pins. 24 OE Output enable logic input. Logic low will turn all HVOUT off. Center Pad --- Should be externally shorted to all PGND and VSS pins. Ground. Should be externally shorted to all PGND and VSS pins. Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 7 CW01 24-Lead QFN Package Outline (K6) 4.00x5.00mm body, 1.00mm height (max), 0.50mm pitch 24 D2 D 24 1 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e E2 E b Top View Bottom View View B Note 3 θ A A3 L Seating Plane L1 A1 Note 2 Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 3.85* 2.50 4.85* 3.50 0.25 4.00 2.65 5.00 3.65 0.30 4.15* 2.80 5.15* 3.80 0.50 BSC L L1 θ †0.30 0.00 0O 0.40 - - †0.50 0.15 14O JEDEC Registration MO-220, Variation VGHD-1, Issue K, June 2006 * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-24QFNK64X5P050, Version A101111. (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-CW01 A011712 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 8