SILABS CY28548 Clock generator for intelâ®crestline chipset Datasheet

CY28548
Clock Generator for Intel®Crestline Chipset
Features
• Compliant to Intel® CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• 33 MHz PCI clock
• 27 MHz Video clocks
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I2C support with readback capabilities
• Scalable low voltage VDD_IO (3.3V to 1.25V)
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clocks with selectable frequency
• 3.3V Power supply
• 100 MHz Differential SRC clocks
• 64-pin QFN/TSSOP packages
• 100 MHz Differential LCD clock
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
CPU
SRC
x2 / x3 x7/11
PCI REF DOT96 USB_48 LCD
x6
x1
x1
x1
x1
Block Diagram
........................ Document #: 001-08400 Rev ** Page 1 of 30
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
27M
x2
CY28548
Pin Configuration
64-Pin QFN
64-Pin TSSOP
CY28548
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PCI0/CR#_A
VDD_PCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/GCLK_SEL
PCIF0/ITP_EN
VSS_PCI
VDD_48
USB_48/FSA
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/27M_NSS
SRCC1/LCDC_100/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRCT2/SATAT
SRCC2/SATAC
VSS_SRC
SRCT3/CR#_C
SRCC3/CR#_D
VDD_SRC
SRCT4
SRCC4
VSS_SRC_IO
SRCT9
SRCC9
SRCC11/CR#_G
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XIN
XOUT
VSS_REF
FSB/TEST_MODE
CKPWRGD/PWRDWN#
VDD_CPU
CPUT0
CPUC0
VSS_CPU
CPUT1
CPUC1
VDD_CPU_IO
NC
SRCT8/CPU2_ITPT
SRCC8/CPU2_ITPC
VDD_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
VSS_SRC
SRCT6
SRCC6
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
QFN Pin Definitions
Pin No.
Name
Type
Description
1
VSS_REF
GND
2
Xout
O, SE 14.318 MHz Crystal output.
3
Xin
4
VDD_REF
5
I
Ground for outputs.
14.318 MHz Crystal input.
PWR
3.3V Power supply for outputs and maintains SMBUS registers during power
down.
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
6
SDATA
I/O
SMBus compatible SDATA.
7
SCLK
I
SMBus compatible SCLOCK.
........................Document #: 001-08400 Rev ** Page 2 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
8
PCI0 / CR#_A
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.
To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair
0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6:
0 = CR#_A controls SRC0 pair (default)
1= CR#_A controls SRC2 pair
9
VDD_PCI
10
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.
To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair
4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4:
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
11
PCI2 / TME
I/O, SE 33 MHz Clock output/3.3V-tolerance input for enabling Trusted Mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
12
PCI3
O, SE 33 MHz Clock output
13
PCI4 / GCLK_SEL
I/O, SE 33 MHz Clock output/3.3V-tolerant input for selecting graphic clock source
on pin 20, 21, 24 and 25
Sampled on CKPWRGD assertion;
PWR
3.3V power supply for PCI PLL
GCLK_SEL
Pin 20
Pin 21
Pin 24
Pin 25
0
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
1
SRCT0
SRCC0
27M_NSS
27M_SS
14
PCIF0 / ITP_EN
I/O, SE 33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
15
VSS_PCI
GND
Ground for outputs.
16
VDD_48
PWR
3.3V power supply for outputs and PLL.
17
USB_48 / FSA
18
VSS_48
19
VDD_IO
20
SRCT0 / DOT96T
O, DIF True 100 MHz Differential serial reference clocks/Fixed True 96 MHz clock
output. Selected via GCLK_SEL at CKPWRGD assertion
21
SRCC0 / DOT96C
O, DIF Complementary 100 MHz Differential serial reference clocks/Fixed
complement 96 MHz clock output.
Selected via GCLK_SEL at CKPWRGD assertion
22
VSS_IO
GND
Ground for outputs.
23
VDD_PLL3
PWR
3.3V Power supply for PLL3.
24
SRCT1 /
LCDT_100/27M_NSS
I/O
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND
Ground for outputs.
PWR
3.3V-1.25V power supply for outputs
O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD
SE
video clock output / Non spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
........................Document #: 001-08400 Rev ** Page 3 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
25
Name
SRCC1 /
LCDC_100/27M_SS
Type
Description
O, DIF, Complementary 100 MHz differential serial reference clock output/CompleSE
mentary 100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
26
VSS_PLL3
GND
Ground for PLL3.
27
VDD_PLL3_IO
PWR
3.3V-1.25V power supply for outputs.
28
SRCT2 / SATAT
O, DIF True 100 MHz differential serial reference clock output.
29
SRCC2 / SATAC
O, DIF Complementary 100 MHz differential serial reference clock output.
30
VSS_SRC
31
SRCT3 / CR#_C
I/O,
DIF
True 100 MHz differential serial reference clock output /3.3V Clock Request
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
32
SRCC3 / CR#_D
I/O,
DIF
Complementary 100 MHz differential serial reference clock output/3.3V Clock
Request #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
33
VDD_SRC_IO
34
SRCT4
O, DIF True 100 MHz differential serial reference clocks.
35
SRCC4
O, DIF Complementary 100 MHz differential serial reference clocks.
GND
PWR
GND
Ground for outputs.
3.3V-1.25V Power supply for outputs.
36
VSS_SRC
37
SRCT9
O, DIF True 100 MHz differential serial reference clocks.
Ground for outputs.
O, DIF Complementary 100 MHz differential serial reference clocks.
38
SRCC9
39
SRCC11/ CR#_G
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_G Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
40
SRCT11/ CR#_H
I/O,
DIF
Complementary 100 MHz Differential serial reference clocks/3.3V CR#_H
Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
41
SRCT10
O, DIF True 100 MHz Differential serial reference clocks.
42
SRCC10
O, DIF Complementary 100 MHz Differential serial reference clocks.
43
VDD_SRC_IO
PWR
44
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
45
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
46
VDD_SRC
47
SRCC6
O, DIF Complementary 100 MHz Differential serial reference clocks.
48
SRCT6
O, DIF True 100 MHz Differential serial reference clocks.
49
VSS_SRC
50
SRCC7/ CR#_E
PWR
GND
I/O,
DIF
3.3V-1.25V power supply for outputs.
3.3V power supply for SRC PLL.
Ground for outputs.
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
........................Document #: 001-08400 Rev ** Page 4 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
Name
51
SRCT7/ CR#_F
Type
I/O,
DIF
Description
True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
52
VDD_SRC_IO
PWR
53
SRCC8 / CPUC2_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
54
SRCT8 / CPUT2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
55
NC
56
VDD_CPU_IO
57
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
58
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
59
VSS_CPU
NC
PWR
GND
3.3V-1.25V Power supply for outputs.
No connect.
3.3V-1.25V Power supply for outputs.
Ground for outputs.
60
CPUC0
O, DIF Complement differential CPU clock outputs.
61
CPUT0
O, DIF True differential CPU clock outputs.
62
VDD_CPU
63
CKPWRGD / PWRDWN#
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
TSSOP Pin Definitions
Pin No.
Name
Type
Description
1
PCI0 / CR#_A
I/O, SE 33 MHz clock/3.3V Clock Request # Input.
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
2
VDD_PCI
3
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
4
PCI2 / TME
I/O, SE 33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
5
PCI3
O, SE 33 MHz clock output
PWR
3.3V Power supply for PCI PLL.
........................Document #: 001-08400 Rev ** Page 5 of 30
CY28548
TSSOP Pin Definitions (continued)
Pin No.
6
Name
PCI4 / GCLK_SEL
Type
Description
I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source
on pin 13, 14, 17and 18
Sampled on CKPWRGD assertion
GCLK_SEL
Pin13
Pin14
Pin17
Pin 18
0
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
1
SRCT0
SRCC0
27M_NSS
27M_SS
7
PCIF0 / ITP_EN
I/O, SE 33 MHz free running clock output / 3.3V LVTTL input to enable SRC8 or
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
Ground for outputs.
9
VDD_48
PWR
3.3V power supply for outputs and PLL.
10
USB_48 / FSA
11
VSS_48
GND
Ground for outputs.
12
VDD_IO
PWR
3.3V-1.25V power supply for outputs
13
SRCT0 / DOT96T
O, DIF True 100 MHz differential serial reference clocks / Fixed True 96 MHz clock
output. Selected via GCLK_SEL at CKPWRGD assertion
14
SRCC0 / DOT96C
O, DIF Complementary 100 MHz differential serial reference clocks / Fixed Complementary 96 MHz clock output. Selected via GCLK_SEL at CKPWRGD assertion
I/O
Fixed 48 MHz clock output / 3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
15
VSS_IO
GND
Ground for outputs
16
VDD_PLL3
PWR
3.3V Power supply for PLL3
17
SRCT1 /
LCDT_100/27M_NSS
O, DIF, True 100 MHz differential serial reference clock output / True 100 MHz LCD
SE
video clock output / Non spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
18
SRCC1 /
LCDC_100/27M_SS
O, DIF, Complementary100 MHz differential serial reference clock output / CompleSE
mentary 100 MHz LCD video clock output / Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
19
VSS_PLL3
GND
Ground for PLL3.
20
VDD_PLL3_IO
PWR
3.3V-1.25V power supply for outputs.
21
SRCT2 / SATAT
O, DIF True 100 MHz differential serial reference clock output.
22
SRCC2 / SATAC
O, DIF Complementary 100 MHz differential serial reference clock output.
23
VSS_SRC
24
SRCT3 / CR#_C
GND
I/O,
DIF
True 100 MHz differential serial reference clock output / 3.3V CR #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
25
SRCC3 / CR#_D
I/O,
DIF
Complementary 100 MHz differential serial reference clock output / 3.3V CR
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
PWR
Ground for outputs.
26
VDD_SRC_IO
27
SRCT4
O, DIF True 100 MHz differential serial reference clocks.
3.3V-1.25V power supply for outputs.
O, DIF Complementary 100 MHz differential serial reference clocks.
28
SRCC4
29
VSS_SRC
30
SRCT9
O, DIF True 100 MHz differential serial reference clocks.
31
SRCC9
O, DIF Complementary 100 MHz differential serial reference clocks.
GND
Ground for outputs.
........................Document #: 001-08400 Rev ** Page 6 of 30
CY28548
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
32
SRCC11/ CR#_G
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_G
Input Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
33
SRCT11/ CR#_H
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_H Input Selected
via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
34
SRCT10
O, DIF True 100 MHz differential serial reference clocks.
35
SRCC10
O, DIF Complementary 100 MHz differential serial reference clocks.
36
VDD_SRC_IO
PWR
37
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
38
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
3.3V-1.25V Power supply for outputs.
39
VDD_SRC
PWR
40
SRCC6
O, DIF Complementary 100 MHz differential serial reference clocks.
41
SRCT6
O, DIF True 100 MHz differential serial reference clocks.
42
VSS_SRC
43
SRCC7/ CR#_E
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input. Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
44
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_FInput.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
GND
PWR
3.3V Power supply for SRC PLL.
Ground for outputs.
45
VDD_SRC_IO
46
SRCC8 / CPUC2_ITP
O, DIF Selectable Complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
47
SRCC8 / CPUC2_ITP
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
48
NC
NC
PWR
3.3V-1.25V power supply for outputs.
No connect.
49
VDD_CPU_IO
50
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
51
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
52
VSS_CPU
GND
3.3V-1.25V Power supply for outputs.
Ground for outputs.
53
CPUC0
O, DIF Complementary differential CPU clock outputs.
54
CPUT0
O, DIF True differential CPU clock outputs.
55
VDD_CPU
56
CKPWRGD / PWRDWN#
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
........................Document #: 001-08400 Rev ** Page 7 of 30
CY28548
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
I
Description
57
FSB / TEST_MODE
58
VSS_REF
GND
59
Xout
O, SE 14.318 MHz Crystal output.
60
Xin
61
VDD_REF
62
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode:
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
14.318 MHz Crystal input.
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power down.
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection /
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
63
SDATA
I/O
64
SCLK
I
SMBus-compatible SDATA.
SMBus-compatible SCLOCK.
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
0
0
0
266 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
166 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
0
0
333 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
0
1
100 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
1
0
400 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
........................Document #: 001-08400 Rev ** Page 8 of 30
CY28548
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
Description
Start
Block Read Protocol
Bit
1
Slave address–7 bits
Write
8:2
9
Acknowledge from slave
Command Code–8 bits
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
Acknowledge from slave
27:21
Slave address–7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
37:30
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
38
46:39
47
....
Acknowledge from slave
....
Stop
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Byte Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
28
Acknowledge from slave
29
Stop
18:11
19
20
27:21
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
........................Document #: 001-08400 Rev ** Page 9 of 30
Command Code–8 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
CY28548
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
HW
FS_C
CPU Frequency Select Bit, set by HW
6
HW
FS_B
CPU Frequency Select Bit, set by HW
5
HW
FS_A
4
0
iAMT_EN
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3
0
Reserved
Reserved
2
0
SRC_Main_SEL
1
0
SATA_SEL
Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL2
0
1
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
CPU Frequency Select Bit, set by HW
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
Byte 1: Control Register 1
Bit
@Pup
Name
7
0
SRC0_SEL
Description
6
0
PLL1_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
5
0
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
4
0
PLL3_CFB3
3
0
PLL3_CFB2
2
0
PLL3_CFB1
1
1
PLL3_CFB0
0
1
Reserved
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
When GCLK_SEL=0, this bit is 1. When GCLK_SEL=1, this bit is 0
Bit 4:1 only applies when SRC_Main_SEL = 0
SeeTable 8: PLL3 / SE configuration table
Reserved
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6
1
USB
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
5
1
PCIF0
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
4
1
PCI4
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3
1
PCI3
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
2
1
PCI2
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
1
1
PCI1
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
0
1
PCI0
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
......................Document #: 001-08400 Rev ** Page 10 of 30
CY28548
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
SRC[T/C]11
Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
Description
6
1
SRC[T/C]10
Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
5
1
SRC[T/C]9
Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
4
1
SRC[T/C]8/CPU2_ITP
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
3
1
SRC[T/C]7
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
2
1
SRC[T/C]6
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
1
Reserved
Reserved
0
1
SRC[T/C]4
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC[T/C]3
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6
1
SRC[T/C]2/SATA
Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
5
1
4
1
SRC[T/C]0/DOT96[T/C]
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3
1
CPU[T/C]1
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2
1
CPU[T/C]0
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1
1
PLL1_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M
0 = Output Disabled, 1 = Output Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
CR#_A_EN
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
Description
6
0
CR#_A_SEL
Set CR#_A  SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
5
0
CR#_B_EN
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
4
0
CR#_B_SEL
Set CR#_B  SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
3
0
CR#_C_EN
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
2
0
CR#_C_SEL
Set CR#_C  SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
......................Document #: 001-08400 Rev ** Page 11 of 30
CY28548
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
1
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
0
0
CR#_D_SEL
Set CR#_D SRC1 or SRC4
0 = CR#_DSRC1, 1 = CR#_DSRC4
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
CR#_E_EN
Enable CR#_E (clk req)  SRC6
0 = Disabled, 1 = Enabled
6
0
CR#_F_EN
Enable CR#_F (clk req)  SRC8
0 = Disabled, 1 = Enabled
5
0
CR#_G_EN
Enable CR#_G (clk req)  SRC9
0 = Disabled, 1 = Enabled
4
0
CR#_H_EN
Enable CR#_H (clk req)  SRC10
0 = Disabled, 1 = Enabled
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
LCD_100_STP_CTRL
If set, LCD_100 stop with PCI_STOP#
0 = Free running, 1 = PCI_STOP# stoppable
0
0
SRC_STP_CTRL
If set, SRCs stop with PCI_STOP#
0 = Free running, 1 = PCI_STOP# stoppable
Byte 7: Vendor ID
Bit
@Pup
Name
7
0
Rev Code Bit 3
Revision Code Bit 3
Description
6
1
Rev Code Bit 2
Revision Code Bit 2
5
1
Rev Code Bit 1
Revision Code Bit 1
4
0
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
......................Document #: 001-08400 Rev ** Page 12 of 30
CY28548
Byte 8: Control Register 8
Bit
@Pup
Name
7
1
Device_ID3
Description
6
0
Device_ID2
5
0
Device_ID1
4
1
Device_ID0
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
27M_NSS_OE
Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
0
1
27M_SS_OE
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Byte 9: Control Register 9
Bit
@Pup
7
0
Name
Description
6
HW
TME_STRAP
5
1
REF drive strength
REF drive strength
0 = Low 1x, 1 = High 2x
4
0
TEST_MODE_SEL
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
2
1
12C_VOUT<2>
1
0
12C_VOUT<1>
0
1
12C_VOUT<0>
PCIF_0_with PCI_STOP# Allows control of PCIF_0 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
Trusted mode enable strap status
0 = Normal, 1 = No overclocking
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
Byte 10: Control Register 10
Bit
@Pup
Name
7
HW
GCLK_SEL latch
6
1
PLL3_EN
Description
Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
PLL3 power down
0 = Power down, 1 = Power up
......................Document #: 001-08400 Rev ** Page 13 of 30
CY28548
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
5
1
PLL2_EN
4
1
SRC_DIV_EN
SRC divider disable
0 = Disabled, 1 = Enabled
3
1
PCI_DIV_EN
PCI divider disable
0 = Disabled, 1 = Enabled
2
1
CPU_DIV_EN
CPU divider disable
0 = Disabled, 1 = Enabled
1
1
CPU1 Stop Enable
Enable CPU_STOP# control of CPU1
0 = Free running, 1= Stoppable
0
1
CPU0 Stop Enable
Enable CPU_STOP# control of CPU0
0 = Free running, 1= Stoppable
PLL2 power down
0 = Power down, 1 = Power up
Byte 11: Control Register 11
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Byte 12: Byte Count
Bit
@Pup
Name
7
0
Reserved
Description
6
0
Reserved
Reserved
5
0
BC5
Byte count
4
0
BC4
Byte count
3
1
BC3
Byte count
2
1
BC2
Byte count
1
0
BC1
Byte count
0
1
BC0
Byte count
Reserved
Byte 13: Control Register 13
Bit
@Pup
Name
7
1
USB drive strength
USB drive strength
0 = Low, 1= High
Description
6
1
PCI/ PCIF drive strength
PCI drive strength
0 = Low, 1 = High
5
0
PLL1_Spread
Select percentage of spread for PLL1
0 = 0.5%, 1=1%
4
1
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
3
1
CPU[T/C]2
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
......................Document #: 001-08400 Rev ** Page 14 of 30
CY28548
Byte 13: Control Register 13 (continued)
Bit
@Pup
Name
Description
2
1
SE1/SE2 drive strength
1 of 2
1
0
Reserved
Reserved
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
SE1 and SE2 Drive Strength Setting 1 of 2 (See Byte
0 = Low, 1= High
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
CPU_DAF_N7
6
0
CPU_DAF_N6
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
0
CPU_DAF_N0
Byte 15: Control Register 15
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
5
0
CPU_DAF_M5
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
1
0
CPU_DAF_M1
0
0
CPU_DAF_M0
Byte 16: Control Register 16
Bit
@Pup
Name
Description
Dial-A-Frequency®
7
0
PCI-E_N7
PCI-E
6
0
PCI-E_N6
PCI-E Dial-A-Frequency Bit N6
5
0
PCI-E_N5
PCI-E Dial-A-Frequency Bit N5
4
0
PCI-E_N4
PCI-E Dial-A-Frequency Bit N4
3
0
PCI-E_N3
PCI-E Dial-A-Frequency Bit N3
2
0
PCI-E_N2
PCI-E Dial-A-Frequency Bit N2
1
0
PCI-E_N1
PCI-E Dial-A-Frequency Bit N1
0
0
PCI-E_N0
PCI-E Dial-A-Frequency Bit N0
Bit N7
Byte 17: Control Register 17
Bit
@Pup
Name
......................Document #: 001-08400 Rev ** Page 15 of 30
Description
CY28548
Byte 17: Control Register 17 (continued)
7
0
SMSW_EN
Enable Smooth Switching
0 = Disabled, 1= Enabled
6
0
SMSW_SEL
Smooth switch select
0 = CPU_PLL, 1 = SRC_PLL
5
0
SE1/SE2 drive strength
2 of 2
4
0
Prog_PCI-E_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
3
0
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
2
0
REF drive strength
2 of 2
REFdrive strength strength Setting 2 of 2
1
0
USB drive strength
2 of 2
USB drive strength strength Setting 2 of 2
0
0
PCI/ PCIF drive strength
2of 2
PCI drive strength strength Setting 2 of 2
SE1 and SE2 drive strength Setting 2 of 2
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The CY28548 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the CY28548 to
operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Crystal Loading
C lo c k C h ip
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive
loading (CL).
C i2
C i1
P in
3 to 6 p
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
X2
X1
C s1
C s2
T ra c e
2 .8 p F
XTAL
Ce1
Ce2
T r im
33pF
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Figure 1. Crystal Capacitive Clarification
Total Capacitance (as seen by the crystal)
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
......................Document #: 001-08400 Rev ** Page 16 of 30
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CY28548
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs.............................................. Stray capacitance (terraced)
Ci ........................................................... Internal capacitance
(lead frame, bond wires, etc.)
®
Dial-A-Frequency (CPU and PCIEX)
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
PD_RESTORE
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
......................Document #: 001-08400 Rev ** Page 17 of 30
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY28548 initiates a full reset. The result of this is
that the clock chip emulates a cold power on start and goes to
the “Latches Open” state. If the PD_RESTORE bit is set to a
‘1’ then the configuration is stored upon PWRDWN# asserted
LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then
the PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PWRDWN# reset is not allowed.
PWRDWN# (Power down) Clarification
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD# is also an asynchronous input for powering
up the system. When PD# is asserted LOW, clocks are driven
to a LOW value and held before turning off the VCOs and the
crystal oscillator.
PWRDWN# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
PWRDWN# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
CY28548
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power down Assertion Timing Waveform
Ts ta b le
< 1 .8 m s
PD#
C P U T , 1 3 3 MH z
C P U C , 1 3 3 MH z
S R C T 1 0 0 MH z
S R C C 1 0 0 MH z
U S B , 4 8 MH z
D OT 9 6 T
D OT 9 6 C
P C I, 3 3 MH z
Td r iv e _ PW R D N #
<300 s , >2 00m V
REF
Figure 4. Power down Deassertion Timing Waveform
FS_A, FS_B ,FS _C ,FS _D
C K _P W R G D
PW R G D _VR M
0.2-0.3 m s
D elay
V D D C lock G en
C lock State
C lock O utputs
C lock V C O
S tate 0
W ait for
VTT_P W R G D #
State 1
D evice is not affected,
VTT_P W R G D # is ignored
Sam ple Sels
S tate 2
O ff
State 3
On
On
O ff
Figure 5. CK_PWRGD Timing Diagram
......................Document #: 001-08400 Rev ** Page 18 of 30
CY28548
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
......................Document #: 001-08400 Rev ** Page 19 of 30
CY28548
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI_STP# Assertion
.
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
T su
PC I_STP#
PC I_F
PC I
SR C 100M H z
Figure 10. PCI_STP# Assertion Waveform
.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transitions to a HIGH level.
T su
T drive_ S R C
P C I_S T P #
P C I_F
PCI
SR C 100 M H z
Figure 11. PCI_STP# Deassertion Waveform
......................Document #: 001-08400 Rev ** Page 20 of 30
CY28548
.
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
CPU_STOP# Asserted
Driven low
Running
Non stoppable
Running
Running
Stoppable
Clock driven high
Clock driven high
Clock# driven low
Clock# driven low
Running
Running
Non stoppable
SMBus OE Disabled
Driven low
Clock driven Low or 20K
pulldown
Table 7. Output Driver Status
All Differential Clocks except
CPU1
All Single-ended Clocks
w/o Strap
w/ Strap
Clock
CPU1
Clock#
Clock
Clock#
Latches Open State
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
Powerdown
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
M1
Low
Hi-z
Low or 20K pulldown Low
Running
Running
.
Table 8. PLL3/SE Configuration Table
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
0
0
0
0
0
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
0
0
0
0
1
100
100
0.5
SRC1 from SRC_Main
0
0
0
1
0
100
100
0.5
LCD_100 from PLL3
0
0
0
1
1
100
100
1
LCD_100 from PLL3
0
0
1
0
0
100
100
1.5
LCD_100 from PLL3
0
0
1
0
1
100
100
2
LCD_100 from PLL3
0
0
1
1
0
N/A
N/A
N/A
N/A
0
0
1
1
1
N/A
N/A
N/A
N/A
0
1
0
0
0
N/A
N/A
N/A
N/A
0
1
0
0
1
N/A
N/A
N/A
N/A
0
1
0
1
0
N/A
N/A
N/A
N/A
0
1
0
1
1
N/A
N/A
N/A
N/A
0
1
1
0
0
N/A
N/A
none
N/A
0
1
1
0
1
N/A
N/A
N/A
N/A
0
1
1
1
0
N/A
N/A
N/A
N/A
0
1
1
1
1
N/A
N/A
N/A
N/A
1
0
0
0
0
N/A
N/A
N/A
1
0
0
0
1
27M_NSS
27M_NSS
0.5
27M_NSS from PLL3
1
0
0
1
0
27M_NSS
27M_NSS
0.5
27M_NSS from PLL3
1
0
0
1
1
27M_NSS
27M_NSS
1
27M_NSS from PLL3
1
0
1
0
0
27M_NSS
27M_NSS
1.5
27M_NSS from PLL3
1
0
1
0
1
27M_NSS
27M_NSS
2
27M_NSS from PLL3
1
0
1
1
0
N/A
N/A
N/A
1
0
1
1
1
N/A
N/A
N/A
1
1
0
0
0
N/A
N/A
N/A
1
1
0
0
1
N/A
N/A
N/A
1
1
0
1
0
N/A
N/A
N/A
1
1
0
1
1
N/A
N/A
N/A
1
1
1
0
0
N/A
N/A
N/A
......................Document #: 001-08400 Rev ** Page 21 of 30
Comment
PLL3 Disabled
CY28548
Table 8. PLL3/SE Configuration Table (continued)
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
1
1
1
0
1
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
N/A
N/A
Comment
N/A
Figure 12. Clock Generator Power up/Run State Diagram
C l o c k O f f t o M1
3.3V
Vcc
2.0V
FSC
T_delay t
CPU_STOP#
FSB
FSA
PCI_STOP#
CKPWRGD/PWRDWN
Off
CK505 SMBUS
CK505 State
Latches Open
Off
M1
BSEL[0..2]
CK505 Core Logic
Off
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 13. BSEL Serial Latching
......................Document #: 001-08400 Rev ** Page 22 of 30
CY28548
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–
4.6
V
VDD_A
Analog Supply Voltage
–
4.6
V
VDD_IO
IO Supply Voltage
1.5
V
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating
Ambient
Functional
0
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-STD-883E Method 1012.1
–
20
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
Max.
Unit
3.135
3.465
V
2.0
VDD + 0.3
V
VSS – 0.3
0.8
V
2.2
–
V
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
3.3 ± 5%
Min.
VDD core
3.3V Operating Voltage
VIH
3.3V Input High Voltage (SE)
VIL
3.3V Input Low Voltage (SE)
VIHI2C
Input High Voltage
SDATA, SCLK
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS_[A,B] Input High Voltage
0.7
1.5
V
VIL_FS
FS_[A,B] Input Low Voltage
VSS – 0.3
0.35
V
VIHFS_C_TEST
FS_C Input High Voltage
2
VDD + 0.3
V
VIMFS_C_NORMAL FS_C Input Middle Voltage
VILFS_C_NORMAL FS_C Input Low Voltage
0.7
1.5
V
VSS – 0.3
0.35
V
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
–
5
A
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0 < VIN < VDD
–5
–
A
VOH
3.3V Output High Voltage (SE) IOH = –1 mA
VOL
3.3V Output Low Voltage (SE)
IOL = 1 mA
2.4
–
V
–
0.4
V
VDD IO
Low Voltage IO Supply Voltage
0.72
0.88
VOH
3.3V Input High Voltage (DIFF)
0.70
0.90
VOL
3.3V Input Low Voltage (DIFF)
0.40
V
IOZ
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
LIN
Pin Inductance
–
V
6
pF
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDD3.3V
Dynamic Supply Current
–
250
mA
......................Document #: 001-08400 Rev ** Page 23 of 30
CY28548
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
ns
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-s duration
–
500
ps
LACC
Long-term Accuracy
–
300
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential at 0.1s
45
55
%
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
9.99900
10.0100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
7.49925
7.50075
ns
TPERIOD
166 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
5.99940
6.00060
ns
TPERIOD
200 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
4.99950
5.00050
ns
TPERIOD
266 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
3.74963
3.75038
ns
TPERIOD
333 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
2.99970
3.00030
ns
TPERIOD
400 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
2.49975
2.50025
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
7.51955
ns
TPERIODSS
166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
6.01444
6.01564
ns
TPERIODSS
200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
5.01203
5.01303
ns
TPERIODSS
266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
3.75902
3.75978
ns
TPERIODSS
333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
3.00722
3.00782
ns
TPERIODSS
400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
2.50601
2.50652
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
7.41425
7.58575
ns
TPERIODAbs
166 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
5.91440
6.08560
ns
TPERIODAbs
200 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
4.91450
5.08550
ns
TPERIODAbs
266 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
3.66463
3.83538
ns
TPERIODAbs
333 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
2.91470
3.08530
ns
TPERIODAbs
400 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
2.41475
2.58525
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
9.91406
10.1362
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
7.41430
7.62340
ns
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
5.91444
6.11572
ns
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
4.91453
5.11060
ns
......................Document #: 001-08400 Rev ** Page 24 of 30
CY28548
AC Electrical Specifications (continued)
Min.
Max.
Unit
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute
period, SSC
Parameter
Description
Measured at 0V differential @ 1 clock
Condition
3.66465
3.85420
ns
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
2.91472
3.10036
ns
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
2.41477
2.59780
ns
–
85
ps
TCCJ
CPU Cycle to Cycle Jitter
Measured at 0V differential
TCCJ2
CPU2_ITP Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TSKEW
CPU0 to CPU1 Clock Skew
Measured at 0V differential
–
100
ps
TSKEW2
CPU2_ITP to CPU0 Clock Skew
Measured at 0V differential
–
150
ps
T R / TF
CPU Rising/Falling Slew rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential @ 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
Measured at 0V differential @ 1 clock
9.87406
10.1762
ns
–
3.0
ns
–
125
ps
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
LACC
SRC Long Term Accuracy
Measured at 0V differential
–
100
ppm
T R / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
Measured at 0V differential
45
55
%
10.4177
ns
ns
TPERIOD
DOT96 Period
Measured at 0V differential at 0.1s
10.4156
TPERIODAbs
DOT96 Absolute Period
Measured at 0V differential at 0.1s
10.1656
10.6677
TCCJ
DOT96 Cycle to Cycle Jitter
Measured at 0V differential at 1 clock
–
250
ps
LACC
DOT96 Long Term Accuracy
Measured at 0V differential at 1 clock
–
100
ppm
T R / TF
DOT96 Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
LCD_100_SSC at 0.7V
TDC
LCD_100 Duty Cycle
Measured at 0V differential
TPERIOD
100 MHz LCD_100 Period
Measured at 0V differential at 0.1s
......................Document #: 001-08400 Rev ** Page 25 of 30
45
55
%
9.99900
10.0010
ns
CY28548
AC Electrical Specifications (continued)
Min.
Max.
Unit
TPERIODSS
Parameter
100 MHz LCD_100 Period, SSC -0.5% Measured at 0V differential at 0.1s
Description
Condition
10.02406
10.02607
ns
TPERIODAbs
100 MHz LCD_100 Absolute Period
Measured at 0V differential at 1 clock
9.74900
10.25100
ns
TPERIODSSAbs 100 MHz LCD_100 Absolute Period,
SSC
Measured at 0V differential @ 1 clock
9.74906
10.3012
ns
–
250
ps
TCCJ
LCD_100 Cycle to Cycle Jitter
Measured at 0V differential
LACC
LCD_100 Long Term Accuracy
Measured at 0V differential
–
100
ppm
T R / TF
LCD_100 Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
PCI/PCIF at 3.3V
TDC
PCI Duty Cycle
Measurement at 1.5V
45
55
%
30.00300
ns
TPERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.99700
TPERIODSS
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
30.08421
30.23459
ns
TPERIODAbs
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.49700
30.50300
ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.56617
30.58421
ns
THIGH
Spread Enabled PCIF and PCI high time Measurement at 2V
12.27095
16.27995
ns
TLOW
Spread Enabled PCIF and PCI low time Measurement at 0.8V
11.87095
16.07995
ns
THIGH
Spread Disabled PCIF and PCI high
time
12.27365
16.27665
ns
TLOW
Spread Disabled PCIF and PCI low time Measurement at 0.8V
11.87365
16.07665
ns
T R / TF
PCIF/PCI Rising/Falling Slew Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
Any PCI clock to Any PCI clock Skew
Measurement at 1.5V
–
1000
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
–
100
ppm
Measurement at 2.V
48_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125
20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
48_M High time
Measurement at 2V
8.216563
11.15198
ns
TLOW
48_M Low time
Measurement at 0.8V
7.816563
10.95198
ns
T R / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
LACC
48M Long Term Accuracy
Measurement at 1.5V
–
100
ppm
27M_NSS/27M_SS at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled 27M Period
Measurement at 1.5V
37.03594
37.03813
ns
Spread Enabled 27M Period
Measurement at 1.5V
37.03594
37.03813
ns
T R / TF
Rising and Falling Edge Rate
Measured between 0.4V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
200
ps
LACC
27_M Long Term Accuracy
Measured at crossing point VOX
–
50
ppm
REF Duty Cycle
Measurement at 1.5V
45
55
%
REF
TDC
......................Document #: 001-08400 Rev ** Page 26 of 30
CY28548
AC Electrical Specifications (continued)
Min.
Max.
Unit
TPERIOD
Parameter
REF Period
Description
Measurement at 1.5V
Condition
69.82033
69.86224
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.83429
70.84826
ns
THIGH
REF High time
Measurement at 2V
29.97543
38.46654
ns
TLOW
REF Low time
Measurement at 0.8V
29.57543
38.26654
ns
T R / TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
REF Clock to REF Clock
Measurement at 1.5V
–
500
ps
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
LACC
Long Term Accuracy
Measurement at 1.5V
–
100
ppm
–
1.8
ms
10.0
–
ns
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
L1
22
50
PCI/USB
Measurement
Point
L2
L1 = 0.5", L2 = 8"
4 pF
Measurement
Point
50
22
L1
L2
4 pF
Figure 14. Single-ended PCI and USB Double Load Configuration
L1
15
L2
50
REF
Measurement
Point
4 pF
L1
15
L2
50
Measurement
Point
4 pF
L1
15
L2
50
Measurement
Point
4 pF
Figure 15. Single-ended REF Triple Load Configuration
......................Document #: 001-08400 Rev ** Page 27 of 30
CY28548
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
For CPU, SRC, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and SRC outputs
M e a s u re m e n t P o in t
L
OUT+
50 O hm
2pF
L= 8"
M e a s u re m e n t P o in t
L
OUT-
50 O hm
2pF
Figure 17. 0.7V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clck-Clck#
Rise
Edge
Rate
VIH = +150V
0.0V
VIL = -150V
Fall
Edge
Rate
VIH = +150V
0.0V
VIL = -150V
Clock-Clock#
Figure 18. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
......................Document #: 001-08400 Rev ** Page 28 of 30
CY28548
V MAX = 1.15V
V MAX = 1.15V
CLK#
Vcross MAX = 550mV
Vcross MAX = 550mV
Vcross MIN = 300mV
Vcross MIN = 300mV
CLK
V MIN = 0.30V
V MIN = 0.30V
CLK#
Vcross delta = 140mV
Vcross delta = 140mV
CLK#
Vcross median +75mV
Vcross median
Vcross m edian -75m V
CLK
ise
Tr
Vcross median
Tf
al
l
CLK#
CLK
Figure 19. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY28548ZXC
64-pin TSSOP
Commercial, 0 to 85C
CY28548ZXCT
64-pin TSSOP–Tape and Reel
Commercial, 0 to 85C
CY28548LFXC
64-pin QFN
Commercial, 0 to 85C
CY28548LFXCT
64-pin QFN–Tape and Reel
Commercial, 0 to 85C
......................Document #: 001-08400 Rev ** Page 29 of 30
CY28548
Package Diagrams
64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64
32
1
DIMENSIONS IN MM MIN.
MAX.
REFERENCE JEDEC MO-153
8.00[0.315]
8.20[0.322]
PART #
6.00[0.236]
6.20[0.244]
Z6424
STANDARD PKG.
ZZ6424
LEAD FREE PKG.
64
33
16.90[0.665]
17.10[0.673]
1.10[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.50[0.020]
BSC
0.85[0.033]
0.95[0.037]
REFERENCE JEDEC MO-220
0.05[0.002]
0.15[0.006]
0.17[0.006]
0.27[0.010]
0.50[0.020]
0.75[0.027]
0°-8°
0.10[0.004]
0.20[0.008]
SEATING
PLANE
64-Lead QFN 9 x 9 mm (Punch Version) LF64A
WEIGHT: 0.2 GRAMS
0.08[0.003]
8.90[0.350]
9.10[0.358]
A
C
1.00[0.039] MAX.
0.05[0.002] MAX.
0.18[0.007]
0.28[0.011]
0.80[0.031] MAX.
8.70[0.342]
8.80[0.346]
PIN1 ID
0.20[0.008] R.
0.20[0.008] REF.
N
N
1
1
0.80 DIA.
2 0.45[0.018]
2
3
8.90[0.350]
9.10[0.358]
8.70[0.342]
8.80[0.346]
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0.30[0.012]
0.50[0.020]
0.24[0.009]
0.60[0.024]
0°-12°
0.50[0.020]
TOP VIEW
7.45[0.293]
7.55[0.297]
C
SEATING
PLANE
SIDE VIEW
......................Document #: 001-08400 Rev ** Page 30 of 30
BOTTOM VIEW
(4X)
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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