ATMEL AT34C04 With reversible software write protection Datasheet

AT34C04
I2C-Compatible 4-Kbit Serial EEPROM
with Reversible Software Write Protection
DATASHEET
Features



Single 1.7V – 3.6V VCC supply
JEDEC JC42.4 (EE1004-v) Serial Presence Detect (SPD) compliant
2-wire serial interface: I2C Fast-Mode Plus (FM+)™ compatible
̶
100kHz, 400kHz, and 1MHz compatibility
Bus Timeout supported
̶

Advanced software data protection features
̶
̶
Individually reversible software write protection on all four 128-byte quadrants
Software procedure to verify each quadrant’s write protection status

16-byte Page Write mode
̶



Partial page writes allowed
Self-timed write cycle (5ms maximum)
Schmitt Trigger, filtered inputs for noise suppression
High-reliability
̶
Endurance: 1,000,000 write cycles
Data retention: 100 years
̶

Low operating current
̶
Write ~1.5mA (typical)
Read ~ 0.2mA (typical)
̶
 Green packaging options (Pb/Halide-free/RoHS compliant)
̶
8-lead JEDEC SOIC, 8-lead TSSOP, and 8-pad UDFN
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
T a b l e o f C o n ten ts
1.
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.
Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.
Device Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.
6.
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2
7.3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1
Set Page Address and Read Page Address Commands . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3
Acknowledge (ACK) Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4
Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
16
16
16
17
18
18
19
20
20
Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
8.2
8.3
9.
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1
8.
6
6
7
7
7
8
9
9
Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1
7.
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
No-Acknowledge (NACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timeout Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-wire Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set RSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clear RSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read RSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Part Marking Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1
Part Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10. Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11. AT34C04 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
12. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.1
12.2
12.3
8S1 — 8-lead JEDEC SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8X — 8-lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8MA2 — 8-pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
1.
Description
The Atmel® AT34C04 is a 1.7V rated minimum operating voltage Serial EEPROM device containing 4096-bits of
Serially Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 512-bytes of eight
bits each. The Serial EEPROM operation is tailored specifically for DRAM memory modules with Serial Presence
Detect (SPD) to store a module’s vital product data such as the module’s size, speed, voltage, data width, and
timing parameters.
The AT34C04 is protocol compatible with the legacy JEDEC EE1002 specification (2-Kbit) devices enabling the
AT34C04 to be utilized in legacy applications without any software changes. The device is designed to respond to
specific software commands that allow users to identify and set which half of the memory the internal address
counter is located. This special page addressing method to select the upper or lower half of the Serial EEPROM is
what facilitates legacy compatibility. However, there is one exception to the legacy compatibility as the AT34C04
does not support the Permanent Write Protection feature.
Additionally, the AT34C04 incorporates a Reversible Software Write Protection (RSWP) feature enabling the
capability to selectively write protect any or all of the four 128-byte quadrants. Once the RSWP is set, it can only be
reversed by sending a specific software command sequence.
The AT34C04 supports the industry standard 2-wire I2C Fast-Mode Plus (FM+) serial interface allowing device
communication to operate at up to 1MHz. A bus timeout feature is supported to help prevent system lock-ups. The
AT34C04 is available in space saving SOIC, TSSOP, and UDFN packages.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
3
2.
Pin Descriptions and Pinouts
Table 2-1.
Pin Descriptions
Symbol
Name and Function
SCL
Serial Clock: The SCL pin is used to provide a clock to the device and is used
to control the flow of data to and from the device. Command and input data
present on the SDA pin is always latched in on the rising edge of SCL, while
output data on the SDA pin is always clocked out on the falling edge of SCL.
Asserted
State
Type
—
Input
—
Input/
Output
—
Input
The SCL pin must either be forced high when the serial bus is idle or pulled-high
using an external pull-up resistor.
Serial Data: The SDA pin is an open-drain bidirectional input/output pin used to
serially transfer data to and from the device.
SDA
The SDA pin must be pulled-high using an external pull-up resistor (not to
exceed 8K in value) and may be wire-ORed with any number of other
open-drain or open-collector pins from other devices on the same bus.
Device Address Inputs: The A0, A1, and A2 pins are used to select the device
address and corresponds to the three Least-Significant Bits (LSBs) of the I2C
FM+ seven bit slave address. These pins can be directly connected to VCC or
GND in any combination, allowing up to eight devices on the same bus.
A0, A1, A2
The A0 pin is also an overvoltage tolerant pin, allowing up to 10V to support the
Reversible Software Write Protection (RSWP) feature (see Section 8.).
NC
No Connect: The NC pin is not bonded to a die pad. This pin can be connected
to GND or left floating.
—
—
VCC
Device Power Supply: The VCC pin is used to supply the source voltage to the
device. Operations at invalid VCC voltages may produce spurious results and
should not be attempted.
—
Power
GND
Ground: The ground reference for the power supply. GND should be connected
to the system ground.
—
Power
Figure 2-1.
Pinouts
8-lead TSSOP
8-lead SOIC
A0
1
8
VCC
A1
2
7
NC
A2
3
6
SCL
GND
4
5
SDA
Top View
Note:
4
A0
A1
A2
GND
1
2
3
4
8
7
6
5
Top View
8-pad UDFN
VCC
NC
SCL
SDA
VCC
NC
SCL
SDA
A0
A1
3 A2
4 GND
8
1
7
2
6
5
(1)
Bottom View
1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.
This pad can be a “no connect” or connected to GND.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
Block Diagram
A0
Hardware
Address
Comparator
Memory
System Control
Module
Power
On Reset
Generator
VCC
High Voltage
Generation Circuit
A1
Quadrant 0
Quadrant 1
4-Kbit EEPROM Array
Quadrant 2
Row Decoder
3.
Quadrant 3
Software Write
Protection
Control
Address Register
and Counter
1 page
Column Decoder
A2
SCL
Data Register
Data & ACK
DOUT Input/Output Control
GND
DIN
Start
Stop
Detector
SDA
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
5
4.
Device Communication
The AT34C04 operates as a slave device and utilizes a simple 2-wire digital serial interface, compatible with the
I2C Fast-Mode Plus (I2C FM+) protocol, to communicate with a host controller, commonly referred to as the bus
Master. The Master initiates and controls all Read and Write operations to the slave devices on the serial bus, and
both the Master and the slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: the Serial Clock (SCL) and the Serial Data (SDA). The
SCL pin is used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive
command and data information from the Master, as well as, to send data back to the Master. Data is always
latched into the AT34C04 on the rising edge of SCL and is always output from the device on the falling edge of
SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize
the effects of input spikes and bus noise.
All command and data information is transferred with the Most-Significant Bit (MSB) first. During the bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been
transferred, the receiving device must respond with either an acknowledge (ACK) or a no-acknowledge (NACK)
response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master. Therefore, nine clock
cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or
Write operation so there must not be any interruptions or breaks in the data stream during each data byte transfer
and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable
while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will
occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master and
the slave devices.The number of data bytes transferred between a Start and a Stop condition is not limited and is
determined by the Master.
In order for the serial bus to be idle, both the SCL and SDA pins must be in the Logic 1 state at the same time.
4.1
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in the
Logic 1 state. The Master uses a Start condition to initiate any data transfer sequence, therefore the Start condition
must precede any command. The AT34C04 will continuously monitor the SDA and SCL pins for a Start condition,
and the device will not respond unless one is given. Please refer to Figure 4-1 on page 7 for more details.
4.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the
Logic 1 state. The Master uses the Stop condition to end a data transfer sequence to the AT34C04 which will
subsequently return to the idle state. The Master can also utilize a repeated Start condition instead of a Stop
condition to end the current data transfer if the Master will perform another operation. Please refer to Figure 4-1 on
page 7 for more details.
6
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
4.3
Acknowledge (ACK)
After every byte of data is received, the AT34C04 must acknowledge to the Master that it has successfully received
the data byte by responding with an ACK. This is accomplished by the Master first releasing the SDA line and
providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the
AT34C04 must output a Logic 0 (ACK) for the entire clock cycle such that the SDA line must be stable in the Logic
0 state during the entire high period of the clock cycle. Please refer to Figure 4-1 on page 7 for more details.
4.4
No-Acknowledge (NACK)
When the AT34C04 is transmitting data to the Master, the Master can indicate that it is done receiving data and
wants to end the operation by sending a NACK response to the AT34C04 instead of an ACK response. This is
accomplished by the Master outputting a Logic 1 during the ACK/NACK clock cycle, at which point the AT34C04
will release the SDA line so that the Master can then generate a Stop condition.
In addition, the AT34C04 can use a NACK to respond to the Master instead of an ACK for certain invalid operation
cases such as an attempt to Write to a read-only register.
Figure 4-1.
Start, Stop, and ACK
SCL
SDA
Must Be
Stable
SDA
Must Be
Stable
1
2
Acknowledge Window
8
9
Stop
Condition
SDA
Acknowledge
Valid
Start
Condition
SDA
Change
Allowed
4.5
SDA
Change
Allowed
The transmitting device (Master or Slave)
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
The receiver (Master or Slave)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
Standby Mode
The AT34C04 incorporates a low-power Standby mode which is enabled:


Upon power-up or
After the receipt of a Stop condition and the completion of any internal operations.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
7
4.6
Device Reset and Initialization
The AT34C04 incorporates an internal Power-On Reset (POR) circuit to help prevent inadvertent operations during
power-up and power down cycles. On a cold power-up, the supply voltage must rise monotonically between
VPOR(max) and VCC(min) without any ring back to ensure a proper power-up (see Figure 4-2). Once the supply voltage
has passed the VPOR(min) threshold, the device internal reset process is initiated. Completion of the internal reset
process occurs within the tINIT time listed in Table 4-1.
Before selecting the device and issuing protocol, a valid and stable supply voltage must be applied and no protocol
should be issued to the device for the time specified by the tINIT parameter. The supply voltage must remain stable
and valid until the end of the protocol transmission, and for a Write instruction, until the end of the internal write
cycle.
Figure 4-2.
VCC
Power-up Timing
Cold
Power-On Reset
Warm
Power-On Reset
tINIT
Device Access
Permitted
VCC (min)
tPOR
VPOR (max)
VPOR (min)
Do Not Attempt
Device Access
During This Time
tPOFF
Time
Table 4-1.
Power-up Conditions
Symbol
8
Parameter
Min
Max
Units
10.0
ms
1.6
V
tPOR
Power-On Reset Time
VPOR
Power-On Reset Voltage Range
1.0
tINIT
Time from Power-On to First Command
10.0
ms
tPOFF
Warm Power Cycle Off Time
1.0
ms
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
4.7
Timeout Function
The AT34C04 supports the industry standard bus Timeout feature to help prevent potential system bus hang-ups.
The device resets its serial interface and will stop driving the bus (will let SDA float high) if the SCL pin is held low
for more than the minimum Timeout (tOUT) specification. The AT34C04 will be ready to accept a new Start condition
before the maximum tOUT has elapsed (see Figure 4-3). This feature does require a minimum SCL clock speed of
10kHz to avoid any timeout issues.
Figure 4-3.
Timeout
tTIMEOUT (MAX)
tTIMEOUT (MIN)
SCL
Device will release Bus and
be ready to accept a new
Start Condition within this Time
4.8
2-wire Software Reset
After an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps:
1.
Create a Start condition.
2.
3.
Clock nine cycles.
Create another Start condition followed by Stop condition as shown in Figure 4-4.
Figure 4-4.
2-wire Software Reset
Dummy Clock Cycles
1
SCL
Start
Condition
2
3
8
9
Start
Condition
Stop
Condition
SDA
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
9
5.
Device Addressing
The AT34C04 requires a 7-bit device address and a Read/Write select bit following a Start condition from the
Master to initiate communication with the Serial EEPROM. The device address byte is comprised of a 4-bit device
type identifier followed by three device address bits (A2, A1, and A0) and a R/W bit and is clocked by the Master on
the SDA pin with the most significant bit first (see Table 5-1).
The AT34C04 will respond to two unique device type identifiers. The device type identifier of ‘1010’(Ah) is
necessary to select the device for reading or writing. The device type identifier of ‘0110’(6h) has multiple
purposes. First, it is used to access the page address function which determines what the internal address counter
is set to. For more information on accessing the page address function, please refer to Section 7.1.1. The device
type identifier of ‘0110’(6h) is also used to access the software write protection feature of the device. Information
on the software write protection functionality can be found in Section 8.
Table 5-1.
AT34C04 Device Address Byte
Bit 7
Bit 6
Function
Bit 5
Bit 4
Bit 3
Device Type Identifier
Bit 2
Bit 1
Device Address
Bit 0
Read/Write
EEPROM Read/Write
1
0
1
0
A2
A1
A0
R/W
Write Protection and
Page Address Functions
0
1
1
0
A2
A1
A0
R/W
The software device address bits (A2, A1, and A0) must match their corresponding hard-wired device address
inputs (A2, A1 and A0) allowing up to eight devices on the bus at the same time (see Table 5-2). The eighth bit of
the address byte is the R/W operation selection bit. A read operation is selected if this bit is a Logic 1, and a Write
operation is selected if this bit is a Logic 0. Upon a compare of the device address byte, the AT34C04 will output an
ACK during the ninth clock cycle; if a compare is not true, the device will output a NACK during the ninth clock
cycle and return the device to the low-power Standby Mode.
Table 5-2.
Device Address Combinations
Software Device
Address Bits
10
Hard-wired Device Address Inputs
A2, A1, A0
A2
A1
A0
000
GND
GND
GND
001
GND
GND
VCC
010
GND
VCC
GND
011
GND
VCC
VCC
100
VCC
GND
GND
101
VCC
GND
VCC
110
VCC
VCC
GND
111
VCC
VCC
VCC
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
6.
Electrical Specifications
6.1
Absolute Maximum Ratings*
Temperature under Bias . . . . . . . . . . -40°C to +125°C
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
Supply voltage
with respect to ground . . . . . . . . . . . . . .-0.5V to +4.3V
All other input voltages
with respect to ground . . . . . . . . . .-0.5V to VCC + 0.5V
All input voltages
with respect to ground . . . . . . . . . .-0.5V to VCC + 0.5V
Table 6-1.
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. Functional operation of the device at these
ratings or any other conditions beyond those indicated
in the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability. Voltage extremes referenced in the “Absolute
Maximum Ratings” are intended to accommodate short
duration undershoot/overshoot conditions and does not
imply or guarantee functional device operation at these
levels for any extended period of time.
DC Characteristics
Applicable over recommended operating range: TA = –20°C to +125°C, VCC = 1.7V to 3.6V (unless otherwise
noted).
Symbol
Parameter
VCC
Supply Voltage
ICC1
Supply Current
VCC = 3.6V
Read at 100kHz
ICC2
Supply Current
VCC = 3.6V
ISB
Standby Current
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Level(1)
VIH
Input High Level(1)
VOL1
Low-Level Output Voltage
Open-Drain
VOL2
IOL
Low-Level Output Current
Test Condition
Min
Typ
Max
Units
3.6
V
0.4
1.0
mA
Write at 100kHz
1.5
3.0
mA
VCC = 1.7V
VIN = VCC or VSS
1.6
3.0
μA
VCC = 3.6V
VIN = VCC or VSS
1.6
4.0
μA
VIN = VCC or VSS
0.1
2.0
μA
VOUT = VCC or VSS
0.1
2.0
μA
-0.5
0.3 * VCC
V
0.7 * VCC
VCC + 0.5
V
1.7
VCC > 2V
IOL = 3mA
0.4
V
VCC ≤ 2V
IOL = 2mA
0.2 * VCC
V
VOL = 0.4V
Freq ≤ 400kHz
3.0
mA
VOL = 0.6V
Freq ≤ 400kHz
6.0
mA
VOL = 0.4V
Freq > 400kHz
20.0
mA
VHV
A0 Pin High Voltage
VHYST1
Input Hysteresis (SDA, SCL)
VCC < 2V
0.10 * VCC
V
VHYST2
Input Hysteresis (SDA, SCL)
VCC ≥ 2V
0.05 * VCC
V
Note:
1.
VHV - VCC ≥ 4.8V
7
10
V
VIL min and VIH max are reference only and are not tested.
AT34C04 [DATASHEET]
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11
Table 6-2.
AC Characteristics
Applicable over recommended operating range: TA = –20°C to +125°C, VCC = 1.7V to 3.6V, CL = 1 TTL Gate and
100μF (unless otherwise noted).
VCC < 2.2V
100kHz
400kHz
1000kHz
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
fSCL
Clock Frequency, SCL
10(2)
100
10(2)
400
10(2)
1000
kHz
tLOW
Clock Pulse Width Low
4700
1300
500
ns
tHIGH
Clock Pulse Width High
4000
600
260
ns
tI
Noise Suppression Time
tBUF
Time the bus must be free before a
new transmission can start(1)
4700
1300
500
ns
tHD.STA
Start Hold Time
4000
600
260
ns
tSU.STA
Start Set-up Time
4700
600
260
ns
tHD.DI
Data In Hold Time
0.0
0.0
0.0
ns
tSU.DAT
Data In Set-up Time
250
100
50
ns
tR
Inputs Rise Time(1)
50
(1)
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
4000
tHD.DAT
Data Out Hold Time
200
tWR
Write Cycle Time
tOUT
Timeout Time
Endurance
25°C, Page Mode(1)
Notes:
12
VCC ≥ 2.2V
1.
2.
50
20
300
120
ns
300
20
300
120
ns
600
3450
200
35
260
900
0
5
25
35
25
1,000,000
This parameter is ensured by characterization only.
The minimum frequency is specified at 10kHz to avoid activating the timeout feature.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
ns
1000
5
25
50
ns
350
ns
5
ms
35
ms
Write Cycles
Figure 6-1.
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
tF
tHIGH
tR
tLOW
SCL
tSU.STA
tHD.STA
tLOW
tHD.DAT
tSU.DAT
tSU.STO
SDA
tBUF
Table 6-3.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1 MHz, VCC = 1.7V - 3.6V.
Symbol
Test condition
CI/O
CIN
Note:
1.
Max
Units
Conditions
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
This parameter is ensured by characterization only.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
13
7.
Read and Write Operations
7.1
Memory Organization
To provide the greatest flexibility and backwards compatibility with the previous generations of SPD devices, the
AT34C04 memory organization is organized into two independent 2-Kbit memory arrays. Each 2-Kbit (256-byte)
section is internally organized into two independent quadrants of 128 bytes with each quadrant comprised of eight
pages of 16 bytes. Including both memory sections, there are four 128-byte quadrants totaling 512 bytes. The
memory array organization details are shown in Section 3. on page 5 and Table 7-1.
7.1.1
Set Page Address and Read Page Address Commands
The AT34C04 incorporates an innovative memory addressing technique that utilizes a Set Page Address (SPA)
and Read Page Address (RPA) commands to select and verify the desired half of the memory enabled to perform
Write and Read operations. Due to the requirement for A0 pin to be driven to VHV, the SPA and the RPA commands
are fully supported in a single DIMM (isolated DIMM) end application or a single DIMM programming station only.
Example:
If SPA = 0, then the first-half or lower 256 bytes of the Serial EEPROM is selected allowing access to
Quadrant 0 and Quadrant 1. Alternately, if SPA = 1, then the second-half or upper 256 bytes of the
Serial EEPROM is selected allowing access to Quadrant 2 and Quadrant 3.
Table 7-1.
SPA Setting and Memory Organization
Block
Set Page Address (SPA)
Quadrant 0
Memory Address Locations
00h to 7Fh
0
Quadrant 1
Quadrant 2
80h to FFh
00h to 7Fh
1
Quadrant 3
80h to FFh
Setting the Set Page Address (SPA) value selects the desired half of the EEPROM for performing Write or Read
operations. This is done by sending the SPA as seen in Figure 7-1. The SPA command sequence requires the
Master to transmit a Start condition followed by sending a control byte of ‘011011*0’ where the ‘*’ in the bit 7
position will dictate which half of the EEPROM is being addressed. A ‘0’ in this position (or 6Ch) is required to set
the page address to the first half of the memory and a ‘1’ (or 6Eh) is necessary to set the page address to the
second half of the memory. After receiving the control byte, the AT34C04 should return an ACK and the Master
should follow by sending two data bytes of don’t care values. The AT34C04 responds with a NACK to each of
these two data bytes although the JEDEC EE1004v specification allows for either an ACK or NACK response. The
protocol is completed by the Master sending a Stop condition to end the operation.
Figure 7-1.
Set Page Address (SPA)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
X
1
SCL
Control Byte
SDA
0
1
1
0
1
Most Significant Data Byte
1
*
0
0
MSB
Start
by
Master
X
X
X
X
X
X
X
Least Significant Data Byte
X
1
MSB
ACK
from
Slave
X
NACK
from
Slave
Bit * = 0: Indicates the page address is located in the first half of the memory.
Bit * = 1: Indicates the page address is located in the second half of the memory.
14
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Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
X
X
X
X
X
X
MSB
NACK
from
Slave
Stop
by
Master
Reading the state of the SPA can be accomplished via the Read Page Address (RPA) command. The Master can
issue the RPA command to determine if the AT34C04’s internal address counter is located in the first 2-Kbit
section or the second 2-Kbit memory section based upon the device’s ACK or NACK response to the RPA
command.
The RPA command sequence requires the Master to transmit a Start bit followed by a control byte of ‘01101101’
(6Dh). If the device’s current address counter (page address) is located in the first half of the memory, the
AT34C04 responds with an ACK to the RPA command. Alternatively, a NACK response to the RPA command
indicates the page address is located in the second half of the memory (see Figure 7-2). Following the control byte
and the device’s ACK or NACK response, the AT34C04 should transmit two data bytes of don’t care values. The
Master should NACK on these two data bytes followed by the Master sending a Stop condition to end the
operation.
After power-up, the SPA is set to zero indicating internal address counter is located in the first half of the memory.
Performing a software reset (see 2-wire Software Reset on page 9) will also set the SPA to zero.
The AT34C04 incorporates a Reversible Software Write Protect (RSWP) feature that allows the ability to
selectively write protect data stored in any or all of the four 128-byte quadrants. See Section 8. “Write Protection”
on page 21 for more information on the RSWP feature.
Figure 7-2.
Read Page Address (RPA)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
X
1
SCL
Control Byte
SDA
0
MSB
Start
by
Master
1
1
0
1
Most Significant Data Byte
1
0
1
*
X
X
X
X
X
X
X
Least Significant Data Byte
X
1
MSB
ACK or NACK
from
Slave
X
X
X
X
X
X
X
MSB
NACK
from
Master
NACK
from
Master
Stop
by
Master
Bit * = 0: ACK indicates the device’s internal address counter is located in the first half of the memory.
Bit * = 1: NACK indicates the device’s internal address counter is located in the second half of the memory.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
15
7.2
Read Operations
All Read operations are initiated by the Master transmitting a Start bit, a device type identifier of ‘1010’ (Ah),
three software address bits (A2, A1, A0) that match their corresponding hard-wired address pins (A2, A1, A0), and
the R/W select bit with a Logic 1 state. In the following clock cycle, the device should respond with an ACK. The
subsequent protocol depends on the type of Read operation desired. There are three Read operations: Current
Address Read, Random Address Read, and Sequential Read.
Caution:
7.2.1
All Read operations should be preceded by the SPA and/or RPA commands to ensure the desired half of
the memory is selected. The reason this is important, for example, during a Sequential Read operation on
the last byte in the first half of the memory (address FFh) with SPA=0 (indicating first half is selected), the
internal address counter will roll-over to address 00h in the first half of memory as opposed to the first byte
in the second half of the memory. For more information on the SPA and RPA commands, see Section 7.1.1
on page 14.
Current Address Read
Following a Start condition, the Master only transmits the device address byte with the R/W select bit set to a
Logic 1 (see Figure 7-3). The AT34C04 should respond with an ACK and then serially transmits the data word
addressed by the internal address counter. The internal data word address counter maintains the last address
accessed during the last Read or Write operation, incremented by one. This address stays valid between
operations as long as power to the device is maintained. The address roll-over during a Read is from the last byte
of the last page to the first byte of the first page of the addressed 2-Kbit (depends on the current SPA setting). To
end the command, the Master does not respond with an ACK but does generate a following Stop condition.
Figure 7-3.
Current Address Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D2
D1
D0
1
SCL
Device Address Byte
SDA
1
0
1
0
A2
A1
Data Word (n)
A0
1
0
MSB
Start
by
Master
7.2.2
D7
D6
D5
D4
D3
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
Random Read
A Random Read operation allows the Master to access any memory location in a random manner and requires a
dummy write sequence to preload the starting data word address. To perform a Random Read, the device address
byte and the word address byte are transmitted to the AT34C04 as part of the dummy write sequence (see Figure
7-4). Once the device address byte and data word address are clocked in and acknowledged by the AT34C04, the
Master must generate another Start condition. The Master initiates a Current Address Read by sending another
device address byte with the R/W select bit to a Logic 1. The AT34C04 acknowledges the device address byte,
increments its internal address counter and serially clocks out the first data word. The device will continue to
transmit sequential data words as long as the Master continues to ACK each data word. To end the sequence, the
Master responds with a NACK and a Stop condition.
16
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Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
Figure 7-4.
Random Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1
A0
0
SCL
Device Address Byte
SDA
1
0
1
0
A2
Word Address Byte
A1
A0
0
0
A7
MSB
A6
A5
A4
A3
A2
MSB
Start
by
Master
ACK
from
Slave
ACK
from
Slave
Dummy Write
1
2
3
4
5
6
7
8
9
1
2
0
1
0
A2
A1
A0
1
0
D7
MSB
5
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
1
MSB
Start
by
Master
7.2.3
4
Data Word (n)
Device Address Byte
1
3
NACK
from
Master
ACK
from
Slave
Stop
by
Master
Sequential Read
A Sequential Read operation is initiated in the same way as a Random Read operation, except after the AT34C04
transmits the first data word, the Master responds with an ACK (instead of a NACK followed by a Stop condition).
As long as the AT34C04 receives an ACK, it will continue to increment the data word address and serially clock out
the sequential data words (see Figure 7-5). When the internal address counter is at the last byte of the last page,
the data word address will roll-over to the beginning of the selected 2-Kbit array (depending on the SPA setting)
starting at address zero, and the Sequential Read operation will continue. The Sequential Read operation is
terminated when the Master responds with a NACK followed by a Stop condition.
Figure 7-5.
Sequential Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D2
D1
D0
0
SCL
Device Address Byte
SDA
1
0
1
0
A2
Data Word (n)
A0
A1
1
0
D7
MSB
Start
by
Master
1
D5
D4
D3
ACK
from
Master
ACK
from
Slave
2
3
4
5
6
7
8
9
1
2
Data Word (n+1)
D7
D6
MSB
D6
D5
D4
D3
D2
3
4
5
6
7
8
9
1
2
D1
D0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
MSB
ACK
from
Master
4
5
6
7
8
9
D1
D0
1
Data Word (n+x)
Data Word (n+2)
MSB
3
D7
D6
D5
D4
D3
D2
MSB
ACK
from
Master
NACK
from
Master
Stop
by
Master
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
17
7.3
Write Operations
The AT34C04 supports single Byte Write and Page Write operations up to the maximum page size of 16 bytes in one
operation. The only difference between a Byte Write and a Page Write operation is the amount of data bytes sent to the
device. Regardless of whether a Byte Write or Page Write operation is performed, the internally self-timed write cycle will
take the same amount of time to write the data to the addressed memory location(s).
Caution:
All Byte Write and Page Write operations should be preceded by the SPA and or RPA commands to ensure
the internal address counter is located in the desired half of the memory.
If a Byte Write or Page Write operation is attempted to a protected quadrant, the AT34C04 will respond (ACK or
NACK) to the write operation according to Table 7-2.
Table 7-2.
Acknowledge Status When Writing Data or Defining Write Protection
Instruction
ACK
Word
Address
ACK
Data
Word
ACK
Write
Cycle
Set RSWP
NACK
Don’t Care
NACK
Don’t Care
NACK
No
Clear RSWP
ACK
Don’t Care
ACK
Don’t Care
ACK
Yes
Byte Write or Page
Write to Protected
Quadrant
ACK
Word
Address
ACK
Data
NACK
No
ACK
Don’t Care
ACK
Don’t Care
ACK
Yes
ACK
Word
Address
ACK
Data
ACK
Yes
Quadrant Status
Write Protected
with Set RSWP
Set RSWP or
Clear RSWP
Not Protected
Byte Write or Page
Write
7.3.1
Byte Write
Following the Start condition from the Master, the device type identifier (‘1010’), the device address bits and the
R/W select bit (set to a Logic 0) are clocked onto the bus by the Master. This indicates to the addressed device that
the Master will follow by transmitting a byte with the word address. The AT34C04 will respond with an ACK during
the ninth clock cycle. Then the next byte transmitted by the Master is the 8-bit word address of the byte location to
be written into the Serial EEPROM. After receiving an ACK from the AT34C04, the Master transmits the data word
to be programmed followed by an ACK from the AT34C04. The Master ends the Write sequence with a Stop
condition during the 10th clock cycle to initiate the internally self-timed write cycle. A Stop condition issued during
any other clock cycle during the Write operation will not trigger the internally self-timed write cycle. Once the write
cycle begins, the pre-loaded data word will be programmed in the amount of time not to exceed the tWR
specification. The tWR time is defined in more detail in Section 7.3.4 on page 20. During this time, the Master should
wait a fixed amount of time set to the tWR specification, or for time sensitive applications, an ACK polling routine can
be implemented. All inputs are ignored by the device during the write cycle and the device will not respond until the
write cycle is complete (see Figure 7-9). The Serial EEPROM will increment its internal address counter each time
a byte is written.
Figure 7-6.
Byte Write
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D2
D1
D0
0
SCL
Device Address Byte
SDA
1
0
1
0
A2
A1
Word Address Byte
A0
0
0
MSB
Start
by
Master
18
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Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
A7
A6
A5
A4
A3
A2
Data Word
A1
A0
0
MSB
ACK
from
Slave
D7
D6
D5
D4
D3
MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
7.3.2
Page Write
The 4-Kbit Serial EEPROM is capable of writing up to 16 data bytes at a time executing the Page Write protocol
sequence. A partial or full Page Write operation is initiated the same as a Byte Write operation except that the
Master does not send a Stop condition after the first data word is clocked in. Instead, after the device has
acknowledged receipt of the first data word, the Master can transmit up to fifteen more data words. The device will
respond with an ACK after each data word is received. The Master must terminate the Page Write sequence with a
Stop condition during the 10th clock cycle (see Figure 7-7) to start the write cycle. A Stop condition issued at any
other clock cycle will not initiate the internally self-timed write cycle and the Write sequence will have to be
repeated again.
Once the write cycle begins, the data words should be programmed in the amount of time not exceed the tWR
parameter (see Figure 7-9). During this time, the Master should wait a fixed amount of time set to the specified tWR
parameter, or for time sensitive applications, an Acknowledge polling routine can be implemented as described in
Section 7.3.3. The tWR time is defined in more detail in Section 7.3.4 on page 20. The lower four bits of the data
word address are internally incremented following the receipt of each data word. The higher data word address bits
are not incremented, retaining the memory page row location. When the internally generated word address
reaches the page boundary, then the following data word is placed at the beginning of the same page. If more than
sixteen data words are transmitted to the device, the data word address will roll-over and the previous data will be
overwritten. The address roll-over during a Write sequence is from the last byte of the current page to the first byte
of the same page.
Figure 7-7.
Page Write
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1
A0
0
SCL
Device Address Byte
SDA
1
0
1
0
A2
A1
Word Address Byte
A0
0
0
A7
MSB
Start
by
Master
1
A5
A4
A3
A2
ACK
from
Slave
ACK
from
Slave
2
3
4
5
6
7
8
9
1
2
D6
D5
D4
D3
D2
3
4
5
6
7
8
9
1
2
D1
D0
0
MSB
D7
D6
D5
D4
D3
D2
D1
D0
0
MSB
ACK
from
Slave
3
4
5
6
7
8
9
D1
D0
0
Data Word (n+15)
Data Word (n+1)
Data Word (n)
D7
A6
MSB
D7
D6
D5
D4
D3
D2
MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
19
7.3.3
Acknowledge (ACK) Polling
An ACK polling routine can be implemented to optimize time sensitive applications that would not prefer waiting the
fixed maximum write cycle time and would prefer to know immediately when the Serial EEPROM write cycle has
completed to start a subsequent operation. Once the internally self timed write cycle has started (the Stop
condition during the 10th clock cycle at the end of the Write sequence), the device inputs are disabled and ACK
polling can be initiated (see
Figure 7-8). An ACK polling routine involves sending a valid Start condition followed by the device address byte.
While the write cycle is in progress, the device will not respond with an ACK indicating the device is busy writing
data. Once complete, the device will ACK and the next device operation can be started.
Figure 7-8.
Acknowledge Polling Flow Chart
Send
Stop
Condition
to Initiate
Write Cycle
Send Any
Write
Protocol
Send Start
Condition
Followed
by Valid
Device Address
Byte
Did
the Device
ACK?
YES
Continue to
Next Operation
NO
7.3.4
Write Cycle Timing
The length of the self timed write cycle, or tWR, is defined as the amount of time from a valid Stop condition that
begins the internal write sequence to the Start condition of the first device address byte sent to the AT34C04 that it
subsequently responds to with an ACK. Figure 7-9 has been included to show this measurement.
Figure 7-9.
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
8
9
9
ACK
ACK
Data Word n
SDA
D0
tWR
Stop
Condition
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Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
Start
Condition
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minumum tWR
can only be determined through
the use of an ACK Polling routine.
Stop
Condition
8.
Write Protection
The AT34C04 incorporates a Reversible Software Write Protection (RSWP) feature that allows the ability to
selectively write protect data stored in each of the four independent 128-byte EEPROM quadrants. Table 8-1
identifies the memory quadrant identifier with its associated quadrant, SPA and memory address locations.
The AT34C04 has three RSWP software commands:



Set RSWP command for setting the RSWP.
Clear RSWP command for resetting all of the quadrants to an unprotected state.
Read RSWP command for checking the RSWP status.
Table 8-1.
8.1
Memory Organization
Block
SPA
Address Locations
Memory Quadrant Identifier
Quadrant 0
0
00h to 7Fh
001
Quadrant 1
0
80h to FFh
100
Quadrant 2
1
00h to 7Fh
101
Quadrant 3
1
80h to FFh
000
Set RSWP
Setting the RSWP is enabled by sending the Set RSWP command, similar to a normal Write command to the
device which programs the write protection to the target quadrant. The Set RSWP sequence requires sending a
control byte of ‘0110MMM0’ (where ‘M’ represents the memory quadrant identifier for the target quadrant to be
write-protected) with the R/W bit set to a Logic 0. In conjunction with sending the protocol, the A0 pin must be
connected to VHV for the duration of the RSWP sequence (see Figure 8-1). The Set RSWP command acts on a
single quadrant only as specified in the Set RSWP command and can only be reversed by issuing the Clear RSWP
command and will unprotect all quadrants in one operation (see Table 8-2).
Example:
If Quadrant 0 and Quadrant 3 are to be write-protected, two separate Set RSWP commands would
be required; however, only one Clear RSWP command is needed to clear and unprotect both
quadrants.
Table 8-2.
Set RSWP and Clear RSWP
Control Byte
Pin
Function
A2
A1
Set RSWP, Quadrant 0
X
Set RSWP, Quadrant 1
Memory Quadrant
Identifier
Device Type Identifier
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
1
0
X
X
1
0
0
0
Set RSWP, Quadrant 2
X
X
1
0
1
0
Set RSWP, Quadrant 3
X
X
0
0
0
0
Clear RSWP
X
X
0
1
1
0
Notes:
1.
2.
3.
A0
VHV
Bit 7
0
Bit 6
1
Bit 5
1
Bit 4
R/W
0
X = Don’t care but recommended to be hard-wired to VCC or GND.
See Table 6-1 for VHV value.
Due to the requirement for the A0 pin to be driven to VHV, the RSWP set and RSWP clear commands are fully
supported in a single DIMM (isolated DIMM) end application or a single DIMM programming station only.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
21
Figure 8-1.
Set RSWP and Clear RSWP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
X
X
X
0/1
SCL
Control Byte
SDA
0
1
1
0
M
Word Address Byte
M
M
0
0
MSB
X
X
X
X
X
X
Data Word
X
X
0/1
MSB
Start
by
Master
X
X
X
X
X
MSB
ACK
from
Slave
Stop
by
ACK or NACK
Master
from
Slave
ACK or NACK
from
Slave
M = Memory Quadrant Identifier
X = Don’t care
8.2
Clear RSWP
Similar to the Set RSWP command, the reversible write protection on all quadrants can be reversed or unprotected
by transmitting the Clear RSWP command. The Clear RSWP sequence requires the Master to send a Start
condition followed by sending a control byte of ‘01100110’(66h) with the R/W bit set to a Logic 0. The AT34C04
should respond with an ACK. The Master transmits a word address byte and data bytes with don’t care values. The
AT34C04 will respond with either an ACK or NACK to both the word address and data word. In conjunction with
sending the protocol, the A0 pin must be connected to VHV for the duration of the Clear RSWP command (see
Figure 8-1). To end the Clear RSWP sequence, the Master sends a Stop condition.
Caution:
8.3
The write protection of individual quadrants cannot be reversed separately, and executing the Clear RSWP
command will clear the write protection on all four quadrants leaving all quadrants with no software write
protection.
Read RSWP
The Read RSWP command allows the ability to check a quadrant’s write protection status. To find out if the
software write protection has been set to a specific quadrant, the same procedure that was used to set the
quadrant’s write protection can be utilized except that the R/W select bit is set to a Logic 1, and the A0 pin is not
required to have VHV (see Table 8-4).
The Read RSWP sequence requires sending a control byte of ‘0110MMM1’ (where the ‘M’ represents the
memory quadrant identifier for the quadrant to be read) with the R/W bit set to a Logic 1 (see Figure 8-2).
If the RSWP has not been set, then the AT34C04 responds to the control byte with an ACK. If the RSWP has been
set, the AT34C04 responds with a NACK. In either case, both Word Address and Data Word bytes will not be
acknowledged. The operation is completed by the Master creating a Stop Condition. A summary of the response is
shown in Table 8-3.
Table 8-3.
22
Acknowledge When Reading Protection Status
Word
Address
Sent
Word
Address
Response
Data Word
Sent
Data
Word
Response
Quadrant Status
Instruction Sent
Instruction
Response
Write Protected
Read RSWP
NACK
Don’t Care
NACK
Don’t Care
NACK
Not Protected
Read RSWP
ACK
Don’t Care
NACK
Don’t Care
NACK
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
Table 8-4.
Read RSWP
Control Byte
Pin
Function
A2
A1
Read RSWP, Quadrant 0
X
X
Read RSWP, Quadrant 1
X
X
Read RSWP, Quadrant 2
X
X
Read RSWP, Quadrant 3
X
X
Note:
1.
Figure 8-2.
Memory Quadrant
Identifier
Device Type Identifier
A0
B7
0, 1
or VHV
B6
0
B5
1
B4
1
0
R/W
B3
B2
B1
B0
0
0
1
1
1
0
0
1
1
0
1
1
0
0
0
1
X = Don’t care but recommend to be hard-wired to VCC or GND.
Read RSWP
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
X
X
X
1
SCK
Control Byte
SDA
0
1
1
0
M
Word Address Byte
M
MSB
Start
by
Master
M
1
0/1
X
X
X
X
X
X
Data Byte
X
X
1
MSB
ACK or NACK
from
Slave
X
X
X
X
X
MSB
NACK
from
Master
NACK
from
Master
Stop
by
Master
M = Memory Quadrant Identifier
X = Don’t care
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
23
9.
Part Marking Detail
9.1
Part Markings
AT34C04: Package Marking Information
8-lead TSSOP
8-lead SOIC
AT5YWW
44 M @
AAAAAAA
ATML5YWW
44 M
@
AAAAAAAA
8-lead UDFN
2.0 x 3.0 mm Body
44
5M@
YXX
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT34C04
Truncation Code ##: 44
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
M = Month
A: January
B: February
...
L: December
6: 2016
7: 2017
8: 2018
9: 2019
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
M: 1.7V min
Grade/Lead Finish Material
5: Industrial (C)
(-20°C to 125°C)/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
8/16/12
TITLE
Package Drawing Contact:
[email protected]
24
34C04SM, AT34C04 Package Marking Information
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
DRAWING NO.
REV.
34C04SM
B
10.
Ordering Code Detail
AT 3 4 C 0 4 - M A 5 M - T
Atmel Designator
Shipping Carrier Option
B
T
=
=
Bulk (tubes)
Tape and reel
Product Family
Voltage Option
34C = I2C-compatible
Serial Presence Detect (SPD)
Serial EEPROM
M
=
1.7V to 3.6V
Device Grade
5
Device Density
=
04 = 4-Kbit
Green, NiPdAu Lead Finish
Temperature Range
(-20°C to +125°C)
Package Option
SS =
X =
MA =
11.
JEDEC SOIC
TSSOP
UDFN
AT34C04 Ordering Information
Additional package types that are not listed below may be available for order. Please contact Atmel for availability details.
Ordering Code(1)
AT34C04-SS5M-B(2)
AT34C04-SS5M-T(3)
AT34C04-X5M-B(2)
(3)
AT34C04-X5M-T
AT34C04-MA5M-T(3)
Notes:
1.
2.
3.
Package
Lead Finish
Voltage
Operational Range
NiPdAu
1.7V to 3.6V
–20C to 125C
8S1
8X
8MA2
Consistent with the general semiconductor market trend, Atmel will supply devices with either gold or copper bond
wires to increase manufacturing flexibility and ensure a long-term continuity of supply. There is no difference in
product quality, reliability, or performance between the two variations.
B = Bulk delivery in tubes

SOIC and TSSOP = 100 per tube
T = Tape and reel

SOIC = 4K per reel

UDFN and TSSOP = 5K per reel
Package Type
8S1
8-lead, 0.150” wide body, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.0 x 3.0mm body, 0.5mm pitch, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead (UDFN)
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
25
12.
Package Information
12.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
26
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
GPC
SWB
DRAWING NO.
REV.
8S1
G
12.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
H
N
L
Top View
End View
A
b
A1
e
A2
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
NOTE
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
–
0.30
4
e
0.65 BSC
L
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
12/8/11
TITLE
Package Drawing Contact:
[email protected]
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
REV.
E
27
12.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
8
1
7
2
Pin#1 ID
6
D2
3
5
4
e (6x)
K
L (8x)
SYMBOL
MIN
NOM
MAX
D
1.90
2.00
2.10
E
2.90
3.00
3.10
D2
1.40
1.50
1.60
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
–
–
0.55
C
L
NOTE
0.152 REF
0.30
e
0.35
0.40
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
3
9/6/12
Package Drawing Contact:
[email protected]
28
TITLE
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
GPC
YNZ
DRAWING NO.
8MA2
REV.
C
13.
Revision History
Doc. Rev.
Date
8827D
12/2013
Comments
Remove Preliminary datasheet status.
Remove part number, AT34C04-MA5M-B.
8827C
07/2013
Update electrical specifications.
Update footers and disclaimer page.
Increase VPOR maximum from 1.5V to 1.6V.
8827B
12/2012
Decrease tI 100kHz maximum from 100ns to 50ns.
Minor changes to DC and AC characteristic tables.
Update datasheet status from advance to preliminary.
8827A
09/2012
Initial document release.
AT34C04 [DATASHEET]
Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013
29
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© 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-8827D-SEEPROM-AT34C04-Datasheet_122013.
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