TI1 OPA2388 Precision, zero-drift, zero-crossover, true rail-to-rail input/output, operational amplifier Datasheet

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OPA388, OPA2388, OPA4388
SBOS777 – DECEMBER 2016
OPAx388 Precision, Zero-Drift, Zero-Crossover, True Rail-to-Rail Input/Output,
Operational Amplifiers
1 Features
3 Description
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The OPAx388 (OPA388, OPA2388, and OPA4388)
series of precision operational amplifiers are ultra-low
noise, fast-settling, zero-drift, zero-crossover devices
that provide rail-to-rail input and output operation.
These features and excellent ac performance,
combined with only 0.25 µV of offset and 0.005 µV/°C
of drift over temperature, makes the OPAx388 ideal
for driving high-precision, analog-to-digital converters
(ADCs) or buffering the output of high-resolution,
digital-to-analog converters (DACs). This design
results in superior performance when driving analogto-digital converters (ADCs) without degradation of
linearity. The OPA388 (single version) is available in
the VSSOP-8, SOT23-5, and SOIC-8 packages. The
OPA2388 (dual version) is offered in the VSSOP-8
and SO-8 packages. The OPA4388 (quad version) is
offered in the TSSOP-14 and SO-14 packages. All
versions are specified over the extended industrial
temperature range (–40°C to +125°C).
Ultra-Low Offset Voltage: ±0.25 µV
Zero-Drift: ±0.005 µV/°C
Zero-Crossover: 140-dB CMRR True RRIO
Low Noise: 7.0 nV√Hz at 1 kHz
No 1/f Noise: 140 nVPP (0.1 Hz to 10 Hz)
Fast Settling: 2 µs (1 V to 0.01%)
Gain Bandwidth: 10 MHz
Single Supply: 2.5 V to 5.5 V
Dual Supply: ±1.25 V to ±2.75 V
True Rail-to-Rail Input and Output
EMI/RFI Filtered Inputs
Industry-Standard Packages:
– Single in SOIC-8, SOT-23-5, and VSSOP-8
– Dual in SOIC-8 and VSSOP-8
– Quad in SOIC-14 and TSSOP-14
Device Information(1)
2 Applications
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PART NUMBER
Bridge Amplifiers
Strain Gauges
Test Equipment
Current Shunt Measurement
Thermocouples, Thermopiles
Electronic Scales
Medical Instrumentation
Resistor Thermal Detectors
Precision Active Filters
OPA388
OPA2388
OPA4388
R4
100 k
Output Voltage (V)
REF5025
R4
100 k
R2
25 k
+5V
+5V
+5V
+SENSE
±
±
VOUT
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm x 3.90 mm
TSSOP (14)
5.00 mm x 4.40 mm
2.53
3
2.52
2
2.51
1
2.5
0
2.49
-1
GND
GND
-SENSE
Load Cell
GND
NŸ
G=5+
-2
2.48
+
+
GND
2.90 mm × 1.60 mm
VSSOP (8)
OPA388
OPA388
R2
10 k
SOT-23 (5)
OPA388 Allows Precision, Low-Error
Measurements
RG
+5V
BODY SIZE (NOM)
4.90 mm × 3.90 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPA388 in a High-CMRR, Instrumentation
Amplifier Application
R3
25 k
PACKAGE
SOIC (8)
Non-Linearity (ppm)
1
RG
RG = 1 kŸ
2.47
±100 ±80 ±60 ±40 ±20
-3
0
20
û5 5 SSP
40
60
80
100
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA388, OPA2388, OPA4388
SBOS777 – DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
5
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA388 ..................................
Electrical Characteristics: VS = ±1.25 V to ±2.75 V
(VS = 2.5 to 5.5 V)......................................................
6.6 Typical Characteristics ..............................................
6.7 Typical Characteristics ..............................................
7
8
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
8.3 System Examples ................................................... 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
6
8
9
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 18
15
15
15
17
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
2
DATE
REVISION
NOTES
December 2016
*
Initial release.
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SBOS777 – DECEMBER 2016
5 Pin Configuration and Functions
DBV Package: OPA388
5-Pin SOT
Top View
OUT
1
V±
2
5
V+
±
+
+IN
D and DGK Packages: OPA388
8-Pin SOIC and VSSOP
Top View
3
4
NC
1
±IN
2
+IN
3
V±
4
±IN
Not to scale
8
NC
±
7
V+
+
6
OUT
5
NC
Not to scale
Pin Functions: OPA388
PIN
OPA388
NAME
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DBV (SOT)
–IN
2
4
I
Inverting input
+IN
3
3
I
Noninverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
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D and DGK Packages: OPA2388
8-Pin SOIC and VSSOP
Top View
D and PW Packages: OPA4388
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
OUT B
±IN A
2
13
±IN D
6
±IN B
+IN A
3
12
+IN D
5
+IN B
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
OUT A
1
8
V+
±IN A
2
7
+IN A
3
V±
4
Not to scale
Not to scale
Pin Functions: OPA2388 and OPA4388
PIN
OPA2388
OPA4388
D (SOIC),
DGK (VSSOP)
D (SOIC),
PW (TSSOP)
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
—
9
I
Inverting input,,channel C
–IN D
—
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
NAME
I/O
DESCRIPTION
+IN B
5
5
I
Noninverting input, channel B
+IN C
—
10
I
Noninverting input, channel C
+IN D
—
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V–
4
11
—
Negative (lowest) power supply
V+
8
4
—
Positive (highest) power supply
4
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SBOS777 – DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS =
(V+) – (V–)
6
Dual-supply
±3
Common-mode
Voltage
Signal input pins
MAX
Single-supply
(V–) – 0.5
V
±0.5
Current
±10
mA
Continuous
Operating, TA
Temperature
–55
150
Junction, TJ
150
Storage, Tstg
(2)
V
(V+) + 0.5
Differential
Output short circuit (2)
(1)
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Single-supply
Dual-supply
Specified temperature
NOM
MAX
2.5
5.5
±1.25
±2.75
–40
125
UNIT
V
°C
6.4 Thermal Information: OPA388
OPA388
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
116
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
60
°C/W
RθJB
Junction-to-board thermal resistance
56
°C/W
ψJT
Junction-to-top characterization parameter
12.8
°C/W
ψJB
Junction-to-board characterization parameter
55.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.25
±5
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
±0.005
±0.05
µV/°C
PSRR
Power-supply rejection
ratio
TA = –40°C to +125°C
±0.1
±1
µV/V
±30
±350
TA = –40°C to +125°C
±7.5
µV
INPUT BIAS CURRENT
IB
Input bias current
TA = 0°C to +85°C
RIN = 100 kΩ
IOS
Input offset current
pA
±400
TA = –40°C to +125°C
±700
±60
±700
TA = 0°C to +85°C
±800
TA = –40°C to +125°C
±800
pA
NOISE
EN
Input voltage noise
eN
Input voltage noise density
IN
Input current noise density
f = 0.1 Hz to 10 Hz
0.14
f = 10 Hz
7
f = 100 Hz
7
f = 1 kHz
7
f = 10 kHz
µVPP
nV/√Hz
7
f = 1 kHz
100
fA/rtHz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = ±1.25 V
124
138
VS = ±2.75 V
124
140
(V–) < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
VS = ±1.25 V
114
134
(V–) – 0.05 V < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
VS = ±2.75 V
124
140
(V–) – 0.1 V < VCM < (V+) + 0.1 V
CMRR
Common-mode rejection
ratio
(V+) + 0.1
V
dB
INPUT IMPEDANCE
zid
Differential input
impedance
100 || 2
MΩ || pF
zic
Common-mode input
impedance
60 || 4.5
TΩ || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.1 V < VO < (V+) – 0.1 V, RLOAD = 10 kΩ
126
148
(V–) + 0.1 V < VO < (V+) – 0.1 V, RLOAD = 10 kΩ,
TA = –40°C to +125°C
120
126
(V–) + 0.2 V < VO < (V+) – 0.2 V, RLOAD = 2 kΩ
126
148
(V–) + 0.25 V < VO < (V+) – 0.25 V, RLOAD = 2 kΩ,
TA = –40°C to +125°C
120
126
dB
FREQUENCY RESPONSE
GBW
Unity-gain bandwidth
SR
Slew rate
G = +1, 4-V step
THD+N
Total harmonic distortion +
noise
G = 1, f = 1 kHz, VO = 1 VRMS
tS
tOR
6
MHz
5
V/µs
0.0005%
To 0.1%
VS = ±2.5 V, G = +1,
1-V step
0.75
To 0.01%
VS = ±2.5 V, G = +1,
1-V step
2
Settling time
Overload recovery time
10
VIN × G = VS
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µs
10
µs
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Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
No load
1
15
RLOAD = 10 kΩ
5
20
RLOAD = 2 kΩ
20
50
5
15
RLOAD = 10 kΩ
10
20
RLOAD = 2 kΩ
40
60
10
25
UNIT
OUTPUT
Positive rail
VO
Voltage output swing from
rail
No load
Negative rail
TA = –40°C to +125°C, both rails, RLOAD = 10 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
VS = 5.5 V
±60
VS = 2.5 V
±30
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, see Figure 23
150
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
TA = –40°C to +125°C, IO = 0 A
VS = ±1.25 V
(VS = 2.5 V)
1.7
2.4
VS = ±2.75 V
(VS = 5.5 V)
1.9
2.6
mA
TEMPERATURE
TA
Specified range
–40
125
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6.6 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution From –40°C to +125°C
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Power Supply
Figure 5
Open-Loop Gain and Phase vs Frequency
Figure 6
Closed-Loop Gain and Phase vs Frequency
Figure 7
Input Bias Current vs Common-Mode Voltage
Figure 8
Input Bias Current vs Temperature
Figure 9
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 10
CMRR and PSRR vs Frequency
Figure 11
CMRR vs Temperature
Figure 12
PSRR vs Temperature
Figure 13
0.1-Hz to 10-Hz Noise
Figure 14
Input Voltage Noise Spectral Density vs Frequency
Figure 15
THD+N Ratio vs Frequency
Figure 16
THD+N vs Output Amplitude
Figure 17
Spectral Content
Figure 18, Figure 19
Quiescent Current vs Supply Voltage
Figure 20
Quiescent Current vs Temperature
Figure 21
Open-Loop Gain vs Temperature
Figure 22
Open-Loop Output Impedance vs Frequency
Figure 23
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
Figure 24
No Phase Reversal
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
Small-Signal Step Response (10-mV Step)
Figure 28, Figure 29
Large-Signal Step Response (4-V Step)
Figure 30 , Figure 31
Settling Time
Figure 32, Figure 33
Short-Circuit Current vs Temperature
Figure 34
Maximum Output Voltage vs Frequency
Figure 35
EMIRR vs Frequency
Figure 36
8
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6.7 Typical Characteristics
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15
50
45
10
Amplifiers (%)
Amplifiers (%)
40
5
35
30
25
20
15
10
5
Figure 1. Offset Voltage Production Distribution
0.05
0.04
0.02
0.01
0
0.03
C001
Figure 2. Offset Voltage Drift Distribution
From –40°C to +125°C
5
5
4
4
3
3
Input Offset Voltage ( V)
Input Offset Voltage ( V)
-0.01
Input Offset Voltage Drift (µV/ƒC)
C002
2
1
0
±1
±2
±3
±4
2
1
0
±1
±2
±3
VCM = ±2.85 V
VCM = 2.85 V
±4
±5
±5
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±3
C001
4
140
3
120
0
1
2
3
C003
2
1
0
±1
±2
180
Open-loop Gain
Open-loop Phase
90
80
60
45
40
20
0
0
VS = ± 2.75 V
135
100
Open-Loop Gain (ƒ)
Open-Loop Gain (dB)
160
VS = ± 1.25 V
±1
Figure 4. Offset Voltage vs Common-Mode Voltage
5
±3
±2
Input Common-mode Voltage (V)
Figure 3. Offset Voltage vs Temperature
Input Offset Voltage ( V)
-0.02
-0.03
Input Offset Voltage (µV)
-0.04
-0.05
5
4
3
2
1
0
-1
-2
-3
-4
0
-5
0
±20
±4
-45
±40
±5
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
Supply Voltage (V)
Figure 5. Offset Voltage vs Supply Voltage
3.0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
C021
Figure 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1500
G = +1
G= +10
G= +100
40
Input Bias Current (pA)
Closed-Loop Gain (dB)
60
20
0
-20
1000
500
0
±500
100
1k
10k
100k
1M
10M
±3
Frequency (Hz)
±2
0
±1
1
2
3
Input Common-mode Voltage (V)
C004
Figure 7. Closed-Loop Gain and Phase vs Frequency
C001
Figure 8. Input Bias Current vs Common-Mode Voltage
1.5
3
2.5
2
Output Voltage (V)
Input Bias Current (nA)
1.3
1.0
0.8
0.5
1.5
0
-0.5
±40°C
-1.5
-2
ios
-2.5
0.0
-3
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
0
20
30
40
50
60
70
80
Common-Mode Rejection Ratio (dB)
100
80
60
CMRR
+PSRR
20
±PSRR
0
180
0.001
160
0.01
140
0.1
120
1
100
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 11. CMRR and PSRR vs Frequency
C001
Common-Mode Rejection Ratio (µV/V)
120
10
100
Figure 10. Output Voltage Swing vs Output Current
(Maximum Supply)
140
1
90
Output Current (mA)
160
40
10
C001
Figure 9. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
125°C
-1
0.3
10
25°C
1
0.5
10
±75
±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C004
C001
Figure 12. CMRR vs Temperature
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Typical Characteristics (continued)
0.001
160
0.01
140
0.1
120
1
100
Input Voltage Noise (50 nV/div)
180
Power-Supply Rejection Ratio (µV/V)
Power-Supply Rejection Ratio (dB)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
10
±75
±50
±25
0
25
50
75
100
125
Time (1 s/div)
150
Temperature (ƒC)
C001
C017
Figure 14. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
1000
100
10
1
0.01
0.001
-100
0.0001
1
10
100
1k
10k
100k
Frequency (Hz)
20
Frequency (Hz)
0.01
-120
0.1
±40
±60
±80
±100
±120
±140
±160
±180
100
1
Output Amplitude (VRMS)
±20
FFT Spectral Content (dBc)
-100
Total Harmonic Distortion + Noise (dB)
0.0001
0.001
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
C004
0
-80
0.01
-120
20k
2k
Figure 16. THD+N Ratio vs Frequency
-60
0.1
0.001
200
C002
Figure 15. Input Voltage Noise Spectral Density
vs Frequency
Total Harmonic Distortion + Noise (%)
-80
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
Total Harmonic Distortion + Noise (dB)
Voltage Noise Spectral Density (nV/¥Hz)
Figure 13. PSRR vs Temperature
1k
10k
Frequency (Hz)
C004
100k
C004
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 10 kΩ, BW = 90 kHz
Figure 17. THD+N vs Output Amplitude
Figure 18. Spectral Content (With 10-kΩ Load)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0
2.5
±40
Quiescent Current (mA)
FFT Spectral Content (dBc)
±20
±60
±80
±100
±120
±140
2
1.5
1
0.5
±160
0
±180
100
1k
10k
100k
Frequency (Hz)
0
0.5
1
1.5
2
2.5
3
Supply Voltage (V)
C004
C001
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 2 kΩ, BW = 90 kHz
Figure 19. Spectral Content (With 2-kΩ Load)
Figure 20. Quiescent Current vs Supply Voltage
2.5
0.001
180
DC Open-loop Gain (dB)
2
1.5
1
0.5
0.01
160
0.1
140
VS = ± 1.1 V
120
1
100
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
10
±75
±25
0
25
50
75
100
125
150
Temperature (ƒC)
Figure 21. Quiescent Current vs Temperature
C001
Figure 22. Open-Loop Gain vs Temperature
100
90
100
G = -1
80
Overshoot (%)
Open-loop Output Impedance (Ÿ)
±50
C001
1k
10
1
70
60
50
40
30
100m
G = +1
20
10
10m
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
10
100
Capacitive Load (pF)
C003
Figure 23. Open-Loop Output Impedance vs Frequency
12
DC Open-loop Gain (µV/V)
Quiescent Current (mA)
VS = ± 2.75 V
1000
C004
Figure 24. Small-Signal Overshoot vs Capacitive Load
(10-mV Step)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Voltage (1 V/div)
Voltage (1.25 V/div)
VIN
VOUT
VOUT
VIN
Time (45 ms/div)
Time (200 ns/div)
C017
C017
Figure 25. No Phase Reversal
Figure 26. Positive Overload Recovery
VOUT
Voltage (2.5 mV/div)
Voltage (1 V/div)
VIN
VIN
VOUT
Time (200 ns/div)
Time (2.5 µs/div)
C017
C017
G = +1
Figure 27. Negative Overload Recovery
Figure 28. Small-Signal Step Response (10-mV Step)
VOUT
VIN
VIN
Voltage (1 V/div)
Voltage (2.5 mV/div)
VOUT
Time (2.5 µs/div)
Time (500 ns/div)
C017
C017
G = –1
Falling output
Figure 29. Small-Signal Step Response (10-mV Step)
Figure 30. Large-Signal Step Response (4-V Step)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VOUT
0.01% Settling = “100µV
Voltage (1 V/div)
Output Voltage (100 µV/div)
VIN
Time (500 ns/div)
Time (500 ns/div)
C017
C017
Rising output
0.01% settling = ±100 µV
Figure 31. Large-Signal Step Response (4-V Step)
Figure 32. Settling Time (1-V Positive Step)
100
0.01% Settling = “200µV
ISC, Sink
Short-Circuit Current (mA)
Output Voltage (100 µV/div)
90
80
70
60
50
ISC, Source
40
30
20
10
0
Time (500 ns/div)
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C017
C001
0.01% settling = ±200 µV
Figure 33. Settling Time (1-V Negative Step)
Figure 34. Short-Circuit Current vs Temperature
7
140
VS = ±2.5V
120
EMIRR IN+ (dB)
Output Voltage (VPP)
6
5
160
Maximum output voltage without
slew-rate induced distortion.
4
3
2
VS = ±0.9V
100
80
60
40
1
20
0
100
1k
10k
100k
Frequency (Hz)
1M
10M
0
10M
100M
1000M
Frequency (Hz)
C001
C004
PRF = –10 dBm
Figure 35. Maximum Output Voltage vs Frequency
14
Figure 36. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx388 family of zero-drift amplifiers is engineered with the unique combination of a proprietary precision
auto-calibration technique paired with a low-noise, low-ripple, input charge pump. These amplifiers offer ultra-low
input offset voltage and drift and achieve excellent input and output dynamic linearity. The OPAx388 operates
from 2.5 V to 5.5 V, is unity-gain stable, and is suitable for a wide range of general-purpose and precision
applications. The integrated, low-noise charge pump allows true rail-to-rail input common-mode operation without
distortion associated with complementary rail-to-rail input topologies (input crossover distortion). The OPAx388
strengths also include 10-MHz bandwidth, 7-nV/√Hz noise spectral density, and no 1/f noise, making the
OPAx388 optimal for interfacing with sensor modules and buffering high-fidelity, digital-to-analog converters
(DACs).
7.2 Functional Block Diagram
Low-noise
Charge-pump
GM_FF
CLK
CLK
CCOMP
+IN
OUT
±IN
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA3x88 family of operational amplifiers can be used with single or dual supplies from an operating range
of VS = 2.5 V (±1.25 V) up to 5.5 V (±2.75 V). Supply voltages greater than 7 V can permanently damage the
device (see Absolute Maximum Ratings). Key parameters that vary over the supply voltage or temperature range
are shown in the Typical Characteristics section.
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Feature Description (continued)
7.3.2 Input Voltage and Zero-Crossover Functionality
The OPAx388 input common-mode voltage range extends 0.1 V beyond the supply rails. This amplifier family is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers. Operating a complementary rail-to-rail input amplifier with signals traversing the transition region
results in unwanted non-linear behavior and polluted spectral content. Figure 37 and Figure 38 contrast the
performance of a traditional complementary rail-to-rail input stage amplifier with the performance of the zerocrossover OPA388. Significant harmonic content and distortion is generated during the differential pair transition
(such a transition does not exist in the OPA388). Crossover distortion is eliminated through the use of a single
differential pair coupled with an internal low-noise charge pump. The OPAx388 maintains noise, bandwidth, and
offset performance throughout the input common-mode range, thus reducing printed circuit board (PCB) and bill
of materials (BOM) complexity through the reduction of power-supply rails.
20
Complementary Input Stage
Input Offset Voltage ( V)
15
OPA388 Zero-Crossover Input Stage
10
5
0
±5
±10
VCM = ±2.85 V
VCM = 2.85 V
±15
±20
±3
±2
0
±1
1
2
3
Input Common-mode Voltage (V)
C003
Figure 37. Input Crossover Distortion Nonlinearity
FFT Spectral Content (dBV)
0
±20
±40
±60
Traditional Rail-to-Rail
Input Stage
±80
±100
±120
OPA388 Zero-Crossover Input Stage
±140
10
100
1k
10k
Frequency (Hz)
C004
Figure 38. Input Crossover Distortion Spectral Content
16
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Feature Description (continued)
Typically, input bias current is approximately ±30 pA. Input voltages exceeding the power supplies, however, can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in Figure 39.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3V.
+5V
IOVERLOAD
10 mA max
VOUT
VIN
5 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 39. Input Current Protection
7.3.3 Input Differential Voltage
The typical input bias current of the OPAx388 during normal operation is approximately 30 pA. In overdriven
conditions, the bias current can increase significantly. The most common cause of an overdriven condition
occurs when the operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied and
a differential input voltage develops across the input pins. This differential input voltage results in activation of
parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit shown in Figure 40. Notice that the input bias
current remains within specification in the linear region.
100 W
Clamp
+In
CORE
-In
100 W
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Equivalent Input Circuit
7.3.4 Internal Offset Correction
The OPA388 family of operational amplifiers uses an auto-calibration technique with a time-continuous, 200-kHz
operational amplifier in the signal path. This amplifier is zero-corrected every 5 µs using a proprietary technique.
At power-up, the amplifier requires approximately 1 ms to achieve the specified VOS accuracy. This design has
no aliasing or flicker noise.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal
rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The OPAx388 operational amplifier
family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both commonmode and differential-mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of
approximately 20 MHz (–3 dB), with a rolloff of 20 dB per decade.
7.4 Device Functional Modes
The OPA388 has a single functional mode and is operational when the power-supply voltage is greater than
2.5 V (±1.25 V). The maximum specified power-supply voltage for the OPAx388 is 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx388 is a unity-gain stable, precision operational amplifier family free from unexpected output and
phase reversal. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time
and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices work
well in applications that run directly from battery power without regulation. The OPAx388 family is optimized for
full rail-to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature, highprecision, low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond the
supplies without input crossover distortion and a rail-to-rail output that swings within 5 mV of the supplies under
normal test conditions. The OPAx388 series of precision amplifiers is suitable for upstream analog signal chain
applications in low or high gains, as well as downstream signal chain functions such as DAC buffering.
8.2 Typical Application
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to 1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx388 because of its low offset
voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and the other
amplifier provides the reference voltage.
Figure 41 shows the solution.
VCC
VCC
VREF
R5
+
U1B
R6
ILOAD
VBUS
+
±
R2
R1
+
VSHUNT
±
+
RSHUNT
VOUT
U1A
R3
RL
VCC
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Bidirectional Current-Sensing Schematic
18
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Typical Application (continued)
8.2.1 Design Requirements
This solution has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to 1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The shunt
voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
where
•
•
VSHUNT = ILOAD ´ RSHUNT
GainDiff_Amp =
R4
R3
VREF = VCC ´
•
R6
R5 + R6
(1)
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of the
difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set to
100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
V
RSHUNT(Max) = SHUNT(Max) = 100 mV = 100 mW
ILOAD(Max)
1A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is divided
down by R1 and R2 before reaching the operational amplifier, U1A. Take care to ensure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA388, that has a common-mode range that extends below the negative supply voltage.
Finally, to minimize offset error, note that the OPA388 has a typical offset voltage of merely ±0.25 µV (±5 µV
maximum).
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPA388 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA388 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
100 mV < VOUT < 3.2 V
(3)
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5.
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
=
GainDiff_Amp =
V
100 mW ´ [1 A - (- 1A)]
RSHUNT ´ (IMAX - IMIN)
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Typical Application (continued)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because this number is
the nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.3 Application Curve
Output Voltage (V)
3.30
1.65
0
-1.0
-0.5
0
Input Current (A)
0.5
1.0
Figure 42. Bidirectional Current-Sensing Circuit Performance:
Output Voltage vs Input Current
8.3 System Examples
8.3.1 Single Operational Amplifier Bridge Amplifier
Figure 43 shows the basic configuration for a bridge amplifier.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
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Figure 43. Single Operational Amplifier Bridge Amplifier Schematic
20
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System Examples (continued)
8.3.2 Precision, Low-Noise, DAC Buffer
The OPA388 can be used for a precision DAC buffer, as shown in Figure 44, in conjunction with the DAC8830.
The OPA388 provides an ultra-low drift, precision output buffer for the DAC. A wide range of DAC codes can be
used in the linear region because the OPA388 employs zero-crossover technology. A precise reference is
essential for maximum accuracy because the DAC8830 is a 16-bit converter.
VDD VREF
RFB
±
INV
Serial Interface
DAC8830
DGND
OPA388
+
VOUT
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Precision DAC Buffer
8.3.3 Load Cell Measurement
Figure 45 shows the OPA388 in a high-CMRR dual-op amp instrumentation amplifier with a trim resistor and 6wire load cell for precision measurement. Figure 46 illustrates the output voltage as a function of load cell
resistance change, along with the nonlinearity of the system.
RG
R3
25 k
R4
100 k
+5V
REF5025
R4
100 k
R2
25 k
+5V
+5V
+5V
+SENSE
±
±
VOUT
OPA388
OPA388
+
+
R2
10 k
GND
GND
-SENSE
Load Cell
GND
G=5+
GND
NŸ
RG
Figure 45. Load Cell Measurement Schematic
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2.53
3
2.52
2
2.51
1
2.5
0
2.49
-1
Non-Linearity (ppm)
Output Voltage (V)
System Examples (continued)
-2
2.48
RG = 1 kŸ
2.47
±100 ±80 ±60 ±40 ±20
-3
0
20
40
60
80
100
û5 5 SSP
C001
Figure 46. Load Cell Measurement Output
9 Power Supply Recommendations
The OPAx388 family of devices is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Parameters
that can exhibit significant variance with regard to operating voltage are presented in the Typical Characteristics
section.
22
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10 Layout
10.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use a
printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as
possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic interference
(EMI) susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring
they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 47. OPA388 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINATI™ is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels in addition
to a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and
frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI™
software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
11.1.1.2 TI Precision Designs
The OPAx388 family is featured on TI Precision Designs, available online at www.ti.com/ww/en/analog/precisiondesigns/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and
offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques (SLOA089)
• DAC883x 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters (SLAS449)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA388
Click here
Click here
Click here
Click here
Click here
OPA2388
Click here
Click here
Click here
Click here
Click here
OPA4388
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
24
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: OPA388 OPA2388 OPA4388
OPA388, OPA2388, OPA4388
www.ti.com
SBOS777 – DECEMBER 2016
Community Resources (continued)
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: OPA388 OPA2388 OPA4388
25
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA388ID
ACTIVE
SOIC
D
8
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
OPA388
OPA388IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA388
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA388IDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA388IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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