STMicroelectronics M24C64-DRDW8TG 64-kbit serial ic bus eeprom - 105c operation Datasheet

M24C64-DRE
64-Kbit serial I²C bus EEPROM - 105°C operation
Datasheet - production data
Features
• Compatible with all I2C bus modes
– 1 MHz
– 400 kHz
– 100 kHz
TSSOP8 (DW)
169 mil width
• Memory array
– 64 Kbits (8 Kbytes) of EEPROM
– Page size: 32 bytes
– Additional Write lockable page
(Identification page)
• Extended temperature and voltage ranges
– -40 °C to 105 °C; 1.8 V to 5.5 V
• Schmitt trigger inputs for noise filtering
SO8 (MN)
150 mil width
• Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 900 k Write cycles at 105 °C
WFDFPN8 (MF)
2 x 3 mm
• Data retention
– more than 50 years at 105 °C
– 200 years at 55 °C
• ESD Protection (Human Body Model)
– 4000 V
• Packages
– RoHS compliant and halogen-free
(ECOPACK2®)
January 2015
This is information on a product in full production.
DocID027358 Rev 1
1/41
www.st.com
1
Contents
M24C64-DRE
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6
Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
2/3
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.3
Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.4
Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.5
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.4
Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.5
Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.6
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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5
Contents
Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of tables
M24C64-DRE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
4/4
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 34
SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 35
WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID027358 Rev 1
M24C64-DRE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C
bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 34
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 35
WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead
2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Description
1
M24C64-DRE
Description
The M24C64-DRE is a 64-Kbit serial EEPROM device operating up to 105 °C. The
M24C64-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2.
The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.
The memory array is based on advanced true EEPROM technology (electrically erasable
programmable memory). The M24C64-DRE is a byte-alterable memory (8 K × 8 bits)
organized as 256 pages of 32 bytes in which the data integrity is significantly improved with
an embedded Error Correction Code logic.
The M24C64-DRE offers an additional Identification Page (32 bytes) in which the ST device
identification can be read. This page can also be used to store sensitive application
parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
7#
%
%
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)/ SHIFT REGISTER
$ATA
REGISTER
9 DECODER
!DDRESS REGISTER
AND COUNTER
PAGE
)DENTIFICATION PAGE
8 DECODER
-36
6/40
DocID027358 Rev 1
M24C64-DRE
Description
Table 1. Signal names
Signal name
Function
Direction
E2, E1, E0
Chip enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
-
VSS
Ground
-
Figure 2. 8-pin package connection
(
9&&
(
:&
(
6&/
966
6'$
$,I
1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
DocID027358 Rev 1
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Signal description
M24C64-DRE
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on this input is used to strobe the data available on SDA(in) and to output
the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected between SDA and VCC (Figure 10 and Figure 11
indicates how to calculate the value of the pull-up resistor).
2.3
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0).
Figure 3. Device select code
6##
6##
-XXX
-XXX
%I
%I
633
633
!I
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/40
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M24C64-DRE
2.5
Signal description
VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
VCC is the supply voltage pin.
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Device operation
3
M24C64-DRE
Device operation
The device supports the I2C protocol (see Figure 4).
The I2C bus is controlled by the bus master and the device is always a slave in all
communications.
The device (bus master or a slave) that sends data on to the bus is defined as a transmitter;
the device (bus master or a slave) is defined as a receiver when reading the data.
Figure 4. I2C bus protocol
3#,
3$!
3$!
)NPUT
34!24
#ONDITION
3#,
3$!
-3"
3$!
#HANGE
34/0
#ONDITION
!#+
34!24
#ONDITION
3#,
3$!
-3"
!#+
34/0
#ONDITION
!)"
10/40
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M24C64-DRE
3.1
Device operation
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
3.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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Device operation
3.5
M24C64-DRE
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2 .
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
address (E2, E1, E0). A device select code handling any value other than 1010b (to select
the memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1, E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
Table 2. Device select code
Device type identifier(1)
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
When accessing the
memory
1
0
1
0
E2
E1
E0
RW
When accessing the
Identification page
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Once the memory device has acknowledged the device select code (Table 2), the memory
device waits for the master to send two address bytes (most significant address byte sent
first, followed by the least significant address byte (Table 3). The memory device responds
to each address byte with an acknowledge bit.
12/40
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M24C64-DRE
Device operation
Address byte
Most
significant
address bits
Table 3. Significant bits within the two address bytes
Note:
Memory
Identification page
(Device type identifier = 1010b)
(Device type identifier = 1011b)
Read
Write
Lock
Identification Identification Identification
page
page
page
Random
Address Read
Write
Read lock
status
b15
X
X
X
X
X
X
b14
X
X
X
X
X
X
b13
X
X
X
X
X
X
b12
A12
A12
X
X
X
X
b11
A11
A11
X
X
X
X
b10
A10
A10
X
0
1
0
b9
A9
A9
X
X
X
X
b8
A8
A8
X
X
X
X
b7
A7
A7
X
X
X
X
b6
A6
A6
X
X
X
X
b5
A5
A5
X
X
X
X
b4
A4
A4
A4
A4
X
X
b3
A3
A3
A3
A3
X
X
b2
A2
A2
A2
A2
X
X
b1
A1
A1
A1
A1
X
X
b0
A0
A0
A0
A0
X
X
A: significant address bit.
X: bit is Don’t Care.
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Device operation
3.6
M24C64-DRE
Identification page
The M24C64-DRE offers an Identification Page (32 bytes) in addition to the 64-Kbit
memory.
The Identification page contains two fields:
Note:
•
Device identification code: the first three bytes are programmed by STMicroelectronics
with the Device identification code, as shown in Table 4.
•
Application parameters: the bytes after the Device identification code are available for
application specific data.
If the end application does not need to read the Device identification code, this field can be
overwritten and used to store application-specific data. Once the application-specific data
are written in the Identification page, the whole Identification page should be permanently
locked in Read-only mode.
The instructions Read, Write and Lock Identification Page are detailed in Section 4:
Instructions.
Table 4. Device identification code
Address in
Identification page
00h
14/40
Content
ST manufacturer code
2C
family code
01h
I
02h
Memory density code
DocID027358 Rev 1
Value
20h
E0h
0Dh (64-Kbit)
M24C64-DRE
4
Instructions
4.1
Write operations
Instructions
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send two address bytes (most significant address byte sent first,
followed by the least significant address byte (Table 3). The device responds to each
address byte with an acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 6.
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Instructions
4.1.1
M24C64-DRE
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the
addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 5.
Figure 5. Write mode sequences with WC = 0 (data write enabled)
7#
!#+
!#+
"YTE ADDR
"YTE ADDR
!#+
$ATA IN
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!#+
16/40
DocID027358 Rev 1
!)D
M24C64-DRE
4.1.2
Instructions
Page Write
The Page Write mode allows up to N(1) bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
Note:
The bus master sends from 1 to N(1) bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte received by the device is
not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte
address counter is incremented. The transfer is terminated by the bus master generating a
Stop condition.
Figure 6. Write mode sequences with WC = 1 (data write inhibited)
7#
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1. N is the number of bytes in a page.
DocID027358 Rev 1
17/41
Instructions
4.1.3
M24C64-DRE
Write Identification Page
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•
Device type identifier = 1011b
•
Most significant address bits A15/A5 are don't care, except for address bit A10 which
must be “0”. Least significant address bits /A0 define the byte location inside the
Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
4.1.4
Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
18/40
•
Device type identifier = 1011b
•
Address bit A10 must be ‘1’; all other address bits are don't care
•
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
DocID027358 Rev 1
M24C64-DRE
4.1.5
Instructions
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 7, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
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DocID027358 Rev 1
19/41
Instructions
4.2
M24C64-DRE
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
Figure 8. Read mode sequences
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4.2.1
!)E
Random Address Read
The Random Address Read is a sequence composed of a truncated Write sequence (to
define a new address pointer value, see Table 3) followed by a current Read.
The Random Address Read sequence is therefore the sum of [Start + Device Select code
with R/W=0 + two address bytes] (without Stop condition, as shown in Figure 8) and [Start
condition + Device Select code with R/W=1]. The memory device acknowledges the
sequence and then outputs the contents of the addressed byte. To terminate the data
transfer, the bus master does not acknowledge the last data byte and then issues a Stop
condition.
20/40
DocID027358 Rev 1
M24C64-DRE
4.2.2
Instructions
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte pointed by the internal address counter. The counter is then incremented.
The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without
acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the Identification page byte location, when accessing the memory, it is
safer to always use the Random Address Read instruction (this instruction loads the
address counter with the byte location to read in the memory) instead of the Current
Address Read instruction.
4.2.3
Sequential Read
A sequential Read can be used after a Current Address Read or a Random Address Read.
After a Read instruction, the device can continue to output the next byte(s) in sequence if
the bus master sends additional clock pulses and if the bus master does acknowledge each
transmitted data byte. To terminate the stream of bytes, the bus master must not
acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8.
The sequential read is controlled with the device internal address counter which is
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
4.2.4
Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The most significant address bits A15/A5
are don't care and the least significant address bits A4/A0 define the byte location inside the
Identification page. The number of bytes to read in the ID page must not exceed the page
boundary.
4.2.5
Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit after the data byte if the Identification page is
unlocked, otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
•
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
•
Stop: the device is then set back into Standby mode by the Stop condition.
DocID027358 Rev 1
21/41
Instructions
4.2.6
M24C64-DRE
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte sent out, for an acknowledgment
during the “9th bit” time. If the bus master does not send the Acknowledge (the master drives
SDA high during the 9th bit time), the device terminates the data transfer and enters its
Standby mode.
22/40
DocID027358 Rev 1
M24C64-DRE
Application design recommendations
5
Application design recommendations
5.1
Supply voltage
5.1.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 7).
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
5.1.2
Power-up conditions
When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to
the minimum VCC operating voltage defined in Table 7.
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC reaches the internal
threshold voltage (this threshold is defined in the DC characteristic Table 11 as VRES).
When VCC passes over the POR threshold, the device is reset and in the following state:
•
in the Standby power mode
•
deselected
As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)]
range (defined in Table 7), the device is ready for operation.
5.1.3
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 7), the device must be in Standby power mode (that
is after a STOP condition or after the completion of the Write cycle tW if an internal Write
cycle is in progress).
DocID027358 Rev 1
23/41
Application design recommendations
5.2
M24C64-DRE
Cycling with Error Correction Code (ECC)
The error correction code (ECC) is an internal logic function which is transparent for the I2C
communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (1). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(1). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 6.
Example 1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example 2: maximum cycling limit reached with unequal byte cycling
Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million
cycles.
1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer
24/40
DocID027358 Rev 1
M24C64-DRE
6
Delivery state
Delivery state
The device is delivered as follows:
•
The memory array is set to all 1s (each byte = FFh).
•
Identification page: the first three bytes define the Device identification code (value
defined in Table 4). The content of the following bytes is Don’t Care.
DocID027358 Rev 1
25/41
Maximum rating
7
M24C64-DRE
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
–0.50
6.5
V
-
5
mA
–0.50
6.5
V
-
4000
V
Lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
Electrostatic pulse (Human Body
model)(2)
see note
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012, C1=100 pF, R1=1500 Ω, R2=500 Ω).
26/40
DocID027358 Rev 1
M24C64-DRE
8
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Cycling performance by groups of four bytes
Symbol
Ncycle
Parameter
Test condition
Write cycle
endurance(1)
Min.
Max.
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V
-
4,000,000
TA = 85 °C, 1.8 V < VCC < 5.5 V
-
1,200,000
TA = 105 °C, 1.8 V < VCC < 5.5 V
-
900,000
Unit
Write
cycle(2)
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,
4*N+1, 4*N+2, 4*N+3] where N is an integer, or for the status register byte (refer also to
Section 5.2: Cycling with Error Correction Code (ECC)). The Write cycle endurance is defined
by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or
a Lock Identification Page instruction is decoded. When using those Write instructions, refer
also to Section 5.2: Cycling with Error Correction Code (ECC).
Table 7. Operating conditions (voltage range R)
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
105
°C
Max.
Unit
Table 8. AC measurement conditions
Symbol
Cbus
Parameter
Min.
Load capacitance
100
-
pF
-
SCL input rise/fall time, SDA input fall time
50
ns
-
Input levels
0.2 VCC to 0.8 VCC
V
-
Input and output timing reference levels
0.3 VCC to 0.7 VCC
V
Figure 9. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
6##
)NPUT AND OUTPUT
4IMING REFERENCE LEVELS
6##
6##
6##
-36
DocID027358 Rev 1
27/41
DC and AC parameters
M24C64-DRE
Table 9. Input parameters
Symbol
Parameter (1)
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
-
-
8
pF
CIN
Input capacitance (other pins)
-
-
6
pF
VIN < 0.3 VCC
30
-
kΩ
VIN > 0.7 VCC
500
-
kΩ
ZL
ZH
Input impedance (E2, E1, E0, WC)(2)
1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
28/40
DocID027358 Rev 1
M24C64-DRE
DC and AC parameters
Table 10. DC characteristics
Symbol
Test conditions (in addition to
those in Table 7 and Table 8)
Parameter
Min.
Max.
Unit
ILI
Input leakage current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC,
device in Standby mode
-
±2
µA
ILO
Output leakage current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
-
±2
µA
fC = 400 kHz, VCC = 5.5 V
-
2
mA
fC = 400 kHz, VCC = 2.5 V
-
2
mA
fC = 400 kHz, VCC = 1.8 V
-
1
mA
fC = 1 MHz, VCC = 5.5 V
-
2
mA
fC = 1 MHz, VCC = 2.5 V
-
2
mA
fC = 1 MHz, VCC = 1.8 V
-
2
mA
During tW
-
2
mA
Device not
t° = 85 °C,
VIN = VSS or VCC, VCC = 1.8 V
-
1
Device not selected(1)(2), t° = 85 °C,
VIN = VSS or VCC, VCC = 2.5 V
-
2
Device not selected(1)(2), t° = 85 °C,
VIN = VSS or VCC, VCC = 5.5 V
-
3
Device not selected(1), t° = 105 °C,
VIN = VSS or VCC, VCC = 1.8 V
-
5
Device not selected(1), t° = 105 °C
VIN = VSS or VCC, VCC = 2.5 V
-
5
Device not selected(1), t° = 105 °C,
VIN = VSS or VCC, VCC = 5.5 V
-
10
Supply current (Read)
ICC
ICC0
Supply current (Write)
selected(1)(2),
ICC1
VIL
VIH
(2)
µA
Input low voltage (SCL, SDA, WC)
-
–0.45
0.3 VCC
V
Input high voltage (SCL, SDA)
-
0.7 VCC
6.5
V
Input high voltage (WC, E2, E1, E0) -
VOL
VRES
Standby supply current
Output low voltage
Internal reset threshold voltage
0.7 VCC VCC +0.6
V
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
-
0.4
V
IOL = 1 mA, VCC = 1.8 V
-
0.3
V
0.5
1.5
V
-
1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
2. Characterized only, not 100% tested.
DocID027358 Rev 1
29/41
DC and AC parameters
M24C64-DRE
Table 11. 400 kHz AC characteristics
Parameter(1)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tQL1QL2 (2)
tXH1XH2
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
tLOW
Clock pulse width low
1300
-
ns
tF
SDA (out) fall time (3)
20
120
ns
Input signal rise time
(4)
(4)
ns
(4)
(4)
ns
100
-
ns
0
-
ns
100
-
ns
-
900
ns
tR
tXL1XL2
tF
Input signal fall time
tDXCH
tSU:DAT
Data in set up time
tCLDX
tHD:DAT
Data in hold time
tCLQX
(5)
tDH
Data out hold time
tCLQV
(6)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tWLDL(2)(7)
tSU:WC
WC set up time (before the Start condition)
0
-
µs
(2)(8)
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
Write time
-
4
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
80
ns
tDHWH
tW
tWR
tNS(2)
-
1. Test conditions (in addition to those in Table 7 and Table 8).
2. Characterized value, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however
recommended by the I²C specification that the input signal rise and fall times be more than 20
ns and less than 300 ns when fC < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in
Figure 10.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
30/40
DocID027358 Rev 1
M24C64-DRE
DC and AC parameters
Table 12. 1 MHz AC characteristics
Parameter(1)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tXH1XH2
Min.
Max.
Unit
0
1
MHz
Clock pulse width high
260
-
ns
tLOW
Clock pulse width low
400
-
ns
tR
Input signal rise time
(2)
(2)
ns
tF
Input signal fall time
(2)
(2)
ns
tF
SDA (out) fall time
-
120
ns
tDXCH
tSU:DAT
Data in setup time
50
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
100
-
ns
-
450
ns
250
-
ns
tXL1XL2
tQL1QL2
(3)
tCLQX
(4)
tDH
Data out hold time
tCLQV
(5)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
tDLCL
tHD:STA Start condition hold time
250
-
ns
tCHDH
tSU:STO Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
-
ns
tWLDL(6)(3)
tSU:WC
WC set up time (before the Start condition)
0
-
µs
(7)(3)
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
Write time
-
4
ms
Pulse width ignored (input filter on SCL and
SDA)
-
80
ns
tDHWH
tW
tWR
tNS (3)
-
1. Test conditions (in addition to those in Table 7 and Table 8).
2. There is no min. or max. values for the input signal rise and fall times. However, it is
recommended by the I²C specification that the input signal rise and fall times be more than
20 ns and less than 120 ns when fC < 1 MHz.
3. Characterized only, not tested in production.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified
in Figure 11.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
DocID027358 Rev 1
31/41
DC and AC parameters
M24C64-DRE
Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC = 400 kHz
"US LINE PULL UP RESISTOR
K
K½
4HE 2 BUS X #BUS TIME CONSTANT
MUST BE BELOW THE NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFT
2
BU
S §
#
BU
S (ERE 2BUS § #BUS NS
6##
2BUS
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S
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3#,
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Figure 11. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C
bus at maximum frequency fC = 1MHz
"US LINE PULL UP RESISTOR K
6##
4HE 2BUS § #BUS TIME CONSTANT
MUST BE BELOW THE NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFT
2
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3#,
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-36
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DocID027358 Rev 1
M24C64-DRE
DC and AC parameters
Figure 12. AC waveforms
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DocID027358 Rev 1
ƚY>ϭY>Ϯ
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Package mechanical data
9
M24C64-DRE
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline
ϴ
ϱ
Đ
ϭ
ϭ
ϰ
ɲ
>
ϭ
W
Ϯ
>ϭ
ď
Ğ
76623$0B9
1. Drawing is not to scale.
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
-
-
1.200
-
-
0.0472
A1
-
0.050
0.150
-
0.0020
0.0059
A2
1.000
0.800
1.050
0.0394
0.0315
0.0413
b
-
0.190
0.300
-
0.0075
0.0118
c
-
0.090
0.200
-
0.0035
0.0079
CP
-
0.100
-
-
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
-
-
0.0256
-
-
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
-
-
0.0394
-
-
α
-
0°
8°
-
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
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DocID027358 Rev 1
M24C64-DRE
Package mechanical data
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
K[Û
$
$
F
FFF
E
H
PP
*$8*(3/$1(
'
N
(
(
$
/
/
62$B9
1. Drawing is not to scale.
Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data
inches (1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
-
-
1.750
-
-
0.0689
A1
-
0.100
0.250
-
0.0039
0.0098
A2
-
1.250
-
-
0.0492
-
b
-
0.280
0.480
-
0.0110
0.0189
c
-
0.170
0.230
-
0.0067
0.0091
ccc
-
-
0.100
-
-
0.0039
D
4.900
4.800
5.000
0.1929
0.1890
0.1969
E
6.000
5.800
6.200
0.2362
0.2283
0.2441
E1
3.900
3.800
4.000
0.1535
0.1496
0.1575
e
1.270
-
-
0.0500
-
-
h
-
0.250
0.500
-
0.0098
0.0197
k
-
0°
8°
-
0°
8°
L
-
0.400
1.270
-
0.0157
0.0500
L1
1.040
-
-
0.0409
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID027358 Rev 1
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Package mechanical data
M24C64-DRE
Figure 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead
2 x 3 mm, package outline
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H
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3LQ
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DDD #
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1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating
(not connected) in the end application.
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DocID027358 Rev 1
M24C64-DRE
Package mechanical data
Table 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm,
mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.700
0.750
0.800
0.0276
0.0295
0.0315
A1
0.025
0.045
0.065
0.0010
0.0018
0.0026
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
D
1.900
2.000
2.100
0.0748
0.0787
0.0827
E
2.900
3.000
3.100
0.1142
0.1181
0.1220
e
-
0.500
-
-
0.0197
-
L1
-
-
0.150
-
-
0.0059
L3
0.300
-
-
0.0118
-
-
D2
1.050
-
1.650
0.0413
-
0.0650
E2
1.050
-
1.450
0.0413
-
0.0571
K
0.400
-
-
0.0157
-
-
L
0.300
-
0.500
0.0118
-
0.0197
(2)
NX
8
ND(3)
4
aaa
0.150
0.0059
bbb
0.100
0.0039
ccc
0.100
0.0039
ddd
0.050
0.0020
eee(4)
0.080
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. NX is the number of terminals.
3. ND is the number of terminals on “D” sides.
4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.
DocID027358 Rev 1
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Part numbering
10
M24C64-DRE
Part numbering
Table 16. Ordering information scheme
Example:
M24 C64-D
R MN 8
T
P /K
Device type
M24 = I2C serial access EEPROM
Device function
C64-D = 64 Kbit (8 K x 8 bits) plus identification page
Operating voltage
R = VCC = 1.8 V to 5.5 V
Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MF = WFDFPN8 (2 x 3 mm)
Device grade
8 = -40 to 105 °C.
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK2®
Process
/K = Manufacturing technology code
1. All package are ECOPACK2® (RoHS-compliant and free of brominated, chlorinated and
antimony-oxide flame retardants)
Note:
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For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
DocID027358 Rev 1
M24C64-DRE
Part numbering
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
DocID027358 Rev 1
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Revision history
11
M24C64-DRE
Revision history
Table 17. Document revision history
40/40
Date
Revision
15-Jan-2015
1
Changes
Initial release.
DocID027358 Rev 1
M24C64-DRE
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID027358 Rev 1
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