ON NJVMJD128T4G Complementary darlington power transistor Datasheet

MJD128T4G (PNP)
Complementary Darlington
Power Transistor
DPAK For Surface Mount Applications
Designed for general purpose amplifier and low speed switching
applications.
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Features
•
•
•
•
•
•
Monolithic Construction With Built−in Base−Emitter Shunt Resistors
High DC Current Gain: hFE = 2500 (Typ) @ IC = 4.0 Adc
Epoxy Meets UL 94 V−0 @ 0.125 in.
ESD Ratings:
♦ Human Body Model, 3B > 8000 V
♦ Machine Model, C > 400 V
NJV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These are Pb−Free Devices*
SILICON
POWER TRANSISTOR
8 AMPERES
120 VOLTS, 20 WATTS
DPAK
CASE 369C
STYLE 1
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MAXIMUM RATINGS
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Symbol
Value
Unit
VCEO
120
Vdc
VCB
120
Vdc
VEB
Collector Current
Continuous
Peak
IC
Base Current
IB
Total Power Dissipation
@ TC = 25°C
Derate above 25°C
PD
Total Power Dissipation*
@ TA = 25°C
Derate above 25°C
PD
5
Vdc
Adc
8
16
120
mAdc
W
W/°C
20
0.16
Operating and Storage Junction
Temperature Range
W
W/°C
1.75
0.014
TJ, Tstg
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
THERMAL CHARACTERISTICS
Thermal Resistance,
Junction−to−Case
Thermal Resistance,
Junction−to−Ambient (Note 1)
Symbol
Max
Unit
RqJC
6.25
°C/W
RqJA
Base
1
Collector
Emitter
A
Y
WW
J128
G
2
AYWW
J128G
4
3
= Assembly Location
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
MJD128T4G
DPAK
(Pb−Free)
2,500/Tape & Reel
NJVMJD128T4G
DPAK
(Pb−Free)
2,500/Tape & Reel
Device
°C
−65 to
+ 150
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Characteristic
MARKING DIAGRAM
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
°C/W
71.4
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 6
1
Publication Order Number:
MJD128/D
MJD128T4G (PNP)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Max
120
−
−
5
−
10
−
2
1000
100
12,000
−
−
−
2
4
−
4.5
−
2.8
4
−
−
300
300
−
Unit
OFF CHARACTERISTICS
VCEO(sus)
Collector−Emitter Sustaining Voltage
(IC = 30 mAdc, IB = 0)
Collector Cutoff Current
(VCE = 120 Vdc, IB = 0)
ICEO
Collector Cutoff Current
(VCB = 100 Vdc, IE = 0)
ICBO
Emitter Cutoff Current
(VBE = 5 Vdc, IC = 0)
IEBO
Vdc
mA
mAdc
mAdc
ON CHARACTERISTICS
hFE
DC Current Gain
(IC = 4 Adc, VCE = 4 Vdc)
(IC = 8 Adc, VCE = 4 Vdc)
Collector−Emitter Saturation Voltage
(IC = 4 Adc, IB = 16 mAdc)
(IC = 8 Adc, IB = 80 mAdc)
VCE(sat)
Base−Emitter Saturation Voltage (1)
(IC = 8 Adc, IB = 80 mAdc)
VBE(sat)
Base−Emitter On Voltage
(IC = 4 Adc, VCE = 4 Vdc)
VBE(on)
−
Vdc
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Current−Gain−Bandwidth Product
(IC = 3 Adc, VCE = 4 Vdc, f = 1 MHz)
|hfe|
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
Cob
Small−Signal Current Gain
(IC = 3 Adc, VCE = 4 Vdc, f = 1 kHz)
hfe
MHz
pF
−
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
PD, POWER DISSIPATION (WATTS)
TA TC
2.5 25
2 20
TC
1.5 15
TA
SURFACE
MOUNT
1 10
0.5
5
0
0
25
50
75
100
T, TEMPERATURE (°C)
Figure 1. Power Derating
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2
125
150
MJD128T4G (PNP)
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS
20,000
VCE = 4 V
h FE, DC CURRENT GAIN
10,000
7000
5000
TJ = 150°C
3000
2000
25°C
1000
700
500
300
200
0.1
-55°C
0.2
0.5 0.7
0.3
1
2
3
5
7
10
IC, COLLECTOR CURRENT (AMP)
3
TJ = 25°C
2.6
IC = 2 A
1.8
1.4
1
0.3
θ V, TEMPERATURE COEFFICIENTS (mV/°C)
V, VOLTAGE (VOLTS)
TJ = 25°C
2.5
2
VBE @ VCE = 4 V
VBE(sat) @ IC/IB = 250
VCE(sat) @ IC/IB = 250
0.5
0.1
0.5 0.7
0.2 0.3
1
2
3
0.5 0.7
5
7
10
7
10
20
30
*IC/IB ≤ hFE/3
+4
+3
+2
+1
0
25°C to 150°C
qVC for VCE(sat)
-1
-2
-3
qVB for VBE
-55°C to 25°C
25°C to 150°C
-55°C to 25°C
-4
-5
0.1
1
2 3
0.5
0.2 0.3
IC, COLLECTOR CURRENT (AMP)
5
7
10
Figure 5. Temperature Coefficients
REVERSE
FORWARD
VCE = 30 V
102
TJ = 150°C
100°C
25°C
10-1
+0.6 +0.4 +0.2
0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4
VBE, BASE−EMITTER VOLTAGE (VOLTS)
hfe , SMALL−SIGNAL CURRENT GAIN
IC, COLLECTOR CURRENT ( m A)
5
10,000
104
100
3
+5
Figure 4. “On” Voltages
105
101
2
IB, BASE CURRENT (mA)
IC, COLLECTOR CURRENT (AMP)
103
1
Figure 3. Collector Saturation Region
3
1
6A
2.2
Figure 2. DC Current Gain
1.5
4A
5000
3000
2000
1000
500
300
200
TC = 25°C
VCE = 4 Vdc
IC = 3 Adc
100
50
30
20
PNP
NPN
10
1
Figure 6. Collector Cut−Off Region
2
5
10
20
50 100
f, FREQUENCY (kHz)
200
Figure 7. Small−Signal Current Gain
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3
500 1000
MJD128T4G (PNP)
300
TJ = 25°C
C, CAPACITANCE (pF)
200
Cob
100
70
Cib
50
30
0.1
0.2
0.5
1
2
10
5
50
20
100
VR, REVERSE VOLTAGE (VOLTS)
Figure 8. Capacitance
5
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
D1, MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
VCC
-30 V
RC SCOPE
RB
51
D1
≈ 8 k ≈ 120
+4V
25 ms
tf
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.1
FOR td AND tr, D1 IS DISCONNECTED
AND V2 = 0
tr, tf ≤ 10 ns
DUTY CYCLE = 1%
ts
1
t, TIME (s)
μ
TUT
V2
APPROX
+8 V
0
V1
APPROX
-12 V
3
2
0.2
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES.
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
Figure 9. Switching Times Test Circuit
1
0.7
0.5
tr
VCC = 30 V
IC/IB = 250
IB1 = IB2
TJ = 25°C
td @ VBE(off) = 0 V
0.3
0.5 0.7 1
3
2
IC, COLLECTOR CURRENT (AMP)
5
7
10
Figure 10. Switching Times
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.05
0.03
SINGLE PULSE
P(pk)
RqJC(t) = r(t) RqJC
RqJC = 6.25°C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t1
READ TIME AT t1
t2
TJ(pk) − TC = P(pk) qJC(t)
DUTY CYCLE, D = t1/t2
0.01
0.02
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2
3
5
10
t, TIME OR PULSE WIDTH (ms)
Figure 11. Thermal Response
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4
20
30
50
100
200 300
500
1000
IC, COLLECTOR CURRENT (AMP)
MJD128T4G (PNP)
20
15
10
500ms
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 12 is based on TJ(pk) = 150°C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided TJ(pk)
< 150°C. TJ(pk) may be calculated from the data in
Figure 11. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
100ms
5
3
2
5ms
0.5
0.3
0.2
BONDING WIRE LIMIT
THERMAL LIMIT
TC = 25°C (SINGLE PULSE)
SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW RATED VCEO
0.1
0.05
0.03
0.02
1ms
TJ = 150°C
1
1
2
3
5
7
10
20
30
dc
50
100 120 200
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 12. Maximum Forward Bias
Safe Operating REA
COLLECTOR
BASE
≈8k
≈ 120
EMITTER
Figure 13. Darlington Schematic
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5
MJD128T4G (PNP)
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
A
E
C
A
b3
B
c2
4
L3
Z
D
1
2
H
DETAIL A
3
L4
NOTE 7
c
SIDE VIEW
b2
e
b
TOP VIEW
0.005 (0.13)
M
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
BOTTOM VIEW
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
SOLDERING FOOTPRINT*
2.58
0.102
5.80
0.228
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
ROTATED 905 CW
6.20
0.244
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
3.00
0.118
1.60
0.063
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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MJD128/D
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