ON NVMFS4C05NWFT3G Power mosfet Datasheet

NVMFS4C05N
Power MOSFET
30 V, 127 A, Single N−Channel, SO−8 FL
Features
•
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVMFS4C05NWF − Wettable Flanks Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
RDS(ON) MAX
2.8 mW @ 10 V
30 V
127 A
4.0 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
D (5−8)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
27.2
A
Continuous Drain
Current RqJA
(Notes 1, 2 and 4)
TA = 25°C
Power Dissipation
RqJA (Notes 1, 2
and 4)
TA = 25°C
Continuous Drain
Current RqJC
(Notes 1, 2, 3
and 4)
TC = 25°C
TA = 80°C
ID
S (1,2,3)
3.61
W
N−CHANNEL MOSFET
PD
MARKING
DIAGRAM
127
Steady
State
D
ID
A
TC = 80°C
Power Dissipation
RqJC (Notes 1, 2, 3
and 4)
TC = 25°C
PD
79
W
TA = 25°C, tp = 10 ms
IDM
174
A
TJ,
TSTG
−55 to
+175
°C
IS
72
A
EAS
42
mJ
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL = 29 Apk, L = 0.1 mH)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
101
© Semiconductor Components Industries, LLC, 2016
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
TL
°C
260
1
S
S
S
G
D
4C05xx
AYWZZ
D
D
4C05N = Specific Device Code for
NVMFS4C05N
4C05WF= Specific Device Code of
NVMFS4C05NWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceabililty
ORDERING INFORMATION
Package
Shipping†
NVMFS4C05NT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS4C05NT3G
SO−8 FL
(Pb−Free)
5000 /
Tape & Reel
NVMFS4C05NWFT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS4C05NWFT3G
SO−8 FL
(Pb−Free)
5000 /
Tape & Reel
Device
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using 650 mm2, 2 oz Cu pad.
3. Assumes heat−sink sufficiently large to maintain constant case temperature
independent of device power.
4. Continuous DC current rating. Maximum current for pulses as long as one
second is higher but dependent on pulse duration and duty cycle.
April, 2016 − Rev. 2
G (4)
21.6
Continuous Drain
Current RqJC
(Notes 1, 2, 3
and 4)
Pulsed Drain
Current
ID MAX
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NVMFS4C05N/D
NVMFS4C05N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
1.9
Junction−to−Ambient – Steady State (Note 5)
RqJA
41.6
Unit
°C/W
5. Surface−mounted on FR4 board using 650 mm2, 2 oz Cu pad.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
12
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 6)
Gate Threshold Voltage
Threshold Temperature Coefficient
Drain−to−Source On Resistance
1.3
VGS(TH)/TJ
RDS(on)
2.2
−5.1
VGS = 10 V
ID = 30 A
2.3
2.8
VGS = 4.5 V
ID = 30 A
3.3
4.0
Forward Transconductance
gFS
VDS = 1.5 V, ID = 15 A
Gate Resistance
RG
TA = 25°C
68
0.3
1.0
V
mV/°C
mW
S
2.0
W
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
1972
VGS = 0 V, f = 1 MHz, VDS = 15 V
1215
Capacitance Ratio
CRSS/CISS
Total Gate Charge
QG(TOT)
14
Threshold Gate Charge
QG(TH)
3.3
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Gate Plateau Voltage
VGP
Total Gate Charge
pF
59
VGS = 0 V, VDS = 15 V, f = 1 MHz
VGS = 4.5 V, VDS = 15 V; ID = 30 A
0.030
nC
6.0
5.0
3.1
V
VGS = 10 V, VDS = 15 V; ID = 30 A
30
nC
td(ON)
11
tr
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
32
QG(TOT)
SWITCHING CHARACTERISTICS (Note 7)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(OFF)
tf
7.0
td(ON)
8.0
tr
td(OFF)
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
ns
21
26
ns
26
5.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.77
TJ = 125°C
0.62
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 10 A
1.1
V
40.2
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
QRR
20.3
ns
19.9
30.2
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
7. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS4C05N
3.8 V
3.6 V
4.5 V
4.2 V
4V
3.4 V
3.2 V
3.0 V
2.8 V
2.6 V
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
TJ = 25°C
10 V
ID, DRAIN CURRENT (A)
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
1
2
3
5
4
ID = 30 A
TJ = 25°C
2.0
2.5
3.0
3.5
4.0
9
8
7
6
5
4
3
2
4.0
5.0
6.0
7.0
8.0
9.0
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.5
12
TJ = 25°C
11
10
9
8
7
6
5
4
VGS = 4.5 V
3
VGS = 10 V
2
1
0
20
40
60
80
100
120
140
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
10000
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 150°C
1.5
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
TJ = −55°C
1.5
Figure 2. Transfer Characteristics
10
1.6
TJ = 25°C
Figure 1. On−Region Characteristics
11
1.7
TJ = 125°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
12
1
3.0
140
130 VDS = 5 V
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5 1.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
TYPICAL CHARACTERISTICS
1.4
1.3
1.2
1.1
1.0
1000
TJ = 125°C
100
TJ = 85°C
0.9
0.8
10
0.7
−50
−25
0
25
50
75
100
125
150
175
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVMFS4C05N
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
2750
2500
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
3000
2250
Ciss
2000
1750
1500
1250
1000
Coss
750
500
250
0
Crss
0
5
10
15
20
25
30
QT
8
6
4
Qgd
Qgs
TJ = 25°C
VDD = 15 V
VGS = 10 V
ID = 30 A
2
0
0
4
8
12
16
20
24
28
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
32
20
1000
VDD = 15 V
ID = 15 A
VGS = 10 V
IS, SOURCE CURRENT (A)
18
td(off)
td(on)
100
tr
tf
10
VGS = 0 V
16
14
12
10
8
6
4
TJ = 125°C
TJ = 25°C
2
1
1
10
0
0.4
100
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
10 ms
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
10
10
100 ms
1
1 ms
0.1
0.01
0.001
0.0001
10 ms
0 V < VGS < 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
1.0
NVMFS4C05N
TYPICAL CHARACTERISTICS
100
R(t) (°C/W)
Duty Cycle = 50%
10 20%
10%
5%
2%
1
1%
0.1
0.01
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
1000
120
ID, DRAIN CURRENT (A)
100
GFS (S)
80
60
40
20
10
20
30
40
50
60
70
TA = 25°C
10
1
1.E−06
0
0
100
80
TA = 85°C
1.E−05
1.E−04
ID (A)
PULSE WIDTH (SECONDS)
Figure 13. GFS vs. ID
Figure 14. Avalanche Characteristics
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5
1.E−03
NVMFS4C05N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
2X
0.10
b
C A B
0.05
c
0.495
8X
4.560
MILLIMETERS
MIN
NOM
MAX
1.10
0.90
1.00
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.30
5.15
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
1.530
e/2
e
L
1
4
3.200
K
4.530
E2
PIN 5
(EXPOSED PAD)
L1
M
1.330
2X
0.905
1
G
0.965
D2
4X
1.000
4X 0.750
BOTTOM VIEW
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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NVMFS4C05N/D