TI1 OPA196 36-v, low-power, low offset voltage, rail-to-rail operational amplifier Datasheet

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OPA196, OPA2196, OPA4196
SBOS869 – JULY 2017
OPAx196 36-V, Low-Power, Low Offset Voltage, Rail-to-Rail Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The OPAx196 family (OPA196, OPA2196, and
OPA4196) is a new generation of 36-V, rail-to-rail etrim™ operational amplifiers (op amps).
1
•
•
•
•
Low Offset Voltage: ±100 µV (maximum)
Low Offset Voltage Drift: ±0.5 µV/°C (typical)
Low Bias Current: ±5 pA (typical)
High Common-Mode Rejection: 140 dB
Low Noise: 15 nV/√Hz at 1 kHz
Rail-to-Rail Input and Output
Differential Input Voltage Range to Supply Rail
Wide Bandwidth: 2.5-MHz GBW
Low Quiescent Current: 140 µA per Amplifier
(typical)
Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI Filtered Inputs
High Capacitive Load Drive Capability: 1 nF
Industry Standard Packages:
– Single in SOIC-8, SOT-5, and VSSOP-8
– Dual in SOIC-8 and VSSOP-8
– Quad in SOIC-14, TSSOP-14, and QFN-16
Unique features, such as differential input-voltage
range to the supply rail, high output current (±65 mA),
and high capacitive load drive of up to 1 nF make the
OPAx196 a robust, high-performance operational
amplifier for high-voltage industrial applications.
The OPAx196 family of op amps is available in
standard packages and is specified from –40°C to
+125°C.
Device Information(1)
PART NUMBER
OPA196
2 Applications
•
•
•
•
•
•
•
•
These devices offer very low offset voltage (±25 μV,
typical), drift (±0.5 μV/°C, typical), and low bias
current (±5 pA, typical) combined with very low
quiescent current (140 μA/channel, typical) across the
entire output range.
Multiplexed Data-Acquisition Systems
Test and Measurement Equipment
High-Resolution ADC Driver Amplifiers
SAR ADC Reference Buffers
Analog Input and Output Modules
High-Side and Low-Side Current Sensing
High-Precision Comparator
Medical Instrumentation
OPA2196
OPA4196
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SOT (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm x 3.90 mm
TSSOP (14)
5.00 mm x 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPA196 in a High-Voltage, Multiplexed, Data-Acquisition System
Analog
Inputs
REF3140
Bridge
Sensor
Thermocouple
4:2
HV
MUX
OPA196
+
+
OPA196
Optical Sensor
Gain
Gain
OPA196
+
OPA625
Antialiasing
Filter
High-Voltage Multiplexed
Input
High-Voltage Level
Translation
VCM
VINP
REF
ADS8864
VINM
Gain
Current Sensing
Gain
RC
Filter
RC
Filter
Reference
Driver
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA196, OPA2196, OPA4196
SBOS869 – JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 26
1
1
1
2
3
5
8
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
9 Power-Supply Recommendations...................... 31
10 Layout................................................................... 31
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: OPA196 .................................. 5
Thermal Information: OPA2196 ................................ 6
Thermal Information: OPA4196 ................................ 6
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V) ................................................................... 7
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS =
4.5 V to 8 V)............................................................... 9
6.9 Typical Characteristics ............................................ 11
7
Application and Implementation ........................ 27
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
July 2017
*
Initial release
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SBOS869 – JULY 2017
5 Pin Configuration and Functions
DBV Package: OPA196
5-Pin SOT
Top View
OUT
1
V±
2
5
V+
±
+
+IN
D and DGK Packages: OPA2196
8-Pin SOIC and VSSOP
Top View
3
4
±IN
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Not to scale
D and DGK Packages: OPA196
8-Pin SOIC and VSSOP
Top View
NC
1
±IN
2
+IN
3
V±
4
D and PW Packages: OPA4196
14-Pin SOIC and TSSOP
Top View
8
NC
OUT A
1
14
OUT D
±
7
V+
±IN A
2
13
±IN D
+
6
OUT
+IN A
3
12
+IN D
5
NC
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Not to scale
(1)
NC = No internal connection.
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OPA196, OPA2196, OPA4196
SBOS869 – JULY 2017
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Pin Functions: OPA196
PIN
OPA196
NAME
+IN
I/O
D (SOIC),
DGK (VSSOP)
DBV (SOT)
3
3
DESCRIPTION
I
Noninverting input
Inverting input
–IN
2
4
I
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V+
7
5
—
Positive (highest) power supply
V–
4
2
—
Negative (lowest) power supply
Pin Functions: OPA2196 and OPA4196
PIN
OPA2196
OPA4196
NAME
D (SOIC),
DGK (VSSOP)
D (SOIC),
PW (TSSOP)
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
—
10
I
Noninverting input, channel C
+IN D
—
12
I
Noninverting input, channel D
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
—
9
I
Inverting input,,channel C
–IN D
—
13
I
Inverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V+
8
4
—
Positive (highest) power supply
V–
4
11
—
Negative (lowest) power supply
4
I/O
DESCRIPTION
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SBOS869 – JULY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS = (V+) – (V–)
Signal input pins
Common-mode
Voltage
MAX
UNIT
±20
(+40, single supply)
V
(V–) – 0.5
(V+) + 0.5
Differential
Current
Output short circuit (2)
±10
mA
Continuous
Continuous
Continuous
–40
150
Operating
Temperature
Junction
150
Storage, Tstg
(1)
(2)
V
(V+) – (V–) + 0.2
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
V(ESD)
Electrostatic
discharge
V(ESD)
Electrostatic
discharge
OPAx196
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
OPA196
OPA2196
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
OPA4196
(1)
(2)
VALUE
UNIT
±3000
V
±1000
V
±500
V
±500
V
MAX
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
NOM
4.5 (±2.25)
36 (±18)
V
–40
125
°C
Specified temperature
6.4 Thermal Information: OPA196
OPA196
8 PINS
THERMAL METRIC (1)
5 PINS
UNIT
D (SOIC)
DGK
(VSSOP)
DBV (SOT)
180.4
158.8
°C/W
RθJA
Junction-to-ambient thermal resistance
115.8
RθJC(top)
Junction-to-case(top) thermal resistance
60.1
67.9
60.7
°C/W
RθJB
Junction-to-board thermal resistance
56.4
102.1
44.8
°C/W
ψJT
Junction-to-top characterization parameter
12.8
10.4
1.6
°C/W
ψJB
Junction-to-board characterization parameter
55.9
100.3
4.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Thermal Information: OPA2196
OPA2196
THERMAL METRIC (1)
8 PINS
UNIT
D (SOIC)
DGK (VSSOP)
RθJA
Junction-to-ambient thermal resistance
107.9
158
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
53.9
48.6
°C/W
RθJB
Junction-to-board thermal resistance
48.9
78.7
°C/W
ψJT
Junction-to-top characterization parameter
6.6
3.9
°C/W
ψJB
Junction-to-board characterization parameter
48.3
77.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4196
OPA4196
THERMAL METRIC
(1)
14 PINS
UNIT
D (SOIC)
PW (TSSOP)
RθJA
Junction-to-ambient thermal resistance
86.4
92.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
46.3
27.5
°C/W
RθJB
Junction-to-board thermal resistance
41.0
33.6
°C/W
ψJT
Junction-to-top characterization parameter
11.3
1.9
°C/W
ψJB
Junction-to-board characterization parameter
40.7
33.1
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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OPA196, OPA2196, OPA4196
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SBOS869 – JULY 2017
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±25
±100
µV
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±18 V
(V+) – 3.0 V < VCM < (V+) – 1.5 V
See Common-Mode Voltage Range
VS = ±18 V,
VCM = (V+) – 1.5 V
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
VS = ±18 V, VCM = (V+) – 3 V
VS = ±18 V, VCM = (V+) – 1.5 V
±25
±100
±0.5
TA = –40°C to +125°C
µV/°C
±0.8
TA = –40°C to +125°C
±0.3
±1
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±5
±20
pA
IOS
Input offset current
±2
±20
pA
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.4
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
7
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise
density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise
density
f = 100 Hz
18
f = 1 kHz
15
f = 100 Hz
53
f = 1 kHz
24
f = 1 kHz
µVPP
nV/√Hz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = ±18 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode
rejection ratio
VS = ±18 V,
(V–) < VCM < (V+) – 3 V
VS = ±18 V,
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
(V+) + 0.1
120
140
114
126
96
120
86
100
V
dB
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
124
134
114
126
126
140
120
134
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Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
2.5
VS = ±18 V, G = 1, 10-V step
To 0.01%, CL = 20 pF
ts
Settling time
To 0.001%, CL = 20 pF
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic
distortion + noise
G = 1, f = 1 kHz, VO = 3.5 VRMS
Crosstalk
Rising
7.5
Falling
5.5
VS = ±18 V, G = 1, 2-V step
0.7
VS = ±18 V, G = 1, 5-V step
1
VS = ±18 V, G = 1, 2-V step
1.8
VS = ±18 V, G = 1, 5-V step
3.7
From overload to negative rail
0.4
From overload to positive rail
MHz
V/µs
µs
µs
1
0.0012%
OPA2196 and OPA4196, at dc
150
dB
OPA2196 and OPA4196, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
VO
Voltage output swing
from rail
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output
impedance
15
50
110
RL = 2 kΩ
200
500
5
15
RL = 10 kΩ
50
110
RL = 2 kΩ
200
500
No load
Negative rail
ISC
5
RL = 10 kΩ
VS = ±18 V
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, See Figure 19
700
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
140
TA = –40°C to +125°C
200
250
µA
TEMPERATURE
8
Thermal protection
180
°C
Thermal hysteresis
30
°C
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6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±25
±100
µV
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±2.25V,
VCM = (V+) – 3 V
(V+) – 3.0 V < VCM < (V+) – 1.5 V
See Common-Mode Voltage Range
VS = ±3V,
VCM = (V+) – 1.5 V
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
VS = ±2.25V, VCM = (V+) – 3 V
VS = ±2.25V, VCM = (V+) – 1.5 V
±25
±100
±0.5
TA = –40°C to +125°C
µV/°C
±0.5
TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V
±1
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±5
±20
pA
IOS
Input offset current
±2
±20
pA
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.4
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
7
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise density
f = 100 Hz
18
f = 1 kHz
15
f = 100 Hz
53
f = 1 kHz
24
f = 1 kHz
1.5
µVPP
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = ±2.25 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode rejection
ratio
VS = ±2.25 V,
(V–) < VCM < (V+) – 3 V
VS = ±2.25 V,
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
(V+) + 0.1
96
110
90
104
96
120
84
100
V
dB
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±2.25V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
VS = ±2.25V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
110
120
100
114
110
126
106
120
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Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
2.2
SR
Slew rate
VS = ±2.25V, G = 1, 1-V step
tOR
Overload recovery time
VIN × G = VS
Crosstalk
Rising
6.5
Falling
5.5
From overload to negative rail
0.4
From overload to positive rail
MHz
V/µs
µs
1
OPA2196 and OPA4196, at dc
150
dB
OPA2196 and OPA4196, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
VO
Voltage output swing from
rail
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output
impedance
15
15
110
RL = 2 kΩ
60
500
5
15
RL = 10 kΩ
15
110
RL = 2 kΩ
60
500
No load
Negative rail
ISC
5
RL = 10 kΩ
VS = ±2.25V
±30
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, see Figure 19
700
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
140
TA = –40°C to +125°C
200
250
µA
TEMPERATURE
10
Thermal protection
180
°C
Thermal hysteresis
30
°C
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6.9 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage vs Common-Mode Voltage
Figure 1
Open-Loop Gain and Phase vs Frequency
Figure 2
Closed-Loop Gain and Phase vs Frequency
Figure 3
Input Bias Current vs Common-Mode Voltage
Figure 4
Input Bias Current vs Temperature
Figure 5
Output Voltage Swing vs Output Current (maximum supply)
Figure 6, Figure 7
CMRR and PSRR vs Frequency
Figure 8
CMRR vs Temperature
Figure 9
PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Noise
Figure 11
Input Voltage Noise Spectral Density vs Frequency
Figure 12
THD+N Ratio vs Frequency
Figure 13
THD+N vs Output Amplitude
Figure 14
Quiescent Current vs Supply Voltage
Figure 15
Quiescent Current vs Temperature
Figure 16
Open Loop Gain vs Temperature
Figure 17, Figure 18
Open Loop Output Impedance vs Frequency
Figure 19
Small Signal Overshoot vs Capacitive Load (100-mV output step)
Figure 20, Figure 21
No Phase Reversal
Figure 22
Overload Recovery
Figure 23
Small-Signal Step Response (100 mV)
Figure 24, Figure 25
Large-Signal Step Response
Figure 26, Figure 27
Settling Time
Figure 28, Figure 29, Figure 30, Figure 31
Short-Circuit Current vs Temperature
Figure 32
Maximum Output Voltage vs Frequency
Figure 33
Propagation Delay Rising Edge
Figure 34
Propagation Delay Falling Edge
Figure 35
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
160
180
15
Open-loop Gain
120
VCM = ±18.1 V
135
Phase
90
100
Gain (dB)
5
±5
80
45
60
0
40
20
±15
Phase (ƒ)
Input Offset Voltage ( V)
140
-45
0
-90
±20
±40
±25
±20
±15
±10
±5
0
5
Common Mode Voltage (V)
10
15
0.1
1.0
10.0 100.0
10k
100k
1M
-135
10M 100M
Frequency (Hz)
C001
Figure 1. Offset Voltage vs Common-Mode Voltage
1k
C001
Figure 2. Open-Loop Gain and Phase vs Frequency
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1000
60
800
G = +1
600
Input Bias Current (pA)
Gain (dB)
40
G = -1
G= -10
G= -100
20
0
400
200
0
±200
±400
±600
±800
-20
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
±1000
±20
±10
±5
0
5
10
15
Common Mode Voltage (V)
Figure 3. Closed-Loop Gain vs Frequency
20
C001
Figure 4. Input Bias Current vs Common-Mode Voltage
20
10
IB IB+
9
18
8
16
7
14
Output Voltage (V)
Input Bias Current (nA)
±15
C004
6
5
4
3
12
10
8
6
2
4
1
2
0
±75
±50
±25
0
25
50
75
100
125
0
150
Temperature (ƒC)
40qC
25qC
85qC
125qC
0
20
40
60
Output Current (mA)
C001
80
100
Sourcing
Figure 6. Output Voltage Swing vs Output Current
Figure 5. Input Bias Current vs Temperature
0
Common-Mode Rejection Ratio (dB)
-4
Output Voltage (V)
140
40qC
25qC
85qC
125qC
-2
-6
-8
-10
-12
-14
-16
-18
120
100
80
60
40
CMRR
+PSRR
20
±PSRR
0
-20
0
20
40
60
Output Current (mA)
80
100
0.1
1.0
10.0
100.0
1k
10k
100k
1M
Frequency (Hz)
10M
C004
Sinking
Figure 7. Output Voltage Swing vs Output Current
12
Figure 8. CMRR and PSRR vs Frequency
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10
5
VS = ±2.25 V, (V±) ” 9CM ” 9
8
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
±3V
6
4
2
0
-2
VS = ±18 V, (V±) ” 9CM ” 9
±3V
-4
-6
-8
4
3
2
1
0
-1
-2
-3
-4
-10
-5
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±75
±50
±25
125
C001
10
100
1k
10k
100k
1M
10M
400 nV/div
0.01
-80
0.001
-100
0.0001
-120
0.00001
-140
20k
Frequency (Hz)
Figure 13. THD+N vs Frequency
Total Harmonic Distortion + Noise (%)
-60
2k
C002
0.5
-40
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 2k- Load
G = +1, 10k- Load
150
Figure 12. Input Voltage Noise Spectral Density
vs Frequency
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
100
Frequency (Hz)
Figure 11. 0.1-Hz to 10-Hz Noise
200
75
10
1
20
50
100
Time (1 s/div)
0.1
25
Figure 10. PSRR vs Temperature
Voltage Noise Spectral Density (nv/¥Hz)
Figure 9. CMRR vs Temperature
1
0
Temperature (ƒC)
C001
G = 1 V/V, RL = 2 k:
G = 1 V/V, RL = 10 k:
G = 1 V/V, RL = 2 k:
G = 1 V/V, RL = 10 k:
0.1
0.01
0.001
0.0005
0.01
0.1
1
Output Amplitude (VRMS)
C004
10
20
Figure 14. THD+N vs Output Amplitude
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
200
200
180
VS = r2.25 V
180
VS = r18 V
Quiescent Current (µA)
Quiescent Current (PA)
160
140
120
100
80
60
VS = ±18 V
160
140
VS = ±2.25 V
120
100
80
60
40
40
20
20
0
0
0
2
4
6
8
10
12
14
Supply Voltage (V)
16
18
±75
20
5.0
4.0
4.0
3.0
3.0
AOL (µV/V)
AOL (µV/V)
25
50
75
100
125
150
C001
VS = ±2.25 V
2.0
VS = ±2.25 V
0.0
±1.0
0
Figure 16. Quiescent Current vs Temperature
5.0
1.0
±25
Temperature (ƒC)
Figure 15. Quiescent Current vs Supply Voltage
2.0
±50
VS = ±18 V
1.0
0.0
±1.0
±2.0
±2.0
±3.0
±3.0
±4.0
±4.0
±5.0
VS = ±18 V
±5.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
RL = 10 kΩ
150
C001
RL = 2 kΩ
Figure 17. Open-Loop Gain vs Temperature
Figure 18. Open-Loop Gain vs Temperature
100k
60
RISO = 0
RISO = 25
50
RISO = 50
ZO (:)
Overshoot (%)
10k
1k
40
30
20
10
0
100
100m
10
1
10
100
1k
10k
Frequency (Hz)
100k
1M
100
10M
Capacitive Load (pF)
1000
C004
G = –1, 100-mV output step
Figure 19. Open-Loop Output Impedance vs Frequency
14
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
20
Output
Input
RISO = 0
RISO = 25
Voltage (5 V/div)
Overshoot (%)
RISO = 50
10
0
10
100
1000
Capacitive Load (pF)
Time (50 Ps/div)
C004
G = 1, 100-mV output step
Figure 22. No Phase Reversal
20 mV/div
Negative overload
Positive overload
t=0
Output (V)
Figure 21. Small-Signal Overshoot vs Capacitive Load
Time (2.5 µs/div)
Time (Ps)
C017
G = 1, CL = 10 pF
VS = ±18 V, G = –10 V/V
Figure 24. Small-Signal Step Response
2 V/div
20 mV/div
Figure 23. Overload Recovery
Time (2.5 µs/div)
Time (2.5 µs/div)
C017
C017
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 25. Small-Signal Step Response
G = 1, CL = 10 pF
Figure 26. Large-Signal Step Response
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
2 V/div
Output Voltage (200 PV/div)
0.01% settling = r200 PV
Time (2.5 µs/div)
Time (500 ns/div)
C017
G = –1, RL = 1 kΩ, CL = 10 pF
Gain = 1, 2-V step, rising, step applied at t = 0 µs on all four plots
Figure 28. 0.01% Settling Time
Figure 27. Large-Signal Step Response
0.01% settling = r500 PV
Output Voltage (200 PV/div)
Output Voltage (200 PV/div)
0.01% settling = r200 PV
Time (500 ns/div)
Time (500 ns/div)
Gain = 1, 5-V step, rising, step applied at t = 0 µs
Gain = 1, 2-V step, falling, step applied at t = 0 µs
Figure 30. 0.01% Settling Time
Figure 29. 0.01% Settling Time
100
Output Voltage (200 PV/div)
Short Circuit Current (mA)
0.01% settling = r500 PV
ISC, Source
80
60
ISC, Sink
40
20
0
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
Time (500 ns/div)
C001
Gain = 1, 5-V step, falling, step applied at t = 0 µs
Figure 31. 0.01% Settling Time
16
Figure 32. Short-Circuit Current vs Temperature
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At TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
35
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
25
20
15
10
Overdrive = 100 mV
Output Voltage (10 V/div)
Output Voltage (VPP)
30
VS = ±4 V
tpLH = 26 µs
VOUT Voltage
5
VS = ±2.25 V
0
100
1k
10k
100k
1M
Frequency (Hz)
Time (10 µs/div)
10M
C001
C017
Output Voltage (10 V/div)
Figure 33. Maximum Output Voltage vs Frequency
Figure 34. Propagation Delay Rising Edge
tpHL = 26 µs
VOUT Voltage
Overdrive = 100 mV
Time (10 µs/div)
C017
Figure 35. Propagation Delay Falling Edge
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7 Detailed Description
7.1 Overview
The OPAx196 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are
set, further communication to the trim structure is permanently disabled. The Functional Block Diagram shows
the simplified diagram of the OPA196 with e-trim.
Unlike previous e-trim op amps, the OPAx196 uses a patented two-temperature trim architecture to achieve a
very low offset voltage and low voltage offset drift over the full specified temperature range. This level of
precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial
sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
OPAx196
NCH Input
Stage
IN+
36-V
Differential
Front End
Slew
Boost
High
Capacitive Load
Compensation
Output
Stage
VOUT
IN-
PCH Input
Stage
e-trim
Package Level Trim
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx196 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 36 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 37. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
VOUT
OPAx196
36 V
~0.7 V
VIN
VIN
V
OPAx196 Provides Full 36V Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 36. OPA196 Input Protection Does Not Limit Differential Input Capability
Vn = +10 V
RFILT
+10 V
1
Ron_mux
Sn
1
D
+10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
Vin±
2
~0.7 V
CFILT
CS
Vout
Idiode_transient
±10 V
Input Low Pass Filter
Vin+
Buffer Amplifier
Simplified Mux Model
Figure 37. Back-to-Back Diodes Create Settling Issues
The OPAx196 family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications. This patented input protection architecture does not introduce additional signal distortion or
delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.
The OPA196 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the
op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping
input signals such as multiplexed data-acquisition systems (see Figure 49).
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Feature Description (continued)
7.3.2 EMI Rejection
The OPAx196 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx196 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 38 shows the results of this testing on the OPAx196. Table 2 shows the EMIRR IN+ values for the
OPAx196 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in the application report EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1k
Frequency (MHz)
10k
PRF = –10 dBm, VS = ±15 V, VCM = 0 V
Figure 38. EMIRR Testing
Table 2. OPA196 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
36 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
45 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
57 dB
®
20
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
62 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
76 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
86 dB
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7.3.3 Phase Reversal Protection
The OPAx196 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx196 is a rail-to-rail input op amp, and therefore the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. This performance is shown in Figure 39.
5 V/div
VIN
VOUT
Time (35 ms/div)
C017
Figure 39. No Phase Reversal
7.3.4 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The OPAx196 has a thermal protection feature that prevents damage from
self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp
output drive for temperatures above approximately 180°C. Thermal protection forces the output to a highimpedance state. The OPAx196 is also designed with approximately 30°C of thermal hysteresis. Thermal
hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPAx196 returns
to normal operation when the output stage temperature falls below approximately 150°C.
The absolute maximum junction temperature of the OPAx196 is 150°C. Exceeding the limits shown in the
Absolute Maximum Ratings table may cause damage to the device. Thermal protection triggers at 180°C
because of unit-to-unit variance, but does not interfere with device operation up to the absolute maximum ratings.
This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but
rather from excessive thermal overload.
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7.3.5 Capacitive Load and Stability
The OPAx196 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 40. The particular op amp circuit configuration, layout, gain,
and output loading are some of the factors to consider when establishing whether an amplifier will be stable in
operation.
Output (50 mV/Div)
G = +1 V/V
Time (2 Ps/Div)
Figure 40. Transient Response with a Purely Capacitive Load of 1 nF
Like many low-power amplifiers, some ringing can occur even with capacitive loads less than 100 pF. In unitygain configurations with no or very light dc loads, place an RC snubber circuit at the OPAx196 output to reduce
any possibility of ringing in lightly-loaded applications. Figure 41 illustrates the recommended RC snubber circuit.
±
Output
Input
+
R 619
C 320 pF
Figure 41. RC Snubber Circuit for Lightly-Loaded Applications in Unity Gain
22
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,
10-Ω to 20-Ω resistor (RISO) in series with the output, as shown in Figure 42. This resistor significantly reduces
ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL and is generally negligible at
low output levels. A high capacitive load drive makes the OPA196 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 42 uses RISO to stabilize the
output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin. Results using
the OPA196 are summarized in Table 3. For additional information on techniques to optimize and design using
this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
±
Vin
-Vs
Figure 42. Extending Capacitive Load Drive With the OPA196
Table 3. OPA196 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
VALUE
Capacitive Load
100 pF
Phase Margin
45°
45°
1000 pF
60°
45°
0.01 µF
60°
45°
0.1 µF
60°
45°
1 µF
60°
RISO (Ω)
280
113
432
68
210
17.8
53.6
3.6
10
Measured
Overshoot (%)
23
23
8
23
8
23
8
23
8
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
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7.3.6 Common-Mode Voltage Range
The OPAx196 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 43. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are active. This transition region varies
modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD
performance are degraded compared to operation outside this region.
+Vsupply
IS1
VINPCH1
NCH4
NCH3
PCH2
VIN+
e-TrimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
-Vsupply
Figure 43. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx196 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in
Figure 44.
Transition
Region
N-Channel
Region
P-Channel
Region
200
200
100
100
Input Offset Voltage ( V)
Input Offset Voltage ( V)
P-Channel
Region
0
±100
OPAx196 e-Trim
Input Offset Voltage vs Vcm
±200
Transition
Region
N-Channel
Region
0
±100
±200
Input Offset Voltage vs Vcm
without e-Trim Input
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
Figure 44. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
24
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 45 for an illustration of the ESD circuits contained in the OPAx196 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
±
+
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
OPAx196
±
+
Power-Supply
ESD Cell
ID
RL
+
VIN
±
VSS
+
±
±VS
TVS
Figure 45. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very high voltage for a very short duration (for example, 1 kV for 100 ns); whereas, an EOS
event is lower voltage for a longer duration (for example, 50 V for 100 ms). The ESD diodes are designed for
out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to
the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption
circuit labeled ESD power-supply circuit. The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
7.4 Device Functional Modes
The OPAx196 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx196 is 36 V (±18 V).
26
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx196 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
2-MHz bandwidth and high capacitive load drive. These features make the OPAx196 a robust, high-performance
operational amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-side Current Measurement
Figure 46 shows the OPA196 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 46 including theory, calculations, simulations, and measured data see the 0-1A, singlesupply, low-side, current sensing solution, see TIPD129.
VCC
5V
LOAD
+
OPA196
VOUT
±
ILOAD
RSHUNT
100m
LM7705
RF
360k
RG
7.5k
Figure 46. OPA196 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 46 is given in Equation 1:
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA196 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA196 to
produce the necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the OPA196 to 49 V/V.
RF
Gain 1
RG
(4)
Choosing RF as 360 kΩ, RG is calculated to be 7.5 kΩ. RF and RG were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 2 shows the measured transfer function of the circuit shown in Figure 46.
5
0.1
4
0.08
Error (%FSR)
Output (V)
8.2.1.3 Application Curves
3
2
1
0.04
0.02
0
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 47. Low-Side, Current-Sense, Transfer Function
28
0.06
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 48. Low-Side, Current-Sense, Full-Scale Error
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Typical Applications (continued)
8.2.2 16-Bit Precision Multiplexed Data-Acquisition System
Figure 49 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR), analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front-end, and a 4-channel differential multiplexer (mux). This
application example shows the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA196 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. The full TI
Precision Design can be found in TIDU181.
1
2
Very Low Output
Impedance
Input-Filter Bandwidth
±20-V,
10-kHz
Sine
Wave
3
High-Impedance Inputs
No Differential Input
Clamps
Fast Settling-Time
Requirements
Attenuate High-Voltage Input
Signal
Fast-Settling Time
Requirements
Stability of the Input Driver
CH0-
Attenuate ADC Kickback
Noise
VREF Output: Value and
Accuracy
Low Temp and Long-Term
Drift
RC
Filter
Voltage
Reference
CH0+
+
OPA196
+
4
Gain
Network
OPA196
RC
Filter
Buffer
Reference
Driver
Gain
Network
+
OPA196
4:2
Mux
REFP
+
CH3+
+
OPA196
+
OPA140
+
Gain
Network
OPA196
VINP
Antialiasing
Filter
SAR
ADC
VINM
CH3-
Gain
Network
±20-V,
10-kHz
Sine
Wave
n
OPA196
High-Voltage Multiplexed Input
CONV
16 Bits
400 kSPS
High-Voltage Level
Translation
VCM
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
n
5
Counter
Fast logic transition
Shmidtt
Trigger
Delay
Digital Counter For
Multiplexer
Figure 49. OPA196 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
8.2.2.1 Design Requirements
The primary objective is to design a ±20-V, differential, 4-channel, multiplexed, data acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
8.2.2.2 Detailed Design Procedure
The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition
system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 49.
The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer
(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The
architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two
primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system
are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,
carefully design each analog circuit block based on the ADC performance specifications in order to achieve the
fastest settling at 16-bit resolution and lowest distortion system. Figure 49 includes the most important
specifications for each individual analog block.
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Typical Applications (continued)
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This
understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system
settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to
level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.
Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final
design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference
voltage with low offset, drift, and noise contributions.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
8.2.3 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx196 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 50 shows the OPA196 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
VCC
VCC
+
VIN
R2
OPA196
+
OPA196
+
VOUT
VEE
RL
VEE
Figure 50. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
30
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9 Power-Supply Recommendations
The OPAx196 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
– Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
• Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
• In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 52, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 51. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RF
VS+
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Operational Amplifier Board Layout for Non-inverting Configuration
32
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder at
http://www.ti.com/tool/tina-ti.
11.1.1.2 TI Precision Designs
TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions
created by TI’s precision analog applications experts and offer the theory of operation, component selection,
simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful
circuits.
11.2 Documentation Support
11.2.1 Related Documentation
• EMI Rejection Ratio of Operational Amplifiers
• 0-1A, Single-Supply, Low-Side, Current Sensing Solution
• Op Amps for Everyone
11.3 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA196
Click here
Click here
Click here
Click here
Click here
OPA2196
Click here
Click here
Click here
Click here
Click here
OPA4196
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA196ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA196
OPA196IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O196
OPA196IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O196
OPA196IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O196
OPA196IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O196
OPA196IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA196
OPA2196ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2196
OPA2196IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 125
2196
OPA2196IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 125
2196
OPA2196IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2196
OPA4196ID
PREVIEW
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4196
OPA4196IDR
PREVIEW
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4196
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2017
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA196IDR
SOIC
D
OPA2196IDR
SOIC
OPA4196IDR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA196IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2196IDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA4196IDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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