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name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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For More Information
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9A110A/MB9A110 Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A110A/MB9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive
embedded control applications.
The MB9A110A Series are based on the ARM® Cortex®-M3 Processor and on-chip Flash memory and SRAM, and peripheral
functions, including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this datasheet are placed into TYPE1 product categories in “FM3 Family Peripheral Manual”.
Features
32-bit ARM® Cortex®-M3 Core
[UART]
Processor version: r2p1
Full duplex double buffer
Up to 40 MHz Frequency Operation
Selection with or without parity supported
Integrated Nested Vectored Interrupt Controller (NVIC): 1
Built-in dedicated baud rate generator
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)*
Various error detection functions available (parity errors,
On-chip Memories
framing errors, and overrun errors)
*: MB9AF111LA, F112LA, F114LA, F112L and F114L do not
support Hardware Flow control
[Flash memory]
Up to 512 Kbyte
[CSIO]
Read cycle: 0 wait-cycle
Full duplex double buffer
Security function for code protection
Built-in dedicated baud rate generator
[SRAM]
Overrun error detection function available
This Series contain a total of up to 32 Kbyte on-chip SRAM.
On-chip SRAM is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M3 core. SRAM1 is connected to System
bus.
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
SRAM0: Up to 16 Kbytes
Master/Slave mode supported
SRAM1: Up to 16 Kbytes
LIN break field generation (can be changed 13- 16bit length)
Multi-function Serial Interface (Max 8 channels)
4 channels with 16 steps×9bit FIFO (ch.4-ch.7), 4 channels
without FIFO (ch.0-ch3)
Cypress Semiconductor Corporation
Document Number: 002-04672 Rev. *D
length)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2 C
LIN break delimiter generation (can be changed 1 - 4bit
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2017
MB9A110A/MB9A110 Series
External Bus Interface*
Multi-function Timer (Max 2 units)
Supports SRAM, NOR Flash device
The Multi-function timer is composed of the following blocks.
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
*: MB9AF111LA, F112LA and F114LA do not support
External Bus Interface
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Output compare × 6 ch/unit
A/D activation compare × 3 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
The following function can be used to achieve the motor
control.
DMA Controller (8 channels)
PWM signal output function
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
DC chopper waveform output function
8 independently configured and operated channels
Dead timer function
Transfer can be started by software or request from the
Input capture function
built-in peripherals
Transfer address area: 32bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D converter activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max 2 units)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
A/D Converter (Max 16 channels)
BIN and ZIN is configurable.
[12-bit A/D Converter]
16-bit position counter
Successive Approximation type
16-bit revolution counter
Built-in 3units*
Two 16-bit compare registers
Conversion time: 1.0 μs@5 V
Dual Timer (32-/16-bit Down Counter)
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4steps)
*: MB9AF111LA, F112LA, F114LA built-in 2units
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each timer
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from Low-Power
Consumption mode.
Interval timer: up to 64 s(Max)@ Sub Clock: 32.768 kHz
16-/32-bit PWC timer
Document Number: 002-04672 Rev. *D
Page 2 of 111
MB9A110A/MB9A110 Series
Watch dog Timer (2 channels)
[Resets]
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Reset requests from INITX pin
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except STOP
modes.
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock Supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
External clock failure (clock stop) is detected, reset is
asserted.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
External frequency anomaly is detected, interrupt or reset is
Capable of pull-up control per pin
Capable of reading pin level directly
This Series includes 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage that has been set,
Low-Voltage Detector generates an interrupt or reset.
Built-in the port relocate function
LVD1: error reporting via interrupt
Up to 83 fast General Purpose I/O Ports@ 100 pin Package
LVD2: auto-reset operation
asserted.
Low-Voltage Detector (LVD)
Some ports are 5V tolerant I/O (MB9AF115MA/NA,
MB9AF116MA/NA only)
Please see "Pin Description" to confirm the corresponding
pins.
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
SLEEP
CRC (Cyclic Redundancy Check) Accelerator
TIMER
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
STOP
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM)*
*: Mb9AF111LA/MA, F112LA/MA, F114LA/MA, F115MA and
F116MA support only SWJ-DP.
[Clocks]
Power Supply
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
VCC = 2.7 V to 5.5 V: Correspond to the wide range voltage.
Main Clock:
4 MHz to 48 MHz
Sub Clock:
32.768 kHz
Built-in High-speed CR Clock:
4 MHz
Built-in Low-speed CR Clock:
100 kHz
Main PLL Clock
Document Number: 002-04672 Rev. *D
Page 3 of 111
MB9A110A/MB9A110 Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 14
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precautions ..................................................................................................................................................... 44
6.1
Precautions for Product Design ................................................................................................................................... 44
6.2
Precautions for Package Mounting .............................................................................................................................. 45
6.3
Precautions for Use Environment ................................................................................................................................ 46
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram ................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 50
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 54
12. Electrical Characteristics ............................................................................................................................................... 58
12.1 Absolute Maximum Ratings ......................................................................................................................................... 58
12.2 Recommended Operating Conditions.......................................................................................................................... 60
12.3 DC Characteristics....................................................................................................................................................... 61
12.3.1 Current rating ............................................................................................................................................................... 61
12.3.2 Pin Characteristics ....................................................................................................................................................... 63
12.4 AC Characteristics ....................................................................................................................................................... 64
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 64
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 65
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 65
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) ......................................... 66
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock
of the main PLL) ........................................................................................................................................................... 66
12.4.6 Reset Input Characteristics .......................................................................................................................................... 67
12.4.7 Power-on Reset Timing................................................................................................................................................ 67
12.4.8 External Bus Timing ..................................................................................................................................................... 68
12.4.9 Base Timer Input Timing .............................................................................................................................................. 75
12.4.10 CSIO/UART Timing .................................................................................................................................................. 76
12.4.11 External Input Timing ................................................................................................................................................ 84
12.4.12 Quadrature Position/Revolution Counter timing ........................................................................................................ 85
12.4.13 I2C Timing ................................................................................................................................................................. 87
12.4.14 ETM timing ............................................................................................................................................................... 88
12.4.15 JTAG Timing ............................................................................................................................................................. 89
12.5 12-bit A/D Converter .................................................................................................................................................... 90
12.6 Low-voltage detection characteristics .......................................................................................................................... 93
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 94
12.7.1 Write / Erase time......................................................................................................................................................... 94
12.7.2 Erase/Write cycles and data hold time ......................................................................................................................... 94
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 95
12.8.1 Return Factor: Interrupt ................................................................................................................................................ 95
12.8.2 Return Factor: Reset .................................................................................................................................................... 97
13. Ordering Information ...................................................................................................................................................... 99
14. Package Dimensions .................................................................................................................................................... 100
15. Errata.............................................................................................................................................................................. 107
Document Number: 002-04672 Rev. *D
Page 4 of 111
MB9A110A/MB9A110 Series
15.1 Part Numbers Affected .............................................................................................................................................. 107
15.2 Qualification Status.................................................................................................................................................... 107
15.3 Errata Summary ........................................................................................................................................................ 107
16. Major Changes .............................................................................................................................................................. 108
Document History ............................................................................................................................................................... 110
Sales, Solutions, and Legal Information ........................................................................................................................... 111
Document Number: 002-04672 Rev. *D
Page 5 of 111
MB9A110A/MB9A110 Series
1. Product Lineup
Memory Size
Product name
MB9AF112LA/MA/NA
MB9AF112L
MB9AF111LA/MA/NA
MB9AF114LA/MA/NA
MB9AF114L
On-chip Flash memory
64 Kbytes
128 Kbytes
256 Kbytes
On-chip SRAM
16 Kbytes
16 Kbytes
32 Kbytes
Product name
MB9AF115MA/NA
MB9AF116MA/NA
On-chip Flash memory
384 Kbytes
512 Kbytes
On-chip SRAM
32 Kbytes
32 Kbytes
Function
MB9AF111LA
MB9AF112LA
MB9AF114LA
MB9AF112L
MB9AF114L
Product name
Pin count
64
Cortex-M3
40 MHz
2.7 V to 5.5 V
8 ch.
CPU
Freq.
Power supply voltage range
DMAC
MB9AF111MA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
80
100
Addr:21-bit (Max)
Data:8-bit
CS:4 (Max)
Support: SRAM, NOR Flash
Addr:25-bit (Max)
Data:8-/16-bit
CS:8 (Max)
Support: SRAM, NOR Flash
External Bus Interface
-
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
8 ch. (Max)
ch.4 to ch.7: FIFO (16 steps x 9-bit)
ch.0 to ch.3: No FIFO
MF-Timer
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
compare
Input capture
Free-run timer
Output compare
Waveform generator
PPG
QPRC
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
8 ch. (Max)
3 ch.
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
1 unit
2 units (Max)
2 ch. (Max)
Dual Timer
1 unit
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) + NMI × 1
51 pins (Max)
9 ch. (2 units)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP
11 pins (Max) + NMI × 1
66 pins (Max)
12 ch. (3 units)
16 pins (Max) + NMI × 1
83 pins (Max)
16 ch. (3 units)
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-04672 Rev. *D
Page 6 of 111
MB9A110A/MB9A110 Series
2. Packages
Product name
Package
MB9AF111LA
MB9AF112LA
MB9AF114LA
MB9AF112L
MB9AF114L
MB9AF111MA
MB9AF112MA
MB9AF114MA
MB9AF115MA
MB9AF116MA
MB9AF111NA
MB9AF112NA
MB9AF114NA
MB9AF115NA
MB9AF116NA
LQFP:LQD064 (0.5 mm pitch)
-
-
-
LQFP:LQG064 (0.65 mm pitch)
-
-
QFN :VNC064 (0.5 mm pitch)
-
-
-
LQFP:LQH080 (0.5 mm pitch)
-
-
LQFP:LQI100 (0.65 mm pitch)
-
-
-
QFP :PQH100 (0.65 mm pitch)
-
-
-
BGA :LBC112 (0.8 mm pitch)
-
-
-
*
-
: Supported
*: MB9AF115NA, MB9AF116NA are planning
Note:
−
Refer to “14. Package Dimensions” for detailed information on each package.
Document Number: 002-04672 Rev. *D
Page 7 of 111
MB9A110A/MB9A110 Series
3. Pin Assignment
LQI100
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1
P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1
P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
2
74
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
3
73
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
4
72
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
5
71
P23/SCK0_0/TIOA7_1/RTO00_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
6
70
P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
7
69
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
P56/INT08_2/DTTI1X_0/MADATA06_1
8
68
P1D/AN13/CTS4_1/IC03_1/MAD21_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
9
67
P1C/AN12/SCK4_1/IC02_1/MAD20_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
10
66
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
11
65
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
12
64
P19/AN09/SCK2_2/MAD17_1
LQFP - 100
47
48
49
50
PE3/X1
VSS
46
PE0/MD1
MD0
45
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
PE2/X0
44
VCC
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
51
43
25
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
P10/AN00
VSS
42
52
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
24
41
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3F/RTO05_0/TIOA5_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
53
40
23
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3E/RTO04_0/TIOA4_1
39
54
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
22
38
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3D/RTO03_0/TIOA3_1
INITX
55
37
21
36
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3C/RTO02_0/TIOA2_1
P47/X1A
56
35
20
VCC
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3B/RTO01_0/TIOA1_1
P46/X0A
57
34
19
VSS
P16/AN06/SCK0_1/MAD14_1
P3A/RTO00_0/TIOA0_1
33
58
C
18
32
P17/AN07/SIN2_2/INT04_1/MAD15_1
P39/DTTI0X_0/ADTG_2
P45/TIOA5_0/RTO15_1/MAD01_1
59
31
17
P44/TIOA4_0/RTO14_1/MAD00_1
AVCC
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1
30
60
P43/TIOA3_0/RTO13_1/ADTG_7
16
29
AVRH
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1
P42/TIOA2_0/RTO12_1
61
28
15
P41/TIOA1_0/RTO11_1/INT13_1
AVSS
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1
27
P18/AN08/SOT2_2/MAD16_1
62
26
63
14
VCC
13
P40/TIOA0_0/RTO10_1/INT12_1
P34/FRCK0_0/TIOB4_1/MADATA11_1
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 8 of 111
MB9A110A/MB9A110 Series
PQH100
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
VCC
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1
P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1
P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
VSS
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P21/SIN0_0/INT06_1/BIN1_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
81
50
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
82
49
P23/SCK0_0/TIOA7_1/RTO00_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
83
48
P1F/AN15/ADTG_5/FRCK0_1/MAD23_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
84
47
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
85
46
P1D/AN13/CTS4_1/IC03_1/MAD21_1
P56/INT08_2/DTTI1X_0/MADATA06_1
86
45
P1C/AN12/SCK4_1/IC02_1/MAD20_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
87
44
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
88
43
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
89
42
P19/AN09/SCK2_2/MAD17_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
90
41
P18/AN08/SOT2_2/MAD16_1
P34/FRCK0_0/TIOB4_1/MADATA11_1
91
40
AVSS
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1
92
39
AVRH
P36/IC02_0/SIN5_2/INT09_1/MADATA13_1
93
38
AVCC
P37/IC01_0/SOT5_2/INT10_1/MADATA14_1
94
37
P17/AN07/SIN2_2/INT04_1/MAD15_1
P38/IC00_0/SCK5_2/INT11_1/MADATA15_1
95
36
P16/AN06/SCK0_1/MAD14_1
P39/DTTI0X_0/ADTG_2
96
35
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3A/RTO00_0/TIOA0_1
97
34
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3B/RTO01_0/TIOA1_1
98
33
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3C/RTO02_0/TIOA2_1
99
32
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3D/RTO03_0/TIOA3_1
100
31
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
20
21
22
23
24
25
26
27
28
29
30
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00
19
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
15
P47/X1A
18
14
P46/X0A
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
13
17
12
VSS
VCC
16
11
C
INITX
10
P45/TIOA5_0/RTO15_1/MAD01_1
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
9
6
P41/TIOA1_0/RTO11_1/INT13_1
8
5
P44/TIOA4_0/RTO14_1/MAD00_1
4
P40/TIOA0_0/RTO10_1/INT12_1
7
3
VSS
VCC
P42/TIOA2_0/RTO12_1
2
P3F/RTO05_0/TIOA5_1
P43/TIOA3_0/RTO13_1/ADTG_7
1
P3E/RTO04_0/TIOA4_1
QFP - 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 9 of 111
MB9A110A/MB9A110 Series
LQH080
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_1
P63/INT03_0/MWEX_1
P0F/NMIX/CROUT_1
P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1
P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1
P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1
P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1
P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1
P07/ADTG_0/MCLKOUT_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
P20/INT05_0/CROUT_0/AIN1_1/MAD24_1
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1
2
59
P21/SIN0_0/INT06_1/BIN1_1
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1
3
58
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1
4
57
P23/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1
5
56
P1B/AN11/SOT4_1/IC01_1/MAD19_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1
6
55
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1
7
54
P19/AN09/SCK2_2/MAD17_1
P56/INT08_2/DTTI1X_0/MADATA06_1
8
53
P18/AN08/SOT2_2/MAD16_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1
9
52
AVSS
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1
10
51
AVRH
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1
12
49
P17/AN07/SIN2_2/INT04_1/MAD15_1
P39/DTTI0X_0/ADTG_2
13
48
P16/AN06/SCK0_1/MAD14_1
P3A/RTO00_0/TIOA0_1
14
47
P15/AN05/SOT0_1/IC03_2/MAD13_1
P3B/RTO01_0/TIOA1_1
15
46
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1
P3C/RTO02_0/TIOA2_1
16
45
P13/AN03/SCK1_1/IC01_2/MAD11_1
P3D/RTO03_0/TIOA3_1
17
44
P12/AN02/SOT1_1/IC00_2/MAD10_1
P3E/RTO04_0/TIOA4_1
18
43
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1
P3F/RTO05_0/TIOA5_1
19
42
P10/AN00
VSS
20
41
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/MAD00_1
P45/TIOA5_0/MAD01_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 10 of 111
MB9A110A/MB9A110 Series
LQD064/LQG064
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3
P0F/NMIX/CROUT_1
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/SIN0_0/INT06_1
P50/INT00_0/AIN0_2/SIN3_1
2
47
P22/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
46
P23/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVSS
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1
10
39
P15/AN05/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1
12
37
P13/AN03/SCK1_1/IC01_2
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA4_1
14
35
P11/AN01/SIN1_1/INT02_1/FRCK0_2
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/AIN0_1
P4A/TIOB1_0/BIN0_1
P4B/TIOB2_0/ZIN0_1
P4C/TIOB3_0/SCK7_1/AIN1_2
P4D/TIOB4_0/SOT7_1/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 11 of 111
MB9A110A/MB9A110 Series
LBC112
1
2
3
4
5
6
7
8
9
10
11
A
VSS
P81
P80
VCC
P0E
P0B
P07
TMS/
SWDIO
TRSTX
VCC
VSS
B
VCC
VSS
P52
P61
P0F
P0C
P08
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0D
P09
P05
VSS
P20
P21
D
P53
P54
P55
VSS
P56
P63
P0A
VSS
P06
P23
AN15
E
P30
P31
P32
P33
Index
P22
AN14
AN12
AN11
F
P34
P35
P36
P39
AN13
AN10
AN09
AVRH
G
P37
P38
P3A
P3D
AN08
AN07
AN06
AVSS
H
P3B
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
J
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
PFBGA - 112
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 12 of 111
MB9A110A/MB9A110 Series
VNC064
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3
P0F/NMIX/CROUT_1
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/SIN0_0/INT06_1
P50/INT00_0/AIN0_2/SIN3_1
2
47
P22/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
46
P23/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
45
P19/AN09/SCK2_2
P30/AIN0_0/TIOB0_1/INT03_2
5
44
P18/AN08/SOT2_2
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2
6
43
AVSS
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
8
41
AVCC
P39/DTTI0X_0/ADTG_2
9
40
P17/AN07/SIN2_2/INT04_1
P3A/RTO00_0/TIOA0_1
10
39
P15/AN05/IC03_2
P3B/RTO01_0/TIOA1_1
11
38
P14/AN04/INT03_1/IC02_2
P3C/RTO02_0/TIOA2_1
12
37
P13/AN03/SCK1_1/IC01_2
P3D/RTO03_0/TIOA3_1
13
36
P12/AN02/SOT1_1/IC00_2
P3E/RTO04_0/TIOA4_1
14
35
P11/AN01/SIN1_1/INT02_1/FRCK0_2
P3F/RTO05_0/TIOA5_1
15
34
P10/AN00
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/AIN0_1
P4A/TIOB1_0/BIN0_1
P4B/TIOB2_0/ZIN0_1
P4C/TIOB3_0/SCK7_1/AIN1_2
P4D/TIOB4_0/SOT7_1/BIN1_2
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04672 Rev. *D
Page 13 of 111
MB9A110A/MB9A110 Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-100
1
QFP-100
79
BGA-112
B1
1
1
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
VCC
Pin state
type
-
P50
2
2
80
C1
2
INT00_0
AIN0_2
SIN3_1
-
E
H
E
H
E
H
E
H
E
I
RTO10_0
(PPG10_0)
MADATA00_1
P51
INT01_0
3
3
81
C2
BIN0_2
SOT3_1
(SDA3_1)
3
-
RTO11_0
(PPG10_0)
MADATA01_1
P52
INT02_0
4
4
82
B3
ZIN0_2
SCK3_1
(SCL3_1)
4
-
RTO12_0
(PPG12_0)
MADATA02_1
P53
SIN6_0
TIOA1_2
5
83
D1
5
-
INT07_2
RTO13_0
(PPG12_0)
MADATA03_1
P54
SOT6_0
(SDA6_0)
6
84
D2
6
-
TIOB1_2
RTO14_0
(PPG14_0)
MADATA04_1
Document Number: 002-04672 Rev. *D
Page 14 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
Pin name
LQFP-64
QFN-64
LQFP-80
I/O circuit
type
Pin state
type
P55
SCK6_0
(SCL6_0)
7
85
D3
7
-
ADTG_1
E
I
E
H
E
H
E
H
E
H
E
H
E
I
RTO15_0
(PPG14_0)
MADATA05_1
P56
8
86
D5
8
-
INT08_2
DTTI1X_0
MADATA06_1
P30
9
87
E1
9
5
AIN0_0
TIOB0_1
INT03_2
-
MADATA07_1
P31
BIN0_0
10
88
E2
10
6
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
-
MADATA08_1
P32
ZIN0_0
11
89
E3
11
7
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
-
MADATA09_1
P33
INT04_0
12
90
E4
12
8
TIOB3_1
SIN6_1
ADTG_6
-
MADATA10_1
P34
13
91
F1
-
-
FRCK0_0
TIOB4_1
MADATA11_1
Document Number: 002-04672 Rev. *D
Page 15 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P35
IC03_0
14
92
F2
-
-
TIOB5_1
E
H
E
H
E
H
E
H
E
I
G
I
G
I
G
I
G
I
INT08_1
MADATA12_1
P36
IC02_0
15
93
F3
-
-
SIN5_2
INT09_1
MADATA13_1
P37
IC01_0
16
94
G1
-
-
SOT5_2
(SDA5_2)
INT10_1
MADATA14_1
P38
IC00_0
17
95
G2
-
-
SCK5_2
(SCL5_2)
INT11_1
MADATA15_1
P39
18
96
F4
13
9
DTTI0X_0
ADTG_2
P3A
19
97
G3
14
10
RTO00_0
(PPG00_0)
TIOA0_1
P3B
20
98
H1
15
11
RTO01_0
(PPG00_0)
TIOA1_1
P3C
21
99
H2
16
12
RTO02_0
(PPG02_0)
TIOA2_1
P3D
22
100
G4
17
13
-
-
B2
-
-
RTO03_0
(PPG02_0)
TIOA3_1
Document Number: 002-04672 Rev. *D
VSS
-
Page 16 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P3E
23
1
H3
18
14
RTO04_0
(PPG04_0)
G
I
G
I
TIOA4_1
P3F
RTO05_0
(PPG04_0)
24
2
J2
19
15
25
3
L1
20
16
VSS
-
26
4
J1
-
-
VCC
-
TIOA5_1
P40
TIOA0_0
27
5
J4
-
-
RTO10_1
(PPG10_1)
G
H
G
H
G
I
G
I
G
I
G
I
INT12_1
P41
TIOA1_0
28
6
L5
-
-
RTO11_1
(PPG10_1)
INT13_1
P42
29
7
K5
-
-
TIOA2_0
RTO12_1
(PPG12_1)
P43
TIOA3_0
30
8
J5
-
-
RTO13_1
(PPG12_1)
ADTG_7
P44
21
31
9
H5
TIOA4_0
-
MAD00_1
RTO14_1
(PPG14_1)
-
P45
22
32
10
L6
TIOA5_0
-
MAD01_1
RTO15_1
(PPG14_1)
-
-
K2
-
-
VSS
-
-
-
J3
-
-
VSS
-
-
-
H4
-
-
VSS
-
Document Number: 002-04672 Rev. *D
Page 17 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
33
11
L2
23
17
C
-
34
12
L4
24
-
VSS
-
35
13
K1
25
18
VCC
-
36
14
L3
26
19
37
15
K3
27
20
38
16
K4
28
21
P46
X0A
P47
X1A
INITX
Pin state
type
D
M
D
N
B
C
E
H
E
I
E
I
E
I
E / I*
I
P48
DTTI1X_1
39
17
K6
29
-
INT14_1
SIN3_2
MAD02_1
P49
22
TIOB0_0
AIN0_1
40
18
J6
30
IC10_1
-
SOT3_2
(SDA3_2)
MAD03_1
P4A
23
TIOB1_0
BIN0_1
41
19
L7
31
IC11_1
-
SCK3_2
(SCL3_2)
MAD04_1
P4B
24
42
20
K7
32
TIOB2_0
ZIN0_1
-
IC12_1
MAD05_1
P4C
TIOB3_0
25
43
21
H6
33
SCK7_1
(SCL7_1)
AIN1_2
-
Document Number: 002-04672 Rev. *D
IC13_1
MAD06_1
Page 18 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P4D
TIOB4_0
26
44
22
J7
34
SOT7_1
(SDA7_1)
E / I*
I
E / I*
I
C
P
J
D
A
A
A
B
BIN1_2
-
FRCK1_1
MAD07_1
P4E
TIOB5_0
45
23
K8
35
27
INT06_2
SIN7_1
ZIN1_2
46
24
K9
36
28
47
25
L8
37
29
MAD08_1
MD1
PE0
MD0
X0
48
26
L9
38
30
49
27
L10
39
31
50
28
L11
40
32
VSS
-
51
29
K11
41
33
VCC
-
52
30
J11
42
34
PE2
X1
PE3
P10
AN00
F
K
F
L
F
K
P11
AN01
53
31
J10
43
35
SIN1_1
INT02_1
FRCK0_2
-
MAD09_1
P12
AN02
54
32
J8
44
36
SOT1_1
(SDA1_1)
IC00_2
-
MAD10_1
-
-
K10
-
-
VSS
-
-
-
J9
-
-
VSS
-
Document Number: 002-04672 Rev. *D
Page 19 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P13
AN03
55
33
H10
45
37
SCK1_1
(SCL1_1)
F
K
F
L
F
K
F
K
F
L
IC01_2
-
MAD11_1
P14
38
56
34
H9
46
AN04
INT03_1
IC02_2
-
SIN0_1
MAD12_1
P15
39
57
35
H7
AN05
IC03_2
47
-
SOT0_1
(SDA0_1)
MAD13_1
P16
AN06
58
36
G10
48
-
SCK0_1
(SCL0_1)
MAD14_1
P17
59
37
G9
49
40
AN07
SIN2_2
INT04_1
-
MAD15_1
60
38
H11
50
41
AVCC
-
61
39
F11
51
42
AVRH
-
62
40
G11
52
43
AVSS
-
P18
63
41
G8
53
44
AN08
SOT2_2
(SDA2_2)
-
F
K
F
K
MAD16_1
P19
45
64
-
42
-
F10
H8
Document Number: 002-04672 Rev. *D
-
AN09
SCK2_2
(SCL2_2)
54
-
MAD17_1
-
VSS
-
Page 20 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P1A
AN10
65
43
F9
55
-
SIN4_1
INT05_1
F
L
F
K
F
K
F
K
F
K
F
K
IC00_1
MAD18_1
P1B
AN11
66
44
E11
56
-
SOT4_1
(SDA4_1)
IC01_1
MAD19_1
P1C
AN12
67
45
E10
-
-
SCK4_1
(SCL4_1)
IC02_1
MAD20_1
P1D
AN13
68
46
F8
-
-
CTS4_1
IC03_1
MAD21_1
P1E
AN14
69
47
E9
-
-
RTS4_1
DTTI0X_1
MAD22_1
P1F
AN15
70
48
D11
-
-
ADTG_5
FRCK0_1
MAD23_1
-
-
B10
-
-
VSS
-
-
-
C9
-
-
VSS
-
Document Number: 002-04672 Rev. *D
Page 21 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P23
57
71
49
46
D10
SCK0_0
(SCL0_0)
TIOA7_1
-
-
E
I
E
I
E
H
E
H
RTO00_1
(PPG00_1)
P22
72
50
E8
58
47
SOT0_0
(SDA0_0)
TIOB7_1
-
ZIN1_1
P21
73
51
C11
59
48
SIN0_0
INT06_1
-
BIN1_1
P20
INT05_0
74
52
C10
60
-
CROUT_0
AIN1_1
MAD24_1
75
53
A11
-
-
VSS
-
76
54
A10
-
-
VCC
-
77
55
A9
61
49
-
P00
TRSTX
E
E
E
E
E
E
E
E
E
E
E
F
MCSX7_1
P01
78
56
B9
62
50
TCK
SWCLK
79
57
B11
63
51
-
P02
TDI
MCSX6_1
P03
80
58
A8
64
52
TMS
SWDIO
P04
81
59
B8
65
53
TDO
SWO
P05
TRACED0
82
60
C8
-
-
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
-
-
D8
Document Number: 002-04672 Rev. *D
-
-
VSS
-
Page 22 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P06
TRACED1
TIOB5_2
83
61
D9
-
-
SOT4_2
(SDA4_2)
E
F
E
G
E
G
E
G
E / I*
H
E / I*
I
E / I*
I
INT01_1
MCSX4_1
P07
66
84
62
A7
ADTG_0
-
MCLKOUT_1
TRACED2
-
SCK4_2
(SCL4_2)
P08
TRACED3
85
63
B7
-
-
TIOA0_2
CTS4_2
MCSX3_1
P09
TRACECLK
86
64
C7
-
-
TIOB0_2
RTS4_2
MCSX2_1
P0A
54
87
65
D7
67
SIN4_0
INT00_2
-
FRCK1_0
MCSX1_1
P0B
55
88
66
A6
68
SOT4_0
(SDA4_0)
TIOB6_1
-
IC10_0
MCSX0_1
P0C
56
89
67
B6
69
SCK4_0
(SCL4_0)
TIOA6_1
-
IC11_0
MALE_1
-
-
D4
-
-
VSS
-
-
-
C3
-
-
VSS
-
Document Number: 002-04672 Rev. *D
Page 23 of 111
MB9A110A/MB9A110 Series
Pin No
LQFP-100
QFP-100
BGA-112
I/O circuit
type
Pin name
LQFP-64
QFN-64
LQFP-80
Pin state
type
P0D
RTS4_0
90
68
C6
70
-
TIOA3_2
E
I
E
I
E
J
E
H
E
I
E
I
E / I*
H
IC12_0
MDQM0_1
P0E
CTS4_0
91
69
A5
71
-
TIOB3_2
IC13_0
MDQM1_1
P0F
92
70
B5
72
57
NMIX
CROUT_1
P63
93
71
D6
73
-
INT03_0
MWEX_1
P62
94
72
C5
74
58
SCK5_0
(SCL5_0)
ADTG_3
-
MOEX_1
P61
95
73
B4
75
59
SOT5_0
(SDA5_0)
TIOB2_2
P60
96
74
C4
76
60
SIN5_0
TIOA2_2
INT15_1
-
MRDY_1
97
75
A4
77
61
VCC
-
98
76
A3
78
62
P80
H
O
99
77
A2
79
63
P81
H
O
100
78
A1
80
64
VSS
-
*: 5V tolerant I/O on MB9AF115MA/NA and MB9AF116MA/NA
Document Number: 002-04672 Rev. *D
Page 24 of 111
MB9A110A/MB9A110 Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Module
ADC
Pin name
Function
BGA-112
LQFP-80
LQFP-64
QFN-64
84
62
A7
66
-
ADTG_1
7
85
D3
7
-
ADTG_2
18
96
F4
13
9
94
72
C5
74
58
ADTG_4
A/D converter external trigger input
pin
-
-
-
-
-
ADTG_5
70
48
D11
-
-
ADTG_6
12
90
E4
12
8
ADTG_7
30
8
J5
-
-
ADTG_8
-
-
-
-
-
AN00
52
30
J11
42
34
AN01
53
31
J10
43
35
AN02
54
32
J8
44
36
AN03
55
33
H10
45
37
AN04
56
34
H9
46
38
AN05
57
35
H7
47
39
AN06
58
36
G10
48
-
AN07
59
37
G9
49
40
AN08
A/D converter analog input pin.
ANxx describes ADC ch.xx.
63
41
G8
53
44
AN09
64
42
F10
54
45
AN10
65
43
F9
55
-
AN11
66
44
E11
56
-
AN12
67
45
E10
-
-
AN13
68
46
F8
-
-
AN14
69
47
E9
-
-
AN15
70
48
D11
-
-
27
5
J4
-
-
19
97
G3
14
10
85
63
B7
-
-
40
18
J6
30
22
9
87
E1
9
5
86
64
C7
-
-
28
6
L5
-
-
20
98
H1
15
11
TIOA1_2
5
83
D1
5
-
TIOB1_0
41
19
L7
31
23
10
88
E2
10
6
6
84
D2
6
-
TIOA0_0
TIOA0_1
Base timer ch.0 TIOA pin
TIOA0_2
TIOB0_0
TIOB0_1
Base timer ch.0 TIOB pin
TIOB0_2
Base Timer
1
QFP-100
ADTG_0
ADTG_3
Base Timer
0
LQFP-100
TIOA1_0
TIOA1_1
TIOB1_1
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
TIOB1_2
Document Number: 002-04672 Rev. *D
Page 25 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Base Timer
2
Pin name
TIOA2_0
TIOA2_1
Base timer ch.2 TIOA pin
BGA-112
LQFP-80
LQFP-64
QFN-64
29
7
K5
-
-
99
H2
16
12
96
74
C4
76
60
TIOB2_0
42
20
K7
32
24
11
89
E3
11
7
TIOB2_2
95
73
B4
75
59
TIOA3_0
30
8
J5
-
-
22
100
G4
17
13
90
68
C6
70
-
43
21
H6
33
25
12
90
E4
12
8
91
69
A5
71
-
31
9
H5
21
-
23
1
H3
18
14
-
-
-
-
-
44
22
J7
34
26
13
91
F1
-
-
TIOB4_2
-
-
-
-
-
TIOA5_0
32
10
L6
22
-
24
2
J2
19
15
TIOA5_2
82
60
C8
-
-
TIOB5_0
45
23
K8
35
27
14
92
F2
-
-
TIOA3_1
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
TIOB3_0
TIOB3_1
Base timer ch.3 TIOB pin
TIOB3_2
TIOA4_0
TIOA4_1
Base timer ch.4 TIOA pin
TIOA4_2
TIOB4_0
TIOB4_1
Base Timer
5
QFP-100
21
TIOA3_2
Base Timer
4
LQFP-100
TIOA2_2
TIOB2_1
Base Timer
3
Function
TIOA5_1
TIOB5_1
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
83
61
D9
-
-
Base Timer
6
TIOB5_2
TIOA6_1
Base timer ch.6 TIOA pin
89
67
B6
69
56
TIOB6_1
Base timer ch.6 TIOB pin
88
66
A6
68
55
Base Timer
7
TIOA7_0
-
-
-
-
-
71
49
D10
57
46
TIOA7_2
-
-
-
-
-
TIOB7_0
-
-
-
-
-
72
50
E8
58
47
-
-
-
-
-
TIOA7_1
TIOB7_1
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
TIOB7_2
Document Number: 002-04672 Rev. *D
Page 26 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Debugger
Pin name
SWCLK
SWDIO
Function
Serial wire debug interface clock
input
Serial wire debug interface data input
/ output
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
78
56
B9
62
50
80
58
A8
64
52
SWO
Serial wire viewer output
81
59
B8
65
53
TCK
JTAG test clock input
78
56
B9
62
50
TDI
JTAG test data input
79
57
B11
63
51
TDO
JTAG debug data output
81
59
B8
65
53
TMS
JTAG test mode state input/output
80
58
A8
64
52
TRACECLK
Trace CLK output of ETM
86
64
C7
-
-
82
60
C8
-
-
83
61
D9
-
-
84
62
A7
-
-
85
63
B7
-
-
TRACED0
TRACED1
TRACED2
Trace data output of ETM
TRACED3
TRSTX
External
Bus
LQFP-100
77
55
A9
61
49
MAD00_1
31
9
H5
21
-
MAD01_1
32
10
L6
22
-
MAD02_1
39
17
K6
29
-
MAD03_1
40
18
J6
30
-
MAD04_1
41
19
L7
31
-
MAD05_1
42
20
K7
32
-
MAD06_1
43
21
H6
33
-
MAD07_1
44
22
J7
34
-
MAD08_1
45
23
K8
35
-
MAD09_1
53
31
J10
43
-
MAD10_1
54
32
J8
44
-
MAD11_1
55
33
H10
45
-
56
34
H9
46
-
MAD13_1
57
35
H7
47
-
MAD14_1
58
36
G10
48
-
MAD15_1
59
37
G9
49
-
MAD16_1
63
41
G8
53
-
MAD17_1
64
42
F10
54
-
MAD18_1
65
43
F9
55
-
MAD19_1
66
44
E11
56
-
MAD20_1
67
45
E10
-
-
MAD21_1
68
46
F8
-
-
MAD22_1
69
47
E9
-
-
MAD23_1
70
48
D11
-
-
MAD24_1
74
52
C10
60
-
MAD12_1
JTAG test reset input
External bus interface address bus
Document Number: 002-04672 Rev. *D
Page 27 of 111
MB9A110A/MB9A110 Series
Pin No
Module
External
Bus
Pin name
Function
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
MCSX0_1
88
66
A6
68
-
MCSX1_1
87
65
D7
67
-
MCSX2_1
86
64
C7
-
-
85
63
B7
-
-
MCSX3_1
MCSX4_1
External bus interface chip select
output pin
83
61
D9
-
-
MCSX5_1
82
60
C8
-
-
MCSX6_1
79
57
B11
63
-
MCSX7_1
77
55
A9
61
-
MDQM0_1
90
68
C6
70
-
91
69
A5
71
-
94
72
C5
74
-
93
71
D6
73
-
MADATA00_1
2
80
C1
2
-
MADATA01_1
3
81
C2
3
-
MADATA02_1
4
82
B3
4
-
MADATA03_1
5
83
D1
5
-
MADATA04_1
6
84
D2
6
-
MADATA05_1
7
85
D3
7
-
MADATA06_1
8
86
D5
8
-
9
87
E1
9
-
MDQM1_1
MOEX_1
MWEX_1
MADATA07_1
MADATA08_1
External bus interface byte mask
signal output
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
External bus interface data bus
10
88
E2
10
-
MADATA09_1
11
89
E3
11
-
MADATA10_1
12
90
E4
12
-
MADATA11_1
13
91
F1
-
-
MADATA12_1
14
92
F2
-
-
MADATA13_1
15
93
F3
-
-
MADATA14_1
16
94
G1
-
-
MADATA15_1
17
95
G2
-
-
89
67
B6
69
-
96
84
74
62
C4
A7
76
66
-
MALE_1
MRDY_1
MCLKOUT_1
Address Latch enable signal for
multiplex
External RDY input signal
External bus clock output
Document Number: 002-04672 Rev. *D
Page 28 of 111
MB9A110A/MB9A110 Series
Pin No
Module
External
Interrupt
Pin name
Function
INT00_0
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
2
80
C1
2
2
82
60
C8
-
-
87
65
D7
67
54
External interrupt request 01
input pin
3
81
C2
3
3
83
61
D9
-
-
External interrupt request 02
input pin
4
82
B3
4
4
53
31
J10
43
35
93
71
D6
73
-
56
34
H9
46
38
INT03_2
9
87
E1
9
5
INT04_0
12
90
E4
12
8
59
37
G9
49
40
INT04_2
10
88
E2
10
6
INT05_0
74
52
C10
60
-
65
43
F9
55
-
INT05_2
11
89
E3
11
7
INT06_1
73
51
C11
59
48
45
23
K8
35
27
5
83
D1
5
-
14
92
F2
-
-
8
86
D5
8
-
15
93
F3
-
-
16
94
G1
-
-
17
95
G2
-
-
27
5
J4
-
-
28
6
L5
-
-
39
17
K6
29
-
96
74
C4
76
60
92
70
B5
72
57
INT00_1
External interrupt request 00
input pin
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT04_1
INT05_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
External interrupt request 03
input pin
External interrupt request 04
input pin
External interrupt request 05
input pin
External interrupt request 06
input pin
External interrupt request 07
input pin
External interrupt request 08
input pin
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
External interrupt request 15
input pin
Non-Maskable Interrupt input
Document Number: 002-04672 Rev. *D
Page 29 of 111
MB9A110A/MB9A110 Series
Pin No
Module
GPIO
Pin name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-04672 Rev. *D
LQFP-100
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
QFP-100
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
BGA-112
LQFP-80
LQFP-64
QFN-64
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
60
59
58
57
49
50
51
52
53
54
55
56
57
34
35
36
37
38
39
40
44
45
48
47
46
Page 30 of 111
MB9A110A/MB9A110 Series
Pin No
Module
GPIO
Pin name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Document Number: 002-04672 Rev. *D
LQFP-100
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
QFP-100
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
BGA-112
LQFP-80
LQFP-64
QFN-64
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
9
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
5
6
7
8
9
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
3
4
60
59
58
62
63
28
30
31
Page 31 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
0
Pin name
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multi
Function
Serial
1
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
Multi
Function
Serial
2
SIN2_2
SOT2_2
(SDA2_2)
SCK2_2
(SCL2_2)
Multi
Function
Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function
Multifunction serial interface ch.0
input pin
Multifunction serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.1
input pin
Multifunction serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a CSIO (operation mode 2)
and as SCL1 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.2
input pin
Multifunction serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.3
input pin
Multifunction serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an I2C
(operation mode 4).
Document Number: 002-04672 Rev. *D
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
73
51
C11
59
48
56
34
H9
46
-
72
50
E8
58
47
57
35
H7
47
-
71
49
D10
57
46
58
36
G10
48
-
53
31
J10
43
35
54
32
J8
44
36
55
33
H10
45
37
59
37
G9
49
40
63
41
G8
53
44
64
42
F10
54
45
2
39
80
17
C1
K6
2
29
2
-
3
81
C2
3
3
40
18
J6
30
-
4
82
B3
4
4
41
19
L7
31
-
Page 32 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
4
Pin name
Function
SIN4_0
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
87
65
D7
67
54
65
43
F9
55
-
82
60
C8
-
-
88
66
A6
68
55
66
44
E11
56
-
83
61
D9
-
-
89
67
B6
69
56
67
45
E10
-
-
84
62
A7
-
-
90
68
C6
70
-
69
47
E9
-
-
86
64
C7
-
-
91
69
A5
71
-
68
46
F8
-
-
CTS4_2
85
63
B7
-
-
SIN5_0
96
74
C4
76
60
15
93
F3
-
-
95
73
B4
75
59
16
94
G1
-
-
94
72
C5
74
58
17
95
G2
-
-
SIN4_1
Multifunction serial interface ch.4
input pin
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
Multifunction serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an I2C
(operation mode 4).
RTS4_0
RTS4_1
Multifunction serial interface ch.4
RTS output pin
RTS4_2
CTS4_0
CTS4_1
Multi
Function
Serial
5
LQFP-100
SIN5_2
SOT5_0
(SDA5_0)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_2
(SCL5_2)
Multifunction serial interface ch.4
CTS input pin
Multifunction serial interface ch.5
input pin
Multifunction serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an I2C
(operation mode 4).
Document Number: 002-04672 Rev. *D
Page 33 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Serial
6
Pin name
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multi
Function
Serial
7
SIN7_1
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
Function
Multifunction serial interface ch.6
input pin
Multifunction serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an I2C
(operation mode 4).
Multifunction serial interface ch.7
input pin
Multifunction serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an I2C
(operation mode 4).
Document Number: 002-04672 Rev. *D
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
5
83
D1
5
-
12
90
E4
12
8
6
84
D2
6
-
11
89
E3
11
7
7
85
D3
7
-
10
88
E2
10
6
45
23
K8
35
27
44
22
J7
34
26
43
21
H6
33
25
Page 34 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Timer
0
Pin name
DTTI0X_0
Function
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
multi-function timer 0
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
18
96
F4
13
9
69
47
E9
-
-
13
91
F1
-
-
70
48
D11
-
-
FRCK0_2
53
31
J10
43
35
IC00_0
17
95
G2
-
-
IC00_1
65
43
F9
55
-
IC00_2
54
32
J8
44
36
IC01_0
16
94
G1
-
-
IC01_1
66
44
E11
56
-
55
33
H10
45
37
DTTI0X_1
FRCK0_0
FRCK0_1
IC01_2
IC02_0
16-bit free-run timer external clock
input pin
16-bit input capture input pin of
multi-function timer 0.
ICxx describes channel number.
15
93
F3
-
-
IC02_1
67
45
E10
-
-
IC02_2
56
34
H9
46
38
IC03_0
14
92
F2
-
-
IC03_1
68
46
F8
-
-
IC03_2
57
35
H7
47
39
19
97
G3
14
10
71
49
D10
-
-
20
98
H1
15
11
21
99
H2
16
12
22
100
G4
17
13
23
1
H3
18
14
24
2
J2
19
15
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
Waveform generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG 0 output mode.
Waveform generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG 0 output mode.
Document Number: 002-04672 Rev. *D
Page 35 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Multi
Function
Timer
1
Pin name
Function
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
Input signal of waveform generator to
control outputs RTO10 to RTO15 of
multi-function timer 1
8
86
D5
8
-
39
17
K6
29
-
16-bit free-run timer ch.1 external
clock input pin
87
65
D7
67
-
44
22
J7
34
-
IC10_0
88
66
A6
68
-
IC10_1
40
18
J6
30
-
IC11_0
89
67
B6
69
-
41
19
L7
31
-
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC11_1
IC12_0
16-bit input capture input pin of
multi-function timer 1.
ICxx describes channel number.
90
68
C6
70
-
IC12_1
42
20
K7
32
-
IC13_0
91
69
A5
71
-
IC13_1
43
21
H6
33
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG 1 output mode.
2
80
C1
2
-
27
5
J4
-
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG 1 output mode.
3
81
C2
3
-
28
6
L5
-
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG 1 output mode.
4
82
B3
4
-
29
7
K5
-
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG 1 output mode.
5
83
D1
5
-
30
8
J5
-
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG 1 output mode.
6
84
D2
6
-
31
9
H5
21
-
Waveform generator output of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG 1 output mode.
7
85
D3
7
-
32
10
L6
22
-
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Document Number: 002-04672 Rev. *D
Page 36 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Quadrature
Position/
Revolution
Counter
0
Pin name
Function
AIN0_0
AIN0_1
BGA-112
LQFP-80
LQFP-64
QFN-64
9
87
E1
9
5
40
18
J6
30
22
2
80
C1
2
2
BIN0_0
10
88
E2
10
6
41
19
L7
31
23
BIN0_2
3
81
C2
3
3
ZIN0_0
11
89
E3
11
7
42
20
K7
32
24
4
82
B3
4
4
74
52
C10
60
-
43
21
H6
33
25
73
51
C11
59
-
44
22
J7
34
26
72
50
E8
58
-
45
23
K8
35
27
ZIN0_1
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
ZIN0_2
Quadrature
Position/
Revolution
Counter
1
QFP-100
AIN0_2
BIN0_1
QPRC ch.0 AIN input pin
LQFP-100
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
Document Number: 002-04672 Rev. *D
Page 37 of 111
MB9A110A/MB9A110 Series
Pin No
Module
Reset
Pin name
INITX
Mode
MD0
MD1
Power
GND
Clock
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
Analog
Power
AVCC
AVRH
Analog
GND
C pin
Function
External Reset Input. A reset is valid
when INITX="L"
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to flash
memory, MD1="L" must be input.
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock
output port
A/D converter analog power supply
pin
A/D converter analog reference
voltage input pin
LQFP-100
QFP-100
BGA-112
LQFP-80
LQFP-64
QFN-64
38
16
K4
28
21
47
25
L8
37
29
46
24
K9
36
28
1
26
35
51
76
97
25
34
50
75
100
48
36
49
37
79
4
13
29
54
75
3
12
28
53
78
26
14
27
15
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
L9
L3
L10
K3
1
25
41
77
20
24
40
80
38
26
39
27
1
18
33
61
16
32
64
30
19
31
20
74
52
C10
60
-
92
70
B5
72
57
60
38
H11
50
41
61
39
F11
51
42
AVSS
A/D converter GND pin
62
40
G11
52
43
C
Power supply stabilization capacity
pin
33
11
L2
23
17
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04672 Rev. *D
Page 38 of 111
MB9A110A/MB9A110 Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
P-ch
When the main oscillation is selected.
P-ch
Digital output
X1
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
Digital input
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
Document Number: 002-04672 Rev. *D
Page 39 of 111
MB9A110A/MB9A110 Series
Type
C
Circuit
Remarks
Digital input
• Open drain output
• CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
When the sub oscillation is selected.
P-ch
Digital output
X1A
• Oscillation feedback resistor
: Approximately 5 MΩ
• With Standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
Digital input
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-04672 Rev. *D
Page 40 of 111
MB9A110A/MB9A110 Series
Type
E
Circuit
Remarks
•
•
•
•
•
P-ch
P-ch
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH=-4 mA, IOL=4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
R
P-ch
Digital output
N-ch
Digital output
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH=-4 mA, IOL=4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04672 Rev. *D
Page 41 of 111
MB9A110A/MB9A110 Series
Type
G
Circuit
Remarks
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH=-12 mA, IOL= 12 mA
• +B input is available
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
•
•
•
•
H
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -20.5 mA, IOL = 18.5 mA
Digital output
N-ch
Digital output
R
Digital input
Standby mode control
Document Number: 002-04672 Rev. *D
Page 42 of 111
MB9A110A/MB9A110 Series
Type
I
Circuit
Remarks
•
•
•
•
•
•
P-ch
Digital output
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
5V tolerant
With standby mode control
IOH=-4 mA, IOL= 4 mA
When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode Input
Document Number: 002-04672 Rev. *D
Page 43 of 111
MB9A110A/MB9A110 Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04672 Rev. *D
Page 44 of 111
MB9A110A/MB9A110 Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Document Number: 002-04672 Rev. *D
Page 45 of 111
MB9A110A/MB9A110 Series
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04672 Rev. *D
Page 46 of 111
MB9A110A/MB9A110 Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be driven to the X0, X0A pin only and the X1,X1A pin should be kept open.
• Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I 2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I 2C bus system with power OFF.
Document Number: 002-04672 Rev. *D
Page 47 of 111
MB9A110A/MB9A110 Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation
(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-04672 Rev. *D
Page 48 of 111
MB9A110A/MB9A110 Series
8. Block Diagram
MB9AF111LA/MA/NA, F112LA/MA/NA/L, F114LA/MA/NA/L, F115MA/NA, F116MA/NA
TRSTX,TCK,
TDI,TMS
TDO
TRACED[3:0],
TRACECLK
SWJ-DP
ETM*1
TPIU*1
ROM
Table
SRAM0
8/16
Kbyte
Cortex-M3 Core I
@40 MHz(Max)
D
Multi-layer AHB (Max 40 MHz)
NVIC
Flash I/F
Sys
AHB-APB Bridge:
APB0(Max 40 MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
Security
On-Chip
Flash
64/128/256/384/512
Kbyte
SRAM1
8/16
Kbyte
DMAC
8ch
CSV
X0
X1
X0A
Main
Osc
Sub
Osc
PLL
CR
4MHz
AHB-AHB
Bridge
CLK
Source Clock
CR
100kHz
MAD[24:0]
CROUT
AVCC,
AVSS,AVRH
External Bus I/F*2
12-bit A/D Converter x 3
MADATA[15:0]
MCSX[7:0],
MOEX,MWEX,
MALE,
MRDY,
MCLKOUT,
MDQM[1:0]
Unit 0
AN[15:0]
Unit 1
TIOB[7:0]
AIN[1:0]
BIN[1:0]
QPRC
2ch.
ZIN[1:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
FRCK[1:0]
DTTI[1:0]X
RTO0[5:0]
RTO1[5:0]
Power-On
Reset
Base Timer
16-bit 8ch. /
32-bit 4ch.
16-bit Input Capture
4ch.
16-bit Free-Run
Timer
3ch.
16-bit Output
Compare
6ch.
LVD Ctrl
AHB-APB Bridge : APB2 (Max 40 MHz)
TIOA[7:0]
Unit 2*2
AHB-APB Bridge : APB1 (Max 40 MHz)
ADTGx
Regulator
Multi-Function Timer x 2
C
IRQ-Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:0]
NMIX
MD[1:0]
MODE-Ctrl
GPIO
Waveform Generator
3ch.
16-bit PPG
3ch.
LVD
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to 7)
2
& HW flow control(ch.4)*
PIN-Function-Ctrl
P0[F:0],
P1[F:0],
.
.
.
Px[x:0]
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
*1: For the MB9AF111LA/MA, F112LA/MA, MB9AF114LA/MA, MB9AF115MA and MB9AF116MA, ETM is not available.
*2: For the MB9AF111LA, F112LA and MB9AF114LA, the External Bus Interface and 12-bit A/D Converter (unit 2) are not available.
And the Multi-function Serial Interface does not support hardware flow control in these products.
Document Number: 002-04672 Rev. *D
Page 49 of 111
MB9A110A/MB9A110 Series
9. Memory Size
See “Memory Size” in “1. Product Lineup” to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4003_F000
Reserved
0x4003_B000
0x4003_A000
0x7000_0000
0x6000_0000
0x4003_9000
External Device
Area
0x4003_8000
0x4003_7000
Reserved
0x4003_5000
32Mbytes
Bit band alias
0x4003_4000
0x4400_0000
0x4200_0000
0x4000_0000
Peripherals
Reserved
0x2400_0000
0x2200_0000
0x2008_0000
0x1FF8_0000
See the next page
"nMemory Map
(2),(3)"
for the memory size
details.
0x0010_2000
0x0010_0000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
32Mbytes
Bit band alias
Reserved
0x2000_0000
0x4003_3000
0x4003_2000
0x4002_8000
Security/CR Trim
EXT-bus I/F
Reserved
Watch Counter
CRC
MFS
Reserved
LVD
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
A/DC
0x4002_6000
QPRC
0x4002_5000
Base Timer
PPG
0x4002_2000
0x4002_1000
0x4002_0000
Reserved
MFT Unit1
MFT Unit0
0x4001_6000
Flash
0x4001_5000
0x4001_3000
0x0000_0000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-04672 Rev. *D
Reserved
0x4002_7000
SRAM1
SRAM0
Reserved
DMAC
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
Page 50 of 111
MB9A110A/MB9A110 Series
Memory Map (2)
MB9AF116MA/NA
MB9AF115MA/NA
0x2008_0000
0x2008_0000
Reserved
0x1FFF_C000
SRAM1
16Kbytes
0x2000_0000
SRAM0
16Kbytes
0x1FFF_C000
0x2000_4000
SRAM1
16Kbytes
0x2000_0000
SRAM0
16Kbytes
0x1FFF_C000
Reserved
0x0010_2000
0x0010_0000
Reserved
0x2000_4000
Reserved
0x0010_1000
0x2008_0000
Reserved
0x2000_4000
0x2000_0000
MB9AF114LA/MA/NA
MB9AF114L
0x0010_1000
0x0010_0000
SRAM0
16Kbytes
Reserved
0x0010_2000
CR trimming
Security
SRAM1
16Kbytes
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x0008_0000
Reserved
Reserved
0x0006_0000
SA10-13(64KBx4)
0x0000_0000
SA4-7(8KBx4)
0x0004_0000
SA10-11(64KBx2)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
SA8-9(48KBx2)
0x0000_0000
Flash 256Kbytes
SA8-9(48KBx2)
Flash 384Kbytes
Flash 512Kbytes
SA10-15(64KBx6)
SA4-7(8KBx4)
See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04672 Rev. *D
Page 51 of 111
MB9A110A/MB9A110 Series
Memory Map (3)
MB9AF112LA/MA/NA
MB9AF112L
MB9AF111LA/MA/NA
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x1FFF_E000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
Reserved
SA4-7(8KBx4)
0x0001_0000
SA8-9(16KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 64Kbytes
SA8-9(48KBx2)
CR trimming
Security
Reserved
Flash 128Kbytes
0x0002_0000
0x0000_0000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
See "MB9A310A/110A Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04672 Rev. *D
Page 52 of 111
MB9A110A/MB9A110 Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000H
0x4000_0FFFH
0x4000_1000H
0x4000_FFFFH
0x4001_0000H
0x4001_0FFFH
Clock/Reset Control
0x4001_1000H
0x4001_1FFFH
Hardware Watchdog timer
0x4001_2000H
0x4001_2FFFH
0x4001_3000H
0x4001_4FFFH
0x4001_5000H
0x4001_5FFFH
Dual-Timer
0x4001_6000H
0x4001_FFFFH
Reserved
0x4002_0000H
0x4002_0FFFH
Multi-function timer unit0
0x4002_1000H
0x4002_1FFFH
Multi-function timer unit1
0x4002_2000H
0x4002_3FFFH
Reserved
0x4002_4000H
0x4002_4FFFH
PPG
0x4002_5000H
0x4002_5FFFH
0x4002_6000H
0x4002_6FFFH
0x4002_7000H
0x4002_7FFFH
A/D Converter
0x4002_8000H
0x4002_DFFFH
Reserved
0x4002_E000H
0x4002_EFFFH
Built-in CR trimming
0x4002_F000H
0x4002_FFFFH
Reserved
0x4003_0000H
0x4003_0FFFH
External Interrupt
0x4003_1000H
0x4003_1FFFH
Interrupt Source Check Register
0x4003_2000H
0x4003_2FFFH
Reserved
0x4003_3000H
0x4003_3FFFH
GPIO
0x4003_4000H
0x4003_4FFFH
Reserved
0x4003_5000H
0x4003_5FFFH
Low-Voltage Detector
0x4003_6000H
0x4003_6FFFH
0x4003_7000H
0x4003_7FFFH
Reserved
0x4003_8000H
0x4003_8FFFH
Multi-function serial Interface
0x4003_9000H
0x4003_9FFFH
CRC
0x4003_A000H
0x4003_AFFFH
Watch Counter
0x4003_B000H
0x4003_EFFFH
Reserved
0x4003_F000H
0x4003_FFFFH
External Bus interface
0x4004_0000H
0x4004_FFFFH
Reserved
0x4005_0000H
0x4005_FFFFH
Reserved
0x4006_0000H
0x4006_0FFFH
0x4006_1000H
0x4006_1FFFH
0x4006_2000H
0x4006_2FFFH
Reserved
0x4006_3000H
0x4006_3FFFH
Reserved
0x4006_4000H
0x41FF_FFFFH
Reserved
Document Number: 002-04672 Rev. *D
AHB
APB0
APB1
APB2
Flash Memory I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
Quadrature Position/Revolution Counter(QPRC)
Reserved
DMAC register
AHB
Reserved
Page 53 of 111
MB9A110A/MB9A110 Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-04672 Rev. *D
Page 54 of 111
MB9A110A/MB9A110 Series
List of Pin Status
Pin status
type
Function group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX input
state
Device
internal
reset state
Run mode
or SLEEP
mode state
Timer mode or STOP
mode state
INITX=0
INITX=1
Power
supply
stable
INITX=1
-
-
-
SPL=0
Power supply stable
Power supply stable
INITX=1
SPL=1
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Main crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
A
Main crystal
oscillator output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
C
INITX input pin
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
D
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
JTAG
selected
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Setting disabled
Setting
disabled
Setting
disabled
Setting disabled
Setting
disabled
Setting
disabled
B
E
GPIO
selected
Maintain
previous state
Maintain
previous state
Maintain
previous state
Trace selected
External interrupt
enabled selected
F
GPIO
selected, or
resource other than
above selected
Document Number: 002-04672 Rev. *D
Hi-Z/ Internal
input fixed at
"0"
Trace output
Maintain
previous state
Maintain
previous state
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Page 55 of 111
MB9A110A/MB9A110 Series
Pin status
type
Function group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
Trace selected
G
H
I
J
Setting disabled
Device
internal
reset state
INITX=0
INITX=1
-
-
-
Setting
disabled
Timer mode or STOP
mode state
Power supply stable
INITX=1
SPL=0
Setting
disabled
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO selected, or
resource other than
above selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
GPIO selected,
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
NMIX selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO selected, or
resource other than
above selected
Run mode
or SLEEP
mode state
Power
supply
stable
INITX=1
Power supply stable
GPIO selected, or
resource other than
above selected
SPL=1
Trace output
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected, or
resource other than
above selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous state
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected, or
resource other than
above selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
K
L
INITX input
state
Document Number: 002-04672 Rev. *D
Page 56 of 111
MB9A110A/MB9A110 Series
Pin status
type
Function group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
Power supply stable
INITX=0
INITX=1
-
-
-
Power supply stable
INITX=1
SPL=0
SPL=1
Input enabled
Input enabled
Maintain
previous
state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Maintain
previous state/
Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous
state
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Input enabled
Input enabled
Input enabled
Input
enabled
Input enabled
Input enabled
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Hi-Z/Input
enabled
Setting disabled
Setting
disabled
Setting
disabled
Sub crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Sub crystal
oscillator output pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enabled
Hi-Z/
Internal input
fixed at "0"
GPIO pin
Hi-Z
Mode input pin
GPIO selected
P
Maintain
previous
state
Input
enabled
Timer mode or STOP mode
state
Maintain
previous state
GPIO selected
N
Run
mode or
SLEEP
mode
state
Power
supply
stable
INITX=1
Hi-Z/ Internal
input fixed at
"0"
M
O
INITX input
state
Device
internal
reset state
*1: Oscillation is stopped at sub timer mode, low-speed CR timer mode, and stop mode.
*2: Oscillation is stopped at stop mode.
Document Number: 002-04672 Rev. *D
Page 57 of 111
MB9A110A/MB9A110 Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Min
Power supply voltage*1, *2
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VCC
AVCC
AVRH
Input voltage*1
VI
Unit
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
VSS - 0.5
VCC + 0.5
(≤ 6.5 V)
V
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
Clamp maximum current
ICLAMP
-2
Clamp total maximum current
Σ[ICLAMP]
Remarks
Max
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
V
mA
*7
+20
mA
*7
10
20
39
4
12
18.5
100
50
- 10
mA
mA
mA
mA
mA
mA
mA
mA
mA
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
mA
mA
mA
mA
12mA type
P80, P81
4mA type
12mA type
mA
mA
mA
mW
°C
P80, P81
"L" level maximum output current*4
IOL
-
"L" level average output current*5
IOLAV
-
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
"H" level maximum output current*4
IOH
-
"H" level average output current*5
IOHAV
-
- 20
- 39
-4
- 12
"H" level total maximum output current
"H" level total average output current*6
Power consumption
Storage temperature
∑IOH
∑IOHAV
PD
TSTG
- 55
- 20.5
- 100
- 50
300
+ 150
5V tolerant
V
V
4mA type
*1: These parameters are based on the condition that V SS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100 ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
Document Number: 002-04672 Rev. *D
Page 58 of 111
MB9A110A/MB9A110 Series
*7:
•
•
•
•
•
See “4. List of Pin Functions” and “5. I/O Circuit Type” about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
+B input(0V to 16V)
Digital output
N-ch
Digital input
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04672 Rev. *D
Page 59 of 111
MB9A110A/MB9A110 Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
Remarks
Power supply voltage
VCC
-
2.7*2
5.5
V
Analog power supply voltage
AVCC
-
2.7
5.5
V
Analog reference voltage
AVRH
-
2.7
AVCC
V
Smoothing capacitor
LQI100
LQH080
LQD064
LQG064
VNC064
LBC112
Operating
temperature
CS
-
1
10
μF
TA
-
- 40
+ 105
°C
- 40
+ 105
°C
TA
When mounted
on four-layer
PCB
When mounted
on double-sided
single-layer PCB
- 40
+ 105
°C
ICC ≤ 35 mA
- 40
+ 85
°C
ICC > 35 mA
PQH100
AVCC = VCC
For built-in regulator*1
*1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or
built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04672 Rev. *D
Page 60 of 111
MB9A110A/MB9A110 Series
12.3 DC Characteristics
12.3.1 Current rating
(VCC = AVCC= 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
ICC
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP
mode
current
ICCS
PLL
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
SLEEP mode
CPU: 40 MHz,
Peripheral: 40 MHz,
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*5
CPU: 40 MHz,
Peripheral: 40 MHz,
Flash 3 Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
*5
Value
Typ*3
Max*4
Unit
Remarks
32
41
mA
*1
21
28
mA
*1
3.9
7.7
mA
*1
0.15
3.2
mA
*1
0.2
3.3
mA
*1
10
15
mA
*1
Peripheral: 4 MHz *2
1.2
4.4
mA
*1
Peripheral: 32 kHz
*6
0.1
3.1
mA
*1
Peripheral: 100 kHz
0.1
3.1
mA
*1
CPU/ Peripheral: 4 MHz *2
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*6
CPU/ Peripheral: 100 kHz
Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
Peripheral: 40 MHz
*5
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA =+25°C, VCC=5.5 V
*4: TA =+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-04672 Rev. *D
Page 61 of 111
MB9A110A/MB9A110 Series
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 105°C)
Parameter
Pin
name
Symbol
Main
TIMER
mode
TIMER
mode
current
ICCT
VCC
STOP
mode
current
ICCH
Value
Typ*2
Max*2
Conditions
Sub
TIMER
mode
STOP mode
TA = + 25°C,
When LVD is off
*3
TA = + 105°C,
When LVD is off
*3
TA = + 25°C,
When LVD is off
*4
TA = + 105°C,
When LVD is off
*4
TA = + 25°C,
When LVD is off
Ta = + 105°C,
When LVD is off
Unit
Remarks
2.5
3
mA
*1
-
6
mA
*1
60
230
μA
*1
-
3.1
mA
*1
35
200
μA
*1
-
3
mA
*1
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Low-voltage detection
circuit (LVD) power
supply current
Symbol
ICCLVD
Pin
name
VCC
Value
Conditions
At operation
for interrupt
Vcc = 5.5 V
Typ
4
Max
Unit
μA
7
Remarks
At not detect
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
Pin
name
VCC
Value
Conditions
At Write/Erase
Typ
11.4
Max
13.1
Unit
Remarks
mA
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Document Number: 002-04672 Rev. *D
Pin
name
Value
Conditions
Typ
Max
Unit
At 1unit operation
0.57
0.72
mA
At stop
0.06
20
μA
At 1unit operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Remarks
AVCC
AVRH
Page 62 of 111
MB9A110A/MB9A110 Series
12.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
"H" level input
voltage
(hysteresis
input)
VIHS
"L" level input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis
input pin,
MD0,1
5V tolerant
I/O pin
CMOS
hysteresis
input pin,
MD0,1
4mA type
"H" level
output voltage
VOH
12mA type
P80, P81
4mA type
"L" level
output voltage
VOL
12mA type
P80, P81
Input leak current
Pull-up resistor
value
Input capacitance
IIL
RPU
CIN
Pull-up pin
Other than
VCC, VSS,
AVCC, AVSS,
AVRH
Document Number: 002-04672 Rev. *D
Value
Conditions
Min
Typ
Max
Unit
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.4
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
μA
Vcc ≥ 4.5 V
IOH = - 4 mA
Vcc < 4.5 V
IOH = - 2 mA
Vcc ≥ 4.5 V
IOH = - 12 mA
Vcc < 4.5 V
IOH = - 8 mA
Vcc ≥ 4.5 V
IOH = - 20.5 mA
Vcc < 4.5 V
IOH = - 13.0 mA
Vcc ≥ 4.5 V
IOL = 4 mA
Vcc < 4.5 V
IOL = 2 mA
Vcc ≥ 4.5 V
IOL = 12 mA
Vcc < 4.5 V
IOL = 8 mA
Vcc ≥ 4.5 V
IOL = 18.5 mA
Vcc < 4.5 V
IOL = 10.5 mA
-
-5
-
+5
Vcc≥ 4.5 V
25
50
100
VCC<4.5 V
30
80
200
-
-
5
15
Remarks
kΩ
pF
Page 63 of 111
MB9A110A/MB9A110 Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Pin
name
Symbol
Input frequency
FCH
Input clock cycle
tCYLH
Input clock pulse width
-
Input clock rising time and
falling time
tCF
tCR
Internal operating
clock*1
frequency
Internal operating
clock*1
cycle time
X0
X1
Value
Conditions
Min
Max
Unit
VCC≥ 4.5 V
VCC<4.5 V
VCC≥ 4.5 V
VCC<4.5 V
VCC≥ 4.5 V
VCC<4.5 V
PWH/tCYLH
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external
clock
ns
When using external
clock
When using external
clock
When using external
clock
FCM
-
-
-
40
MHz
Master clock
FCC
-
-
-
40
MHz
FCP0
FCP1
-
-
-
40
40
MHz
MHz
Base clock
(HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
FCP2
-
-
-
40
MHz
APB2 bus clock*2
tCYCC
-
-
25
-
ns
tCYCP0
tCYCP1
-
-
25
25
-
ns
ns
Base clock
(HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCP2
-
-
25
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.
X0
Document Number: 002-04672 Rev. *D
Page 64 of 111
MB9A110A/MB9A110 Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
FCL
Input clock cycle
tCYLL
Input clock pulse width
Pin
name
Symbol
X0A
X1A
-
Value
Conditions
Min
Typ
Unit
Max
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL
PWL/tCYLL
45
-
55
%
When using external clock
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Frequency stability time
Symbol
FCRH
tCRWT
Value
Conditions
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA = 0°C to + 70°C
3.84
4
4.16
TA = - 40°C to + 105°C
3.8
4
4.2
TA = - 40°C to + 105°C
3
4
5
-
-
-
90
Unit
MHz
Remarks
When trimming *1
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the
High-speed CR clock as a source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRL
Document Number: 002-04672 Rev. *D
Conditions
-
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 65 of 111
MB9A110A/MB9A110 Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
PLL oscillation stabilization wait time (LOCK UP time) *1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency *2
tLOCK
fPLLI
fPLLO
FCLKPLL
Value
Min
100
4
13
200
-
Typ
-
Max
16
75
300
40
Unit
Remarks
μs
MHz
multiple
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock of the main
PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
PLL oscillation stabilization wait time (LOCK UP time) *1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency *2
tLOCK
fPLLI
fPLLO
FCLKPLL
Value
Min
100
3.8
50
190
-
Typ
4
-
Max
4.2
71
300
40
Unit
Remarks
μs
MHz
multiple
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master
clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-04672 Rev. *D
Page 66 of 111
MB9A110A/MB9A110 Series
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Pin name
INITX
Value
Conditions
-
Min
Unit
Max
500
-
Remarks
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Power supply shut down time
tOFF
Power ramp rate
dV/dt
Time until releasing Power-on reset
tPRT
Pin name
Value
Conditions
Remarks
Typ
Max
50
-
-
ms
*1
Vcc:0.2 V to 2.70 V
0.9
-
1000
mV/us
*2
-
0.446
-
0.744
ms
VCC
Unit
Min
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6. Low-voltage detection characteristics”
Document Number: 002-04672 Rev. *D
Page 67 of 111
MB9A110A/MB9A110 Series
12.4.8 External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Output frequency
Pin name
tCYCLE
MCLKOUT
Minimum clock cycle time
-
Value
Conditions
Min
Unit
Max
VCC ≥ 4.5 V
-
40
MHz
VCC < 4.5 V
-
32
MHz
VCC ≥ 4.5 V
25
-
ns
VCC < 4.5 V
31.25
-
ns
Note:
−
The external bus clock output is a divided clock of HCLK. For more information about setting of clock divider,
see "Chapter 12: External Bus Interface" in "FM3 Family Peripheral Manual"
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
VIH
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
Remarks
Signal input characteristics
VIL
Signal output characteristics
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-04672 Rev. *D
Page 68 of 111
MB9A110A/MB9A110 Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
MOEX
Min pulse width
MCSX ↓→Address output
delay time
MOEX ↑→
Address hold time
MCSX ↓→
MOEX ↓ delay time
MOEX ↑→
MCSX ↑ time
MCSX ↓→
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑→
Data hold time
MWEX
Min pulse width
MWEX ↑→ Address output
delay time
MCSX ↓→
MWEX ↓ delay time
MWEX ↑→
MCSX ↑ delay time
MCSX ↓ →
MDQM ↓ delay time
MCSX ↓ →
Data output time
MWEX ↑→
Data hold time
Symbol
tOEW
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
Pin name
MOEX
MCSX[7:0]
MAD[24:0]
MOEX
MAD[24:0]
MOEX
MCSX[7:0]
MCSX
MDQM[1:0]
MOEX
MADATA[15:0]
MOEX
MADATA[15:0]
tWEW
MWEX
tWEH - AX
MWEX
MAD[24:0]
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MWEX
MCSX[7:0]
MCSX
MDQM[1:0]
MCSX
MADATA[15:0]
MWEX
MADATA[15:0]
Value
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Min
Max
Unit
MCLK×n-3
-
-9
-12
MCLK×m-9
MCLK×m-12
20
38
+9
+ 12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m-9
MCLK×m-12
0
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
0
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-04672 Rev. *D
Page 69 of 111
MB9A110A/MB9A110 Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
tDS-OE
MADATA[15:0]
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
Document Number: 002-04672 Rev. *D
Page 70 of 111
MB9A110A/MB9A110 Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Address delay time
Symbol
tCSL
MCLK
MCSX[7:0]
tCSH
tREL
MCLK
MOEX
MOEX delay time
tREH
MCLK
MADATA[15:0]
MCLK
MADATA[15:0]
tDS
tDH
tWEL
MCLK
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
MCLK ↑→
Data output time
MCLK ↑→
Data output time
tDQML
tDQMH
MCLK
MDQM[1:0]
MCLK,
MADATA[15:0]
MCLK
MADATA[15:0]
tODS
tOD
Value
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC< 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
MCLK
MAD[24:0]
tAV
MCSX delay time
Data set up→
MCLK ↑time
MCLK ↑→
Data hold time
Pin name
Min
Max
9
12
9
12
9
12
9
12
9
12
1
1
1
1
1
Unit
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
1
1
1
1
MCLK+1
1
1
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance CL = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 002-04672 Rev. *D
Page 71 of 111
MB9A110A/MB9A110 Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Multiplexed
Address delay time
tALE-CHMADV
Multiplexed
Address hold time
tCHMADH
Pin name
VCC ≥ 4.5 V
MALE
MADATA[15:0]
Value
Conditions
Min
0
VCC < 4.5 V
Unit
Max
10
ns
20
VCC ≥ 4.5 V
MCLK×n+0
MCLK×n+10
VCC < 4.5 V
MCLK×n+0
MCLK×n+20
ns
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04672 Rev. *D
Page 72 of 111
MB9A110A/MB9A110 Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK ↑→
Multiplexed
Address delay time
tCHMADV
MCLK ↑→
Multiplexed
Data output time
tCHMADX
Pin name
MCLK
ALE
VCC ≥ 4.5 V
VCC < 4.5 V
VCC≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK
MADATA[15:0]
Value
Conditions
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04672 Rev. *D
Page 73 of 111
MB9A110A/MB9A110 Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
MCLK ↑
MRDY input
setup time
tRDYI
Pin name
MCLK
MRDY
Value
Conditions
Min
VCC ≥ 4.5 V
19
VCC < 4.5 V
37
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04672 Rev. *D
Page 74 of 111
MB9A110A/MB9A110 Series
12.4.9 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
TIOAn/TIOBn
(when using as
ECK,TIN)
tTIWH
tTIWL
Value
Conditions
-
tTIWH
Min
Unit
Max
2tCYCP
-
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
TIOAn/TIOBn
(when using as
TGIN)
Conditions
-
tTRGH
TGIN
VIHS
Value
Min
2tCYCP
Max
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “8. Block Diagram” in this datasheet.
Document Number: 002-04672 Rev. *D
Page 75 of 111
MB9A110A/MB9A110 Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Pin
name
Symbol
Baud rate
-
-
Serial clock cycle time
tSCYC
SCK ↓→ SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓→ SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑→ SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
-
Master mode
Slave mode
VCC≥ 4.5 V
Min
Max
VCC<4.5 V
Min
Max
Conditions
Unit
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 76 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
VIL
tSHSL
VIL
SIN
VIH
tR
tSLOVE
SOT
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-04672 Rev. *D
Page 77 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↑→ SOT delay time
tSHOVI
SCKx
SOTx
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↑→ SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
-
Master mode
Slave mode
VCC≥ 4.5 V
Min
Max
VCC<4.5 V
Min
Max
Conditions
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 78 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-04672 Rev. *D
Page 79 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↑→ SOT delay time
tSHOVI
SCKx
SOTx
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
-
Master mode
Slave mode
VCC≥ 4.5 V
Min
Max
VCC<4.5 V
Min
Max
Conditions
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 80 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-04672 Rev. *D
Page 81 of 111
MB9A110A/MB9A110 Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Baud rate
Serial clock cycle time
tSCYC
SCKx
SCK ↓→ SOT delay time
tSLOVI
SCKx
SOTx
SIN → SCK ↑ setup time
tIVSHI
SCK ↑→SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓
tSLOVE
→ SOT delay time
SIN → SCK ↑ setup time
tIVSHE
SCK ↑→ SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
-
Master mode
Slave mode
VCC ≥ 4.5 V
Min
Max
VCC<4.5 V
Min
Max
Conditions
Unit
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL= 30 pF.
Document Number: 002-04672 Rev. *D
Page 82 of 111
MB9A110A/MB9A110 Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tSHSL
tR
SCK
tSLSH
VIH
VIH
VIL
tF
VIL
VIL
VIH
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS= 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
Conditions
VIL
Document Number: 002-04672 Rev. *D
tSHSL
VIH
Max
tCYCP + 10
tCYCP + 10
-
CL = 30 pF
tR
SCK
Min
5
5
VIL
Remarks
ns
ns
ns
ns
tF
tSLSH
VIH
Unit
VIL
VIH
Page 83 of 111
MB9A110A/MB9A110 Series
12.4.11 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Value
Conditions
Min
Max
Unit
ADTG
Input pulse width
tINH
tINL
FRCKx
ICxx
DTTIxX
INTxx,
NMIX
Remarks
A/D converter trigger input
-
2tCYCP*
-
ns
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP*
-
ns
2tCYCP + 100*
-
ns
500
-
ns
Free-run timer input clock
Input capture
Wave form generator
External interrupt
NMI
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see “8. Block
Diagram” in this datasheet.
Document Number: 002-04672 Rev. *D
Page 84 of 111
MB9A110A/MB9A110 Series
12.4.12 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
tAHL
tALL
tBHL
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC = "0"
QCR:CGSC = "0"
tZABE
QCR:CGSC = "1"
tABEZ
QCR:CGSC = "1"
Unit
Max
2tCYCP *
-
ns
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this
datasheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-04672 Rev. *D
tBLL
Page 85 of 111
MB9A110A/MB9A110 Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04672 Rev. *D
Page 86 of 111
MB9A110A/MB9A110 Series
12.4.13 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
SCL clock frequency
(Repeated) START condition hold time
SDA ↓→ SCL ↓
SCL clock "L" width
SCL clock "H" width
(Repeated) START condition setup time
SCL ↑→ SDA ↓
Data hold time
SCL ↓→ SDA ↓↑
Data setup time
SDA ↓↑→ SCL ↑
STOP condition setup time
SCL ↑→ SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Noise filter
Symbol
Standard-mode
Min
Max
Conditions
Fast-mode
Min
Max
Unit
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
0
3.45
0
0.9 *3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
tHDDAT
tSP
CL = 30 pF,
R = (Vp/IOL) *1
-
*2
Remarks
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "8. Block Diagram" in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-04672 Rev. *D
Page 87 of 111
MB9A110A/MB9A110 Series
12.4.14 ETM timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Data hold
Symbol
tETMH
TRACECLK
frequency
Pin name
TRACECLK
TRACED[3:0]
Value
Min
Max
Conditions
Unit
VCC≥ 4.5 V
2
9
VCC< 4.5 V
2
15
VCC≥ 4.5 V
-
40
MHz
VCC < 4.5 V
-
32
MHz
VCC≥ 4.5 V
25
-
ns
VCC < 4.5 V
31.25
-
ns
Remarks
ns
1/tTRACE
TRACECLK
TRACECLK
Clock cycle time
tTRACE
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04672 Rev. *D
Page 88 of 111
MB9A110A/MB9A110 Series
12.4.15 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
TMS, TDI setup time
tJTAGS
TCK
TMS,TDI
VCC≥ 4.5 V
TMS, TDI hold time
tJTAGH
TCK
TMS,TDI
VCC≥ 4.5 V
tJTAGD
TCK
TDO
TDO delay time
Min
Value
Max
Unit
15
-
ns
15
-
ns
VCC≥ 4.5 V
-
25
VCC < 4.5 V
-
45
VCC < 4.5 V
VCC < 4.5 V
Remarks
ns
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-04672 Rev. *D
Page 89 of 111
MB9A110A/MB9A110 Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Pin
name
Symbol
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
VZT
VFST
ANxx
ANxx
Conversion time
-
-
Sampling time
Ts
-
Compare clock cycle*3
Tcck
State transition time to
operation permission
Value
Typ
Min
Max
Unit
1.0*1
1.2*1
± 1.7
± 1.7
±8
AVRH±8
-
12
± 4.5
± 2.5
± 15
AVRH±15
-
*2
-
-
*2
-
-
-
50
-
2000
ns
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistor
RAIN
-
-
-
Interchannel disparity
Analog port input leak current
-
ANxx
-
-
3.8
4
5
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
-
AVCC
V
2
bit
LSB
LSB
mV
mV
μs
ns
kΩ
Remarks
AVRH = 2.7 V to 5.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
LSB
μA
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns
AVCC< 4.5 V, HCLK=40 MHz sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual
Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1)
*3: The compare time (Tc) is the value of (Equation 2)
Document Number: 002-04672 Rev. *D
Page 90 of 111
MB9A110A/MB9A110 Series
Analog
signal source
ANxx
Analog input pin
Rext
Comparator
RAIN
CAIN
(Equation 1) Ts≥ (RAIN + Rext) × CAIN × 9
Ts:
Sampling time
RAIN:
Input resistor of A/D = 2 kΩ
4.5 V ≤ AVCC≤ 5.5 V
Input resistor of A/D = 3.8 kΩ
2.7 V ≤ AVCC< 4.5 V
CAIN:
Input capacity of A/D = 12.9 pF
2.7 V ≤ AVCC≤ 5.5 V
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-04672 Rev. *D
Page 91 of 111
MB9A110A/MB9A110 Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Actual conversion
characteristics
Ideal characteristics
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
V(N+1)T
0x(N-1)
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04672 Rev. *D
Page 92 of 111
MB9A110A/MB9A110 Series
12.6 Low-voltage detection characteristics
Low-voltage detection reset
(TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Typ
Min
Max
Unit
Remarks
Detected voltage
VDL
-
2.25
2.45
2.65
V
When voltage drops
Released voltage
VDH
-
2.30
2.50
2.70
V
When voltage rises
Interrupt of low-voltage detection
(TA = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
tLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Value
Typ
Min
Max
Unit
Remarks
2.58
2.8
3.02
V
When voltage drops
2.67
2.9
3.13
V
When voltage rises
2.76
3.0
3.24
V
When voltage drops
2.85
3.1
3.34
V
When voltage rises
2.94
3.2
3.45
V
When voltage drops
3.04
3.3
3.56
V
When voltage rises
3.31
3.6
3.88
V
When voltage drops
3.40
3.7
3.99
V
When voltage rises
3.40
3.7
3.99
V
When voltage drops
3.50
3.8
4.10
V
When voltage rises
3.68
4.0
4.32
V
When voltage drops
3.77
4.1
4.42
V
When voltage rises
3.77
4.1
4.42
V
When voltage drops
3.86
4.2
4.53
V
When voltage rises
3.86
4.2
4.53
V
When voltage drops
3.96
4.3
4.64
V
When voltage rises
-
-
2240 × tCYCP *
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04672 Rev. *D
Page 93 of 111
MB9A110A/MB9A110 Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Sector erase
time
Unit
Max*
Large Sector
0.7
3.7
Small Sector
0.3
1.1
12
64K/128K/256KByte
384K/512KByte
Half word (16-bit)
write time
Chip erase time
Typ*
Remarks
s
Includes write time prior to internal erase
384
μs
Not including system-level overhead time
5.2
23.6
s
8
38.4
s
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Erase/Write cycles and data hold time
Erase/write cycles
(cycle)
1,000
20*
10,000
10*
100,000
5*
Data hold time
(year)
Remarks
*: At average + 85°C
Document Number: 002-04672 Rev. *D
Page 94 of 111
MB9A110A/MB9A110 Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Value
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Typ
Unit
Max*
tCYCC
ns
40
80
μs
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-04672 Rev. *D
Page 95 of 111
MB9A110A/MB9A110 Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual
about the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in “FM3 Family Peripheral Manual".
Document Number: 002-04672 Rev. *D
Page 96 of 111
MB9A110A/MB9A110 Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Typ
Unit
Max*
SLEEP mode
308
444
μs
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
308
444
μs
428
684
μs
Sub TIMER mode
428
684
μs
STOP mode
428
684
μs
Low-speed CR TIMER mode
Trcnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-04672 Rev. *D
Start
Page 97 of 111
MB9A110A/MB9A110 Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See “Chapter 6: Low Power Consumption Mode” and “Operations of Standby Modes” in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See “Chapter 6: Low Power Consumption Mode” in “FM3 Family Peripheral Manual”.
−
The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.7. Power-on Reset Timing in
12.4. AC Characteristics in 12. Electrical Characteristics” for the detail on the time during the power-on reset/low -voltage
detection reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04672 Rev. *D
Page 98 of 111
MB9A110A/MB9A110 Series
13. Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9AF111LAPMC1-G-JNE2
64 Kbyte
16 Kbyte
MB9AF112LAPMC1-G-JNE2
128 Kbyte
16 Kbyte
MB9AF114LAPMC1-G-JNE2
256 Kbyte
32 Kbyte
MB9AF111LAPMC-G-JNE2
64 Kbyte
16 Kbyte
MB9AF112LAPMC-G-JNE2
128 Kbyte
16 Kbyte
MB9AF114LAPMC-G-JNE2
256 Kbyte
32 Kbyte
MB9AF112LPMC-G-MJE1
128 Kbyte
16 Kbyte
MB9AF114LPMC-G-MJE1
256 Kbyte
32 Kbyte
MB9AF111LAQN-G-AVE2
64 Kbyte
16 Kbyte
MB9AF112LAQN-G-AVE2
128 Kbyte
16 Kbyte
MB9AF114LAQN-G-AVE2
256 Kbyte
32 Kbyte
MB9AF111MAPMC-G-JNE2
64 Kbyte
16 Kbyte
MB9AF112MAPMC-G-JNE2
128 Kbyte
16 Kbyte
MB9AF114MAPMC-G-JNE2
256 Kbyte
32 Kbyte
MB9AF115MAPMC-G-JNE2
384 Kbyte
32 Kbyte
MB9AF116MAPMC-G-JNE2
512 Kbyte
32 Kbyte
MB9AF111NAPMC-G-JNE2
64 Kbyte
16 Kbyte
MB9AF112NAPMC-G-JNE2
128 Kbyte
16 Kbyte
MB9AF114NAPMC-G-JNE2
256 Kbyte
32 Kbyte
MB9AF115NAPMC-G-JNE2
384 Kbyte
32 Kbyte
MB9AF116NAPMC-G-JNE2
512 Kbyte
32 Kbyte
MB9AF111NAPF-G-JNE1
64 Kbyte
16 Kbyte
MB9AF112NAPF-G-JNE1
128 Kbyte
16 Kbyte
MB9AF114NAPF-G-JNE1
256 Kbyte
32 Kbyte
MB9AF115NAPF-G-JNE1
384 Kbyte
32 Kbyte
MB9AF116NAPF-G-JNE1
512 Kbyte
32 Kbyte
MB9AF111NABGL-GE1
64 Kbyte
16 Kbyte
MB9AF112NABGL-GE1
128 Kbyte
16 Kbyte
MB9AF114NABGL-GE1
256 Kbyte
32 Kbyte
Document Number: 002-04672 Rev. *D
Package
Packing
Plastic LQFP
(0.5 mm pitch), 64-pin
(LQD064)
Plastic LQFP
(0.65 mm pitch), 64-pin
(LQG064)
Plastic QFN
(0.5 mm pitch), 64-pin
(VNC064)
Plastic LQFP
(0.5 mm pitch), 80-pin
(LQH080)
Tray
Plastic LQFP
(0.5 mm pitch), 100-pin
(LQI100)
Plastic QFP
(0.65 mm pitch), 100-pin
(PQH100)
Plastic PFBGA
(0.8 mm pitch), 112-pin
(LBC112)
Page 99 of 111
MB9A110A/MB9A110 Series
14. Package Dimensions
Package Type
LQFP 100
Package Code
LQI100
D
D1
75
4
D
5 7
51
D1
51
50
76
4
5 7
75
50
76
E1 E
5 4
7
E1 E
5 4
7
3
6
26
100
1
26
25
1
25
2 5 7
e
100
BOTTOM VIEW
0.1 0 C A-B D
3
0.2 0 C A-B D
b
TOP VIEW
8
0.0 8
C A-B
D
2
A
9
A
SEAT ING
PLA NE
A'
0.25
L1
0.0 8 C
c
A1
b
10
SECTION A-A'
L
SIDE VIEW
SYMBOL
DETAIL A
DIMENSIONS
MIN.
NOM. MAX.
1.70
A
A1
0.05
b
0.15
0.15
0.27
c
0.09
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.50 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE.
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
Document Number: 002-04672 Rev. *D
002-11500 *A
Page 100 of 111
MB9A110A/MB9A110 Series
Package Type
QFP 100
Package Code
PQH100
D
D1
4
5 7
80
51
81
51
50
80
50
81
31
100
E1 E
5
7
6
3
4
31
100
1
30
e
3
0.40 C A-B D
30
2 5 7
1
0.20 C A-B D
b
0.13
C A-B
D
BOTTOM VIEW
8
TOP VIEW
2
9
A
A'
SEATING
PLANE
L2
c
10
b
0.10 C
SECTION A-A'
DETAIL A
SIDE VIEW
SYMBOL
DIMENSIONS
MIN.
NOM. MAX.
A1
0.05
0.45
b
0.27
c
0.11
A
3.35
0.32
0.23
D
23.90 BSC
D1
20.00 BSC
e
0.65 BSC
E
17.90 BSC
E1
14.00 BSC
0
L
0.37
0.73
8
0.88
L1
1.95 REF
L2
0.25 BSC
1.03
002-15156 **
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
Document Number: 002-04672 Rev. *D
Page 101 of 111
MB9A110A/MB9A110 Series
Package Type
LQFP 80
Package Code
LQH080
D
D1
60
4
5 7
41
41
40
61
60
40
61
21
80
5
7
E1
E
4
3
6
80
21
1
20
D
e
20
2 5 7
0.10 C A-B D
3
b
0.08
C A-B
1
BOTTOM VIEW
D
0.20 C A-B D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SYMBOL
SEATING
PLANE
9
L1
L
0.25
A1
10
c
b
SECTION A-A'
DIMENSIONS
MIN. NOM. MAX.
A
1. 70
A1
0.05
0.15
b
0.15
0.27
c
0.09
0.20
D
14.00 BSC.
D1
12.00 BSC.
e
0.50 BSC
E
14.00 BSC.
E1
12.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
002-11501 **
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
Document Number: 002-04672 Rev. *D
Page 102 of 111
MB9A110A/MB9A110 Series
Package Type
LQFP 64
Package Code
LQD064
4
D
D1
48
5 7
33
33
32
49
48
32
49
17
64
5
7
E1
E
4
3
6
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
A
2
9
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
c
b
SECTION A-A'
10
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1. 70
0.00
0.20
b
0.15
0.2
c
0.09
0.20
D
12.00 BSC.
D1
10.00 BSC.
e
0.50 BSC
E
12.00 BSC.
E1
10.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
002-11499 **
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-04672 Rev. *D
Page 103 of 111
MB9A110A/MB9A110 Series
Package Type
LQFP 64
Package Code
LQG064
D
D1
48
4
5 7
33
33
32
49
48
32
49
17
64
E1 E
5
7
4
3
17
64
1
16
e
1
16
2 5 7
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.13
C A-B
D
8
TOP VIEW
2
A
A
A'
0.10 C
SEATI NG
PLA NE
0.2 5
L1
L
9
A1
10
c
b
SEC TION A -A'
SIDE VIEW
SYMBOL
DIMENSION
MIN.
NOM. MAX.
1.70
A
A1
0.00
0.20
b
0.27
c
0.09
0.32
0.37
0.20
D
14.00 BSC
D1
12.00 BSC
e
0.65 BSC
E
14.00 BSC
E1
12.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-04672 Rev. *D
Page 104 of 111
MB9A110A/MB9A110 Series
Package Type
PFBGA 112
Package Code
LBC112
A
0.20 C
11
2X
10
9
6
8
7
6
5
4
3
2
1
L
PIN A1
CORNER
INDEX MARK
K
J
H
G
F
E
D
7
C
B
A
6
B
0.20 C
TOP VIEW
2X
BOTTOM VIEW
DETAIL A
5
112x φ b
C
0.10 C
DETAIL A
0.08
C A B
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
2. SOLDER BALL POSITION DESIGNATIO
N PER JEP95, SECTION 3, SPP-020.
A
-
-
1.45
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.25
0.35
0.45
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
10.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
E
10.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
D1
8.00 BSC
E1
8.00 BSC
MD
11
N
112
0.35
0.45
eD
0.80 BSC
eE
0.80 BSC
SD
0.00
SE
PLANE PARALLEL TO DATUM C.
11
ME
b
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
0.00
6. "SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.55
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
002-13225 **
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
Document Number: 002-04672 Rev. *D
Page 105 of 111
MB9A110A/MB9A110 Series
Package Type
QFN 64
Package Code
VNC064
0.10
D
0.10 C
2X
D2
A
48
33
33
32
49
C A B
48
32
49
0.10
C A B
5
(ND-1)
E
e
17
64
1
INDEXMARK
8
E2
16
9
B
e
L
0.10 C
TOP VIEW
64
17
16
BOTTOM VIEW
2X
b
1
4
0.10
0.05
C A B
C
0.10 C
A
0.05 C
SEATINGPLANE
C
A1
SIDE VIEW
DIMENSIONS
NOTES:
SYMBOL
MIN. NOM. MAX.
A
A1
0.90
0.00
0.05
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4
D
9.00 BSC
E
9.00 BSC
b
0.20 0.25 0.30
D2
6.00 BSC
E2
6.00 BSC
6.
7.
e
0.50 BSC
8
R
0.20 REF
L
0.35
0.40 0.45
N
64
ND
16
5
9
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
002-13234 **
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
Document Number: 002-04672 Rev. *D
Page 106 of 111
MB9A110A/MB9A110 Series
15. Errata
This chapter describes the errata for MB9A110 product family. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
MB9AF111LPMC1-G-JNE2, MB9AF112LPMC1-G-JNE2, MB9AF114LPMC1-G-JNE2,
MB9AF111LPMC-G-JNE2, MB9AF112LPMC-G-JNE2, MB9AF114LPMC-G-JNE2,
MB9AF112LPMC-G-MJE1, MB9AF114LAPMC-G-JNE2,
MB9AF111LQN-G-AVE2, MB9AF112LQN-G-AVE2, MB9AF114LQN-G-AVE2,
MB9AF111MPMC-G-JNE2, MB9AF112MPMC-G-JNE2, MB9AF114MPMC-G-JNE2,
MB9AF115MPMC-G-JNE2, MB9AF116MPMC-G-JNE2,
MB9AF111NPMC-G-JNE2, MB9AF112NPMC-G-JNE2, MB9AF114NPMC-G-JNE2,
MB9AF115NPMC-G-JNE2, MB9AF116NPMC-G-JNE2,
MB9AF111NPF-G-JNE1, MB9AF112NPF-G-JNE1, MB9AF114NPF-G-JNE1,
MB9AF115NPF-G-JNE1, MB9AF116NPF-G-JNE1,
MB9AF111NBGL-GE1, MB9AF112NBGL-GE1, MB9AF114NBGL-GE1
15.2 Qualification Status
Product Status: In Production − Qual.
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
Watch Counter issue
Refer to 15.1
Rev. initial rev.
Fixed in Rev. A
Watch Counter issue
PROBLEM DEFINITION
The underflow interruption does not occur.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
The condition is when underflow interruption occurs.
SCOPE OF IMPACT
The underflow interruption does not occur as specified.
WORKAROUND
This error cannot be avoided by any software, except not using Watch Counter interrupt.
FIX STATUS
This issue was fixed in Rev. A.
Document Number: 002-04672 Rev. *D
Page 107 of 111
MB9A110A/MB9A110 Series
16. Major Changes
Spansion Publication Number: DS706-00011
Page
Section
Revision 1.0
Revision 2.0
-
8
34 to 37
-
PRODUCT LINEUP
Function
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
External Interrupts
SIGNAL DESCRIPTION
Multi-function Serial (ch.0 to ch.7)
I/O CIRCUIT TYPE
42, 43
51
54
69
71
72
79
88
HANDLING DEVICES
Power supply pins
MEMORY SIZE
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Main Clock Input Characteristics
(4-2) Operating Conditions of Main PLL
(7) External Bus Timing
External bus clock output Characteristics
(8) Base Timer Input Timing
Trigger input timing
(10) External input timing
12-bit A/D Converter
Electrical characteristics for the A/D converter
94
Revision 2.1
Revision 3.0
FEATURES
3
External Bus Interface
Document Number: 002-04672 Rev. *D
Change Results
Initial release
Revised series name and part number:
MB9A110 Series→MB9A110A Series
MB9AF111L → MB9AF111LA
MB9AF112L → MB9AF112LA
MB9AF114L → MB9AF114LA
MB9AF111M → MB9AF111MA
MB9AF112M → MB9AF112MA
MB9AF114M → MB9AF114MA
MB9AF115M → MB9AF115MA
MB9AF116M → MB9AF116MA
MB9AF111N → MB9AF111NA
MB9AF112N → MB9AF112NA
MB9AF114N → MB9AF114NA
MB9AF115N → MB9AF115NA
MB9AF116N → MB9AF116NA
Added the package.
LCC-64P-M24
Added the following description.
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Corrected the following description.
7pins (Max) → 8pins (Max)
Corrected the description for function.
Added "LIN pin"
Deleted "UART pin"
Corrected the following schematic for "TypeB".
CMOS level hysteresis input → Digital input
Corrected the following schematic for "TypeC".
Control Pin → Digital output
Corrected the description.
Added "MEMORY SIZE".
Added the items FCM to the Internal operating clock frequency.
Added the description.
Added the Note.
Corrected the footnote.
Corrected the value of "Full-scale transition voltage".
Min: -20 → AVRH-20
Max: +20 → AVRH+20
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Corrected the value of "Reference voltage".
Min: AVSS → 2.7
Company name and layout design change
Added the description of Maximum area size
Page 108 of 111
MB9A110A/MB9A110 Series
Page
9
44, 46
44, 45
51
Section
53
PACKAGES
I/O CIRCUIT TYPE
I/O CIRCUIT TYPE
HANDLING DEVICES
HANDLING DEVICES
Crystal oscillator circuit
HANDLING DEVICES
C Pin
BLOCK DIAGRAM
54
MEMORY SIZE
51
52
55
56, 57
MEMORY MAP
Memory map(1)
MEMORY MAP
Memory map(2)(3)
64, 65
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
66
ELECTRICAL CHARACTERISTICS
2. Recommended Operation Conditions
67, 68
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current rating
71
72
73
75-77
82-89
96
101
105
106
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1)(4-2) Operating Conditions of Main PLL
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(6) Power-on Reset Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) External Bus Timing
ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(8) CSIO/UART Timing
ELECTRICAL CHARACTERISTICS
5. 12bit A/D Converter
ELECTRICAL CHARACTERISTICS
9. Return Time from Low-Power Consumption
Mode
ORDERING INFORMATION
PACKAGE DIMENSIONS
Change Results
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Added the description of I2C to the type of E, F and I
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
Changed to the following description
See "Memory size" in "PRODUCT LINEUP" to confirm the memory size.
Modified the area of "External Device Area"
Added the summary of Flash memory sector and the note
Added the Clamp maximum current
Added the output current of P80 and P81
Added about +B input
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current
Added Frequency stability time at Built-in high-speed CR
Added Main PLL clock frequency
Added the figure of Main PLL connection
Added Time until releasing Power-on reset
Changed the figure of timing
Modified Data output time
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero
transition voltage and Full-scale transition voltage
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Change to full part number
Deleted FPT-64P-M24, FPT-64P-M23, FPT-80P-M21, FPT-100P-M20
Note: Please see “Document History” about later revised information.
Document Number: 002-04672 Rev. *D
Page 109 of 111
MB9A110A/MB9A110 Series
Document History
Document Title: MB9A110A/MB9A110 Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-04672
Orig. of
Submission
Change
Date
–
AKIH
12/16/2014
5198491
AKIH
Revision
ECN
**
*A
Description of Change
Migrated to Cypress and assigned document number 002-04672.
No change to document contents or format.
04/07/2016
Updated to Cypress format.
Added series “MB9A110”. (Page1)
Changed package code as the following in 2 Packages (Page 7), 3 Pin Assignment
(Page 8 to 12), 12.2 Recommended Operating Conditions (Page 60), 13 Ordering
Information (Page 99) and 14 Package Dimensions (Page 100 to 106).
“FTP-64P-M38” to LQD064, “FTP-64P-M39” to LQG064,
“LCC-64P-M24” to “VNC064”, FPT-80P-M37” to “LQH080”,
“FPT-100P-M23” to “LQI100”, “FTP-100P-M06” to “PQH100”,
*B
5316949
MMIW
06/21/2016
“BGA-112P-M04” to “LBC112”
Changed “J-TAG” to” JTAG” in 4 List of Pin Functions (Page 27).
Added note 4 List of Pin Functions (Page 38).
Changed “Ta” to “TA” in 12.2 Recommended Operating Conditions (Page 60).
Added Product number “MB9AF112L” and “MB9AF114L” in Features (Page1), in 1
Product Lineup (Page6), 2 Packages (Page7) and 10 Memory Map (Page51 to 52).
Added Part number “MB9AF112LPMC-G-MJE1” and “MB9AF114LPMC-G-MJE1” in
13 Ordering Information (Page 99).
Updated “12.4.7 Power-on Reset Timing”(page 67)
Updated “14. Package Dimensions”(page 100-106)
Added “15. Errata”(page 107)
*C
5490454
YSKA
03/09/2017
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 90)
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”(Page 76, 78, 80, 82)
*D
5768637
YSAT
Document Number: 002-04672 Rev. *D
06/12/2017
Adapted new cypress logo
Page 110 of 111
MB9A110A/MB9A110 Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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Document Number: 002-04672 Rev. *D
June 12, 2017
Page 111 of 111