TI1 BQ24076RGTT 1.5-a high battery voltage li-ion battery chargers with power-path management ic Datasheet

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bq24076, bq24078
SLUSCM1 – OCTOBER 2017
bq2407x 1.5-A High Battery Voltage Li-Ion Battery Chargers
with Power-Path Management IC
1 Features
3 Description
•
The bq2407x is a family of integrated Li-Ion battery
linear chargers with system power path management
functionality targeted at space-constrained portable
applications. The devices operate from either a USB
port or an AC adapter and support charge currents up
to 1.5 A. The input voltage range with input
overvoltage
protection
supports
unregulated
adapters. The USB input current limit accuracy and
start up sequence allow the bq2407x to meet USB-IF
inrush current specifications. Additionally, the input
dynamic power management (VIN-DPM) prevents
system crashes because of incorrectly configured
USB sources and maximizes the power available
from the adapter.
1
•
•
•
•
•
•
•
•
•
•
•
•
Fully Compliant USB Charger
– Selectable 100-mA and 500-mA Maximum
Input Current
– 100-mA Maximum Current Limit Ensures
Compliance to USB-IF Standard
– Input-Based Dynamic Power Management
(VIN-DPM) for Protection Against Poor USB
Sources
28-V Input Rating with Overvoltage Protection
Integrated Dynamic Power Path Management
(DPPM) Function Simultaneously and
Independently Powers the System and Charges
the Battery
Supports up to 1.5-A Charge Current with Current
Monitoring Output (ISET)
Programmable Input Current Limit up to 1.5 A for
Wall Adapters
System Output Tracks Battery Voltage
Battery Disconnect Function with SYSOFF Input
Programmable Pre-Charge and Fast-Charge
Safety Timers
Reverse Current, Short-Circuit, and Thermal
Protection
NTC Thermistor Input
Proprietary Start-up Sequence Limits Inrush
Current
Battery Charge Voltage, VBAT:
– bq24076 - 4.4 V (typ)
– bq24078 - 4.35 V (typ)
Status Indication – Charging/Done, Power Good
The bq2407x features dynamic power path
management (DPPM) that powers the system while
simultaneously and independently charging the
battery. The DPPM circuit reduces the charge current
when the input current limit causes the system output
to fall to the DPPM threshold; thus, supplying the
system load at all times while monitoring the charge
current separately. This feature reduces the number
of charge and discharge cycles on the battery, allows
for proper charge termination and enables the system
to run with a defective or absent battery pack.
Device Information(1)
PART NUMBER
PACKAGE
bq24076
BODY SIZE (NOM)
VQFN (16)
bq24078
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
1kW
1kW
7
9
CHG
IN
IN
13
OUT
10
11
EN 2
5
BAT
2
3
1mF
SYSTEM
4.7mF
SYSOFF
4.7mF
12
ISET
6
TS
1
TEMP
16
ILM
PACK+
EN1
15
TMR
System
ON/OFF
Control
bq24076
bq24078
VSS
CE
8
4
Smart Phones
Portable Media Players
Portable Navigation Devices
Low-Power Handheld Devices
Portable Gaming
Headsets
Wearables
Home Automation
Portable Medical
14
•
•
•
•
•
•
•
•
•
PGOOD
2 Applications
1.18kW
1.13kW
PACK-
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24076, bq24078
SLUSCM1 – OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
8.7
5
5
5
6
6
6
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Ratings ...................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
9.4 Device Functional Modes........................................ 24
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ................................................ 26
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 32
12.3 Thermal Considerations ........................................ 33
13 Device and Documentation Support ................. 34
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
34
14 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
2
DATE
REVISION
NOTES
October 2017
*
Initial release.
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5 Description (continued)
Additionally, the regulated system input enables instant system turn-on when plugged in even with a totally
discharged battery. The power-path management architecture also lets the battery supplement the system
current requirements when the adapter cannot deliver the peak system currents, thus enabling the use of a
smaller adapter.
The battery is charged in three phases: conditioning, constant current, and constant voltage. In all charge
phases, an internal control loop monitors the IC junction temperature and reduces the charge current if the
internal temperature threshold is exceeded. The charger power stage and charge current sense functions are
fully integrated. The charger function has high accuracy current and voltage regulation loops, charge status
display, and charge termination. The input current limit and charge current are programmable using external
resistors.
6 Device Comparison Table
VOVP
VBAT(REG)
VOUT(REG)
VDPPM
OPTIONAL
FUNCTION
bq24072
6.6 V
4.2 V
VBAT + 225 mV
VO(REG) – 100 mV
TD
bq24073
6.6 V
4.2 V
4.4 V
VO(REG) – 100 mV
TD
bq24074
10.5 V
4.2 V
4.4 V
VO(REG) – 100 mV
ITERM
bq24075
6.6 V
4.2 V
5.5 V
4.3 V
SYSOFF
bq24076
6.6 V
4.4 V
VBAT + 210mV
VBAT +100 mV
SYSOFF
bq24078
6.6 V
4.35 V
VBAT + 210mV
VBAT +100 mV
SYSOFF
bq24079
6.6 V
4.1 V
5.5 V
4.3 V
SYSOFF
PART NUMBER (1)
(1)
(2)
(2)
For all available packages, see the orderable addendum at the end of the data sheet
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
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7 Pin Configuration and Functions
ISET
SYSOFF
TMR
IN
15
14
13
8
4
VSS
CE
Pad
7
3
PGOOD
BAT
Thermal
6
2
EN1
BAT
5
1
EN2
TS
16
RGT Package
16-Pin VQFN
Top View
12
ILIM
11
OUT
10
OUT
9
CHG
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BAT
2, 3
I/O
CE
4
I
Charge Enable Active-Low Input. Connect CE to a high logic level to suspend charging. When CE is high, OUT is active and
battery supplement mode is still available. Connect CE to a low logic level to enable the battery charger. CE is internally
pulled down with approximately 285 kΩ. Do not leave CE unconnected to ensure proper operation.
CHG
9
O
Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high impedance when
charging is complete and when charger is disabled. Connect CHG to the desired logic voltage rail using a 1kΩ-100kΩ
resistor, or use with an LED for visual indication.
EN1
6
I
EN2
5
I
ILIM
12
I
Adjustable Current Limit Programming Input. Connect a 1100-Ω to 8-kΩ resistor from ILIM to VSS to program the maximum
input current (EN2=1, EN1=0). The input current includes the system load and the battery charge current. Leaving ILIM
unconnected disables all charging.
IN
13
I
Input Power Connection. Connect IN to the external DC supply (AC adapter or USB port). The input operating range is 4.35 V
to 6.6 V (bq24076 and bq24078). The input can accept voltages up to 26 V without damage but operation is suspended.
Connect bypass capacitor 1 μF to 10 μF to VSS.
ISET
16
I/O
Fast Charge Current Programming Input. Connect a 590-Ω to 8.9-kΩ resistor from ISET to VSS to program the fast charge
current level. Charging is disabled if ISET is left unconnected. While charging, the voltage at ISET reflects the actual charging
current and can be used to monitor charge current. See Charge Current Translator for more details.
OUT
10, 11
O
System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and above the regulation
voltage. When the input is out of the operation range, OUT is connected to VBAT except when SYSOFF is high. Connect OUT
to the system load. Bypass OUT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
PGOOD
7
O
Open-drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is detected. PGOOD is
high-impedance when the input power is not within specified limits. Connect PGOOD to the desired logic voltage rail using a
1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
SYSOFF
15
I
System Enable Input. Connect SYSOFF high to turn off the FET connecting the battery to the system output. When an
adapter is connected, charging is also disabled. Connect SYSOFF low for normal operation. SYSOFF is internally pulled up
to VBAT through a large resistor (approximately 5 MΩ). Do not leave SYSOFF unconnected to ensure proper operation.
Thermal
Pad
–
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad
must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the
primary ground input for the device. VSS pin must be connected to ground at all times.
TMR
14
I
Timer Programming Input. TMR controls the pre-charge and fast-charge safety timers. Connect TMR to VSS to disable all
safety timers. Connect a 18-kΩ to 72-kΩ resistor between TMR and VSS to program the timers a desired length. Leave TMR
unconnected to set the timers to the default values.
4
Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the battery. Bypass
BAT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
Input Current Limit Configuration Inputs. Use EN1 and EN2 control the maximum input current and enable USB compliance.
See Table 2 for the description of the operation states. EN1 and EN2 are internally pulled down with ≉285 kΩ. Do not leave
EN1 or EN2 unconnected to ensure proper operation.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
TS
1
I
External NTC Thermistor Input. Connect the TS input to the NTC thermistor in the battery pack. TS monitors a 10-kΩ NTC
thermistor. For applications that do not use the TS function, connect a 10-kΩ fixed resistor from TS to VSS to maintain a valid
voltage level on TS.
VSS
8
–
Ground. Connect to the thermal pad and to the ground rail of the circuit.
Table 1. EN1/EN2 Settings
EN2
EN1
MAXIMUM INPUT CURRENT INTO IN PIN
0
0
100 mA. USB100 mode
0
1
500 mA. USB500 mode
1
0
Set by an external resistor from ILIM to VSS
1
1
Standby (USB suspend mode)
8 Specifications
8.1 Absolute Maximum Ratings (1)
over the 0°C to 125°C operating free-air temperature range (unless otherwise noted)
VI
Input Voltage
II
Input Current
MIN
MAX
UNIT
IN (with respect to VSS)
–0.3
28
V
BAT (with respect to VSS)
–0.3
5
V
OUT, EN1, EN2, CE, TS, ISET, PGOOD, CHG, ILIM,
TMR, ITERM, SYSOFF, TD (with respect to VSS)
–0.3
7
V
1.6
A
5
A
BAT (Discharge mode)
5
A
BAT (Charging mode)
1.5 (2)
A
15
mA
IN
OUT
Output Current
(Continuous)
IO
Output Sink Current
CHG, PGOOD
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
8.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±1500
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VI
MIN
MAX
IN voltage range
4.35
26
UNIT
V
IN operating voltage range
4.35
6.4
V
IIN
Input current, IN pin
1.5
A
IOUT
Current, OUT pin
4.5
A
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Recommended Operating Conditions (continued)
MIN
MAX
UNIT
IBAT
Current, BAT pin (Discharging)
ICHG
Current, BAT pin (Charging)
TJ
Junction Temperature
RILIM
Maximum input current programming resistor
RISET
Fast-charge current programming resistor
(2)
590
8900
Ω
RITERM
Termination current programming resistor
0
15
kΩ
RTMR
Timer programming resistor
18
72
kΩ
(1)
(2)
4.5
A
1.5 (1)
A
–40
125
°C
1100
8000
Ω
The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
Use a 1% tolerance resistor for RISET to avoid issues with the RISET short test when using the maximum charge current setting.
8.4 Thermal Information
bq2407x
THERMAL METRIC (1)
RGT (VQFN)
UNIT
16 PIN
RθJA
Junction-to-ambient thermal resistance
44.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.2
°C/W
RθJB
Junction-to-board thermal resistance
17.2
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Dissipation Ratings
PACKAGE (1)
RGT
(1)
(2)
(2)
POWER RATING
RθJA
RθJC
39.47 °C/W
2.4 °C/W
TA ≤ 25°C
TA = 85°C
2.3 W
225 mW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. The pad is
connected to the ground plane by a 2 × 3 via matrix.
8.6 Electrical Characteristics
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
MAX
UNIT
INPUT
UVLO
Undervoltage lock-out
VIN: 0 V → 4 V
3.2
Vhys
Hysteresis on UVLO
VIN: 4 V → 0 V
200
VIN(DT)
Input power detection threshold
Input power detected when VIN > VBAT + VIN(DT)
VBAT = 3.6 V, VIN: 3.5 V → 4 V
55
Vhys
Hysteresis on VIN(DT)
VBAT = 3.6 V, VIN: 4 V → 3.5 V
20
tDGL(PGOOD)
Deglitch time, input power detected status
Time measured from VIN: 0 V → 5 V 1 μs
rise-time to PGOOD = LO
VOVP
Input overvoltage protection threshold
VIN: 5 V → 7 V
Vhys
Hysteresis on OVP
VIN: 7 V → 5V
tDGL(OVP)
Input overvoltage blanking time (OVP fault deglitch)
tREC
Input overvoltage recovery time
Time measured from VIN: 11 V → 5 V with 1 μs
fall-time to PGOOD = LO
80
3.4
V
300
mV
130
mV
mV
1.2
6.4
6.6
ms
6.8
V
110
mV
50
μs
1.2
ms
1.3
mA
ILIM, ISET SHORT-CIRCUIT DETECTION (CHECKED DURING STARTUP)
ISC
6
Current source
VIN > UVLO and VIN > VBAT + VIN(DT)
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Electrical Characteristics (continued)
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSC
MIN
TYP
MAX
VIN > UVLO and VIN > VBAT + VIN(DT)
520
CE = LO or HI, input power not detected,
No load on OUT pin, TJ = 85°C
4.1
EN1= HI, EN2=HI, VIN = 6 V, TJ= 85°C
39
50
EN1= HI, EN2=HI, VIN = 10 V, TJ= 85°C
91
200
UNIT
mV
QUIESCENT CURRENT
IBAT(PDWN)
Sleep current into BAT pin
IIN
Standby current into IN pin
ICC
Active supply current, IN pin
7
μA
μA
CE = LO, VIN = 6 V, no load on OUT pin,
VBAT > VBAT(REG), (EN1, EN2) ≠ (HI, HI)
1.5
mA
300
475
mV
50
100
mV
POWER PATH
VDO(IN-OUT)
VIN – VOUT
VIN = 4.3 V, IIN = 1 A, VBAT = 4.2 V
VDO(BAT-OUT)
VBAT – VOUT
IOUT = 1 A, VIN = 0 V, VBAT > 3 V
VO(REG)
OUT pin voltage regulation
IINmax
Maximum input current
VIN > VOUT + VDO(IN-OUT), VBAT < 3.2 V
3.31
3.41
3.51
VIN > VOUT + VDO(IN-OUT), VBAT ≥ 3.2 V
VBAT +
145mV
VBAT +
210mV
VBAT +
275mV
EN1 = LO, EN2 = LO
90
95
100
EN1 = HI, EN2 = LO
450
475
500
V
mA
EN2 = HI, EN1 = LO
KILIM/RILIM
A
ILIM = 500 mA to 1.5 A
1500
1610
1720
ILIM = 200 mA to 500 mA
1330
1525
1720
KILIM
Maximum input current factor
IINmax
Programmable input current limit range
EN2 = HI, EN1 = LO, RILIM = 8 kΩ to 1.1 kΩ
VIN-DPM
Input voltage threshold when input current is
reduced
EN2 = LO, EN1 = X
VDPPM
Output voltage threshold when charging current is
reduced
VBSUP1
Enter battery supplement mode
AΩ
200
1500
mA
4.35
4.5
4.63
V
VBAT +
125mV
VBAT +
100mV
VBAT +
85mV
V
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 10 Ω → 2 Ω
VOUT ≤ VBAT
–40mV
V
VOUT ≥
VBAT–20mV
V
VBSUP2
Exit battery supplement mode
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 2 Ω → 10 Ω
VO(SC1)
Output short-circuit detection threshold, power-on
VIN > VUVLO and VIN > VBAT + VIN(DT)
0.8
0.9
1
VO(SC2)
Output short-circuit detection threshold, supplement
mode VBAT – VOUT > VO(SC2) indicates short-circuit
VIN > VUVLO and VIN > VBAT + VIN(DT)
200
250
300
tDGL(SC2)
Deglitch time, supplement mode short circuit
tREC(SC2)
Recovery time, supplement mode short circuit
V
mV
250
μs
60
ms
BATTERY CHARGER
IBAT
Source current for BAT pin short-circuit detection
VBAT = 1.5 V
VBAT(SC)
BAT pin short-circuit detection threshold
VBAT rising
VBAT(REG)
Battery charge voltage
VLOWV
Pre-charge to fast-charge transition threshold
tDGL1(LOWV)
Deglitch time on pre-charge to fast-charge transition
tDGL2(LOWV)
Deglitch time on fast-charge to pre-charge transition
7.5
11
mA
1.8
2
V
('76)
4.358
4.4
4.44
('78)
4.31
4.35
4.39
3
3.1
V
VIN > VUVLO and VIN > VBAT + VIN(DT)
Battery fast charge current range
VBAT(REG) > VBAT > VLOWV, VIN = 5 V CE = LO,
EN1 = LO, EN2 = HI
Battery fast charge current
CE = LO, EN1= LO, EN2 = HI,
VBAT > VLOWV, VIN = 5 V, IINmax > ICHG, no load on OUT pin,
thermal loop and DPPM loop not active
ICHG
KISET
Fast charge current factor
IPRECHG
Pre-charge current
KPRECHG
Pre-charge current factor
ITERM
4
1.6
Termination comparator detection threshold
(internally set)
IBIAS(ITERM)
Current for external termination-setting resistor
tDGL(TERM)
Deglitch time, termination detected
VRCH
Recharge detection threshold
tDGL(RCH)
Deglitch time, recharge threshold detected
2.9
ms
25
ms
100
1500
KISET/RISET
797
V
25
890
mA
A
975
AΩ
AΩ
KPRECHG/RISET
A
60
88
118
CE = LO, (EN1, EN2) ≠ (LO, LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and thermal
loop not active
0.09×ICHG
0.1×ICHG
0.11×ICHG
CE = LO, (EN1, EN2) = (LO, LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and thermal
loop not active
0.027×ICHG
0.033×ICHG
0.040×ICHG
72
75
78
A
VIN > VUVLO and VIN > VBAT + VIN(DT)
25
VIN > VUVLO and VIN > VBAT + VIN(DT)
VBAT(REG)
–140mV
VBAT(REG)
–100mV
VBAT(REG)
–60mV
62.5
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Electrical Characteristics (continued)
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDGL(NO-IN)
Delay time, input power loss to OUT LDO turn-off
VBAT = 3.6 V. Time measured from
VIN: 5 V → 3 V 1 μs fall-time
IBAT(DET)
Sink current for battery detection
VBAT = 2.5 V
tDET
Battery detection timer
BAT high or low
MIN
TYP
5
7.5
MAX
20
UNIT
ms
10
250
mA
ms
BATTERY CHARGING TIMERS
tPRECHG
Pre-charge safety timer value
TMR = floating
1440
1800
2160
s
tMAXCHG
Charge safety timer value
TMR = floating
14400
18000
21600
s
tPRECHG
Pre-charge safety timer value
18 kΩ < RTMR < 72 kΩ
RTMR × KTMR
tMAXCHG
Charge safety timer value
18 kΩ < RTMR < 72 kΩ
10×R TMR ×KTMR
KTMR
Timer factor
36
48
s
s
60
s/kΩ
BATTERY-PACK NTC MONITOR (1)
INTC
NTC bias current
VIN > UVLO and VIN > VBAT + VIN(DT)
VHOT
High temperature trip point
Battery charging, VTS Falling
VHYS(HOT)
Hysteresis on high trip point
Battery charging, VTS Rising from VHOT
VCOLD
Low temperature trip point
Battery charging, VTS Rising
VHYS(COLD)
Hysteresis on low trip point
Battery charging, VTS Falling from VCOLD
tDGL(TS)
Deglitch time, pack temperature fault detection
TS fault detected to charger disable
VDIS(TS)
TS function disable threshold
TS unconnected
72
75
80
μA
270
300
330
mV
2000
2100
30
mV
2200
mV
300
mV
50
ms
VIN - 200mV
V
125
°C
155
°C
20
°C
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
TJ(OFF)
Thermal shutdown temperature
TJ(OFF-HYS)
Thermal shutdown hysteresis
TJ Rising
LOGIC LEVELS ON EN1, EN2, CE, SYSOFF, TD
VIL
Logic LOW input voltage
0
0.4
VIH
Logic HIGH input voltage
1.4
6
V
V
IIL
Input sink current
VIL= 0 V
1
μA
IIH
Input source current
VIH= 1.4 V
10
μA
ISINK = 5 mA
0.4
V
LOGIC LEVELS ON PGOOD, CHG
VOL
(1)
8
Output LOW voltage
These numbers set trip points of 0°C and 50°C while charging, with 3°C hysteresis on the trip points, with a Vishay Type 2 curve NTC
with an R25 of 10 kΩ.
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8.7 Typical Characteristics
VIN = 6 V, EN1=1, EN2=0, bq24078 application circuit, TA = 25°C, unless otherwise noted.
0.7
500
0.6
Dropout Voltage (VIN - VOUT)
600
IBAT (mA)
400
300
200
100
0
0.5
0.4
0.3
0.2
0.1
0
120
125
130
135
Temperature (oC)
140
145
0
25
50
75
Junction Temperature (°C)
100
125
IL = 1 A
Figure 2. Dropout Voltage vs Temperature
Figure 1. Thermal Regulation
4.6
120
4.4
VO - Output Voltage (V)
Dropout Voltage (VBAT - VOUT)
100
VBAT = 3 V
80
60
VBAT = 3.9 V
40
4.2
4
3.8
3.6
3.4
20
3.2
3
0
0
25
50
75
Junction Temperature (°C)
100
2
125
2.5
3
3.5
VBAT - Battery Voltage (V)
4
4.5
VIN = 5 V
IL = 1 A
Figure 4. bq24078
Output Regulation Voltage vs Battery Voltage
Figure 3. Dropout Voltage vs Temperature
No Input Supply
4.45
3.80
3.78
4.43
VO - Output Voltage (V)
VO - Output Voltage (V)
3.76
3.74
3.72
3.70
3.68
3.66
3.64
4.40
4.38
4.35
4.33
3.62
4.30
3.60
0
25
50
75
100
125
0
25
Junction Temperature (°C)
50
75
100
125
Junction Temperature (°C)
VIN = 5 V, VBAT = 3.5 V, IL = 1 A
VIN = 5 V, IL = 1 A
Figure 5. bq24078
Output Regulation Voltage vs Temperature
Figure 6. bq24076
Output Regulation Voltage vs Temperature
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Typical Characteristics (continued)
VIN = 6 V, EN1=1, EN2=0, bq24078 application circuit, TA = 25°C, unless otherwise noted.
6.70
VOVP - Output Voltage Threshold (V)
VBAT - Regulation Voltage (V)
4.500
4.450
4.400
4.350
4.300
4.250
4.200
0
5
10
15
VI Rising
6.60
6.55
VI Falling
6.50
6.45
0
30
25
20
6.65
25
Junction Temperature (°C)
50
75
Junction Temperature (°C)
100
125
6.6 V
Figure 7. bq24076
BAT Regulation Voltage vs Temperature
Figure 8. bq24076/78
Overvoltage Protection Threshold vs Temperature
310
IBAT - Fast Charge Current (mA)
IBAT - Fast Charge Current (A)
1.05
1.03
1.01
0.99
0.97
0.95
305
300
295
290
285
280
3
3.2
3.6
3.8
3.4
VBAT - Battery Voltage (V)
4
4.2
3
RISET = 900 Ω
3.2
3.4
3.6
3.8
VBAT - Battery Voltage (V)
4
4.2
RISET = 3 kΩ
Figure 9. Fastcharge Current vs Battery Voltage
Figure 10. Fastcharge Current vs Battery Voltage
105
31.5
103
IBAT - Precharge Current (mA)
IBAT - Precharge Current (A)
104
102
101
100
99
98
97
96
31
30.5
30
29.5
29
95
2
2.2
2.4
2.6
2.8
3
28.5
2
2.2
VBAT - Battery Voltage (V)
RISET = 900 Ω
2.8
3
RISET = 3 kΩ
Figure 11. Precharge Current vs Battery Voltage
10
2.4
2.6
VBAT - Battery Voltage (V)
Figure 12. Precharge Current vs Battery Voltage
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9 Detailed Description
9.1 Overview
The bq2407x devices are integrated Li-Ion linear chargers and system power path management devices targeted
at space-limited portable applications. The device powers the system while simultaneously and independently
charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for
proper charge termination and enables the system to run with a defective or absent battery pack. This feature
also allows instant system turn-on even with a totally discharged battery. The input power source for charging the
battery and running the system can be an AC adapter or a USB port. The devices feature Dynamic Power Path
Management (DPPM), which shares the source current between the system and battery charging, and
automatically reduces the charging current if the system load increases. When charging from a USB port, the
input dynamic power management (VIN-DPM) circuit reduces the input current if the input voltage falls below a
threshold, thus preventing the USB port from crashing. The power-path architecture also permits the battery to
supplement the system current requirements when the adapter cannot deliver the peak system currents.
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9.2 Functional Block Diagram
250mV
V O(SC1)
V BAT
OUT-SC1
t DGL(SC2)
OUT-SC2
Q1
IN
OUT
EN2
Short Detect
225mV
Precharge
V IN-LOW
USB100
USB500
ILIM
ISET
2.25V
Fastcharge
TJ
V REF-ILIM
USB-susp
TJ(REG)
Short Detect
V DPPM
V O(REG)
V OUT
EN2
EN1
Q2
V BAT (REG)
V BAT
BAT
V OUT
CHARGEPUMP
I BIAS-ITERM
40mV
V LOWV
225mV
(’72, ’73, ’75)
ITERM
bq24074
SYSOFF
(bq24075
bq24079
bq24076
bq24078)
Supplement
V RCH
VBAT(SC)
tDGL(RCH)
tDGL2(LOWV)
tDGL(TERM)
V IN
tDGL1(LOWV)
I TERM-floating
~3V
BAT-SC
V BAT + VIN-DT
tDGL(NO-IN)
t DGL(PGOOD)
V UVLO
INTC
V HOT
Charge Control
TS
t DGL(TS)
V COLD
V OVP
t BLK(OVP)
V DIS(TS)
EN1
EN2
USB Suspend
TD
(bq24072,
bq24073)
CE
CHG
Halt timers
V IPRECHG
V ICHG
Dynamically
Controlled
Oscillator
Reset timers
PGOOD
V ISET
Fast-Charge
Timer
Timer fault
TMR
Pre-Charge
Timer
~100mV
Timers disabled
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9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
The bq2407x family remains in power down mode when the input voltage at the IN pin is below the undervoltage
threshold (UVLO).
During the power down mode the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1
FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance.
The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During power down mode, the
VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
9.3.2 Power On
When VIN exceeds the UVLO threshold, the bq2407x powers up. While VIN is below VBAT + VIN(DT), the host
commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT
pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to
OUT is ON. (If SYSOFF is high, Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for
overload conditions on OUT.
Once VIN rises above VBAT + VIN(DT), PGOOD is driven low to indicate the valid power status and the CE, EN1,
and EN2 inputs are read. The device enters standby mode if (EN1 = EN2 = HI) or if an input overvoltage
condition occurs. In standby mode, Q1 is OFF and Q2 is ON so OUT is connected to the battery input. (If
SYSOFF is high, FET Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for overload
conditions on OUT.
When the input voltage at IN is within the valid range: VIN > UVLO AND VIN > VBAT + VIN(DT) AND VIN < VOVP, and
the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) ≠ (HI, HI)] all internal
timers and other circuit blocks are activated. The device then checks for short-circuits at the ISET and ILIM pins.
If no short conditions exists, the device switches on the input FET Q1 with a 100mA current limit to checks for a
short circuit at OUT. When VOUT is above VO(SC1), the FET Q1 switches to the current limit threshold set by EN1,
EN2 and RILIM and the device enters into the normal operation. During normal operation, the system is powered
by the input source (Q1 is regulating), and the device continuously monitors the status of CE, EN1 and EN2 as
well as the input voltage conditions.
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Feature Description (continued)
PGOOD = Hi-Z
CHG = Hi-Z
BATTFET ON
UVLO <VIN <VOVP
and
VIN >V BAT +VIN(DT)
No
Yes
PGOOD = Low
EN1=EN2=1
Yes
No
Yes
ILIM or ISET short?
No
Begin Startup
I IN(MAX) 100mA
VOUT short?
Yes
No
Input Current
Limit set by EN1
and EN2
No
CE = Low
Yes
Begin Charging
Figure 13. Startup Flow Diagram
14
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Feature Description (continued)
9.3.3 Overvoltage Protection (OVP)
The bq2407x accepts inputs up to 28 V without damage. Additionally, an overvoltage protection (OVP) circuit is
implemented that shuts off the internal LDO and discontinues charging when VIN > VOVP for a period long than
tDGL(OVP). When in OVP, the system output (OUT) is connected to the battery and PGOOD is high impedance.
Once the OVP condition is removed, a new power on sequence starts (see Power On). The safety timers are
reset and a new charge cycle will be indicated by the CHG output.
9.3.4 Dynamic Power-Path Management
The bq2407x features an OUT output that powers the external load connected to the battery. This output is
active whenever a source is connected to IN or BAT. The following sections discuss the behavior of OUT with a
source connected to IN to charge the battery and a battery source only.
9.3.4.1 Input Source Connected (ADAPTER or USB)
With a source connected, the dynamic power-path management (DPPM) circuitry of the bq2407x monitors the
input current continuously. For the bq24076/78, OUT is regulated to 210 mV above the voltage at BAT. When the
BAT voltage falls below 3.2 V, OUT is clamped to 3.41 V. This allows for proper startup of the system load even
with a discharged battery. The current into IN is shared between charging the battery and powering the system
load at OUT. The bq2407x has internal selectable current limits of 100 mA (USB100) and 500 mA (USB500) for
charging from USB ports, as well as a resistor-programmable input current limit.
10 μC
50 μC
20 mA/div
USB100 Current Limit
The bq2407x is USB IF compliant for the inrush current testing. The USB specification allows up to 10 μF to be
hard started, which establishes 50 μC as the maximum inrush charge value when exceeding 100 mA. The input
current limit for the bq2407x prevents the input current from exceeding this limit, even with system capacitances
greater than 10 μF. The input capacitance to the device must be selected small enough to prevent a violation
(<10 μF), as this current is not limited. Figure 14 demonstrates the start-up of the bq2407x and compares it to
the USB-IF specification.
100 μs/div
Figure 14. USB-IF Inrush Current Test
The input current limit selection is controlled by the state of the EN1 and EN2 pins as shown in the EN1/EN2
Settings table in Pin Configuration and Functions. When using the resistor-programmable current limit, the input
current limit is set by the value of the resistor connected from the ILIM pin to VSS, and is given by the equation:
IIN-MAX = KILIM/RILIM
(1)
The input current limit is adjustable up to 1.5 A. The valid resistor range is 1.1 kΩ to 8 kΩ.
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Feature Description (continued)
When the IN source is connected, priority is given to the system load. The DPPM and Battery Supplement
modes are used to maintain the system load. Figure 16 illustrates examples of the DPPM and supplement
modes. These modes are explained in detail in the following sections.
9.3.4.1.1 Input DPM Mode (VIN-DPM)
The bq2407x utilizes the VIN-DPM mode for operation from current-limited USB ports. When EN1 and EN2 are
configured for USB100 (EN2=0, EN1=0) or USB500 (EN2=0, EN1=1) modes, the input voltage is monitored. If
VIN falls to VIN-DPM, the input current limit is reduced to prevent the input voltage from falling further. This prevents
the bq2407x from crashing poorly designed or incorrectly configured USB sources. Figure 15 shows the VIN-DPM
behavior to a current limited source. In this figure, the input source has a 400-mA current limit and the device is
in USB500 mode (EN1=1, EN2=0).
IOUT
200mA/div
Input collapses
VIN
(5V)
Input regulated to VIN_DPM
500mV/div
USB500 Current Limit
IIN
200mA/div
Input current limit is
reduced to prevent
crashing the supply
200mA/div
IBAT
4 ms/div
Figure 15. VIN-DPM Waveform
9.3.4.1.2 DPPM Mode
When the sum of the charging and system load currents exceeds the maximum input current (programmed with
EN1, EN2, and ILIM pins), the voltage at OUT decreases. Once the voltage on the OUT pin falls to VDPPM, the
bq2407x enters DPPM mode. In this mode, the charging current is reduced as the OUT current increases in
order to maintain the system output. Battery termination is disabled while in DPPM mode.
9.3.4.1.3 Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at OUT reduces further. When the OUT voltage drops below the
VBSUP1 threshold, the battery supplements the system load. The battery stops supplementing the system load
when the voltage at OUT rises above the VBSUP2 threshold.
During supplement mode, the battery supplement current is not regulated (BAT-FET is fully on), however there is
a short circuit protection circuit built in. Figure 31 demonstrates supplement mode. If during battery supplement
mode, the voltage at OUT drops VO(SC2) below the BAT voltage, the OUT output is turned off if the overload
exists after tDGL(SC2). The short circuit recovery timer then starts counting. After tREC(SC2), OUT turns on and
attempts to restart. If the short circuit remains, OUT is turned off and the counter restarts. Battery termination is
disabled while in supplement mode.
16
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Feature Description (continued)
1200 mA
IOUT
900 mA
A
400 mA
0 mA
IIN
900 mA
500 mA
0 mA
IBAT
500 mA
0 mA
-300 mA
DPPM Loop Active
Supplement Mode
VOUT
3.8 V
3.7 V
~3.6 V
Figure 16. bq24076/78 DPPM and Battery Supplement Modes (VOREG = VBAT + 210 mV, VBAT = 3.6 V)
9.3.4.2 Input Source Not Connected
When no source is connected to the IN input, OUT is powered strictly from the battery. During this mode the
current into OUT is not regulated, similar to Battery Supplement Mode, however the short circuit circuitry is
active. If the OUT voltage falls below the BAT voltage by 250 mV for longer than tDGL(SC2), OUT is turned off. The
short circuit recovery timer then starts counting. After tREC(SC2), OUT turns on and attempts to restart. If the short
circuit remains, OUT is turned off and the counter restarts. This ON/OFF cycle continues until the overload
condition is removed.
9.3.5 Battery Charging
Set CE low to initiate battery charging. First, the device checks for a short-circuit on the BAT pin by sourcing
IBAT(SC) to the battery and monitoring the voltage. When the BAT voltage exceeds VBAT(SC), the battery charging
continues. The battery is charged in three phases: conditioning pre-charge, constant current fast charge (current
regulation) and a constant voltage tapering (voltage regulation). In all charge phases, an internal control loop
monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is
exceeded.
Figure 17 illustrates a normal Li-Ion charge cycle using the bq2407x:
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Feature Description (continued)
PRECHARGE
CC FAST CHARGE
CV TAPER
DONE
VBAT(REG)
IO(CHG)
Battery Current
Battery Voltage
VLOWV
CHG = Hi-z
I(PRECHG)
I(TERM)
Figure 17. Typical Charge Cycle
In the pre-charge phase, the battery is charged at with the pre-charge current (IPRECHG). Once the battery voltage
crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage
reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the
battery approaches full charge. When the battery current reaches ITERM, the CHG pin indicates charging done by
going high-impedance.
Note that termination detection is disabled whenever the charge rate is reduced because of the actions of the
thermal loop, the DPPM loop or the VIN(LOW) loop.
The value of the fast-charge current is set by the resistor connected from the ISET pin to VSS, and is given by
the equation:
ICHG = KISET/RISET
(2)
The charge current limit is adjustable up to 1.5 A. The valid resistor range is 590 Ω to 5.9 kΩ. If ICHG is
programmed as greater than the input current limit, the battery will not charge at the rate of ICHG, but at the
slower rate of IIN(MAX) (minus the load current on the OUT pin, if any). In this case, the charger timers will be
proportionately slowed down.
9.3.5.1 Charge Current Translator
When the charger is enabled, internal circuits generate a current proportional to the charge current at the ISET
input. The current out of ISET is 1/400 (±10%) of the charge current. This current, when applied to the external
charge current programming resistor, RISET, generates an analog voltage that can be monitored by an external
host to calculate the current sourced from BAT.
VISET = ICHARGE / 400 × RISET
18
(3)
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Feature Description (continued)
Begin Charging
Battery short detected?
Yes
No
Start Precharge
CHG = Low
No
VBAT > VLOWV
No
tPRECHARGE
Elapsed?
Yes
End Charge
Flash CHG
Start Fastcharge
ICHARGE set by ISET
No
IBAT < ITERM
No
t FASTCHARGE
Elapsed?
Yes
End Charge
Flash CHG
Charge Done
CHG = Hi-Z
TD = Low
(’72, ’73 Only)
(’74, ’75 = YES)
No
Yes
Termination Reached
BATTFET Off
Wait for VBAT < VRCH
No
VBAT < VRCH
Yes
Run Battery Detection
Battery Detected?
No
Yes
Figure 18. Battery Charging Flow Diagram
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Feature Description (continued)
9.3.5.2 Battery Detection and Recharge
The bq2407x automatically detects if a battery is connected or removed. Once a charge cycle is complete, the
battery voltage is monitored. When the battery voltage falls below VRCH, the battery detection routine is run.
During battery detection, current (IBAT(DET)) is pulled from the battery for a duration tDET to see if the voltage on
BAT falls below VLOWV. If not, charging begins. If it does, then it indicates that the battery is missing or the
protector is open. Next, the precharge current is applied for tDET to close the protector if possible. If VBAT < VRCH,
then the protector closed and charging is initiated. If VBAT > VRCH, then the battery is determined to be missing
and the detection routine continues.
9.3.5.3 Battery Disconnect (SYSOFF Input, bq24076, bq24078)
The bq24076 and bq24078 feature a SYSOFF input that allows the user to turn the FET Q2 off and disconnect
the battery from the OUT pin. This is useful for disconnecting the system load from the battery, factory
programming where the battery is not installed or for host side impedance track fuel gauging, such as bq27500,
where the battery open circuit voltage level must be detected before the battery charges or discharges. The
/CHG output remains low when SYSOFF is high. Connect SYSOFF to VSS, to turn Q2 on for normal operation.
SYSOFF is internally pulled to VBAT through ~5 MΩ resistor.
9.3.5.4 Dynamic Charge Timers (TMR Input)
The bq2407x devices contain internal safety timers for the pre-charge and fast-charge phases to prevent
potential damage to the battery and the system. The timers begin at the start of the respective charge cycles.
The timer values are programmed by connecting a resistor from TMR to VSS. The resistor value is calculated
using the following equation:
tPRECHG = KTMR × RTMR
tMAXCHG = 10 × KTMR × RTMR
(4)
(5)
Leave TMR unconnected to select the internal default timers. Disable the timers by connecting TMR to VSS.
Reset the timers by toggling the CE pin, or by toggling EN1, EN2 pin to put the device in and out of USB
suspend mode (EN1 = HI, EN2 = HI).
Note that timers are suspended when the device is in thermal shutdown, and the timers are slowed proportionally
to the charge current when the device enters thermal regulation.
During the fast charge phase, several events increase the timer durations.
• The system load current activates the DPPM loop which reduces the available charging current
• The input current is reduced because the input voltage has fallen to VIN(LOW)
• The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
During each of these events, the internal timers are slowed down proportionately to the reduction in charging
current. For example, if the charging current is reduced by half for two minutes, the timer clock is reduced to half
the frequency and the counter counts half as fast resulting in only one minute of "counting" time.
If the pre charge timer expires before the battery voltage reaches VLOWV, the bq2407x indicates a fault condition.
Additionally, if the battery current does not fall to ITERM before the fast charge timer expires, a fault is indicated.
The CHG output flashes at approximately 2 Hz to indicate a fault condition. The fault condition is cleared by
toggling CE or the input power, entering/ exiting USB suspend mode, or an OVP event.
9.3.5.5 Status Indicators (PGOOD, CHG)
The bq2407x contains two open-drain outputs that signal its status. The PGOOD output signals when a valid
input source is connected. PGOOD is low when (VBAT + VIN(DT)) < VIN < VOVP. When the input voltage is outside
of this range, PGOOD is high impedance.
The charge cycle after power-up, CE going low, or exiting OVP is indicated with the CHG pin on (low - LED on),
whereas all refresh (subsequent) charges will result in the CHG pin off (open - LED off). In addition, the CHG
signals timer faults by flashing at approximately 2 Hz.
20
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Table 2. PGOOD Status Indicator
INPUT STATE
PGOOD OUTPUT
VIN < VUVLO
High-impedance
VUVLO < VIN < VBAT + VIN(DT)
High-impedance
VBAT + VIN(DT) < VIN < VOVP
Low
VIN > VOVP
High-impedance
Table 3. CHG Status Indicator
CHARGE STATE
CHG OUTPUT
Charging
Charging suspended by thermal loop
Safety timers expired
Low (for first charge cycle)
Flashing at 2 Hz
Charging done
Recharging after termination
IC disabled or no valid input power
High-impedance
Battery absent
9.3.5.6 Thermal Regulation and Thermal Shutdown
The bq2407x contain a thermal regulation loop that monitors the die temperature. If the temperature exceeds
TJ(REG), the device automatically reduces the charging current to prevent the die temperature from increasing
further. In some cases, the die temperature continues to rise despite the operation of the thermal loop,
particularly under high VIN and heavy OUT system load conditions. Under these conditions, if the die
temperature increases to TJ(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the
battery still powers the load on OUT. Once the device die temperature cools by TJ(OFF-HYS), the input FET Q1 is
turned on and the device returns to thermal regulation. Continuous overtemperature conditions result in a
"hiccup" mode. During thermal regulation, the safety timers are slowed down proportionately to the reduction in
current limit.
Note that this feature monitors the die temperature of the bq2407x. This is not synonymous with ambient
temperature. Self heating exists due to the power dissipated in the IC because of the linear nature of the battery
charging algorithm and the LDO associated with OUT. A modified charge cycle with the thermal loop active is
shown in Figure 19. Battery termination is disabled during thermal regulation.
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PRECHARGE
THERMAL
REGULATION
CC FAST
CHARGE
CV TAPER
DONE
VO(REG)
IO(CHG)
Battery Voltage
Battery Current
V(LOWV)
HI-z
I(PRECHG)
I(TERM)
TJ(REG)
IC Junction Temperature, TJ
Figure 19. Charge Cycle Modified by Thermal Loop
9.3.6 Battery Pack Temperature Monitoring
The bq2407x features an external battery pack temperature monitoring input. The TS input connects to the NTC
thermistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature
conditions. During charging, INTC is sourced to TS and the voltage at TS is continuously monitored. If, at any
time, the voltage at TS is outside of the operating range (VCOLD to VHOT), charging is suspended. The timers
maintain their values but suspend counting. When the voltage measured at TS returns to within the operation
window, charging is resumed and the timers continue counting. When charging is suspended due to a battery
pack temperature fault, the CHG pin remains low and continues to indicate charging.
For applications that do not require the TS monitoring function, connect a 10-kΩ resistor from TS to VSS to set
the TS voltage at a valid level and maintain charging.
The allowed temperature range for 103AT-2 type thermistor is 0°C to 50°C. However, the user may increase the
range by adding two external resistors. See Figure 20 for the circuit details. The values for Rs and Rp are
calculated using the following equations:
22
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æ
ì
üö
VH ´ VC
2
´ (RTC - RTH )ý ÷
çç (RTH +RTC ) - 4 íRTH ´ RTC +
÷
(VH - VC ) ´ ITS
î
þø
è
2
-(RTH + RTC ) ±
Rs =
Rp =
(6)
VH ´ (R TH + RS )
ITS ´ (R TH + RS ) - VH
where
•
•
•
•
•
•
RTH: Thermistor Hot Trip Value found in thermistor data sheet
RTC: Thermistor Cold Trip Value found in thermistor data sheet
VH: IC's Hot Trip Threshold = 0.3 V nominal
VC: IC's Cold Trip Threshold = 2.1 V nominal
ITS: IC's Output Current Bias = 75 µA nominal
NTC Thermsitor Semitec 103AT-4
(7)
Rs and Rp 1% values were chosen closest to calculated values in Table 4.
Table 4. Calculated Values
COLD TEMP RESISTANCE
AND TRIP THRESHOLD, Ω (°C)
HOT TEMP RESISTANCE AND
TRIP THRESHOLD, Ω (°C)
EXTERNAL BIAS RESISTOR,
Rs (Ω)
EXTERNAL BIAS RESISTOR,
Rp (Ω)
28000 (–0.6)
4000 (51)
0
∞
28480 (–1)
3536 (55)
487
845000
28480 (–1)
3021 (60)
1000
549000
33890 (–5)
4026 (51)
76.8
158000
33890 (–5)
3536 (55)
576
150000
33890 (–5)
3021 (60)
1100
140000
RHOT and RCOLD are the thermistor resistance at the desired hot and cold temperatures, respectively. The
temperature window cannot be tightened more than using only the thermistor connected to TS, it can only be
extended.
I NTC
bq2407x
RS
TS
+
PACK+
TEMP
VCOLD
RP
+
PACK-
VHOT
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Figure 20. Extended TS Pin Thresholds
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9.4 Device Functional Modes
9.4.1 Sleep Mode
When the input is between UVLO and VIN(DT), the device enters sleep mode. After entering sleep mode for >20
mS the internal FET connection between the IN and OUT pin is disabled and pulling the input to ground will not
discharge the battery, other than the leakage on the BAT pin. If one has a full 1000-mAHr battery and the
leakage is 10 μA, then it would take 1000 mAHr / 10 μA = 100000 hours (11.4 years) to discharge the battery.
The self-discharge of the battery is typically five times higher than this.
9.4.2 Explanation of Deglitch Times and Comparator Hysteresis
NOTE
Figure 21 to Figure 25 are not to scale.
VOVP
VOVP - Vhys(OVP)
VIN
Typical Input Voltage
Operating Range
t < tDGL(OVP)
VBAT + VIN(DT)
VBAT + VIN(DT) - Vhys(INDT)
UVLO
UVLO - Vhys(UVLO)
PGOOD
tDGL(PGOOD)
tDGL(OVP)
tDGL(NO-IN)
tDGL(PGOOD)
Figure 21. Power-Up, Power-Down, Power Good Indication
tDGL1(LOWV)
VBAT
VLOWV
t < tDGL1(LOWV)
tDGL1(LOWV)
tDGL2(LOWV)
ICHG
Fast-Charge
Fast-Charge
IPRE-CHG
t < tDGL2(LOWV)
Pre-Charge
Pre-Charge
Figure 22. Precharge to Fast-Charge, Fast- to Pre-Charge Transition – tDGL1(LOWV), tDGL2(LOWV)
24
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Device Functional Modes (continued)
VBAT
VRCH
Re-Charge
t < tDGL(RCH)
tDGL(RCH)
Figure 23. Recharge – tDGL(RCH)
Turn
Q2 OFF
Force
Q2 ON
tREC(SC2)
Turn
Q2 OFF
tREC(SC2)
Force
Q2 ON
VBAT - VOUT
Recover
VO(SC2)
t < tDGL(SC2)
tDGL(SC2)
tDGL(SC2)
t < tDGL(SC2)
Figure 24. OUT Short-Circuit – Supplement Mode
VCOLD
VCOLD - Vhys(COLD)
t < tDGL(TS)
Suspend
Charging
tDGL(TS)
VTS
Resume
Charging
VHOT - Vhys(HOT)
VHOT
Figure 25. Battery Pack Temperature Sensing – TS Pin. Battery Temperature Increasing
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The bq2407x devices power the system while simultaneously and independently charging the battery. The input
power source for charging the battery and running the system can be an AC adapter or a USB port. The devices
feature dynamic power-path management (DPPM), which shares the source current between the system and
battery charging and automatically reduces the charging current if the system load increases. When charging
from a USB port, the input dynamic power management (VIN-DPM) circuit reduces the input current limit if the
input voltage falls below a threshold, preventing the USB port from crashing. The power-path architecture also
permits the battery to supplement the system current requirements when the adapter cannot deliver the peak
system currents.
The bq2407x is configurable to be host controlled for selecting different input current limits based on the input
source connected, or a fully stand alone device for applications that do not support multiple types of input
sources.
10.2 Typical Application
VIN = UVLO to VOVP, IFASTCHG = 800 mA, IIN(MAX) = 1.3 A, Battery Temperature Charge Range = 0°C to 50°C,
6.25-hour Fastcharge Safety Timer
R4
1.5 kW
R5
1.5 kW
SYSTEM
IN
C1
1 mF
GND
CHG
DC+
PGOOD
Adaptor
OUT
C2
4.7 mF
VSS
bq24076
bq24078
HOST
EN2
EN1
TS
SYSOFF
CE
BAT
PACK-
R1
46.4 kW
ISET
TMR
C3
4.7 mF
ILM
PACK+
TEMP
R2
1.18 kW
R3
1.13 kW
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Figure 26. Using bq24076/bq24078 in a Host-Controlled Charger Application
26
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Typical Application (continued)
10.2.1 Design Requirements
• Supply voltage = 5 V
• Fast charge current of approximately 800 mA; ISET - pin 16
• Input current limit = 1.3 A; ILIM - pin 12
• Termination current threshold = 110 mA; ITERM – pin 15 (bq24074 only)
• Safety timer duration, Fast-Charge = 6.25 hours; TMR – pin 14
• TS – Battery Temperature Sense = 10 kΩ NTC (103AT-2)
10.2.2 Detailed Design Procedure
10.2.2.1 bq2407x Charger Design Example
See Figure 26 for a schematic of the design example.
10.2.2.1.1 System ON/OFF (SYSOFF) (bq24076 or bq24078 only)
Connect SYSOFF high to disconnect the battery from the system load. Connect SYSOFF low for normal
operation
10.2.2.2 Calculations
10.2.2.2.1 Program the Fast Charge Current (ISET):
RISET = KISET / ICHG
KISET = 890 AΩ from the electrical characteristics table.
RISET = 890 AΩ / 0.8 A = 1.1125 kΩ
Select the closest standard value, which for this case is 1.13 kΩ. Connect this resistor between ISET (pin 16)
and VSS.
10.2.2.2.2 Program the Input Current Limit (ILIM)
RILIM = KILIM / II_MAX
KILIM = 1550 AΩ from the electrical characteristics table.
RISET = 1550 AΩ / 1.3 A = 1.192 kΩ
Select the closest standard value, which for this case is 1.18 kΩ. Connect this resistor between ILIM (pin 12) and
VSS.
10.2.2.2.3 Program 6.25-hour Fast-Charge Safety Timer (TMR)
RTMR = tMAXCHG / (10 × KTMR )
KTMR = 48 s/kΩ from the electrical characteristics table.
RTMR = (6.25 hr × 3600 s/hr) / (10 × 48 s/kΩ) = 46.8 kΩ
Select the closest standard value, which for this case is 46.4 kΩ. Connect this resistor between TMR (pin 2) and
VSS.
10.2.2.3 TS Function
Use a 10-kΩ NTC thermistor in the battery pack (103AT-2). For applications that do not require the TS
monitoring function, connect a 10-kΩ resistor from TS to VSS to set the TS voltage at a valid level and maintain
charging.
10.2.2.4
CHG and PGOOD
LED Status: Connect a 1.5-kΩ resistor in series with a LED between OUT and CHG to indicate charging status.
Connect a 1.5-kΩ resistor in series with a LED between OUT and PGOOD to indicate when a valid input source
is connected.
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Typical Application (continued)
Processor Monitoring Status: Connect a pullup resistor (on the order of 100 kΩ) between the power rail of the
processor and CHG and PGOOD.
10.2.2.5 Selecting IN, OUT, and BAT Pin Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin,
input, output and battery pins. Using the values shown on the application diagram, is recommended. After
evaluation of these voltage signals with real system operational conditions, one can determine if capacitance
values can be adjusted toward the minimum recommended values (DC load application) or higher values for fast
high amplitude pulsed load applications. Note if designed high input voltage sources (bad adaptors or wrong
adaptors), the capacitor needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values
so a 16-V capacitor may be adequate for a 30-V transient (verify tested rating with capacitor manufacturer).
28
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Typical Application (continued)
10.2.3 Application Curves
VIN
5 V/div
VCHG
5 V/div
Charging Initiated
VOUT
4.4 V
1 A/div
500 mV/div
VBAT
3.6 V
IBAT
VPGOOD
5 V/div
2 V/div
VBAT
Battery Inserted
500 mA/div
IBAT
Battery Detection Mode
4 ms/div
400 ms/div
RLOAD = 10 Ω
Figure 27. Adapter Plug-In
Battery Connected
VCHG
Figure 28. Battery Detection
Battery Inserted
5 V/div
IOUT
500 mA/div
IBAT
500 mA/div
VOUT
4.4 V
200 mV/div
1 A/div
IBAT
VBAT
2 V/div
Battery
Removed
Battery Detection Mode
400 ms/div
400 ms/div
RLOAD = 20 Ω to 9 Ω
Figure 29. Battery Detection
Battery Removed
IOUT
IBAT
Supplement Mode
Figure 30. Entering and Exiting DPPM Mode
1 A/div
IOUT
500 mA/div
IBAT
1 A/div
Supplement Mode
VOUT
3.81 V
VOUT
4.4 V
VBAT
3.8 V
500 mV/div
500 mA/div
200 mV/div
VBAT
3.6 V
Tracking to VBAT +210 mV
1 ms/div
1 ms/div
RLOAD = 25 Ω to 4.5 Ω
RLOAD = 20 Ω to 4.5 Ω
Figure 31. Entering and Exiting Battery Supplement Mode
Figure 32. Entering and Exiting Battery Supplement Mode
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Typical Application (continued)
VCE
5 V/div
VCHG
5 V/div
1 V/div
VBAT
3.6 V
IBAT
Mandatory Precharge
500 mA/div
10 V/div
VIN
VOUT
4.4 V
VBAT
4.2 V
500 mV/div
IBAT
1 A/div
10 ms/div
40 ms/div
VIN = 6 V to 15 V
Figure 33. Charger ON/OFF Using CE
VSYSOFF
VOUT
5.5 V
Figure 34. OVP Fault
5 V/div
VSYSOFF
2 V/div
VBAT
4V
VBAT
4V
5 V/div
2 V/div
VOUT
Battery Powering
System
500 mA/div
System Power Off
IBAT
IBAT
500 mA/div
4 ms/div
400 ms/div
VIN = 0 V
VIN = 6 V
Figure 35. System ON/OFF With Input Connected
bq24076, bq24078
30
RLOAD = 10 Ω
Figure 36. System ON/OFF With Input Not Connected
bq24076, bq24078
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11 Power Supply Recommendations
Some adapters implement a half rectifier topology, which causes the adapter output voltage to fall below the
battery voltage during part of the cycle. To enable operation with adapters under those conditions, the bq2407x
family keeps the charger on for at least 20 msec (typical) after the input power puts the part in sleep mode. This
feature enables use of external adapters using 50 Hz networks. The input must not drop below the UVLO voltage
for the charger to work properly. Thus, the battery voltage should be above the UVLO to help prevent the input
from dropping out. Additional input capacitance may be needed.
12 Layout
12.1 Layout Guidelines
•
•
•
•
To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2407x, with short
trace runs to both IN, OUT and GND (thermal pad).
All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces
The bq2407x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is
also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full
PCB design guidelines for this package are provided in QFN/SON PCB Attachment Application Note
(SLUA271).
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12.2 Layout Example
Figure 37. Layout Schematic
32
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12.3 Thermal Considerations
The bq24076/78 family is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad
should be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in
QFN/SON PCB Attachment Application Note (SLUA271). The most common measure of package thermal
performance is thermal impedance (θJA ) measured (or modeled) from the chip junction to the air surrounding the
package surface (ambient). The mathematical expression for θJA is:
θJA = (TJ - T) / P
where
•
•
•
TJ = chip junction temperature
T = ambient temperature
P = device power dissipation
(8)
Factors that can influence the measurement and calculation of θJA include:
•
•
•
•
•
Whether or not the device is board mounted
Trace size, composition, thickness, and geometry
Orientation of the device (horizontal or vertical)
Volume of the ambient air surrounding the device under test and airflow
Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage
increases to ≉3.4 V within the first 2 minutes. The thermal time constant of the assembly typically takes a few
minutes to heat up so when doing maximum power dissipation calculations, 3.4 V is a good minimum voltage to
use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the
PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of
time. The fast charge current will start to taper off if the part goes into thermal regulation.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(BAT)] × I(BAT)
(9)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or
higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop
is always active.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq24076
Click here
Click here
Click here
Click here
Click here
bq24078
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24076RGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B24076
BQ24076RGTT
ACTIVE
VQFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B24076
BQ24078RGTR
ACTIVE
VQFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B24078
BQ24078RGTT
ACTIVE
VQFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B24078
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ24076RGTR
VQFN
RGT
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24076RGTT
VQFN
RGT
16
250
180.0
12.5
3.3
3.3
1.1
8.0
12.0
Q2
BQ24078RGTR
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ24078RGTT
VQFN
RGT
16
250
180.0
12.5
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24076RGTR
VQFN
RGT
16
3000
338.0
355.0
50.0
BQ24076RGTT
VQFN
RGT
16
250
205.0
200.0
33.0
BQ24078RGTR
VQFN
RGT
16
3000
338.0
355.0
50.0
BQ24078RGTT
VQFN
RGT
16
250
205.0
200.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
SCALE 3.600
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1.68 0.07
(0.2) TYP
5
12X 0.5
8
EXPOSED
THERMAL PAD
4
9
4X
1.5
SYMM
1
12
16X
PIN 1 ID
(OPTIONAL)
13
16
0.1
0.05
SYMM
16X
0.30
0.18
C A B
0.5
0.3
4222419/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(0.58)
TYP
12X (0.5)
(2.8)
9
4
( 0.2) TYP
VIA
5
(R0.05)
ALL PAD CORNERS
8
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222419/B 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
SYMM
8
(R0.05) TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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