TI LP38869 1a flexcap, low-dropout linear regulator with 0.75% accuracy Datasheet

LP38869
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SNVS877B – AUGUST 2012 – REVISED APRIL 2013
LP38869 1A FlexCap, Low-Dropout Linear Regulator with 0.75% Accuracy
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FEATURES
DESCRIPTION
•
•
•
The LP38869 low-dropout linear regulator operates
with an input voltage supply from +2.7V to +5.5V
input, and delivers a specified 1A load current with a
low 200 mV dropout. The high 50 dB PSRR at 100
kHz results from a high gain control loop that also
yields excellent transient response. Coupled with a
high accuracy output voltage, ±0.75 % over
temperature, the LP38869 is an ideal power supply
for FPGAs, DSPs or MCUs. Output voltage is preset
at +2.5V, or may be adjustable between +0.8V to +5V
with an external resistor divider.
1
2
•
•
•
•
•
•
•
•
•
•
•
Operating Input Supply Range: +2.7V to + 5.5V
Maximum Continuous Output Current: 1A
Preset Output Voltage of 2.5V, or Adjustable
Output Voltage From 0.8V to 5.0V
Pre-Set Output Initial VOUT Tolerance ±0.5%
Adjustable VREF Tolerance of ±0.75%
PSRR of 50dB at 100kHz
Low 200 mV Dropout at 1A
Typical 2 µA Supply Current in Shutdown
Mode
Adjustable Soft-Start for Output Current
Fold-Back Output Current Limit
Stable With Ceramic, Tantalum, or Aluminum
Capacitors
Stable With 1uF Input/Output Capacitors
Thermal Shutdown
16-pin HTSSOP Package
The LP38869 only needs 1 μF output capacitance for
stability. The FlexCap compensation allows the use of
any type of output capacitor, regardless of ESR.
Other features include: Soft-Start; delayed reset
output; low-power shutdown; short-circuit protection;
and thermal shutdown protection
Ground Pin Current: Typically less than 1 mA at 1A
load
Shutdown Mode: Typically 2 µA quiescent current
when the SHDN pin is pulled low.
APPLICATIONS
•
•
•
•
Simplified Compensation: Stable with any type of
output capacitor.
DSA, FPGA and MCU Power Supply
SMPS Post-Regulator
Applications Requiring Sequencing
Gibabit SERDES Termination Supply
Typical Application Circuit
VIN
1 PF
IN
OUT
IN
OUT
VOUT
1 PF
OUT
IN
LP38869
IN
OUT
RST
ONOFF-
CSS
SHDN
SET
SS
GND
RESET
DAP
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LP38869
SNVS877B – AUGUST 2012 – REVISED APRIL 2013
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Connection Diagram
N/C
1
16
N/C
IN
2
15
OUT
IN
3
14
OUT
IN
4
13
OUT
IN
5
12
OUT
RST
6
11
SET
SHDN
7
10
GND
SS
8
9
N/C
Exposed Pad
on Bottom
(DAP)
Figure 1. Top View
16-Pin HTSSOP
Pin Descriptions for 16-Pin HTSSOP Packages
Pin #
Pin Name
1
N/C
2, 3, 4, 5
IN
6
RST
7
SHDN
2
Description
Application Information
No Connection
No Internal Electrical Connection
Positive power input
Operates from +2.7V to +5.5V. Bypass capacitor is required, located close to the
package; 1 μF is recommended as a minimum value
RESET Output
Open-drain output is low when VOUT is 8% below normal regulation voltage. If
regulation returns RST remains low for at least 3ms afterwards. Use large value
pull-up resistor (100 kΩ) to VOUT to obtain output voltage.
SHUTDOWN Input
A logic low state on the SHDN input will turn the regulator off, and will discharge
any capacitor on the SS pin. A logic high on the SHDN pin will turn the regulator
ON.
8
SS
Soft-Start control
Connect a capacitor from SS to GND. If SS is left open SS feature is disabled
9
N/C
No Connection
No Internal Electrical Connection
10
GND
Power Ground
Return connection for input and output voltages.
11
SET
Operational Mode Selection
Used to select between Pre-Set Mode or Adjustable Mode. Connect to ground
(Pre-Set Mode) or to a resistor divider from VOUT to SET pin to GND (Adjustable
Mode).
12, 13,
14, 15
OUT
Regulated output
Regulated output voltage. A bypass capacitor is required, located close to the
package; 1 μF recommended as the minimum value
16
N/C
No Connection
No Internal Electrical Connection
DAP
Exposed
Pad
Thermal Connection
Solder the DAP to a copper plane under the package to improve thermal
performance. DAP can be connected to ground at device Pin 10. Optionally, but
not recommended, the DAP can be left floating. Do not connect DAP to any
potential other than ground. See Operating Region and Power Dissipation.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN to GND (Survival)
-0.3V to 6.0V
All other inputs to GND
-0.3V to 6.0V
Power Dissipation (Survival)
Internally Limited
IOUT (Survival)
Internally Limited
ESD Rating (3),Human Body Model
2 kV
Storage Temperature Range
-65°C to +150°C
Junction Temperature
Peak Reflow Temperature
(1)
(2)
(3)
(4)
150°C
(4)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-A114.
Peak Reflow Temperatures for Surface Mount devices are defined in Absolute Maximum Ratings for Soldering (literature number
SNOA549).
Operating Ratings (1)
VIN Voltage
2.7V to 5.5V
VSHDN Voltage
0V to 5.5V
VRST Voltage
0V to VIN
Junction Temperature (TJ)
(1)
(2)
(2)
−40°C to +125°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD),
maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). See Operating Region and Power
Dissipation.
Electrical Characteristics
Unless otherwise specified: VIN = VOUT(NOM) + 500 mV, VSHDN = VIN, IOUT = 10 mA, CIN = 1 μF MLCC, COUT = 1 μF MLCC, SS =
Open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of
-40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
UVLO
Input Under-Voltage Lock-Out
VOUT
VREF
(2)
Conditions
Input Voltage Operating Range
ΔUVLO
(1)
Parameter
VIN
Min
Typ
Max
Units
2.7
-
5.5
V
2.27
2.45
2.58
V
-
64
-
mV
3.0V ≤ VIN ≤ 5.5V,
IOUT = 1 mA, TJ = 25°C
-0.50
-
0.50
IOUT = 1 mA
-0.75
-
0.75
794
800
806
mV
ΔVIN = 3.0 to 5.5V
-
0.0011
-
%/V
ΔIOUT = 1 mA to 1A
-
0.2
1.85
%/A
VIN Rising or Falling
Includes Hysteresis
UVLO Hysteresis
Output Voltage Accuracy
(Pre-Set Mode)
Regulated Feedback Voltage
(Adjustable Mode)
ΔVOUT(LINE)
Line Regulation
ΔVOUT(LOAD)
Load Regulation
(1)
(2)
IOUT = 150 mA
%
Line Regulation is the % change in VOUT from VOUT(NOM) for every 1V change in VIN,Line Regulation = (( ΔVOUT / VOUT(NOM)) / ΔVIN ) x
100%
Load Regulation is the % change in VOUT from VOUT(NOM) for every 1A change in IOUT, Load Regulation = (( ΔVOUT / VOUT(NOM) ) /
ΔIOUT ) x 100%
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Electrical Characteristics (continued)
Unless otherwise specified: VIN = VOUT(NOM) + 500 mV, VSHDN = VIN, IOUT = 10 mA, CIN = 1 μF MLCC, COUT = 1 μF MLCC, SS =
Open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of
-40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IOUT = 100 µA
-
0.6
2
IOUT = 1A
-
0.7
-
-
2
20
µA
IGND
Ground Pin Current
IOFF
Shutdown Supply Current
VSHDN = 0.0V, VIN = +5.5V, VOUT = 0V
Adjustable Output Voltage Range
1 mA ≤ IOUT ≤ 1 A
0.8
-
5
V
Maximum Output Current
Continuous
1.0
-
-
A
ISC
Short Circuit Current
VOUT = 0V
1.0
1.9
-
A
ILIM
In Regulation Current Limit
VSET = 0.760V, -40°C ≤ TJ ≤ 85°C
2.0
VSET = 0.760V
1.9
3
-
A
VSET(TH)
SET Dual Mode Threshold
Threshold is where SET pin voltage rising
from 0.0V deactivates the Pre-Set Mode
35
87
138
mV
SET Pin Bias Current
VSET = +0.900V
-
2
300
nA
IOUT = 1 mA
-
0.2
-
IOUT = 1.0A
-
185
330
1.60
0.86
-
0.78
0.58
IOUT(MAX)
ISET
VDO
Dropout Voltage
(3)
VSHDN(ON)
SHDN ON Threshold
VSHDN rising until output is acitve
+2.7V ≤ VIN ≤ +5.5V
VSHDN(OFF)
SHDN OFF Threshold
VSHDN falling until output is shutdown
+2.7V ≤ VIN ≤ +5.5V
-
VSHDN Hysteresis
+2.7V ≤ VIN ≤ +5.5V
-
80
-
VSHDN = 0V
-
0.002
0.1
VSHDN = 5.5V
-
0.002
0.1
ΔVSHDN
mA
mV
V
mV
ISHDN
SHDN Input Bias Current
ISS
Soft-Start Charge Current
VSS= 0.0V
-
6.7
-
µA
RST Output Low Voltage
IRST(SINK) = 1 mA
-
0.007
0.1
V
Operating Input Voltage (VIN)
Range for RST Valid
IRST(SINK) = 10 μA
1.0
-
5.5
V
RST Leakage
VIN = 5.5V, VRST = 5.5V
-
0.0
1
µA
VRST(TH)
RST Threshold
VOUT falling from VOUT(NOM) until RST pin
goes low
86
92
97
%
OUT
ΔVRST
RST Hysteresis
VOUT rising from VRST(TH) until RST pin goes
high
-
10
-
mV
RST Release Delay time
Time from when VOUT returns to normal to
when VRST goes high
1.0
3
5.5
ms
PSRR
Ripple Rejection
F = 100 kHz, COUT = 1 µF Ceramic,
IOUT = 300 mA
-
54
-
dB
VNOISE
Output Noise
f = 10Hz to 100 kHz, COUT = 1µF Ceramic,
IOUT = 150 mA
-
50
-
µVRMS
Thermal Shutdown
TJ rising
-
160
-
Thermal Shutdown Hysteresis
TJ falling from TSD
-
15
-
IRST
tRST(DELAY)
µA
AC Parameters
Thermal Characteristics
TSD
ΔTSD
(3)
4
°C
Dropout voltage (VDO) is defined as the minimum input to output differential voltage at which the output voltage drops to 100 mV below
the nominal value. For any output voltage less than 2.5V, the minimum VIN operating voltage of 2.7V is the limiting factor, and dropout
voltage is not a valid parameter.
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Typical Performance Characteristics
Unless otherwise specified: TJ = 25°C, VIN = 5.0V, VSHDN = VIN, VSET = 0.0V, VOUT = 2.5V, SS = Open, CIN = 1 µF, COUT = 1 µF
MLCC, IOUT = 100mA
VOUT vs. IOUT
VREF vs. Temperature (TJ), VIN = 2.7V
1.0
VREFVARIATION FROM 0.800V (%)
OUTPUT VOLTAGE VARIATION (%)
0.5
0.4
0.3
0.2
VIN = 5.5V
0.1
0.0
-0.1
-0.2
-0.3
VIN = 3.0V
-0.4
-0.5
1m
10m
100m
OUTPUT CURRENT (A)
0.8
0.6
Adjustable Mode
0.4
VIN= 2.7V
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
1
-50
-25
0
25 50 75 100 125
TEMPERATURE, TJ(°C)
Figure 2.
Figure 3.
VREF vs. Temperature (TJ), VIN = 5.5V
IGND vs. VIN
VREFVARIATION FROM 0.800V (%)
1.0
0.8
0.6
Adjustable Mode
0.4
VIN= 5.5V
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25 50 75 100 125
TEMPERATURE, TJ(°C)
Figure 4.
Figure 5.
IGND vs. IOUT, VIN = 2.7V
IGND vs IOUT, VIN = 3.0V
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ = 25°C, VIN = 5.0V, VSHDN = VIN, VSET = 0.0V, VOUT = 2.5V, SS = Open, CIN = 1 µF, COUT = 1 µF
MLCC, IOUT = 100mA
IGND vs IOUT, VIN = 5.5V
IGND vs Temperature (TJ), VIN = 2.7V
Figure 8.
Figure 9.
IGND vs Temperature (TJ), VIN = 3.0V
IGND vs Temperature (TJ), VIN = 5.5V
Figure 10.
Figure 11.
Dropout Voltage (VDO) vs IOUT
Dropout Voltage (VDO) vs VIN
300
DROPOUT VOLTAGE, VDO(mV)
DROPOUT VOLTAGE, VDO(mV)
450
400
350
300 RDS(ON)= 200 m
250
200
150
100
50
0
200
150
100
50
0
0
250 500 750 1000 1250 1500
OUTPUT CURRENT (mA)
Figure 12.
6
IOUT= 500mA
250
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ = 25°C, VIN = 5.0V, VSHDN = VIN, VSET = 0.0V, VOUT = 2.5V, SS = Open, CIN = 1 µF, COUT = 1 µF
MLCC, IOUT = 100mA
PSRR vs Frequency
Output Noise Density
10
100
OUTPUT NOISE ( 9¥+])
90
80
PSRR (dB)
70
60
50
40
1
100m
30
20
10
0
10m
1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10
100
1k
10k
FREQUENCY (Hz)
Figure 14.
Figure 15.
Output Noise vs. IOUT
Output Noise
100
500
90
400
80
300
OUTPUT NOISE ( V)
OUTPUT NOISE ( VRMS)
100k
70
60
50
40
30
200
100
0
-100
-200
20
-300
10
-400
0
-500
1m
10m
100m
OUTPUT CURRENT (A)
1
0
10
20
30
TIME (ms)
40
50
Figure 16.
Figure 17.
Load Transient Response, VIN = 5.0V
Load Transient Response, VIN = 3.0V
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ = 25°C, VIN = 5.0V, VSHDN = VIN, VSET = 0.0V, VOUT = 2.5V, SS = Open, CIN = 1 µF, COUT = 1 µF
MLCC, IOUT = 100mA
Load Transient Response, 10mA to 3A
Line Transient Response, IOUT = 250mA
Figure 20.
Figure 21.
Line Transient Response, IOUT = 1A
VSHDN to VOUT Delay Time
Figure 22.
Figure 23.
SHDN Thresholds vs Temperature (TJ)
1.6
1.5
1.5
1.4
1.4
1.3
1.3
VSHDN(V)
VSHDN(V)
SHDN Thresholds vs VIN
1.6
1.2
1.1
Rising 'ON' Threshold
1.0
1.1
1.0
0.9
0.8
0.8
0.6
2.5
Rising 'ON' Threshold
0.7
Falling 'OFF' Threshold
3.0
3.5
4.0 4.5
VIN(V)
5.0
5.5
Figure 24.
8
1.2
0.9
0.7
VIN= 3.00V
Falling 'OFF' Threshold
0.6
-50 -25 0
25 50 75 100 125
TEMPERATURE, TJ(°C)
Figure 25.
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Typical Performance Characteristics (continued)
Unless otherwise specified: TJ = 25°C, VIN = 5.0V, VSHDN = VIN, VSET = 0.0V, VOUT = 2.5V, SS = Open, CIN = 1 µF, COUT = 1 µF
MLCC, IOUT = 100mA
SET Threshold (VSET(TH)) vs VIN
Soft-Start, CSS= 100nF
Figure 26.
Figure 27.
UVLO vs Temperature (TJ)
RST Output, VOUT Rising
2.70
UVLO THRESHOLD (V)
2.65
2.60
2.55
2.50
VINRising (ON)
2.46
2.40
2.35
2.30
2.25
VINFalling (OFF)
2.20
-50 -25 0
25 50 75 100 125
TEMPERATURE, TJ(°C)
Figure 28.
Figure 29.
RST Output, VOUT Falling
Figure 30.
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BLOCK DIAGRAM
IN
OUT
THERMAL
SENSOR
SHDN
SHUTDOWN
LOGIC
ERROR
AMPLIFIER
+
SENSE
RST
COMPARATOR
VSS
VRST(TH)
736 mV
RST
3 ms DELAY
TIMER &
INVERTER
+
VREF
800 mV
TSD
MOSFET DRIVER
WITH FOLDBACK
CURRENT LIMIT
-
PRE-SET MODE
ADJUSTABLE MODE
SET
ISS
6.7 µA
+
MODE
COMPARATOR
VSET(TH)
87 mV
SS
LP38869
GND
Figure 31. Functional Block Diagram
10
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APPLICATIONS INFORMATION
The LP38869 is a dual mode LDO that operates either as a fixed output, 2.5V regulator, or as an adjustable
output regulator from +0.8V to +5.0V. Output current is specified to be a minimum of 1A. The output requires a
minimum 1µF of capacitance for stability.
Referring to the functional block diagram at Figure 31, the device consists or a 800 mV reference (VREF), error
amplifier, MOSFET driver, P-channel pass transistor, internal feedback divider, soft-start function, reset timer,
and dual mode comparator, and a low VOUT (RST) comparator.
With the 800 mV reference connected to the error amplifier’s inverting input, the error amplifier compares this
reference with the selected feedback voltage and amplifies the difference. Usually the feedback voltage is
connected to the error amplifier’s inverting input, but in the case of the LP38869 the logic is inverted to drive a Pchannel MOSFET. The MOSFET driver takes the error amplifier output and applies the appropriate gate drive to
the P-channel transistor. For a high feedback voltage, the MOSFET gate is pulled higher, allowing less current to
flow to the output. The low VOUT comparator senses when the feedback voltage has dropped 8% below its
expected level, causing RST pin to go low. The Dual Mode comparator monitors the voltage at the SET pin and
selects the feedback path. If the SET pin voltage is below the typical 87 mV threshold, the internal feedback path
is used and the output voltage is regulated to the factory-preset voltage. Otherwise, the output voltage is set with
the external resistor-divider.
Capacitor Selection and Regulator Stability
Capacitors are required at the LP38869’s input and output. Connect a 1 µF or greater capacitor(s) between VIN
and GND (CIN), and between VOUT and GND (COUT). Due to the LP38869’s relatively high bandwidth, use only
surface mount ceramic capacitors that have a low equivalent series resistance (ESR) and high self-resonant
frequency (SRF). Make the input and output traces at least 2.5mm wide (the width of the four parallel pins), and
connect CIN and COUT within 6mm of the IC to minimize the impact of PC board trace inductance. The width of
the ground trace should be maximized underneath the IC to ensure a good connection between device pin 10
(GND) and the ground side of the capacitors.
The output capacitor’s ESR and SRF can affect stability and output noise. Use capacitors with a SRF of greater
than 5 MHz and with an ESR of 60 mΩ or less to insure stability and optimum transient response. This is
particularly true in applications with lower output voltage (VOUT < 2V) and higher output current (IOUT > 500 mA).
Since some capacitor dielectrics may vary over bias voltage and temperature, consult the capacitor manufacturer
specifications to ensure that the capacitors meet these requirements over all voltage and temperature conditions.
Internal P-Channel Pass Transistor
The LP38869 features a 1A P-channel MOSFET pass transistor. Unlike similar designs using PNP pass
transistors, P-channel MOSFETs require no continuous base (gate) drive, which reduces quiescent current. PNP
based regulators also waste considerable current in dropout when the pass transistor saturates and uses a high
base drive current under large loads. The LP38869 does not suffer from these problems and typically consumes
only 600 uA of quiescent current, even in dropout.
VIN
IN
IN
IN
CIN
1 PF
IN
OUT
OUT
OUT
VOUT
COUT
1 PF
OUT
LP38869
RST
ONOFFCSS
RESET
SET
SHDN
SS
GND
DAP
Figure 32. Typical Operating Circuit with Preset Output Voltage
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Input-Output (Drop Out) Voltage
A regulator’s minimum input-to-output voltage differential (dropout voltage) determines the lowest usable input
voltage. In battery-powered systems, this determines the useful end-of-life battery voltage. Since a 200 mΩ Pchannel MOSFET is used as the pass device, dropout voltage is the product of RDS(ON) and load current passing
through it. The LP38869 operating current remains low in dropout.
For output voltages that are less than the UVLO threshold, the UVLO threshold itself will determine the minimum
input voltage.
Output Voltage Selection
The LP38869 features Dual Mode operation. Connect the SET pin to GND as shown in Figure 32 for the Preset
Mode where the output voltage is preset at the factory. In the Adjustable Mode, set the output voltage between
+0.8V to +5.0V through two external resistors (R1 and R2) connected as a voltage divider to the SET pin as
shown in Figure 33. The output voltage is set by the following equation.
VOUT = VREF x (1 + (R1 / R2) )
(1)
where VREF = 800 mV.
Solving for R1 with a known value for R2:
R1 = R2 x ((VOUT / VREF) - 1)
(2)
In the Adjustable Mode the current through R1 and R2 should be much greater than the SET pin bias current to
minimize any error that the bias current may cause. Up to 10 kΩ is acceptable for R2, with R1 scaled for the
appropriate VOUT.
In the Pre-Set voltage mode, the impedance between the SET pin and ground should be less than 10 kΩ.
Otherwise, spurious conditions could cause the voltage at the SET pin to exceed the typical 87 mV Dual Mode
threshold.
In the Adjustable Mode the resistors used for R1 and R2 should be high quality, tight tolerance, and with
matching temperature coefficients. It is important to remember that, although the value of VREF is ensured, the
final value of VOUT in the Adjustable Mode is not. The use of low quality resistors for R1 and R2 can easily
produce an Adjustable Mode VOUT value that is unacceptable.
Shutdown Mode
A logic low on the SHDN pin disables the LP38869. In shutdown mode, the pass transistor, control circuitry,
reference, and all bias currents are turned off, reducing supply current to typically 2 µA. Connect SHDN to the IN
pin for continuous operation if the function is not needed. In shutdown mode the RST pin is low and the SoftStart capacitor is discharged.
RST Comparator
The open-drain RST pin goes low when VOUT falls 8% below its nominal output voltage. The RST pin remains
low for 3 ms after VOUT has returned to its normal value. A 100 kΩ pull-up resistor from the RST pin to a suitable
logic supply voltage (typically VOUT) provides a logic control signal. The RST output logic signal can be used as a
power on-reset signal to a micro-controller, or can drive an external LED for indicating a power failure. The RST
pin is low during shutdown. The RST status remains valid for VIN as low as 1V. When VIN is less than 1V the
RST pin status may not be valid.
12
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VIN
CIN
1 PF
IN
IN
IN
OUT
IN
OUT
VOUT
OUT
COUT
1 PF
OUT
LP38869
R1
RST
ONOFFCSS
SHDN
SS
DAP
RESET
SET
GND
R2
Figure 33. Typical Operating Circuit Adjustable Output Voltage
Soft-Start
As shown in Figure 34, a capacitor on the SS pin allows a gradual ramp-up of the LP38869’s output current,
reducing the initial in-rush current peaks at startup. When SHDN pin is driven low, the soft-start capacitor is
discharged to 0.0V. When the SHDN is driven high, or power is applied to the device, a constant 6.7 µA current
charges the Soft-Start capacitor from 0.0V. The resulting linear ramp voltage on SS increases the current-limit
comparator threshold, limiting the P-channel gate drive. While the voltage on the Soft-Start pin (VSS) is less than
approximately 300 mV there will be no output current. When Vss rises above approximately 300mV, the output
current limit will rise from zero to approximately 250 mA. As VSS continues to rise the current limit will also rise
proportionally so that when VSS is at typically 1.25V the current limit will be at approximately 1A. As the current
limit rises above 1A, the current limit control will pass from VSS to internal biasing circuitry. See the Soft-Start
Capacitor Selection section for details.
There is a delay time between when SHDN enables the LP38869 and when Soft-Start begins ramping up the
output current limit. This delay time allows the LP38869 internal biasing to fully turn on and settle. The delay time
is set by the time required for the Soft-Start charge current (ISS) to charge the Soft-Start capacitor from 0.0V to
typically 300 mV. This delay time accounts for approximately 25% of the total Soft-Start time (tSS). With a 100 nF
Soft-Start capacitor, the delay is approximately 4 ms with the remainder of the tSS time (approximately 15 ms)
allocated to raising the output current limit from zero to 1A.
Leaving the SS pin floating (open) will disable the Soft-Start feature by setting the tSS time to zero.
If the current demand from the load is significantly less than 1A, the time needed for the current limit to ramp up
to meet the actual current demand, after the delay time, will be a small fraction of the tSS time.
Soft-Start Capacitor Selection
Unlike typical Soft-Start circuits that control the rise of the output voltage, the LP38869 Soft-Start controls rise of
the output current limit. The resulting voltage rise across the load will depend on any reactive composition of the
load.
A capacitor (CSS) connected from the SS pin to GND causes the LP38869’s output current to slowly rise from
zero during start-up, reducing stress on the power path components and input supply. Soft-Start time (tSS) is
defined as the time from start-up (i.e. t = 0) until the current limit reaches 1A. The current limit will continue to
rise beyond 1A as the SS capacitor continues to charge to a higher voltage.
Typically, the current limit will be at 1A when the voltage on the SS capacitor (Vss) has charged to 1.25V.
The time from start-up (VSS = 0V) to when the output current limit reaches 1A (VSS = 1.25V) , can be estimated
by:
tSS = (CSS / ISS) x 1.25V
(3)
This can be simplified to:
tSS = 0.186 x CSS
(4)
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where CSS is in nF, and the calculated tSS result is in milli-seconds.
Typical Soft-Start capacitor values are between 10nF to 100nF. The typical tSS with a CSS of 100 nF is:
tSS = (100 nF / 6.7 uA ) x 1.25V = 18.6 ms
(5)
Use of a low leakage capacitor for CSS is required, and voltage rating of 5V for CSS is adequate.
Because the CSS ramp is applied to the output current-limit comparator, the actual time for the output voltage to
ramp-up depends on the actual load current demand and output capacitor value. Leaving the SS pin open will
disable the Soft-Start behavior by setting the tSS time to zero.
Current Limiting
The LP38869 features a 2A current limit when the output voltage is in regulation. When the output voltage drops
by 8% below its nominal value, the current limit folds back to 1.7A. While the LP38869 output can be shorted to
ground for an indefinite period of time without damaging the device, power dissipation due to continuous output
currents of more than 1A may stress, or damage, adjacent components. The nominal current limit can be
reduced by holding the voltage at the Soft-Start (SS) pin below 1.25V. For VSS rising from approximately 300 mV
to 1,25V the current limits scale proportionately with the VSS by:
ILIM = 1A x (VSS / 1.25V)
(6)
Since the SS pin sources a typical 6.7 µA current (ISS), the current limit can be reduced below 1A by connecting
a resistor (RSS) between the SS pin and GND, so that:
ILIM = 1A x (( ISS x RSS) / 1.25V))
(7)
where the typical ISS = 6.7 µA.
The useful range of RSS values is approximately 75 kΩ to 200 kΩ. RSS values less than 75 kΩ may not be able to
reliably raise VSS above the minimum needed (typically 300 mV) to activate the current limit. RSS values greater
than 200 kΩ will only have a marginal impact on the nominal current limit.
With RSS in place, Soft-Start can still be achieved by placing a capacitor (CSS) in parallel with RSS. The output
current now ramps up asymptotically to the reduced current limit rather than the nominal value, increasing the
soft-start time. The time required for the current limit to reach 90% of its steady-state value with RSS in place is
estimated by:
tSS = 2.5 x RSS x CSS
(8)
VIN
CIN
1 PF
IN
IN
IN
OUT
OUT
IN
OUT
VOUT
COUT
1 PF
OUT
LP38869
R1
RST
ONOFFRSS
CSS
SHDN
SS
DAP
RESET
SET
GND
R2
Figure 34. Typical Operating Circuit Soft-Start and Current Limit Reduction
14
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Figure 35. Typical Soft-Start Current Limit Behavior with CSS = 100 nF
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the LP38869. When the junction temperature
exceeds typically TJ = +160°C, the thermal sensor turns off the pass transistor, allowing the LP38869 to cool.
The thermal sensor turns the pass transistor on once the IC’s junction temperature drops by approximately 15°C.
Continuous short-circuit conditions will eventually result in a pulsed output current with a frequency that depends
on the thermal resistance and thermal mass of the LP38869 package and PC board combination as well as the
ambient temperature. Thermal overload protection is designed to protect the LP38869 in the event of fault
conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of TJ =
150°C. Parametric ratings are not ensured if the junction rises above 125°C.
Operating Region and Power Dissipation
Maximum power dissipation of the LP38869 depends on the thermal resistance of the case and circuit board, the
temperature difference between the die junction and ambient air, and the rate of air flow. The power dissipation
across the device is defined by:
PDISS = IOUT X (VIN – VOUT)
(9)
The resulting maximum power dissipation is:
PDISS(MAX) = (TJ(MAX) - TA(MAX)) / (θJA
(10)
Where (TJ(MAX) - TA(MAX)) is the maximum allowable junction temperature rise above the surrounding ambient air;
and θJA is thermal resistance from the junction through the package DAP, to the PC board, copper traces, and
other materials into the surrounding air.
Figure 36 uses this formula to show a range of allowable dissipation values that will keep the junction
temperature (TJ(MAX)) inside the Maximum Operating Junction Temperature of 125°C.
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4.0
JA= 50°C/W
3.5
JA= 56°C/W
PDISS(MAX)(W)
3.0
JA= 65°C/W
2.5
JA= 131°C/W
2.0
1.5
1.0
0.5
0.0
-50 -25
0
25 50 75 100 125
AMBIENT TEMPERATURE, TA(°C)
Figure 36. Maximum Dissipation vs. Ambient Temperature
Figure 37 shows the allowable power dissipation factors for a typical multi-layer PC board at ambient
temperatures of +25°C, +50°C, and +70°C for the AbsMax junction temperature of 150°C.
OUTPUT CURRENT (A)
1.2
1.0
0.8
0.6
TA= 75°C
TA= 50°C
0.4
TA= 25°C
0.2
0.0 For TJ= 150°C and
0
1
JA= 50°C/W
2
3
VIN- VOUT(V)
4
5
Figure 37. Maximum Output Current vs Input-Output Differential Voltage
The LP38869 HTSSOP package features an exposed thermal pad on its underside. This exposed pad lowers the
package’s thermal resistance by providing a direct thermal heat path from the die to the PC board. Connect the
exposed thermal pad to circuit ground using a large copper pad (1 square inch is the recommended minimum),
or use multiple thermal vias to the ground plane of a multi-layer PCB.
For the LP38869MH in the HTSSOP Exposed Pad 16-Lead package, the junction-to-case thermal rating, θJC, is
16.2°C/W, where the case is the bottom of the package at the center of the Exposed Pad. Typical junction-toambient thermal performance for the LP38869MH, using the JESD51 standards, is summarized in the following
table.
16
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BOARD TYPE
THERMAL VIAS
θJA
JEDEC 2-Layer
JESD 51-3
None
141°C/W
0
131°C/W
1
78°C/W
2
65°C/W
3
59°C/W
4
56°C/W
6
53°C/W
9
50°C/W
JEDEC 4-Layer
JESD 51-7
Noise, PSRR, and Transient Response
The LP38869 is designed to achieve low dropout voltage and low quiescent current in battery-powered systems
while still maintaining good noise, transient response, and AC rejection (see PSRR vs. Frequency in the Typical
Operating Characteristics). When operating from very noisy sources, supply noise rejection and transient
response can be improved by increasing the input and output capacitor values and employing passive post
filtering. The LP38869 output noise is typically 50 µVRMS.
Reverse Input-Output Voltage
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed. Alternately, this could also happen if a secondary supply is
connected to the LP38869 output.
While VIN is greater than the UVLO threshold, and the SHDN pin is above the VSHDN(ON) threshold, the control
loop circuitry will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the
control circuit will drive the gate of the pass element to the full ON condition when the output voltage begins to
fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of
the pass element and the output to input voltage differential. This will condition will continue until VIN falls below
the UVLO threshold, or the SHDN pin voltage falls below the VSHDN(OFF) threshold.
The internal PFET pass element in the LP38869 has an inherent parasitic (body) diode. During normal operation,
the input voltage is higher than the output voltage and the body diode is reverse biased. However, if the output is
turned OFF, either by VIN < UVLO or VSHDN < VSHDN(OFF), and the output voltage is more than 500 mV (typical)
above the input voltage the body diode becomes forward biased and current flows from the output pin to the
input pin through the body diode.
The reverse current in the body diode should be limited to less than 1A continuous and less than 5A peak.
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LP38869MH/NOPB
ACTIVE
HTSSOP
PWP
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP38869
MH
LP38869MHE/NOPB
ACTIVE
HTSSOP
PWP
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP38869
MH
LP38869MHX/NOPB
ACTIVE
HTSSOP
PWP
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP38869
MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LP38869MHE/NOPB
HTSSOP
PWP
16
250
178.0
12.4
LP38869MHX/NOPB
HTSSOP
PWP
16
2500
330.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
8.3
1.6
8.0
12.0
Q1
6.95
8.3
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP38869MHE/NOPB
HTSSOP
PWP
LP38869MHX/NOPB
HTSSOP
PWP
16
250
210.0
185.0
35.0
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0016A
MXA16A (Rev A)
www.ti.com
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