ISSI IS31AP2121 2x20w stereo / 1x 40w mono digital audio amplifier Datasheet

IS31AP2121
2X20W STEREO / 1X 40W MONO DIGITAL AUDIO AMPLIFIER
WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE
Preliminary Information
October 2014
GENERAL DESCRIPTION
FEATURES
The IS31AP2121 is a digital audio amplifier capable of
driving 20W (BTL) each to a pair of 8Ω speakers and
40W (PBTL) to a 4Ω speaker operating at 24V supply
without external heat-sink or fan. The IS31AP2121 is
also capable of driving 4Ω, 10W (SE)x2 + 8Ω, 20W
(BTL)x1 at 24V supply for 2.1CH application.

The IS31AP2121 can provide advanced audio
processing functions, such as volume control, 20 EQ
bands, audio mixing, 3D surround sound and Dynamic
Range Control (DRC). These are fully programmable
via a simple I2C control interface. Robust protection
circuits are provided to protect the IS31AP2121 from
damage due to accidental erroneous operating
condition. The full digital circuit design of IS31AP2121
is more tolerant to noise and PVT (Process, Voltage,
and Temperature) variation than the analog Class-AB
or Class-D audio amplifier counterpart implemented by
analog circuit design. IS31AP2121 is pop free during
instantaneous power on/off or mute/shut down
switching because of its robust built-in anti-pop circuit.
APPLICATIONS

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
TV audio
Boom-box, CD and DVD receiver, docking system
Powered speaker
Wireless audio

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16/18/20/24-bits input with I2S, Left-alignment and
Right-alignment data format
PSNR & DR (A-weighting)
Loudspeaker: 104dB (PSNR), 110dB (DR) @24V
Multiple sampling frequencies (FS)
- 32kHz / 44.1kHz / 48kHz and
- 64kHz / 88.2kHz / 96kHz and
- 128kHz / 176.4kHz / 192kHz
System clock = 64x, 128x, 192x, 256x, 384x,
512x, 576x, 768x, 1024x Fs
- 64x~1024x FS for 32kHz / 44.1kHz / 48kHz
- 64x~512x FS for 64kHz / 88.2kHz / 96kHz
- 64x~256x FS for 128kHz / 176.4kHz / 192kHz
Supply voltage
- 3.3V for digital circuit
- 10V~26V for speaker driver
Supports 2.0CH/2.1CH/Mono configuration
Loudspeaker output power for at 24V
- 10W × 2CH into 8Ω @0.16% THD+N for stereo
- 15W × 2CH into 8Ω @0.19% THD+N for stereo
- 20W × 2CH into 8Ω @0.25% THD+N for stereo
Sound processing including:
- 20 bands parametric speaker EQ
- Volume control (+24dB ~ -103dB, 0.125dB/step),
- Dynamic range control (DRC)
- Dual band dynamic range control
- Power clipping
- 3D surround sound
- Channel mixing
- Noise gate with hysteresis window
- Bass/Treble tone control
- Bass management crossover filter
- DC-blocking high-pass filter
Anti-pop design
Short circuit and over-temperature protection
Supports I2C control without MCLK
I2C control interface with selectable device
address
Support BCLK system
Support hardware and software reset
Internal PLL
LV Under-voltage shutdown and HV Under-voltage
detection
Power saving mode
1
IS31AP2121
TYPICAL APPLICATION CIRCUIT
Figure 1 Typical Application Circuit (For Stereo)
VCC
2
470 F 0.1 F 0.1 F
47
48
VDD
1M
1M
3,44
4.7k
4.7k
23
24
25
Micro
Controller
19
1 F
1 F
14
15
21
Digital
Audio
Source
20
22
VCCLA
VCCRA
VCCLB
VCCRB
GNDL
34,41
37
38 0.1 F 0.1 F
GNDR
8
PBTL
SDA
DVDD
SCL
DGND
RSTB
PDB
VCC
35
VDD
470 F
OUTLA
330pF
13,27
9,28
1
46
OUTLB
330pF
39
OUTRB
SDATA
BEAD
Speaker
4
*Note 4
15 H
6A
18
36
1nF
220nF
330pF
LRCIN
100nF
BEAD
OUTLB
OUTRA
MCLK
OUTRA
*Note 2
0.1 F
18
OUTLA
BCLK
*Note 4
15 H
6A
18
IS31AP2121
ERRORB
BEAD
100nF
1nF
18
330pF
BEAD
OUTRB
Figure 2 Typical Application Circuit (For Mono)
Pin
Logic
0
1
PDB
Power Down
Normal
RSTB
Reset
Normal
PBTL
Stereo
Mono
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IS31AP2121
Figure 3 Typical Application Circuit (For 2.1CH) (Note 5)
Pin
Logic
0
1
PDB
Power Down
Normal
RSTB
Reset
Normal
PBTL
X
X
Note 1: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 7A.
Note 2: These capacitors should be placed as close to speaker jack as possible, and their values should be determined according to EMI test
results.
Note 3: The snubber circuit can be removed while the VCC ≤20V.
Note 4: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 14A.
Note 5: 2.1CH configuration, it programs by I2C via register address 0x11, D4 bit SEM.
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IS31AP2121
PIN CONFIGURATION
Pin Configuration (Top View)
48
47
46
45
44
43
42
41
40
39
38
37
GNDL
GNDL
OUTLB
NC
VCCLB
NC
NC
VCCRB
NC
OUTRB
GNDR
GNDR
Package
DVDD
ERRORB
MCLK
NC
NC
NC
PDB
LRCIN
BCLK
SDATA
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
eLQFP-48
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IS31AP2121
PIN DESCRIPTION
No.
Pin
Description
1
OUTLA
Left channel output A.
2
VCCLA
Left channel supply A.
3,44
VCCLB
Left channel supply B.
4~6,10~12
NC
Not connected.
7
CLK_OUT
PLL ratio setting pin during power up, this pin
is monitored on the rising edge of reset. PMF
register will be default set at 1 or 4 times PLL
ratio.
Low: PMF [3:0]=[0000], 1 time of PLL ratio to TTL output buffer, internal pull low with
avoid system MCLK over flow. High: PMF
an 80kΩ resistor.
[3:0]=[0100], 4 times of PLL ratio.
This pin could be clock output pin also during
normal operating if EN_CLK_OUT register bit
is enabled.
8
PBTL
Stereo/mono configuration pin (Low: Stereo;
High: Mono).
9,28
DGND
Digital ground.
13,27
DVDD
Digital power.
14
ERRORB
ERRORB pin is a dual function pin. One is
I2C address setting during power up. The
other one is error status report (low active). It
sets by register of A_SEL_FAULT at address
0x13 D6 to enable it.
This pin is monitored on the rising edge
of reset. A value of Low (15kΩ pull
down) sets the I2C device address to
0x30 and a value of High (15kΩ pull up)
sets it to 0x31.
15
MCLK
Master clock input.
Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩ resistor.
16~18,26
NC
Not connected.
19
PDB
Power down, low active.
Schmitt trigger TTL input buffer, internal
pull High with a 330kΩ resistor.
20
LRCIN
Left/Right clock input (FS).
Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩ resistor.
21
BCLK
Bit clock input (64FS).
Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩ resistor.
22
SDATA
I2S serial audio data input.
Schmitt trigger TTL input buffer
23
SDA
I2C serial data.
Schmitt trigger TTL input buffer
24
SCL
I2C serial clock input.
Schmitt trigger TTL input buffer
25
RSTB
Reset, low active.
Schmitt trigger TTL input buffer, internal
pull High with a 330kΩ resistor.
29~33,40
NC
Not connected.
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Characteristics
5
IS31AP2121
PIN DESCRIPTION (CONTINUE)
No.
Pin
Description
34,41
VCCRB
Right channel supply B.
35
VCCRA
Right channel supply A.
36
OUTRA
Right channel output A.
37,38
GNDR
Right channel ground.
39
OUTRB
Right channel output B.
42,43,45
NC
Not connected.
46
OUTLB
Left channel output B.
47,48
GNDL
Left channel ground.
Thermal Pad
Connect to DGND.
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Characteristics
6
IS31AP2121
ORDERING INFORMATION
INDUSTRIAL RANGE: 0°C TO +70°C
Order Part No.
Package
QTY
IS31AP2121-LQLS1
e-LQFP-48, Lead-free
250/Tray
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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IS31AP2121
ABSOLUTE MAXIMUM RATINGS
Supply for driver stage (VCCR, VCCL), VCC
Supply for digital circuit (DVDD), VDD
Input voltage (SDA,SCL,RSTB,PDB,ERRORB,MCLK,
BCLK,LRCIN,SDATA,PBTL), VIN
Thermal resistance, θJA
Junction temperature range, TJ
Storage temperature range, TSTG
ESD (HBM)
ESD (CDM)
-0.3V ~ +30V
-0.3V ~ +3.6V
-0.3V ~ +3.6V
27.4°C/W
0°C ~ 150°C
-65°C ~ +150°C
TBD
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply for driver stage to VCCR/L
VDD
Supply for digital circuit
Condition
Min.
Typ.
Max.
Unit
10
26
V
3.15
3.45
V
TJ
Junction operating temperature
0
125
°C
TA
Ambient operating temperature
0
70
°C
Typ.
Max.
Unit
DC ELECTRICAL CHARACTERISTICS
TA=25°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
IPDH
VCC supply current during power down VCC = 24V
10
200
µA
IPDL
DVDD supply current during power
down
VDD = 3.3V, PBTL=Low
13
20
µA
ICCH
Quiescent current for VCC (50%/50%
PWM duty)
VCC = 24V
37
mA
ICCL
Quiescent current for DVDD (Un-mute) VDD = 3.3V, PBTL=Low
70
mA
VUVH
Under-voltage disabled (For DVDD)
2.8
V
VUVL
Under-voltage enabled (For DVDD)
2.7
V
RDS(ON)
ISC
TS
Static drain-to-source on-state resistor,
PMOS
Static drain-to-source on-state resistor,
NMOS
L/R channel over-current protection
Mono channel over-current protection
260
VCC =24V, ID = 500mA
mΩ
230
VCC =24V, ID =500mA
(Note 1)
7
14
A
Junction temperature for driver
shutdown
158
°C
Temperature hysteresis for recovery
from shutdown
33
°C
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IS31AP2121
DC ELECTRICAL CHARACTERISTICS (CONTINUE)
TA=25°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Logic Electrical Characteristics
VIH
High level input voltage
VDD =3.3V
VIL
Low level input voltage
VDD =3.3V
VOH
High level output voltage
VDD =3.3V
VOL
Low level output voltage
VDD =3.3V
CIN
Input capacitance
2.0
V
0.8
2.4
V
V
0.4
6.4
V
pF
Note 1: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly connected with external LC filters. Please
refer to the application circuit example for recommended LC filter configuration.
AC ELECTRICAL CHARACTERISTICS
TA=25°C, VCC=24V, VDD = 3.3V, fS = 48kHz, RL=8Ω with passive LC lowpass filter (L= 15µH, RDC= 63mΩ,
C=220nF), input is 1kHz sinewave, volume is 0dB unless otherwise specified.
Symbol
PO
Parameter
RMS output power (Note 2)
Condition
Min.
Typ.
THD+N=0.25%, +8dB volume
20
THD+N=0.19%, +8dB volume
15
THD+N=0.16%, +8dB volume
10
Max.
Unit
W
Total harmonic distortion +
noise
PO = 7.5W
0.15
%
VNO
Output noise
20Hz ~ 20kHz (Note 3)
120
µV
SNR
Signal-to-noise ratio
+8dB volume, input level is -9dB
(Note 3)
104
dB
Dynamic range
+8dB volume, input level is -68dB
(Note 3)
110
dB
Power supply ripple rejection VRIPPLE = 1VRMS at 1kHz
-71
dB
Channel separation
-81
dB
THD+N
DR
PSRR
1W @1kHz
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IS31AP2121
I2C DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)
Standard Mode
Symbol
Fast Mode
Parameter
Unit
Min.
Max.
Min.
Max.
0
100
0
400
fSCL
Serial-Clock frequency
tBUF
Bus free time between a STOP and a START
condition
4.7
1.3
μs
tHD, STA
Hold time (repeated) START condition
4.0
0.6
μs
tSU, STA
Repeated START condition setup time
4.7
0.6
μs
tSU, STO
STOP condition setup time
4.0
0.6
μs
tHD, DAT
Data hold time
0
tSU, DAT
Data setup time
250
100
ns
tLOW
SCL clock low period
4.7
1.3
μs
tHIGH
SCL clock high period
4.0
0.6
μs
3.45
0
0.9
kHz
μs
tR
Rise time of both SDA and SCL signals,
receiving
1000
20+0.1Cb
300
ns
tF
Fall time of both SDA and SCL signals,
receiving
300
20+0.1Cb
300
ns
Cb
Capacitive load for each bus line
400
400
pF
VNL
Noise margin at the low level for each
connected device (including hysteresis)
0.1VDD
0.1VDD
V
VNH
Noise margin at the high level for each
connected device (including hysteresis)
0.2VDD
0.2VDD
V
I2S DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)
Symbol
Parameter
Condition
Min.
10.41
Typ.
Max.
Unit
31.25
μs
tLR
LRCIN period (1/FS)
tBL
BCLK rising edge to LRCIN edge
50
ns
tLB
LRCIN edge to BCLK rising edge
50
ns
tBCC
BCLK period (1/64FS)
162.76
488.3
ns
tBCH
BCLK pulse width high
81.38
244
ns
tBCL
CBLK pulse width low
81.38
244
ns
tDS
SDATA set up time
50
ns
tDH
SDATA hold time
50
ns
Note 2: Thermal dissipation is limited by package type and PCB design. The external heat-sink or system cooling method should be adopted
for maximum power output.
Note 3: Measured with A-weighting filter.
Note 4: Guaranteed by design.
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IS31AP2121
Figure 4 I2C Timing
Figure 5 I2S
Figure 6 Left-Alignment
Figure 7 Right-Alignment
Figure 8 System Clock Timing
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IS31AP2121
Figure 9 Timing Relationship (Using I2S format as an example)
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IS31AP2121
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
VCC = 24V
RL = 8Ω
Strero
10
5
2
THD+N(%)
THD+N(%)
5
RL = 8Ω
VCC = 24V
Strereo
10
1
0.5
10kHz
0.2
0.1
2
PO = 10W
1
PO = 5W
0.5
PO = 1W
0.2
0.1
0.05
1kHz
20Hz
PO = 0.25W
0.05
0.02
PO = 0.5W
0.02
0.01
1m
5m 10m
50m 100m
500m 1
2
5
10 20
0.01
20
50
50
100
200
Output Power(W)
1k
2k
20k
5k
Frequency(Hz)
Figure 10 THD+N vs. Output Power
Figure 11 THD+N vs. Frequency
+2
+0
VCC = 24V
RL = 8Ω
PO = 1W
Stereo
+1.5
VCC = 24V
RL = 8Ω
Stereo
-20
Crosstalk(dB)
+1
+0.5
dBr
500
+0
-0.5
-40
-60
-80
Left to Right
1
-100
-1.5
-2
20
Right to Left
50
100
200
500
1k
2k
5k
10k
-120
20
20k
50
100
200
Frequency(Hz)
10k
20k
16k
18k 20k
VCC = 24V
RL = 8Ω
Stereo
+0
-20
-20
-30
-40
-40
dBV
dBV
5k
+20
VCC = 24V
RL = 8Ω
Stereo
-10
2k
Figure 13 Cross-Talk
+20
+0
1k
Frequency(Hz)
Figure 12 Frequency Response
+10
500
-50
-60
-60
-80
-70
-80
-100
-90
-100
-110
-120
-120
0k
2k
4k
6k
8k
10k
12k
14k
16k
Frequency(Hz)
Figure 14 Spectrum at Peak SNR at -1dB Signal Input
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18k 20k
-140
0k
2k
4k
6k
8k
10k
12k
14k
Frequency(Hz)
Figure 15 Spectrum at -60dB Signal Input Level
13
IS31AP2121
100
VCC=12V
VCC=8V
90
Efficiency(%)
80
VCC=15V
70
60
VCC=18V
50
VCC=24V
40
30
20
RL = 8Ω
Stereo
10
0
0
5
10
15
20
25
30
35
40
45
50
Output Power(W)
Figure 16 Efficiency vs. Output Power (Power Saving Mode)
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IS31AP2121
FUNCTIONAL BLOCK DIAGRAM
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IS31AP2121
APPLICATIONS INFORMATION
IS31AP2121 has a built-in PLL internally, the default
volume is muted. IS31AP2121 will activate while the
de-mute command via I2C is programmed.
PDB
PDB
OPERATION MODES
Without I2C Control
The default settings, Bass, Treble, EQ, Volume,
DRC, PLL, Subwoofer Bandwidth, …, and Subwoofer gain are applied to register table content
when using IS31AP2121 without I2C control. The
more information about default settings, please refer
to the highlighted column of register table section.
-103dB
Figure 17 Power Down Timing Diagrams With Mute
With I2C Control
When using I2C control, user can program suitable
parameters into IS31AP2121 for their specific
applications. Please refer to the register table
section to get the more detail.
PDB
PDB
INTERNAL PLL
IS31AP2121 has a built-in PLL internally. The
MCLK/FS ratio will be fixed at 1024x, 512x, or 256x
with a sample frequency of 48kHz, 96kHz, or
192kHz respectively. A carrier clock frequency is the
frequency divided by 128 of master clock.
-103dB
Table 1 MCLK/FS Ratio
FS
MCLK Frequency
48kHz
49.152MHz
44.1kHz
45.158MHz
32kHz
32.768MHz
RESET
When the RSTB pin is lowered, IS31AP2121 will
clear the stored data and reset the register table to
default values. IS31AP2121 will exit reset state at
the 256th MCLK cycle after the RSTB pin is raised to
high.
POWER DOWN CONTROL
IS31AP2121 has a built-in volume fade-in/fade-out
design for power down and mute function. The
relative power down timing diagrams for
loudspeakers are shown below.
Figure 18 Power Down Timing Diagrams
The volume level will be decreased to -∞dB in
several LRCIN cycles. Once the fade-out procedure
is finished, IS31AP2121 will turn off the power
stages, stop clock signals (MCLK, BCLK) from
feeding into digital circuit and turn off the current of
the internal analog circuits. After PDB pin is pulled
low, IS31AP2121 needs up to 256 LRCIN clocks to
finish the above works before entering power down
state. Users can’t program IS31AP2121 during
power down state, but all the settings of register
table will still be kept except that DVDD is removed.
If the PD function is disabled in the midway of the
fade-out procedure, IS31AP2121 will also execute
the fade-in procedure. In addition, IS31AP2121 will
establish the analog circuits’ bias current and feed
the clock signals (MCLK, BCLK) into digital circuits.
Then, IS31AP2121 will return to its normal operation
without power down.
SELF-PROTECTION CIRCUITS
IS31AP2121 has built-in protection circuits including
thermal, short-circuit and under-voltage detection
circuits.
Thermal Protection
When the internal junction temperature is higher
than 158°C, power stages will be turned off and
IS31AP2121 will return to normal operation once the
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IS31AP2121
temperature drops to 125°C. The temperature
values may vary around 10%.
Low indicates an I2C address of 0x30, and high an
address of 0x31.
Short-Circuit Protection
OUTPUT CONFIGURATION
The short-circuit protection circuit protects the output
stage when the wires connected to loudspeakers are
shorted to each other or GND/VDD. For normal 24V
operations, the current flowing through the power
stage will be less than 7A for stereo configuration or
less than 14A for mono configuration. Otherwise, the
short-circuit detectors may pull the ERRORB pin to
DGND, disabling the output stages. When the overtemperature or short-circuit condition occurs, the
open-drain ERRORB pin will be pulled low and
latched into ERROR state.
The bit 4 [SEM] of address 0X11 and PBTL pin
defines the configuration mode. IS31AP2121 can be
configured to stereo, mono via PBTL pin (the bit 4
[SEM] of address 0X11 default is low). 2.1CH output
mode configuration, user can via I2C to program it
from the bit 4 [SEM] of address 0X11. Table 2
provides a reference of available configuration.
Once the over-temperature or short-circuit condition
is removed, IS31AP2121 will exit ERROR state
when one of the following conditions is met: (1)
RSTB pin is pulled low. (2) PDB pin is pulled low. (3)
Master mute is enabled through the I2C interface.
Table 2 Output Configurations
[SEM]
PBTL
Configuration Mode
0
0
Stereo
0
1
Mono
1
x
2.1CH
Under-voltage Protection
Once the VDD voltage is lower than 2.7V,
IS31AP2121 will turn off its loudspeaker power
stages and cease the operation of digital processing
circuits. When VDD becomes larger than 2.8V,
IS31AP2121 will return to normal operation.
ANTI-POP DESIGN
IS31AP2121 will generate appropriate control
signals to suppress pop sounds during initial power
on/off, power down/up, mute, and volume level
changes.
3D SURROUND SOUND
IS31AP2121 provides the virtual surround sound
technology with greater separation and depth voice
quality for stereo signals.
I2C CHIP SELECT
Figure 19 Output Configurations
ERRORB is an input pin during power. It can be
pulled High (15kΩ pull up) or Low (15kΩ pull down).
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IS31AP2121
POWER ON SEQUENCE
Hereunder is IS31AP2121’s power on sequence. Give a de-mute command via I2C when the whole system is
stable.
Figure 20 Power On Sequence
Table 2 Power On Sequence
Symbol
Condition
POWER OFF SEQUENCE
Hereunder is IS31AP2121’s power off sequence.
Min.
Max.
Unit
t1
0
-
ms
VCC
t2
0
-
ms
VDD
t3
10
-
ms
t4
0
-
ms
MCLK
t5
10
-
ms
BCLK
LRCIN
t6
10
-
ms
RSTB
t7
0
-
ms
t8
200
-
ms
t9
20
-
ms
I2C
OUT
t10
DEF=L
-
0.1
ms
t11
DEF=H
-
0.1
ms
t12
25
-
ms
t13
25
-
ms
t14
-
22
ms
-
0.1
ms
t15
DEF=L or H
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PDB
t4
t5
t3
t2
t1
Don’t Care
Figure 21 Power Off Sequence
18
IS31AP2121
Table 3 Power Off Sequence
Symbol
Min.
t1 (With I2C Control)
35ms
t1 (Without I2C Control)
5ms
t2
0ms (Note)
t3
0ms
t4
1ms
t5
1ms
Note: When t2 is less than 0.1ms, pop noise may
occur.
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19
IS31AP2121
I2C-BUS TRANSFER PROTOCOL
INTRODUCTION
IS31AP2121 employs I2C-bus transfer protocol. Two
wires, serial data and serial clock carry information
between the devices connected to the bus. Each
device is recognized by a unique 7-bit address and
can operate as either a transmitter or a receiver. The
master device initiates a data transfer and provides
the serial clock on the bus. IS31AP2121 is always
an I2C slave device.
PROTOCOL
START and STOP Condition
START is identified by a high to low transition of the
SDA signal. A START condition must precede any
command for data transfer. A STOP is identified by a
low to high transition of the SDA signal. A STOP
condition terminates communication between
IS31AP2121 and the master device on the bus. In
both START and STOP, the SCL is stable in the
high state.
only occurs when SCL signal is low. IS31AP2121
samples the SDA signal at the rising edge of SCL
signal.
Device Addressing
The master generates 7-bit address to recognize
slave devices. When IS31AP2121 receives 7-bit
address matched with 0110000 or 0110001
(ERRORB pin state during power up), IS31AP2121
will acknowledge at the 9th bit (the 8th bit is for R/W
bit). The bytes following the device identification
address are for IS31AP2121 internal sub-addresses.
Data Transferring
Each byte of SDA signaling must consist of 8
consecutive bits, and the byte is followed by an
acknowledge bit. Data is transferred with MSB first,
as shown in the figure below. In both write and read
operations, IS31AP2121 supports both single-byte
and multi-byte transfers. Refer to the figure below for
detailed data-transferring protocol.
Data Validity
The SDA signal must be stable during the high
period of the clock. The high or low change of SDA
Figure 22 Data Transferring
REGISTER DEFINITIONS
The IS31AP2121’s audio signal processing data flow is shown below. Users can control these functions by
programming appropriate settings in the register table. In this section, the register table is summarized first. The
definition of each register follows in the next section.
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IS31AP2121
Dual Band DRC Enable (Only for stereo mode, PBTL=Low)
Dual Bands DRC Disable
L
LRCIN
ASRC
PreScal
BCLK
M11
EQ1
EQ2
EQ7
EQ8
LCH
EQ1
EQ2
EQ7
EQ8
RCH
EQ1
EQ2
EQ3
EQ4
M12
SDATA
I2S
M21
R
MCLK
ASRC
PreScal
PLL
M22
M31
SUB
M32
LCH
HPF
RCH
HPF
RCH
LPF
Surround
Surroun
DRC1
Clipping
1
HPFdc
PostScal
2
FIR
S/H2
SDM
Volume
DRC1
Clipping
1
HPFdc
PostScal
2
FIR
S/H2
SDM
Volume
DRC2
Clipping
2
HPFdc
PostScal
2
FIR
S/H2
SDM
Volume
OUTLA
PWM
OUTLB Power
OUTRA Stage
OUTRB
I2C
SCL
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SDA
21
IS31AP2121
Table 4 Register Function
Address
Name
Table
Default
00h
State Control 1 Register
5
000x 0100
01h
State Control 2 Register
6
x000 0100
02h
State Control 3 Register
7
0xxx 1111
03h
Master Volume Control Register
8
0001 1000
04h~06h
Channel 1~3 Volume Register
9
0001 0100
07h,08h
Bass/Treble Tone Register
10
xxx1 0000
09h
Bass Management Crossover Frequency Register
11
xxxx 0010
0Ah
State Control 4 Register
12
1001 0000
Channel 1~2 Configuration Register
13
xxx1 0010
0Dh
Channel 3 Configuration Register
14
xxx1 0000
0Eh
DRC Limiter Attack/Release Rate Register
15
0110 1010
-
-
0Bh~0Ch
0Fh~10h
Reserved
11h
State Control 5 Register
16
xx11 0010
12h
VCC Under-voltage Selection Register
17
1xxx 0001
13h
Noise Gate Gain Register
18
x000 xx00
14h
Coefficient RAM Base Address Register
19
x000 0000
20~24
-
25
xxxx 0000
-
-
15h~23h
24h
25h~29h
User-Defined Coefficients Register
Coefficients Control Register
Reserved
2Ah
Power Saving Mode Switching Level Register
26
xxx0 1101
2Bh
Volume Fine Tune Register
27
0011 1111
Note: The reserved registers are not allowed to write any bits in them, or the IC will be abnormal.
Table 5 00h State Control 1 Register
Bit
D7:D5
D4
D3
Name
IF
-
PWML_X
Default
000
x
0
Bit
D2
D1
D0
Name
PWMR_X
LV_UVSEL
LREXC
Default
1
0
0
IS31AP2121 supports multiple serial data input
formats including I2S, Left-alignment and Rightalignment. These formats are selected by users via
D7~D5 of address 00h. The left/right channels can
be exchanged to each other by programming to
address 00h/D0, LREXC.
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IF
000
001
010
011
100
101
Others
Input Format
I2S 16-24 bits
Left-alignment 16-24 bits
Right-alignment 16 bits
Right-alignment 18 bits
Right-alignment 20 bits
Right-alignment 24 bits
Not available
PWML_X
0
1
OUTLA/B exchange
No exchanged
L/R exchanged
PWMR_X
0
1
OUTRA/B exchange
L/R exchanged
No exchanged
22
IS31AP2121
LV_UVSEL
0
1
LV Under-voltage Selection
2.7V
3.0V
LREXC
0
1
Left/Right Channel Exchanged
No exchange
L/R exchange
Table 6 01h State Control 2 Register
Bit
D7:
D6
D5:D4
D3:D0
Name
-
BCLK_SEL
FS
PMF
Default
x
0
00
0100
IS31AP2121 has a built-in PLL and multiple
MCLK/Fs ratios are supported. Detail setting is
shown in the following table.
BCLK_SEL
0
1
MCLK-less (BCLK system)
Disabled
Enable
FS
00
01
1x
Sampling Frequency
32/44.1/48kHz
64/88.2/96kHz
128/176.4/192kHz
Multiple MCLK/FS Ratio Setting
1024x(FS=00)/ 512x(FS=01)/
256x(FS=1x)
0001
64x
0010
128x
0011
192x
0100
256x
0101
384x (Not available when FS=1x)
0110
512x (Not available when FS=1x)
0111
576x (Not available when FS=01,1x)
1000
768x (Not available when FS=01,1x)
1001
1024x (Not available when
FS=01,1x)
Others
Not available
Note: The FS × PMF should be lower than
49.152MHz, or the system will be error.
PMF
0000
EN_CLK_OUT PLL Clock Output
0
Disabled
1
Enable
MUTE
0
1
Master Mute
All channel not muted
All channel muted
CMx
0
1
Channel x Mute
Channel x not muted
Only channel x muted
Table 8 03h Master Volume Control Register
Bit
D7:D0
Name
MV
Default
0001 1000
IS31AP2121 supports both master-volume (03h
Register) and channel-volume control (04h, 05h and
06h Registers) modes. Both volume control settings
range from +12dB ~ -103dB and 0.5dB per step.
Note that the master volume control is added to the
individual channel volume control as the total volume
control. For example, if the master volume level is
set at, Level A (in dB unit) and the channel volume
level is set at Level B (in dB unit), the total volume
control setting is equal to Level A plus with Level B.
-103dB ≤ Total volume (Level A + Level B) ≤ +24dB.
MV
0000 0000
0000 0001
0000 0010
…
0001 1000
…
1110 0110
1110 0111
Others
Master Volume
+12.0dB
+11.5dB
+11.0dB
0dB
-103.0dB
-∞
-∞
Table 7 02h State Control 3 Register
Bit
D7
D6:D4
Name
EN_CLK_OUT
-
Default
0
xxx
D3
D2:D0
MUTE CM1:CM3
1
111
IS31AP2121 has mute function including master
mute and channel mute. When master mute is
enabled, all 3 processing channels are muted. User
can mute these 3 channels individually by channel
mute. When the mute function is enabled or disabled,
the fade-out or fade-in process will be initiated.
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IS31AP2121
Table 9 04h~06h Channel 1~3 Volume Registers
Bit
D7:D0
Name
CxV
Default
0001 0100
CxV
0000 0000
0000 0001
…
0001 0100
…
1110 0110
1110 0111
Others
XO
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Channel x Volume
+12.0dB
+11.5dB
+2dB
-103.0dB
-∞
-∞
Bass Management Crossover Frequency
80Hz
100Hz
120Hz
140Hz
160Hz
180Hz
200Hz
300Hz
400Hz
500Hz
600Hz
700Hz
800Hz
900Hz
1000Hz
Reserved
Table 10 07h/08h Bass/Treble Tone Registers
Bit
D7:D5
D6:D0
Name
-
BTC/TTC
Default
xxx
10000
Last two sets of EQ can be programmed as
bass/treble tone boost and cut. When, 0Ah Register,
D6, BTE is set to high, the EQ-7 and EQ-8 will
perform as bass and treble respectively. The -3dB
corner frequency of bass is 360Hz, and treble is
7kHz. The gain range for both filters is +12db ~ 12dB with 1dB per step.
BTC/TTC
00000
…
00100
00101
…
10000
10001
…
111xx
Bass/Treble Gain Setting
+12dB
+12dB
+11dB
Table 12 0Ah State Control 4 Register
Bit
D7
D6
D5
D4
Name
SRBP
BTE
TBDRCE
NGE
Default
1
0
0
1
Bit
D3
D2
D1
D0
Name
EQL
PSL
DSPB
HPB
Default
0
0
0
0
The IS31AP2121 provides several DSP setting as
following.
SRBP Surround Bypass
0
Surround enable
1
Surround bypass
BTE
0
1
0dB
-1dB
-12dB
Table 11 09h Bass Management Crossover
Frequency Register
Bit
D7:D4
D3:D0
Name
-
XO
Default
xxxx
0010
The IS31AP2121 provides bass management
crossover frequency selection. A 1st order high-pass
filter (Channel 1 and 2) and a 2nd order low-pass
filter (Channel 3) at selected frequency are
performed.
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Bass/Treble Selection Bypass
Bass/treble disable
Bass/treble enable
TBDRCE Two Band DRC Enable
0
Two band DRC disable
1
Two band DRC enable
NGE
0
1
Noise Gate Enable
Noise gate disable
Noise gate enable
EQL
0
1
EQ Link
Each channel uses individual EQ
Channel-2 uses channel-1 EQ
PSL
0
1
Post-Scale Link
Each channel uses individual post-scale
Use channel-1 post-scale
24
IS31AP2121
DSPB EQ Bypass
0
EQ enable
1
EQ bypass
HPB
0
1
Table 14 0Dh Channel 3 Configuration Register
DC Blocking HPF Bypass
HPF DC enable
HPF DC bypass
Table 13 0Bh~0Ch Channel 1~2 Configuration
Registers
Bit
D7:D5
D4
D3
Name
-
CxDRCM
CxPCBP
Default
xxx
1
0
Bit
D2
D1
D0
Name
CxDRCBP
CxHPFBP
CxVBP
Default
0
1
0
The IS31AP2121 can configure each channel to
enable or bypass DRC and channel volume and
select the limiter set. IS31AP2121 support two mode
of DRC, RMS and PEAK detection which can be
selected via D4.
Bit
D7:D5
D4
D3
Name
-
C3DRCM
C3PCBP
Default
xxx
1
0
Bit
D2
D1
D0
Name
C3DRCBP
C3HPFBP
C3VBP
Default
0
0
0
The IS31AP2121 can configure each channel to
enable or bypass DRC and channel volume and
select the limiter set. IS31AP2121 support two mode
of DRC, RMS and PEAK detection which can be
selected via D4.
C3DRCM
0
1
Channel 3 DRC Mode
Peak detection
RMS detection
C3PCBP
0
1
Channel 3 Power Clipping Bypass
Channel 3 PC enable
Channel 3 PC bypass
C3DRCBP
0
1
Channel 3 DRC Bypass
Channel 3 DRC enable
Channel 3 DRC bypass
C3HPFBP
0
1
Channel 3 Bass Management LPF
Bypass
Channel 3 LPF enable
Channel 3 LPF bypass
Channel 3 Volume Bypass
Channel 3 volume operation
Channel 3 volume bypass
CxDRCM
0
1
Channel 1/2 DRC Mode
Peak detection
RMS detection
CxPCBP
0
1
Channel 1/2 Power Clipping Bypass
Channel 1/2 PC enable
Channel 1/2 PC bypass
CxDRCBP
0
1
Channel 1/2 DRC Bypass
Channel 1/2 DRC enable
Channel 1/2 DRC bypass
C3VBP
0
1
CxHPFBP
Channel 1/2 Bass Management HPF
Bypass
Table 15 0Eh DRC Limiter Attack/Release Rate
Register
0
1
Channel 1/2 HPF enable
Channel 1/2 HPF bypass
CxVBP
0
Channel 1/2 Volume Bypass
Channel 1/2’s master volume
operation
Channel 1/2’s master volume
bypass
1
Bit
D7:D5
D6:D0
Name
LA
LR
Default
0110
1010
The IS31AP2121 defines a set of limiter. The
attack/release rates are defines as following table.
LA
0000
0001
0010
0011
0100
0101
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DRC Attack Rate
3dB/ms
2.667dB/ms
2.182dB/ms
1.846dB/ms
1.333dB/ms
0.889dB/ms
25
IS31AP2121
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.4528dB/ms
0.2264dB/ms
0.15dB/ms
0.1121dB/ms
0.0902dB/ms
0.0752dB/ms
0.0645dB/ms
0.0563dB/ms
0.0501dB/ms
0.0451dB/ms
LR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DRC Release Rate
0.5106dB/ms
0.1371dB/ms
0.0743dB/ms
0.0499dB/ms
0.0360dB/ms
0.0299dB/ms
0.0264dB/ms
0.0208dB/ms
0.0198dB/ms
0.0172dB/ms
0.0147dB/ms
0.0137dB/ms
0.0134dB/ms
0.0117dB/ms
0.0112dB/ms
0.0104dB/ms
DIS_MCLK_DET Disable MCLK Detect Circuit
0
Enable MCLK detect circuit
1
Disable MCLK detect circuit
D7:D6
Name
-
Default
xx
Power Saving Mode
Disable
Enable
PWM_SEL
0
1
PWM Modulation
Qua-ternary
Ternary
Table 17 12h VCC Under-voltage Selection
Register
Bit
D7
D6:D4
D3:D0
Name
Dis_HVUV
-
HV_UVSEL
Default
1
xxx
0001
IS31AP2121 can disable HV under-voltage detection
via D7. IS31AP2121 support multi-level HV undervoltage detection via D3~ D0, using this function,
IS31AP2121 will fade out signal to avoid pop sounds
if high voltage supply disappear before low voltage
supply.
Table 16 11h State Control 5 Register
Bit
QT_EN
0
1
D5
D4
D3
SW_RSTB LVUV_FADE
1
SEM
1
0
Bit
D2
D1
D0
Name
DIS_MCLK_DET
QT_EN
PWM_SEL
Default
0
1
0
SW_RSTB
0
1
Software Reset
Reset
Normal operation
LVUV_FADE
0
1
Low Under-voltage Fade
No fade
fade
SEM
0
1
Single End Mode
2.0 mode (2BTL or 1PBTL)
2.1 mode (2SE+1BTL)
Dis_HVUV
0
1
Disable HV Under-voltage Selection
Enable
Disable
HV_UVSEL
0000
0001
0011
0100
1100
Others
UV Detection Level
8.2V
9.7V
13.2V
15.5V
19.5V
9.7V
Table 18 13h Noise Gate Gain Register
Bit
D7
D6
D5
Name
-
A_SEL_FAULT
D_MOD
Default
x
0
0
Bit
D4
D3:D2
D1:D0
Name
DIS_NG_FADE
-
NG_GAIN
Default
0
xx
00
The ERRORB pin of IS31AP2121 is a dual function
pin. It is treated as an I2C device address selection
input when D6 is set as low. It will become as an
ERROR output pin when D6 is set as high.
IS31AP2121 provide noise gate function if receiving
2048 signal sample points smaller than noise gate
attack level. User can change noise gate gain via
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IS31AP2121
D1~ D0. When noise gate function occurs, input
signal will multiply noise gate gain (x1/8, x1/4 x1/2,
x0). User can select fade out or not via D4.
A_SEL_FAULT I2C Address Selection or ERROR
output
0
I2C address selection
1
ERROR output
D_MOD
0
1
Delta Quaternary Modulation
Disable
Enable
DIS_NG_FADE Disable Noise Gate Fade
0
Fade
1
No fade
NG_GAIN
00
01
10
11
Noise Gate Gain
x1/8
x1/4
x1/2
Mute
Table 19 14h Coefficient RAM Base Address
Register
Bit
D7
D6:D0
Name
-
CFA
Default
x
000 0000
An on-chip RAM in IS31AP2121 stores user-defined
EQ and mixing coefficients. The content of this
coefficient RAM is indirectly accessed via coefficient
registers, which consist of one base address register
(14h), five sets of registers (15h ~ 23h) of three
consecutive 8-bit entries for each 24-bit coefficient,
and one control register (24h) to control access of
the coefficients in the RAM.
CFA
Coefficient RAM Base Address
Table 20 15h~17h User-Defined Coefficients
Registers
(Top/Middle/Bottom 8-bits of coefficients A1)
Bit
D7:D0
Name
C1B
Default
-
Table 21 18h~1Ah User-Defined Coefficients
Registers
(Top/Middle/Bottom 8-bits of coefficients A2)
Bit
D7:D0
Name
C2B
Default
-
Table 22 1Bh~1Dh User-Defined Coefficients
Registers
(Top/Middle/Bottom 8-bits of coefficients A1)
Bit
D7:D0
Name
C3B
Default
-
Table 23 1Eh~20h User-Defined Coefficients
Registers
(Top/Middle/Bottom 8-bits of coefficients B2)
Bit
D7:D0
Name
C4B
Default
-
Table 24 21h~23h User-Defined Coefficients
Registers
(Top/Middle/Bottom 8-bits of coefficients A0)
Bit
D7:D0
Name
C5B
Default
-
Table 25 24h Coefficients Control Register
Bit
D7:D4
D3
D2
D1
D0
Name
-
RA
R1
WA
W1
Default
xxxx
0
0
0
0
RA
0
1
R1
0
1
WA
0
1
W1
0
1
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Enable of Reading a Set of Coefficients from
RAM
Read complete
Read enable
Enable of Reading a Single Coefficient from
RAM
Read complete
Read enable
Enable of Writing a Set of Coefficients to
RAM
Write complete
Write enable
Enable of Writing a Single Coefficient to
RAM
Write complete
Write enable
27
IS31AP2121
Table 26 2Ah Power Saving Mode Switching
Level Register
Bit
D7:D5
D4:D0
Name
QT_SW_WINDOW
QT_SW_LEVEL
Default
000
01101
If the PWM exceeds the programmed switching
power level (default 26×40ns), the modulation
algorithm will change from quaternary into power
saving mode. It results in higher power efficiency
during larger power output operations. If the PWM
drops below the programmed switching power level power saving mode hysteresis window, the
modulation algorithm will change back to quaternary
modulation.
QT_SW_WINDOW
000
001
010
011
100
101
110
111
Power Saving Mode
Hysteresis Window
2
3
4
5
6
7
8
9
MV_FT
00
01
10
11
Master Volume Fine Tune
0dB
-0.125dB
-0.25dB
-0.375dB
C1V_FT
00
01
10
11
Channel 1 Volume Fine Tune
0dB
-0.125dB
-0.25dB
-0.375dB
C2V_FT
00
01
10
11
Channel 2 Volume Fine Tune
0dB
-0.125dB
-0.25dB
-0.375dB
C3V_FT
00
01
10
11
Channel 3 Volume Fine Tune
0dB
-0.125dB
-0.25dB
-0.375dB
RAM ACCESS
QT_SW_LEVEL
00000 4
00001 4
…
01101 26
01110 28
01111 30
…
11110 60
11111 62
The procedure to read/write coefficient(s) from/to
RAM is as followings:
Switching Level
Read A Single Coefficient From RAM:
1. Write 7-bits of address to I2C address-0X14
2. Write 1 to R1 bit in address-0X24
3. Read top 8-bits of coefficient in I2C address-0X15
4. Read middle 8-bits of coefficient in I2C address0X16
5. Read bottom 8-bits of coefficient in I2C address0X17
Read A Set Of Coefficients From RAM:
Table 27 2Bh Volume Fine Tune Register
Bit
D7:D6
D5:D4
D3:D2
D1:D0
Name
MV_FT
C1V_FT
C2V_FT
C3V_FT
Default
00
11
11
11
IS31AP2121 supports both master-volume fine tune
and channel-volume control fine tune modes. Both
volume control settings range from 0dB ~ -0.375dB
and 0.125dB per step. Note that the master volume
fine tune is added to the individual channel volume
fine tune as the total volume fine tune.
Integrated Silicon Solution, Inc. – www.issi.com
Rev. 0A, 10/17/2014
1. Write 7-bits of address to I2C address-0X14
2. Write 1 to RA bit in address-0X24
3. Read top 8-bits of coefficient A1 in I2C address0X15
4. Read middle 8-bits of coefficient A1in I2C
address-0X16
5. Read bottom 8-bits of coefficient A1 in I2C
address-0X17
6. Read top 8-bits of coefficient A2 in I2C address0X18
7. Read middle 8-bits of coefficient A2 in I2C
address-0X19
8. Read bottom 8-bits of coefficient A2 in I2C
address-0X1A
9. Read top 8-bits of coefficient B1 in I2C address0X1B
28
IS31AP2121
10. Read middle 8-bits of coefficient B1 in I2C
address-0X1C
11. Read bottom 8-bits of coefficient B1 in I2C
address-0X1D
12. Read top 8-bits of coefficient B2 in I2C address0X1E
13. Read middle 8-bits of coefficient B2 in I2C
address-0X1F
14. Read bottom 8-bits of coefficient B2 in I2C
address-0X20
15. Read top 8-bits of coefficient A0 in I2C address0X21
16. Read middle 8-bits of coefficient A0 in I2C
address-0X22
17. Read bottom 8-bits of coefficient A0 in I2C
address-0X23
16. Write bottom 8-bits of coefficient A0 in I2C
address-0X23
17. Write 1 to WA bit in address-0X24
Note: the read and write operation on RAM
coefficients works only if LRCIN (Pin 15) switching
on rising edge. And, before each writing operation, it
is necessary to read the address-0X24 to confirm
whether RAM is writable current in first. If the logic of
W1 or WA is high, the coefficient writing is prohibited.
USER-DEFINED EQUALIZER
The IS31AP2121 provides 20 parametric Equalizer
(EQ). Users can program suitable coefficients via
I2C control interface to program the required audio
band frequency response for every EQ. The transfer
function
Write A Single Coefficient From RAM:
1. Write 7-bis of address to I2C address-0X14
2. Write top 8-bits of coefficient in I2C address-0X15
3. Write middle 8-bits of coefficient in I2C address0X16
4. Write bottom 8-bits of coefficient in I2C address0X17
5. Write 1 to W1 bit in address-0X24
Write A Set Of Coefficients From RAM:
1. Write 7-bits of address to I2C address-0X14
2. Write top 8-bits of coefficient A1 in I2C address0X15
3. Write middle 8-bits of coefficient A1 in I2C
address-0X16
4. Write bottom 8-bits of coefficient A1 in I2C
address-0X17
5. Write top 8-bits of coefficient A2 in I2C address0X18
6. Write middle 8-bits of coefficient A2 in I2C
address-0X19
7. Write bottom 8-bits of coefficient A2 in I2C
address-0X1A
8. Write top 8-bits of coefficient B1 in I2C address0X1B
9. Write middle 8-bits of coefficient B1 in I2C
address-0X1C
10. Write bottom 8-bits of coefficient B1 in I2C
address-0X1D
11. Write top 8-bits of coefficient B2 in I2C address0X1E
12. Write middle 8-bits of coefficient B2 in I2C
address-0X1F
13. Write bottom 8-bits of coefficient B2 in I2C
address-0X20
14. Write top 8-bits of coefficient A0 in I2C address0X21
15. Write middle 8-bits of coefficient A0 in I2C
address-0X22
Integrated Silicon Solution, Inc. – www.issi.com
Rev. 0A, 10/17/2014
H (z) 
A0  A1 z 1  A2 z 2
1  B1 z 1  B2 z  2
The data format of 2’s complement binary code for
EQ coefficient is 3.21. i.e., 4-bits for integer (MSB is
the sign bit) and 21-bits for mantissa. Each
coefficient range is from 0x800000 (-4) to 0x7FFFFF
(+3.999999523). These coefficients are stored in
User Defined RAM and are referenced in following
manner:
CHxEQyA0=A0
CHxEQyA1=A1
CHxEQyA2=A2
CHxEQyB1=-B1
CHxEQyB2=-B2
Where x and y represents the number of channel
and the band number of EQ equalizer.
All user-defined filters are path-through, where all
coefficients are defaulted to 0 after being powered
up, except the A0 that is set to 0x200000 which
represents 1.
MIXER
The IS31AP2121 provides mixers to generate the
extra audio source from the input left and right
channels. The coefficients of mixers are defined in
range from 0x800000 (-1) to 0x7FFFFF
(0.9999998808). The function block diagram is as
following figure:
29
IS31AP2121
ATTACK THRESHOLD
The IS31AP2121 provides power limited function.
When the input RMS exceeds the programmable
attack threshold value, the output power will be
limited by this threshold power level via gradual gain
reduction. Two sets of power limit are provided. One
is used of channel 1 and channel 2, while the other
is used for channel 3. Attack threshold is defined by
24-bit representation and is stored in RAM address
0X71 and 0X72.
RELEASE THRESHOLD
Figure 23 Mixer Function Block Diagram
PRE-SCALE
For each audio channel, IS31AP2121 can scale
input signal level prior to EQ processing which is
realized by a 24-bit signed fractional multiplier. The
pre-scale factor, ranging from -1 (0x800000) to
0.9999998808 (0x7FFFFF), for this multiplier, can be
loaded into RAM. The default values of the prescaling factors are set to 0x7FFFFF. Programming
of RAM is described in RAM access.
POST-SCALE
The IS31AP2121 provides an additional
multiplication after equalizing and before
interpolation stage, which is realized by a 24-bit
signed fractional multiplier. The post-scaling factor,
ranging from -1 (0x800000) to 0.9999998808
(0x7FFFFF), for this multiplier, can be loaded into
RAM. The default values of the post-scaling factors
are set to 0x7FFFFF. All channels can use the
channel-1 post-scale factor by setting the post-scale
link. Programming of RAM is described in RAM
access.
After IS31AP2121 has reached the attack threshold,
its output power will be limited to that level. The
output power level will be gradually adjusted to the
programmable release threshold level. Two sets of
power limit are provided. One is used of channel 1
and channel 2, while the other is used for channel 3.
Release threshold is defined by 24-bit representation
and is stored in RAM address 0X73 and 0X74. The
following table shows the attack and release
threshold’s numerical representation.
Table 29 Sample Calculation For Attack And
Release Threshold
Hex
Power
dB Linear Decimal
(3.21 Format)
(VCC^2)/R
0
1
2097152
200000
(VCC^2)/2R
-3
0.5
1048576
100000
(VCC^2)/4R
-6
0.25
524288
80000
(VCC^2)/R
×L
x
L=
D=
10(x/10) 2097152×L
H=
dec2hex(D)
To best illustrate the power limit function, please
refer to the following figure.
POWER CLIPPING
The IS31AP2121 provides power clipping function to
avoid excessive signal that may destroy loud
speaker. Two sets of power clipping are provided.
One is used for both channel 1 and channel 2, while
the other is used for channel 3. The power clipping
level is defined by 24-bit representation and is stored
in RAM address 0X6F and 0X70. The following table
shows the power clipping level’s numerical
representation.
Table 28 Sample Calculation for Power Clipping
Max.
Hex
dB Linear Decimal
Amplitude
(3.21 Format)
VCC
0
1
2097152
200000
VCC×0.707
-3
0.707
1482686
169FBE
VCC×0.5
-6
0.5
1048576
100000
VCC×L
x
D=
H=
L=
10(x/20) 2097152×L dec2hex(D)
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Rev. 0A, 10/17/2014
30
IS31AP2121
Attack Threshold
Release Threshold
Input
Release Threshold
Attack Threshold
Gain
∆gain2
∆gain1
∆t1
Touch Attack
Threshold
Attack rate=∆gain1/∆t1
Release rate=∆gain2/∆t2
∆t2
Under Release
Threshold
Attack Threshold
Release Threshold
Output
Release Threshold
Attack Threshold
Figure 24 Attack And Release Threshold
NOISE GATE ATTACK LEVEL
DRC ENERGY COEFFICIENT
When both left and right signals have 2048
consecutive sample points less than the
programmable noise gate attack level, the audio
signal will multiply noise gate gain, which can be set
at x1/8, x1/4, x1/2, or zero if the noise gate function
is enabled. Noise gate attack level is defined by 24bit representation and is stored in RAM address
0X75.
NOISE GATE RELEASE LEVEL
After entering the noise gating status, the noise gain
will be removed whenever IS31AP2121 receives any
input signal that is more than the noise gate release
level. Noise gate release level is defined by 24-bit
representation and is stored in RAM address 0X76.
The following table shows the noise gate attack and
release threshold level’s numerical representation.
Table 30 Sample Calculation for Noise Gate Attack
and Release Level
Input
Hex
Linear
Decimal
Amplitude
(1.23 Format)
0dB
-100dB
-110dB
xdB
1
8388607
7FFFFF
-5
83
53
-5.5
26
1A
D=
8388607×L
H=
dec2hex(D)
10
10
L=
10(x/20)
Integrated Silicon Solution, Inc. – www.issi.com
Rev. 0A, 10/17/2014
Figure 25 Digital Processing of Calculating RMS Signal Power
The above figure illustrates the digital processing of
calculating RMS signal power. In this processing, a
DRC energy coefficient is required, which can be
programmed for different frequency range. Two sets
of energy coefficients are provided. One is used of
channel 1 and channel 2, while the other is used for
channel3. Energy coefficient is defined by 24-bit
representation and is stored in RAM address 0X77
and 0X78. The following table shows the DRC
energy coefficient numerical representation.
31
IS31AP2121
Table 31 Sample Calculation for DRC Energy
Coefficient
DRC Energy
Hex
dB Linear Decimal
Coefficient
(1.23 Format)
1
0
1
8388607
7FFFFF
1/256
-48.2 1/256
32768
8000
1/1024
-60.2 1/1024
8192
2000
L
x
D=
L=
H=
10(x/20) 8388607×L dec2hex(D)
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Rev. 0A, 10/17/2014
32
IS31AP2121
THE USER DEFINED RAM
The contents of user defined RAM is represented in following table.
Table 32 User Defined RAM
Address
Name
0x00
0x01
0x02
Channel 1
EQ1
Coefficient
Default
Address
CH1EQ1A1
0x000000
0x32
CH1EQ1A2
0x000000
0x33
Name
Channel 2
EQ1
Coefficient
Default
CH2EQ1A1
0x000000
CH2EQ1A2
0x000000
CH2EQ1B1
0x000000
CH2EQ1B2
0x000000
CH1EQ1B1
0x000000
0x34
CH1EQ1B2
0x000000
0x35
0x04
CH1EQ1A0
0x200000
0x36
CH2EQ1A0
0x200000
0x05
CH1EQ2A1
0x000000
0x37
CH2EQ2A1
0x000000
CH1EQ2A2
0x000000
0x38
CH2EQ2A2
0x000000
CH2EQ2B1
0x000000
0x03
0x06
0x07
Channel 1
EQ2
Channel 2
EQ2
CH1EQ2B1
0x000000
0x39
0x08
CH1EQ2B2
0x000000
0x3A
CH2EQ2B2
0x000000
0x09
CH1EQ2A0
0x200000
0x3B
CH2EQ2A0
0x200000
0x0A
CH1EQ3A1
0x000000
0x3C
CH2EQ3A1
0x000000
CH1EQ3A2
0x000000
0x3D
CH2EQ3A2
0x000000
CH2EQ3B1
0x000000
0x0B
0x0C
Channel 1
EQ3
Channel 2
EQ3
CH1EQ3B1
0x000000
0x3E
0x0D
CH1EQ3B2
0x000000
0x3F
CH2EQ3B2
0x000000
0x0E
CH1EQ3A0
0x200000
0x40
CH2EQ3A0
0x200000
0x0F
CH1EQ4A1
0x000000
0x41
CH2EQ4A1
0x000000
CH1EQ4A2
0x000000
0x42
CH2EQ4A2
0x000000
CH2EQ4B1
0x000000
0x10
0x11
Channel 1
EQ4
Channel 2
EQ4
CH1EQ4B1
0x000000
0x43
0x12
CH1EQ4B2
0x000000
0x44
CH2EQ4B2
0x000000
0x13
CH1EQ4A0
0x200000
0x45
CH2EQ4A0
0x200000
0x14
CH1EQ5A1
0x000000
0x46
CH2EQ5A1
0x000000
CH1EQ5A2
0x000000
0x47
CH2EQ5A2
0x000000
CH2EQ5B1
0x000000
0x15
0x16
Channel 1
EQ5
Channel 2
EQ5
CH1EQ5B1
0x000000
0x48
0x17
CH1EQ5B2
0x000000
0x49
CH2EQ5B2
0x000000
0x18
CH1EQ5A0
0x200000
0x4A
CH2EQ5A0
0x200000
0x19
CH1EQ6A1
0x000000
0x4B
CH2EQ6A1
0x000000
CH1EQ6A2
0x000000
0x4C
CH2EQ6A2
0x000000
CH2EQ6B1
0x000000
0x1A
0x1B
Channel 1
EQ6
Channel 2
EQ6
CH1EQ6B1
0x000000
0x4D
0x1C
CH1EQ6B2
0x000000
0x4E
CH2EQ6B2
0x000000
0x1D
CH1EQ6A0
0x200000
0x4F
CH2EQ6A0
0x200000
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33
IS31AP2121
Table 32 User Defined RAM (Continues)
Address
Name
0x1E
0x1F
0x20
Channel 1
EQ7
Coefficient
Default
Address
CH1EQ7A1
0x000000
0x50
CH1EQ7A2
0x000000
0x51
Name
Channel 2
EQ7
Coefficient
Default
CH2EQ7A1
0x000000
CH2EQ7A2
0x000000
CH2EQ7B1
0x000000
CH2EQ7B2
0x000000
CH1EQ7B1
0x000000
0x52
CH1EQ7B2
0x000000
0x53
0x22
CH1EQ7A0
0x200000
0x54
CH2EQ7A0
0x200000
0x23
CH1EQ8A1
0x000000
0x55
CH2EQ8A1
0x000000
CH1EQ8A2
0x000000
0x56
CH2EQ8A2
0x000000
CH2EQ8B1
0x000000
0x21
0x24
0x25
Channel 1
EQ8
Channel 2
EQ8
CH1EQ8B1
0x000000
0x57
0x26
CH1EQ8B2
0x000000
0x58
CH2EQ8B2
0x000000
0x27
CH1EQ8A0
0x200000
0x59
CH2EQ8A0
0x200000
0x28
CH1EQ9A1
0x000000
0x5A
CH2EQ9A1
0x000000
CH1EQ9A2
0x000000
0x5B
CH2EQ9A2
0x000000
CH2EQ9B1
0x000000
0x29
0x2A
Channel 3
EQ1
Channel 3
EQ2
CH1EQ9B1
0x000000
0x5C
0x2B
CH1EQ9B2
0x000000
0x5D
CH2EQ9B2
0x000000
0x2C
CH1EQ9A0
0x200000
0x5E
CH2EQ9A0
0x200000
0x2D
CH3EQ1A1
0x000000
0x5F
CH3EQ2A1
0x000000
CH3EQ1A2
0x000000
0x60
CH3EQ2A2
0x000000
CH3EQ2B1
0x000000
0x2E
0x2F
Channel 3
EQ3
Channel 3
EQ4
CH3EQ1B1
0x000000
0x61
0x30
CH3EQ1B2
0x000000
0x62
CH3EQ2B2
0x000000
0x31
CH3EQ1A0
0x200000
0x63
CH3EQ2A0
0x200000
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Rev. 0A, 10/17/2014
34
IS31AP2121
Table 32 User Defined RAM (Continues)
Address
Name
Coefficient
Default
0x64
Channel 1 Mixer1
M11
0x7FFFFF
0x65
Channel 1 Mixer2
M12
0x000000
0x66
Channel 2 Mixer1
M21
0x000000
0x67
Channel 2 Mixer2
M22
0x7FFFFF
0x68
Channel 3 Mixer1
M31
0x400000
0x69
Channel 3 Mixer2
M32
0x400000
0x6A
Channel 1 Prescale
C1PRS
0x7FFFFF
0x6B
Channel 2 Prescale
C2PRS
0x7FFFFF
0x6C
Channel 1 Postscale
C1POS
0x7FFFFF
0x6D
Channel 2 Postscale
C2POS
0x7FFFFF
0x6E
Channel 3 Postscale
C3POS
0x7FFFFF
0x6F
CH1.2 Power Clipping
PC1
0x200000
0x70
CH3 Power Clipping
PC2
0x200000
0x71
CH1.2 DRC Attack Threshold
DRC1_ATH
0x200000
0x72
CH1.2 DRC Release Threshold
DRC1_RTH
0x80000
0x73
CH3 DRC Attack Threshold
DRC2_ATH
0x200000
0x74
CH3 DRC Release Threshold
DRC2_RTH
0x80000
0x75
Noise Gate Attack Level
NGAL
0x0001A
0x76
Noise Gate Release Level
NGRL
0x000053
0x77
DRC1 Energy Coefficient
DRC1_EC
0x8000
0x78
DRC2 Energy Coefficient
DRC2_EC
0x2000
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Rev. 0A, 10/17/2014
35
IS31AP2121
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 26 Classification Profile
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Rev. 0A, 10/17/2014
36
IS31AP2121
PACKAGE INFORMATION
eLQFP-48
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Rev. 0A, 10/17/2014
37

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