Freescale MC33662LEF Lin 2.1 / saej2602-2, lin physical layer Datasheet

Freescale Semiconductor
Advance Information
Document Number: MC33662
Rev. 7.0, 1/2014
LIN 2.1 / SAEJ2602-2, LIN
Physical Layer
33662
The Local Interconnect Network (LIN) is a serial communication
protocol, designed to support automotive networks in conjunction with
a Controller Area Network (CAN). As the lowest level of a hierarchical
network, LIN enables cost-effective communication with sensors and
actuators when all the features of CAN are not required.
The three 33662 versions are designed to operate at different
maximum baud rates. The 33662LEF and 33662BLEF, and the
33662SEF and 33662BSEF, offer a normal baud rate (20 kbps), and
the 33662JEF and 33662BJEF, a slow baud rate (10 kbps). They
integrate a fast baud rate (above 100 kbps), as reported by the RXD pin
for test and programming modes. They provide excellent EMC
(Electromagnetic Compatibility) and Radiated Emission performance,
ESD (Electrostatic Discharge) robustness, and safe behavior, in the
event of a LIN bus short-to-ground, or a LIN bus leakage during lowpower mode. This device is powered by SMARTMOS technology.
LINCELL
Features
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
• Operational from a VSUP of 7.0 to 18 V DC, functional up to 27 V DC,
and handles 40 V during Load Dump
• Compatible with LIN Protocol Specification 1.3, 2.0, 2.1, and
SAEJ2602-2
• Active bus wave shaping, offering excellent radiated emission
performance
• Sustains up to 15.0 kV minimum ESD IEC61000-4-2 on the LIN Bus,
20 kV on the WAKE pin, and 25 kV on the VSUP pin
• Very high immunity against electromagnetic interference
• Low standby current in Sleep mode
• Overtemperature protection
• Local and remote Wake-up capability reported by the RXD pin
• Fast baud rate selection reported by RXD pin
• 5.0 V and 3.3 V compatible digital inputs without any required
external components
Applications
• Automotive Market:
• Body electronics (BCM, gateway, roof, door,
lighting, HVAC)
• Powertrain (EMS, start & stop), BMS
• Safety & Chassis (TPMS, seat belt)
VBAT
33662
VSUP
CAN SBC
or
Regulator
12 V
5.0 V
or 3.3 V
WAKE
VDD
MCU
INH
EN
RXD
TXD
LIN
LIN Interface
GND
Figure 1. 33662 Master LIN Bus Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2011-2014. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
(Add an R2 suffix for Tape and Reel
orders)
MC33662LEF (1)
MC33662BLEF
MC33662SEF (1)
MC33662BSEF
MC33662JEF (1)
MC33662BJEF
Maximum Baud Rate
Temperature Range (TA)
Package
- 40 to 125 °C
8 SOICN
20 kbps
20 kbps with restricted limits for
transmitter and receiver symmetry
10 kbps
Notes
1. In Sleep mode, the total module current consumption may be higher than expected if the external pull-up resistor on the RxD pin
is implemented. There may be an unexpected glitch on RxD as INH goes low.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VSUP
X1
INH_ON
INH
EN
200 k
Control Unit
RXD
EN-SLEEP
30 k
RXD_INT
Receiver
EN_RXD
725 k
LIN
LIN_EN
 
TXD
TXD_INT
Slope
Control
WAKE
GND
Figure 2. 33662 Simplified Internal Block Diagram
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
RXD
1
8
INH
EN
2
7
VSUP
WAKE
3
6
LIN
TXD
4
5
GND
Figure 3. 33662 8-SOICN Pin Connections
Table 2. 33662 8-SOICN Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Pin
PIN NAME
Pin Function
Formal Name
Definition
1
RXD
Output
Data Output
This pin is the receiver output of the LIN interface which reports the state
of the bus voltage to the MCU interface.
2
EN
Input
Enable Control
3
WAKE
Input
Wake Input
This pin is a high-voltage input used to wake-up the device from Sleep
mode.
4
TXD
Input
Data Input
This pin is the transmitter input of the LIN interface which controls the
state of the bus output.
5
GND
Ground
Ground
This pin is the device ground pin.
6
LIN
Input/Output
LIN Bus
This bidirectional pin represents the single-wire bus transmitter and
receiver.
7
VSUP
Power
Power Supply
This pin is the device battery level power supply.
8
INH
Output
Inhibit Output
This pin can have two main functions: controlling an external switchable
voltage regulator having an inhibit input, or driving an external bus
resistor in the master node application.
This pin controls the operation mode of the interface.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
V
Normal Operation (DC)
VSUP(SS)
-0.3 to 27
- Pulse 1 (test up to the limit for Damage - Class A(2))
VSUP(S1)
-100
- Pulse 2a (test up to the limit for Damage - Class A(2))
VSUP(S2A)
+75
- Pulse 3a (test up to the limit for Damage - Class A )
VSUP(S3A)
-150
- Pulse 3b (test up to the limit for Damage - Class A(2))
VSUP(S3B)
+100
VSUP(S5B)
-0.3 to 40
VWAKE(SS)
-27 to 40
Transient input voltage with external component (according to ISO7637-2 & ISO76373 & “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive
Applications” specification Rev1.1 / December 2nd, 2009) (See Table 4 and Figure 4)
(2)
- Pulse 5b (Class
A)(2)
WAKE
V
Normal Operation within series 2*18 k resistor (DC)
Transient input voltage with external component (according to ISO7637-2 & ISO76373 & “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive
Applications” specification Rev1.1 / December 2nd, 2009) (See Table 4 and Figure 5)
- Pulse 1 (test up to the limit for Damage - Class D(3))
VWAKE(S1)
-100
(3)
VWAKE(S2A)
+75
(3)
VWAKE(S3A)
-150
(3)
VWAKE(S3B)
+100
VLOG
- 0.3 to 5.5
VBUS(SS)
-27 to 40
- Pulse 1 (test up to the limit for Damage - Class D(3))
VBUS(S1)
-100
- Pulse 2a (test up to the limit for Damage - Class D(3))
VBUS(S2A)
+75
- Pulse 3a (test up to the limit for Damage - Class D(3))
VBUS(S3A)
-150
- Pulse 3b (test up to the limit for Damage - Class D(3))
VBUS(S3B)
+100
VINH
- 0.3 to VSUP +0.3
- Pulse 2a (test up to the limit for Damage - Class D )
- Pulse 3a (test up to the limit for Damage - Class D )
- Pulse 3b (test up to the limit for Damage - Class D )
Logic Voltage (RXD, TXD, EN Pins)
LIN Bus Voltage
V
V
Normal Operation (DC)
Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 & ISO7637-3
& “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive
Applications” specification Rev1.1 / December 2nd, 2009) (See Table 4 and Figure 6)
INH Voltage / Current
V
DC Voltage
Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 & ISO7637-3
& “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive
Applications” specification Rev1.1 / December 2nd, 2009) (See Table 4 and Figure 7)
- Pulse 1 (test up to the limit for Damage - Class D(3))
VINH(S1)
-100
(3)
VINH(S2A)
+75
(3)
- Pulse 3a (test up to the limit for Damage - Class D )
VINH(S3A)
-150
D(3))
VINH(S3B)
+100
- Pulse 2a (test up to the limit for Damage - Class D )
- Pulse 3b (test up to the limit for Damage - Class
Notes
2. Class A: All functions of a device/system perform as designed during and after exposure to disturbance.
3. Class D: At least one function of the transceiver stops working properly during the test, and will return to proper operation automatically
when the exposure to the disturbance has ended. No physical damage of the IC occurs.
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS (CONTINUED)
ESD Capability - AECQ100
V
Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 )
LIN pin versus GND
VESD1-1
± 10.0 k
Wake pin versus GND
VESD1-2
± 8.0 k
All other pins
VESD1-4
± 4.0 k
Corner pins (Pins 1, 4, 5 and 8)
VESD2-1
± 750
All other pins (Pins 2, 3, 6 and 7)
VESD2-2
± 500
VESD3-1
± 200
VESD4-1
± 15 k
VESD4-2
± 15 k
VESD4-3
±25 k
WAKE (2*18 k serial resistor)
VESD4-4
±20 k
INH pin
VESD4-5
±2.0 k
VESD4-6
>± 15 k
VESD5-1
± 20 k
VESD5-2
± 25 k
VESD5-3
±25 k
VESD5-4
±25 k
Charge Device Model - JESD22/C101 (CZAP = 4.0 pF
Machine Model - JESD22/A115 (CZAP = 220 pF, RZAP = 0 )
All pins
According to “Hardware Requirements for LIN, CAN and Flexray Interfaces in
Automotive Applications” specification Rev1.1 / December 2nd, 2009 (CZAP = 150 pF,
RZAP = 330 )
Contact Discharge, Unpowered
LIN pin without capacitor
LIN pin with 220 pF capacitor
VSUP (10 µF to ground)
LIN pin with 220 pF capacitor and indirect ESD coupling (according to ISO10605
- Annex F)
According to ISO10605 - Rev 2008 test specification
(2.0 k / 150 pF) - Unpowered - Contact discharge
LIN pin without capacitor
LIN pin with 220 pF capacitor
VSUP (10 µF to ground)
WAKE (2*18 k serial resistor)
(2.0 k / 330 pF) - Powered - Contact discharge
LIN pin without capacitor
VESD6-1
±8 k
LIN pin with 220 pF capacitor
VESD6-2
± 10 k
VSUP (10 µF to ground)
VESD6-3
±12 k
WAKE (2*18 k serial resistor)
VESD6-4
±15 k
TA
TJ
- 40 to 125
- 40 to 150
Storage Temperature
TSTG
- 40 to 150
C
Thermal Resistance, Junction to Ambient
RJA
150
°C/W
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Peak Package Reflow Temperature During Solder Mounting (4)
C
TSOLDER
240
°C
Thermal Shutdown Temperature
TSHUT
150 to 200
°C
Thermal Shutdown Hysteresis Temperature
THYST
20
°C
Notes
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 4. Limits / Maximum Test Voltage for Transient Immunity Tests
Test Pulse
VS [V]
Pulse repetition
frequency [Hz]
(1/T1)
Test Duration [min]
Ri []
Remarks
1
2a
3a
3b
-100
+75
-150
+100
2
2
10000
10000
1 for function test
10 for damage test
10
2
50
50
t2 = 0 s
DUT
Transient Pulse
Generator
(Note)
VSUP
D1
GND
10 µF
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 4. Test Circuit for Transient Test Pulses (VSUP)
DUT
1.0 nF
WAKE
18 k
18 k
Transient Pulse
Generator
(Note)
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 5. Test Circuit for Transient Test Pulses (WAKE)
DUT
1.0 nF
LIN
Transient Pulse
Generator
(Note)
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 6. Test Circuit for Transient Test Pulses (LIN)
DUT
1.0 nF
INH
Transient Pulse
Generator
(Note)
GND
DUT GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2a, 3a, 3b.
Figure 7. Test Circuit for Transient Test Pulses (INH)
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
7.0
13.5
18.0
V
Functional Operating Voltage(5)
VSUPOP
6.7
–
27
V
Load Dump
VSUPLD
–
–
40
V
3.5
–
5.3
–
270
–
5.8
–
6.7
VUVHYST
–
130
–
VSUP  13.5 V, Recessive State
IS1
—
6.0
11
13.5 V < VSUP < 27 V
IS2
—
—
20
VSUP  13.5 V, Shorted to GND
IS3
—
24
70
Bus Recessive, Excluding INH Output Current
IS(REC)
—
4.0
6.0
Bus Dominant, Excluding INH Output Current
IS(DOM)
—
6.0
8.0
VSUP PIN (DEVICE POWER SUPPLY)
Nominal Operating Voltage
Power-On Reset (POR) Threshold
VPOR
VSUP Ramp Down and INH goes High to Low
Power-On Reset (POR) Hysteresis
VPORHYST
VSUP Undervoltage Threshold (positive and negative)
VUVL, VUVH
Transmission disabled and LIN bus goes in recessive state
VSUP Undervoltage Hysteresis (VUVL - VUVH)
V
mV
V
Supply Current in Sleep Mode
mV
A
Supply Current in Normal or Slow or Fast Mode
mA
RXD OUTPUT PIN (LOGIC)
Low Level Output Voltage
VOL
IIN  1.5 mA
V
0
—
0.9
VEN = 5.0 V, IOUT  250 A
4.25
—
5.25
VEN = 3.3 V, IOUT  250 A
3.0
—
3.5
High Level Output Voltage
VOH
V
TXD INPUT PIN (LOGIC)
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Input Voltage
VIH
2.0
—
—
V
VINHYST
100
300
600
mV
Input Threshold Voltage Hysteresis
Pull-up Current Source
A
IPU
VEN = 5.0 V, 1.0 V < VTXD < 3.5 V
- 60
- 35
- 20
EN INPUT PIN (LOGIC)
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Input Voltage
VIH
2.0
—
—
V
VINHYST
100
400
600
mV
RPD
100
230
350
kohm
Input Voltage Threshold Hysteresis
Pull-down Resistor
5.
For the functional operating voltage, the device is functional and all features are operating. The electrical parameters are noted under
conditions 7.0 V VSUP 18V, -40oC TA 125o C, GND = 0 V.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Operating Voltage Range(7)
VBAT
8.0
–
18
V
Supply Voltage Range
VSUP
7.0
–
18
V
VSUP_NON_OP
-0.3
–
40
V
40
90
200
-1.0
–
–
LIN PHYSICAL LAYER - TRANSCEIVER
LIN(6)
Voltage Range (within which the device is not destroyed)
Current Limitation for Driver Dominant State
IBUS_LIM
Driver ON, VBUS = 18 V
Input Leakage Current at the Receiver
IBUS_PAS_DOM
Driver off; VBUS = 0 V; VBAT = 12 V
Leakage Output Current to GND
µA
–
–
20
-1.0
–
1.0
IBUS_NO_GND
GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V
VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(9)
mA
IBUS_PAS_REC
Driver Off; 8.0 V VBAT  18 V; 8.0 V VBUS  18 V; VBUS  VBAT;
VBUS VSUP
Control Unit Disconnected from Ground(8)
mA
mA
IBUSNO_BAT
–
–
10
µA
Receiver Dominant State(10)
VBUSDOM
–
–
0.4
VSUP
Receiver Recessive State(11)
VBUSREC
0.6
–
–
VSUP
Receiver Threshold Center
VBUS_CNT
0.475
0.5
0.525
(VTH_DOM + VTH_REC)/2
Receiver Threshold Hysteresis
VSUP
VHYS
(VTH_REC - VTH_DOM)
VSUP
–
–
0.175
VLINDOM_LEVEL
–
–
0.25
VSUP
VBAT_SHIFT
VSHIFT_BAT
0
–
11.5%
VBAT
GND_SHIFT
VSHIFT_GND
0
–
11.5%
VBAT
LIN Wake-up Threshold from Sleep Mode
VBUSWU
–
4.3
5.3
V
LIN Pull-up Resistor to VSUP
RSLAVE
20
30
60
k
30
pF
LIN dominant level with 500 680  and 1.0 k load on the LIN bus
LIN Internal
Capacitor(12)
Overtemperature
Shutdown(13)
Overtemperature Shutdown Hysteresis
CLIN
TLINSD
150
160
200
°C
TLINSD_HYS
–
20
–
°C
Notes
6. Parameters guaranteed for 7.0 V VSUP  18 V.
7.
8.
9.
10.
11.
12.
13.
Voltage range at the battery level, including the reverse battery diode.
Loss of local ground must not affect communication in the residual network.
Node has to sustain the current that can flow under this condition. The bus must remain operational under this condition.
LIN threshold for a dominant state.
LIN threshold for a recessive state.
This parameter is guaranteed by process monitoring but not production tested.
When an overtemperature shutdown occurs, the LIN transmitter and receiver are in recessive state and INH switched off. This parameter
is tested with a test mode on ATE and characterized at laboratory.
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
—
—
50
—
—
30
Unit
INH OUTPUT PIN
Driver ON Resistance (Normal Mode)
Current load capability

INHON
IINH = 50 mA
IINH_LOAD
From 7.0 V < VSUP < 18 V
Leakage Current (Sleep Mode)
mA
A
ILEAK
0 < VINH < VSUP
-5.0
—
5.0
TINHSD
150
160
200
°C
TINHSD_HYS
—
20
—
°C
High to Low Detection Threshold (5.5 V < VSUP < 7 V)
VWUHL1
2.0
—
3.9
V
Low to High Detection Threshold (5.5 V < VSUP < 7 V)
VWULH1
2.4
—
4.3
V
VWUHYS1
0.2
—
0.8
V
High to Low Detection Threshold (7 V  VSUP < 27 V)
VWUHL2
2.4
—
3.9
V
Low to High Detection Threshold (7 V  VSUP < 27 V)
VWULH2
2.9
—
4.3
V
VWUHYS2
0.2
—
0.8
V
IWU
—
—
5.0
µA
Overtemperature Shutdown
(14)
Overtemperature Shutdown Hysteresis
WAKE INPUT PIN
Hysteresis (5.5 V < VSUP < 7 V)
Hysteresis (7 V  VSUP < 27 V)
Wake-up Input Current (VWAKE < 27 V)
Notes
14. When an overtemperature shutdown occurs, the INH high side is switched off and the LIN transmitter and receiver are in recessive state.
This parameter is tested with a test mode on ATE and characterized at laboratory.
33662
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(15), (16)
33662L AND 33662S DEVICES
Duty Cycle 1:
D1
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
%
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V VSUP18 V
Duty Cycle 2:
0.396
—
—
—
—
0.581
D2
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V VSUP18 V
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(15), (16)
33662J DEVICE
Duty Cycle 3:
D3
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
%
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V VSUP18 V
Duty Cycle 4:
0.417
—
—
—
—
0.590
BRFAST
—
—
100
t TRAN_SYM
-7.25
—
7.25
D4
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V VSUP18 V
LIN PHYSICAL LAYER
DRIVER CHARACTERISTICS FOR FAST SLEW RATE
Fast Bit Rate (Programming Mode)
kBit/s
LIN PHYSICAL LAYER
TRANSMITTER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(19)
33662S DEVICE
s
Symmetry of Transmitter delay(18)
tTRAN_SYM = MAX (tTRAN_SYM60%, tTRAN_SYM40%)
tTRAN_SYM60% = | tTRAN_PDF60% - tTRAN_PDR60% |
tTRAN_SYM40% = | tTRAN_PDF40% - tTRAN_PDR40% |
Notes
15. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 8.
16. See Figure 9.
17. See Figure 10.
18. See Figure 11
19. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
t REC_PD
—
—
6.0
t REC_SYM
- 2.0
—
2.0
t REC_PD_S
—
—
5.0
t REC_SYM_S
- 1.3
—
1.3
Unit
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS ACCORDING LIN2.1(20)
33662L AND 33662J AND 33662S DEVICES
Propagation Delay and Symmetry(21)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
s
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS WITH TIGHTEN LIMITS(22)
33662S DEVICE
Propagation Delay and Symmetry(23)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
s
LIN PHYSICAL LAYER
RECEIVER CHARACTERISTICS - LIN SLOPE 1.0 V/ns(22)
33662S DEVICE
Propagation Delay and Symmetry(24)
Propagation Delay of Receiver, tREC_PD _FAST= MAX (tREC_PDR_FAST,
tREC_PDF_FAST)
s
t REC_PD_FAST
Symmetry of Receiver Propagation Delay, tREC_PDF_FAST - tREC_PDR_FAST t REC_SYM_FAST
—
—
6.0
- 1.3
—
1.3
SLEEP MODE AND WAKE-UP TIMINGS
Sleep Mode Delay Time (25)
t SD
after EN High to Low to INH High to Low with 100 µA load on INH
µs
50
—
91
40
70
100
WAKE-UP TIMINGS
Bus Wake-up Deglitcher (Sleep Mode) (26)
t WUF
EN Wake-up Deglitcher (27)
t LWUE
EN High to INH Low to High
Wake-up Deglitcher (28)
s
s
—
—
15
10
48
70
t TXDDOM
3.75
5.0
6.25
ms
t FIRST_DOM
—
50
80
µs
s
t WF
Wake state change to INH Low to High
TXD TIMING
TXD Permanent Dominant State Delay(29)
FIRST DOMINANT BIT VALIDATION
First dominate bit validation delay when device in Normal Mode(30)
Notes
20. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
21. See Figure 12.
22. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 8.
23. See Figure 12
24. See Figure 13
25. See Figure 25 and 26
26. See Figure 16, 19, and Figure 20
27. See Figure 14, 17, Figure 21, Figure 25 and Figure 26
28. See Figure 15, 18, Figure 25 and Figure 26
29. The LIN is in recessive state and the receiver is still active.
30. See Figure 14, 17, 15, 18, 16, 19 and Figure 24
33662
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
EN Low Pulse Duration to Enter in Fast Baud Rate using Toggle Function (31)
t1
Min
Typ
Max
—
—
45
12.5
—
—
12.5
—
—
12.5
—
—
Unit
FAST BAUD RATE TIMING
s
EN High to Low and Low to High
TXD Low Pulse Duration to Enter in Fast Baud Rate using Toggle Function (31)
t2
Delay Between EN Falling Edge and TXD Falling Edge to Enter in Fast Baud
Rate Using Toggle Function (31)
t3
Delay Between TXD Rising Edge and EN Rising Edge to Enter in Fast Baud
Rate Using Toggle Function (31)
t4
RXD Low Level duration after EN rising edge to validate the Fast Baud Rate
entrance(31)
t5
µs
µs
µs
µs
1.875
6.25
Notes
31. See Figure 22 and 23
TIMING DIAGRAMS
VSUP
VSUP
TXD
R0
LIN
RXD
GND
C0
Note R0 and C0: 1.0 k/1.0 nF, 660 /6.8 nF, and 500 /10 nF.
Figure 8. Test Circuit for Timing Measurements
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
TBIT
TBIT
tBUS_DOM(MAX)
VLIN_REC
tBUS_REC(MIN)
THREC(MAX) 74.4% VSUP
Thresholds of
receiving node 1
THDOM(MAX) 58.1% VSUP
LIN
Thresholds of
receiving node 2
THREC(MIN) 42.2% VSUP
THDOM(MIN) 28.4% VSUP
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1
tREC_PDF(1)
tREC_PDR(1)
RXD
Output of receiving Node 2
tREC_PDF(2)
tREC_PDR(2)
Figure 9. LIN Timing Measurements for Normal Baud Rate (33662L and 33662S)
TXD
TBIT
TBIT
tBUS_DOM(MAX)
VLIN_REC
tBUS_REC(MIN)
THREC(MAX) 77.8% VSUP
Thresholds of
receiving node 1
THDOM(MAX) 61.6% VSUP
LIN
Thresholds of
receiving node 2
THREC(MIN) 38.9% VSUP
THDOM(MIN) 25.1% VSUP
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1
tREC_PDF(1)
tREC_PDR(1)
RXD
Output of receiving Node 2
tREC_PDR(2)
tREC_PDF(2)
Figure 10. LIN Timing Measurements for Slow Baud Rate (33662J)
33662
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
VLIN_REC
VBUSREC
60% VSUP
VBUSDOM
40% VSUP
LIN BUS SIGNAL
VSUP
tTRAN_PDR40%
tTRAN_PDR60%
tTRAN_PDF60%
tTRAN_PDF40%
Figure 11. LIN Transmitter Timing for 33662S
VLIN_REC
VBUSREC
60% VSUP
VBUSDOM
40% VSUP
VSUP
LIN BUS SIGNAL
RXD
tREC_PDF
tREC_PDR
Figure 12. LIN Receiver Timing
VLIN_REC
VBUSREC
VBUSDOM
1V/ns
60% VSUP
40% VSUP
VSUP
LIN BUS SIGNAL
RXD
tREC_PDF_FAST
tREC_PDR_FAST
Figure 13. LIN Receiver Timing LIN slope 1V/ns
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
FUNCTIONAL DIAGRAMS
EN
INH
LIN
VBUSWU
tWUF
Normal Mode
t LWUE
INH
TXD
tFIRST_DOM
tFIRST_DOM
EN
TXD
LIN
RXD
RXD (High Z)
(High Z)
WAKE
WAKE
Figure 16. LIN Bus Wake-up with TXD High
Figure 14. EN Pin Wake-up with TXD High
WAKE
EN
WAKE after deglitcher
INH
t WF
INH
Awake Mode
t LWUE
tFIRST_DOM
EN
TXD
Normal Mode
tFIRST_DOM
LIN
TXD
RXD
LIN
RXD
(High Z)
(High Z)
Awake Mode
Figure 15. WAKE Pin Wake-up with TXD High
WAKE
Figure 17. EN Pin Wake-up with TXD Low
33662
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
WAKE
WAKE after deglitcher
tWUF
t WF
INH
VBUSWU
LIN
INH
tFIRST_DOM
tFIRST_DOM
EN
EN
TXD
TXD
RXD (High Z)
Awake Mode
LIN
RXD
(High Z)
WAKE
Awake Mode
Figure 18. WAKE Pin Wake-up with TXD Low
Figure 19. LIN Bus Wake-up with TXD Low
INH
EN
TXD
No wake-up
t>tWUF
LIN
(High Z)
RXD
WAKE
Device in
Communication Mode
Preparation to Sleep Mode
No communication available
LIN wake-up event not take into account
Sleep Mode
No communication available
Wake & LIN wake-up events
allowed
Awake
mode
Normal Mode
t SD
Figure 20. LIN Bus Wake-up with LIN bus in Dominant During the Preparation to Sleep Mode
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
EN pin
tLWUE
EN internal signal
tLWUE
EN pin
t < tLWUE
EN internal signal
5V
EN pin
t < tLWUE
5V
EN internal signal
Figure 21. EN Pin Deglitcher
t 1 (45 s)
EN
Fast Baud Rate entrance
t 2 (12.5 s)
TXD
t 3 (12.5 s)
t 4 (12.5 s)
LIN
Fast Baud Rate validation
RXD
t5
Figure 22. Fast Baud Rate Selection (Toggle Function)
t 1 (45 s)
EN
Exit Fast Baud Rate
t 2 (12.5 s)
TXD
t 3 (12.5 s)
t 4 (12.5 s)
LIN
RXD stays High for Normal or Slow mode validation
RXD
Figure 23. Fast Baud Rate Mode Exit (back to Normal or Slow slew rate)
33662
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
VSUP
POR (3.5-5.3 V)
160 µs
EN
(High or Low)
INH
tFIRST_DOM
TXD
(High or Low)
LIN
(High or Low)
LIN
Awake Mode
RXD
POR (3.5-5.3 V)
EN
Normal Mode
INH
TXD
VUVL
VSUP
RXD
(High Z)
(High Z)
*: this parameter is guaranteed by design
Figure 24. Power Up and Down Sequences
INH
t LWUE
EN
TXD
LIN
(High Z)
RXD
t WF
WAKE
WAKE after deglitcher
Device in
Communication Mode
Preparation to Sleep Mode
No communication allowed
LIN wake-up event not take into
account
Sleep
Mode
t SD
Figure 25. Sleep Mode Sequence
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
INH
INH
t LWUE
EN
EN
TXD
TXD
No communication
allowed
LIN
No communication
allowed
LIN
(High Z)
RXD
t LWUE
(High Z)
RXD
WAKE
(case 1)
WAKE
(case 2)
WAKE after deglitcher
(case 1)
WAKE after deglitcher
(case 2)
t = tWF
Device in
Communication Mode
Preparation to
Sleep Mode
t tWF
Awake Mode
t < t SD
The device does not enter in Sleep Mode
INH
Device in
Communication Mode
Awake Mode
Preparation to Sleep Mode (t < tSD)
The device does not enter in Sleep Mode
t LWUE
EN
TXD
No communication
allowed
LIN
RXD
(High Z)
WAKE
(case 3)
t tWF
WAKE after deglitcher
(case 3)
t tSD
Device in
Communication Mode
Preparation to
Sleep Mode
Sleep Awake Mode
Mode
Figure 26. Examples of Sleep Mode Sequences
33662
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33662L, 33662J, and 33662S are a physical layer
component dedicated to automotive LIN sub-bus
applications.
The 33662L and 33662S features include a 20 kbps baud
rate and the 33662J a 10 kbps baud rate. They integrate fast
baud rate for test and programming modes, excellent ESD
robustness, immunity against disturbance, and radiated
emission performance. They have safe behavior in case of a
LIN bus short-to-ground, or a LIN bus leakage during low
power mode.
Digital inputs are 5.0 and 3.3 V compatible without any
external required components.
The INH output can be used to control an external voltage
regulator, or to drive a LIN bus pull-up resistor.
FUNCTIONAL PIN DESCRIPTION
POWER SUPPLY PIN (VSUP)
The VSUP supply pin is the power supply pin for the
33662L, or 33662J, or 33662S. In an application, the pin is
connected to a battery through a serial diode, for reverse
battery protection. The DC operating voltage is from 7.0 to
18 V. This pin can sustain a standard automotive load dump
condition up to 40 V. To avoid a false bus message, an
undervoltage on VSUP disables the transmission path (from
TXD to LIN) when VSUP falls below 6.7 V. Supply current in
Sleep mode is typically 6.0 A.
LIN overtemperature
OR
INH overtemperature
INH switched off &
LIN transmitter and receiver disabled
INH_ON
INH
LIN Driver
Slope Control
EN_sleep
VSUP Undervoltage
30 k
TXD Dominant
EN
725 k
LIN
X1
35µA
GROUND PIN (GND)
In case of a ground disconnection at the module level, the
33662L, 33662J, and 33662S do not have significant current
consumption on the LIN bus pin when in the recessive state.
VSUP
LIN Wake up
TXD
RXD
Receiver
Figure 27. LIN Interface
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems, and is
compliant to the LIN bus specification 1.3, 2.0, 2.1, and
SAEJ2602-2.
The LIN interface is only active during Normal mode (See
Figure 27).
Transmitter Characteristics
The LIN driver is a low side MOSFET with internal
overcurrent thermal shutdown. An internal pull-up resistor
with a serial diode structure is integrated so no external pullup components are required for the application in a slave
node. An additional pull-up resistor of 1.0 k must be added
when the device is used in the master node.
The LIN pin exhibits no reverse current from the LIN bus
line to VSUP, even in the event of a GND shift or VSUP
disconnection. The 33662 is tested according to the
application conditions (i.e. in normal mode and recessive
state during communication).
The transmitter has a 20 kbps baud rate (Normal baud
rate) for the 33662L and 33662S devices, or 10 kbps baud
rate (Slow baud rate) for the 33662J device. As soon as the
device enters in Normal mode, the LIN transmitter will be able
to send the first dominant bit only after the tFIRST_DOM delay.
tFIRST_DOM delay has no impact on the receiver. The receiver
will be enabled as soon as the device enters in Normal mode.
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Receiver Characteristics
The receiver thresholds are ratiometric with the device
supply pin.
If the VSUP voltage goes below the VSUP undervoltage
threshold (VUVL, VUVH), the bus enters into a recessive state
even if communication is sent to TXD.
200 k
RXD
LIN_RXD
To exit the Fast Baud Rate and return in Normal or Slow
baud rate, a toggle function is needed. At the end of the
toggle function, the RXD pin stays high to signal Fast Baud
Rate exit (See Figure 23). The device enters into Fast Baud
Rate at room and hot temperature.
DATA INPUT PIN (TXD)
The TXD input pin is the MCU interface to control the state
of the LIN output. When TXD is LOW (dominant), LIN output
is LOW; when TXD is HIGH (recessive), the LIN output
transistor is turned OFF. TXD pin thresholds are 3.3 V and
5.0 V compatible.
This pin has an internal pull-up current source to force the
recessive state if the input pin is left floating.
If the pin stays low (dominant sate) more than 5.0 ms
(typical value), the LIN transmitter goes automatically into
recessive state.
VSUP
EN_RXD
In case of LIN thermal shutdown, the transceiver and
receiver are in recessive and INH turned off. When the
temperature is below the TLINSD, INH and LIN will be
automatically enabled.
The Fast Baud Rate selection is reported by the RXD pin.
Fast Baud Rate is activated by the toggle function (See
Figure 22). At the end of the toggle function, just after EN
rising edge, RXD pin is kept low for t5 to flag the Fast Baud
Rate entry (See Figure 22).
EN
X1
Receiver
30 k
LIN
Slope
Control
Figure 28. RXD Interface
The RXD output pin is the receiver output of the LIN
interface. The low level is fixed. The high level is dependent
on EN voltage. If EN is set at 3.3 V, RXD VOH is 3.3 V. If EN
is set at 5.0 V, RXD VOH is 5.0 V.
In Sleep mode, RXD is high-impedance. When a wake-up
event is recognized from the WAKE pin or from the LIN bus
pin, RXD is pulled LOW to report the wake-up event. An
external pull-up resistor may be needed.
ENABLE INPUT PIN (EN)
EN input pin controls the operation mode of the interface.
If EN = 1, the interface is in Normal mode, TXD to LIN after
tFIRST_DOM delay and LIN to RXD paths are both active. EN
pin thresholds are 3.3 V and 5.0 V compatible. RXD VOH
level follows EN pin high level. The device enters the Sleep
mode by setting EN LOW for a delay higher than tSD (70 µs
typ. value) and if the WAKE pin state doesn’t change during
this delay (see Figure 25).
DATA OUTPUT PIN (RXD)
A combination of the logic levels on the EN and TXD pins
allows the device to enter into the Fast Baud Rate mode of
operation (see Figure 22).
RXD output pin is the MCU interface, which reports the
state of the LIN bus voltage.
INHIBIT OUTPUT PIN (INH)
In Normal or Slow baud rate, LIN HIGH (recessive) is
reported by a high voltage on RXD; LIN LOW (dominant) is
reported by a low voltage on RXD.
The RXD output structure is a tristate output buffer (See
Figure 28).
The INH output pin is connected to an internal high side
power MOSFET. The pin has two possible main functions. It
can be used to control an external switchable voltage
regulator having an inhibit input. It can also be used to drive
the LIN bus external resistor in the master node application,
thanks to its high drive capability. This is illustrated in
Figure 30 and 31.
In Sleep mode, INH is turned OFF. If a voltage regulator
inhibit input is connected to INH, the regulator will be
disabled. If the master node pull-up resistor is connected to
INH, the pull-up resistor will be unpowered and left floating.
In case of a INH thermal shutdown, the high side is turned
off and the LIN transmitter and receiver are in recessive state.
An external 10 to 100 pF capacitor on INH pin is advised
in order to improve EMC performances.
33662
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
WAKE INPUT PIN (WAKE)
The WAKE pin is a high voltage input used to wake-up the
device from the Sleep mode. WAKE is usually connected to
an external switch in the application.
The WAKE pin has a special design structure and allows
wake-up from both HIGH to LOW or LOW to HIGH
transitions. When entering into Sleep mode, the device
monitors the state of the WAKE pin and stores it as a
reference state. The opposite state of this reference state will
be the wake-up event used by the device to enter again into
Normal mode.
If the Wake pin state changes during the Sleep mode
Delay Time (tSD) or before EN goes low with a deglitcher
lower than tWF, the device will not enter the Sleep mode, but
will go into Awake mode (See Figure 26).
An internal filter is implemented to avoid a false wake-up
event due to parasitic pulses (See Figure 15 and 18). WAKE
pin input structure exhibits a high-impedance, with extremely
low input current when voltage at this pin is below 27 V. Two
serial resistors should be inserted in order to limit the input
current mainly during transient pulses and ESD. The total
recommended resistor value is 33 k. An external 10 to
100 nF capacitor is advised for better EMC and ESD
performances.
Important The WAKE pin should not be left open. If the
wake-up function is not used, WAKE should be connected to
ground to avoid a false wake-up.
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
As described below and depicted in Figure 29 and
Table 7, the 33662L, 33662J, and 33662S have two
operational modes, Normal and Sleep. In addition, there are
two transitional modes: Awake mode and Preparation to
Sleep mode. The Awake mode allows the device to go into
Normal mode. The Preparation to Sleep mode allows the
device to go into Sleep mode.
NORMAL OR SLOW BAUD RATE
In the Normal mode, the LIN bus can transmit and receive
information.
The 33662L and 33662S (20 kbps) have a slew rate and
timing compatible with Normal Baud Rate and LIN protocol
specification 1.3, 2.0, and 2.1.
The 33662J (10 kbps) has a slew rate and timing
compatible with Low Baud Rate.
From Normal mode, the three devices can enter into Fast
Baud Rate (Toggle function).
FAST BAUD RATE
In Fast Baud Rate, the slew rate is around 10 times faster
than the Normal Baud Rate. This allows very fast data
transmission (> 100 kbps) -- for instance, for electronic
control unit (ECU) tests and microcontroller program
download. The bus pull-up resistor might be adjusted to
ensure a correct RC time constant in line with the high baud
rate used.
Fast Baud Rate is entered via a special sequence (called
toggle function) as follows:
1- EN pin set LOW while TXD is HIGH
2- TXD stays HIGH for 12.5 µs min
3- TXD set LOW for 12.5 µs min
4- TXD pulled HIGH for 12.5 µs min
5- EN pin set LOW to HIGH while TXD still HIGH
The device enters into the Fast Baud Rate if the delay
between Step 1 to Step 5 is 45 µs maximum. The toggle
function is described in Figures 22. Once in Fast Baud Rate,
the same toggle function just described previously is used to
bring the device back into Normal Baud Rate.
Fast Baud Rate selection is reported to the MCU by RXD
pin. Once the device enters in this Fast Baud Rate, the RXD
pin goes at low level for t5. When the device returns in Normal
Baud Rate with the same toggle function, the RXD pin stays
high. Both sequences are illustrated in Figures 22 and 23.
PREPARATION TO SLEEP MODE
To enter the Preparation to Sleep mode, EN must be low
for a delay higher than tLWUE.
If the WAKE pin state doesn’t change during tSD and tLWUE
then the 33662 goes into Sleep mode.
If the WAKE pin state changes during tSD and if tWF is
reached after end of tSD then the device goes into Sleep
mode after the end of tSD timing.
If the WAKE pin state changes during tSD and tWF delay
has been reached before the end of tSD then the device goes
into Awake mode.
If the WAKE pin state changes before tSD and the delay
tWF ends during tSD then the device goes into Awake mode.
If EN goes high for a delay higher than tLWUE, the 33662
returns to Normal mode.
SLEEP MODE
To enter into Sleep mode, EN must be low for a delay
longer than tSD and the Wake pin must stay in the same state
(High or Low) during this delay.
The device conditions to not enter in Sleep mode but enter
in Awake mode are detailed in the Preparation into Sleep
mode chapter. See Figure 26.
In Sleep mode, the transmission path is disabled and the
device is in Low Power mode. Supply current from VSUP is
very low (6.0 µA typical value). Wake-up can occur from LIN
bus activity, from the EN pin and from the WAKE input pin. If
during the preparation to Sleep mode delay (tSD), the LIN bus
goes low due to LIN network communication, the device still
enters into the Sleep mode. The device can be awakened by
a recessive to dominant start, followed by a dominant to
recessive state after t > tWUF.
After a Wake-up event, the device enters into Awake
mode.
In the Sleep mode, the internal 725 kOhm pull-up resistor
is connected and the 30 kOhm is disconnected.
DEVICE POWER-UP (Awake Transitional Mode)
At power-up (VSUP rises from zero), when VSUP is above
the Power On Reset voltage, the device automatically
switches after a 160 µs delay time to the Awake transitional
mode. It switches the INH pin to a HIGH state and RXD to a
LOW state. See Figure 24.
DEVICE WAKE-UP EVENTS
The 33662L, 33662J, and 33662S can be awakened from
Sleep mode by three wake-up events:
• Remote wake-up via LIN bus activity
• Via the EN pin
• Toggling the WAKE pin
Remote Wake from LIN Bus (Awake Transitional Mode)
The device is awakened by a LIN dominant pulse longer
than tWUF. Dominant pulse means: a recessive to dominant
transition, wait for t > tWUF, then a dominant to recessive
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
transition. This is illustrated in Figure 16 and 19. Once the
wake-up is detected (during the dominant to recessive
transition), the device enters into Awake mode, with INH
HIGH and RXD pulled LOW.
Once in the Awake mode, the EN pin has to be set to 3.3 V
or 5.0 V (depending on the system) to enter into Normal
mode. Once in Normal mode, the device has to wait tfirst_dom
delay before transmitting the first dominant bit.
Wake-up from EN pin
The device can be waked-up by a LOW to HIGH transition
of the EN pin. When EN is switched from LOW to HIGH and
stays HIGH for a delay higher than tLWUE, the device is
awakened and enters into Normal mode. See Figure 14 and
17. Once in Normal mode, the device has to wait tFIRST_DOM
delay before transmitting the first dominant bit.
Wake-up from WAKE Pin (Awake Transitional Mode)
Just before entering the Sleep mode, the WAKE pin state
is stored. A change in the level longer than the deglitcher time
(70 µs maximum) will generate a wake-up, and the device
enters into the Awake Transitional mode, with INH HIGH and
RXD pulled LOW. See Figure 15 and 18. The device goes
into Normal mode when EN is switched from LOW to HIGH
and stays HIGH for a delay higher than tLWUE. Once in
Normal mode, the device has to wait tFIRST_DOM delay before
transmitting the first dominant bit.
FAIL-SAFE FEATURES
The table below describes the 33662 protections.
BLOCK
FAULT
Power
Supply
Power on Reset
(POR)
INH
INH Thermal
Shutdown
FUNCTIONAL
MODE
CONDITION
RESPONSE
RECOVERY
CONDITION
RECOVERY
FUNCTIONALITY MODE
All modes
VSUP < 3.5 V (min)
then power up
No internal supplies
Condition gone
Device goes in Awake
mode whatever the
previous device mode
Normal,
Awake &
Preparation to
Sleep modes
Temperature >
160 °C (typ)
INH high side turned
off. LIN transmitter
and receiver in
recessive state
Condition gone
Device returns in same
functional mode
VSUP < VUVL
LIN transmitter in
recessive state
Condition gone
Device returns in same
functional mode
TXD pin low for more
than 5.0 ms (typ)
LIN transmitter in
recessive state
Condition gone
Device returns in same
functional mode
Condition gone
Device returns in same
functional mode
VSUP undervoltage
TXD Pin Permanent
Dominant
Normal
LIN
LIN Thermal
Shutdown
Normal mode
Temperature >
160 °C (typ)
LIN transmitter and
receiver in recessive
state
INH high side turned
off
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Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Power Up
EN HIGH to LOW for t > tLWUE
VSUP > VPOR
Awake
Toggle
Function(33)
EN LOW to HIGH for t > tLWUE
Internal WAKE(30) state
changes during tSD
LIN bus dominant pulse
for t > tWUF(31)
or
WAKE pin state
changes for t > tWF(32)
Preparation
to Sleep
Internal WAKE(30) state
doesn’t change during tSD
Fast Baud
Rate (10x)
EN HIGH to LOW
for t > tLWUE
EN LOW to HIGH
for t > tLWUE
Normal Baud Rate for
33662L and 33662S
or
Slow Baud Rate
for 33662J
Toggle
Function(33)
Sleep
EN LOW to HIGH for t > tLWUE
Notes
32. Internal WAKE is the WAKE signal filtered by tWF (WAKE deglitcher)
33.
34.
35.
See Figure 15 and Figure 18
See figures Figure 14 and Figure 17
The Toggle Function is guaranteed at ambient and hot temperature
Figure 29. Operational and Transitional Modes State Diagram
Table 7. Explanation of Operational and Transitional Modes State Diagram
Operational/
Transitional
Sleep
Awake
LIN
INH
EN
TXD
RXD
Recessive state, driver off with
725 k pull-up
OFF
LOW
X
High-impedance.(36)
HIGH if external pull-up to VDD
LOW
X
LOW.
Recessive state, driver off. 
725 k pull-up active
(low)
ON
If external pull-up, HIGH-to-LOW
transition reports wake-up
(high)
Preparation to
Sleep mode
Recessive state, driver off with 
725 k pull-up
Normal mode
Driver active. 30 k pull-up active ON
Normal Baud Rate for 33662L
(high)
and 33662S
ON
High-impedance. HIGH if
external pull-up to VDD
LOW
X
HIGH
LOW to drive LIN bus in dominant
(high)
Report LIN bus state:
HIGH to drive LIN bus in recessive • Low LIN bus dominant
• High LIN bus recessive
Slow Baud Rate for 33662J
Fast Baud Rate (> 100 kbps) for
33662L, 33662S, & 33662J
X = Don’t care.
Notes
36. Only applies to 33662B. The 33662 will have a leakage current of typically 95 A if a pull-up resistor is implemented.
COMPATIBILITY WITH LIN1.3
Following the Consortium LIN specification Package,
Revision 2.1, November 24, 2006, Chapter 1.1.7.1
Compatibility with LIN1.3, page 15.
The LIN 2.1 physical layer and is backward compatible
with the LIN 1.3 physical layer, but not the other way around.
The LIN 2.1 physical layer sets harder requirements, i.e. a
node using the LIN 2.1 physical layer can operate in a LIN 1.3
cluster.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33662 can be configured for several applications.
Figure 30 and 31 show master and slave node applications.
An additional pull-up resistor of 1.0 k in series with a diode
C1
22µF
D1
VBAT
R4
2.2k
between the INH and LIN pins must be added when the
device is used in the master node.
R2
18k
C2
100nF
VSUP
R3
18k
X1
Regulator
VDD
VDD
MCU
VDD
5V or
3.3V
Control
Unit
200 k
**
12V
INH_ON
EN
I/O
RXD
RXD
INH
EN_sleep
D2
30 k
RXD_Int Receiver
EN_RXD
725 k
LIN
R1
1.0 k
LIN Bus
LIN_en
TXD
35µA
TXD_Int
TXD
Slope
Control
WAKE
C3
100nF
GND
*: Optional. 2.2k if implemented
Figure 30. Master Node Typical Application
C1
22µF
D1
VBAT
R4
2.2k
R2
18k
C2
100nF
VSUP
R3
18k
X1
Regulator
VDD
MCU
12V
5V or
3.3V
VDD
INH_ON
EN
I/O
VDD
**
RXD
Control
Unit
200 k
RXD
INH
EN_sleep
RXD_Int Receiver
EN_RXD
TXD
725 k
LIN
LIN Bus
LIN_en
35µA
TXD
30 k
TXD_Int
Slope
Control
WAKE
C3
100nF
GND
*: Optional. 2.2k if implemented
Figure 31. Slave Node Typical Application
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and do a keyword search on the 98A
drawing number below.
EF SUFFIX
8-PIN
98ASB42564B
REVISION V
33662
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EF SUFFIX
8-PIN
98ASB42564B
REVISION V
33662
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
REVISION HISTORY
PACKAGE DIMENSIONS
REVISION HISTORY
REVISION
DATE
3.0
8/2011
Initial release
4.0
9/2011
Changed the PC part numbers in the Ordering Information Table to MC
5.0
1/2014
•
•
•
DESCRIPTION OF CHANGES
•
•
6.0
1/2014
•
•
7.0
1/2014
•
Added MC33662BLEF, MC33662BJEF, and MC33662BSEF to the ordering information.
Updated Device Variations table
Changed LIN dominant level with 500 680  and 1.0 k load on the LIN bus from 0.3 to
0.25
Changed LIN Wake-up Threshold from Sleep Mode from 5.0 to 5.3
MC33662LEF/MC33662SEF/MC33662JEF INH pin HBM level 8.0 KV removed to reflect
performance
Corrected MC33662BLEF, MC33662BJEF, and MC33662BSEF to PC in the ordering
information.
Minor corrections to format.
Changed MC33662BLEF, MC33662BJEF, and MC33662BSEF to MC in the ordering
information. Now qualified.
33662
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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Document Number: MC33662
Rev. 7.0
1/2014